®
Alt er a Cor pora t ion 1
MAX 9000
Programmable Logic
Device Family
Ju n e 2003, ve r. 6.5 Data Sheet
DS-M9000-6.5
Includes
MAX 9000A
Features... ■High-performan ce CMOS EEP ROM-based programmable logic
devices (PLDs) built on third-generation Multiple Array MatriX
(MAX®) architecture
■5.0-V in-system programmability (ISP) through built-in IEEE Std.
1149.1 Joint Test Action Group (JTAG) interface
■Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE
Std. 1149.1-1990
■High-density erasable programmable logic device (EPLD) family
ranging from 6,000 to 12,000 usable gates (see Table 1)
■10-ns pin-to-pin logic delays with counter frequencies of up to
144 MHz
■Fully compliant with the peripheral component interconnect Special
Int ere st Gr oup’s ( PC I SIG) PCI Local Bus Specification, Revision 2.2
■Dual-output macrocell for independent use of combinatorial and
registered logic
■FastTrack® Interconnect for fast, predictable interconnect delays
■Input/output registers with clear and clock enable on all I/O pins
■Programmable output slew-rate control to reduce switching noise
■MultiVolt™ I/O interface operation, allowing devices to interface with
3.3-V and 5.0-V d e vices
■Configurable expander product-term distribution allowing up to 32
pro du ct term s per macroc ell
■Programmable power-saving mode for more than 50% power
reduction in each macrocell
Table 1. MAX 9000 De vice Fe atures
Feature EPM9320
EPM9320A EPM9400 EPM9480 EPM9560
EPM9560A
Usable gates 6,000 8,000 10,000 12,000
Flipflops 484 580 676 772
Macrocells 320 400 480 560
Logic array blocks (LABs) 20 25 30 35
Maxim um us er I/O pins 168 159 175 216
tPD1 (ns) 10 15 10 10
tFSU (ns) 3.0 5 3.0 3.0
tFCO (ns) 4.5 7 4.8 4.8
fCNT (MHz) 144 118 144 144
2Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
...and More
Features
■Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
■Programmable security bit for protection of proprietary designs
■Software d esign suppor t and automa tic place- and-route provided by
Altera’s MA X+ PLUS®II development system on Windows-based
PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM
RISC System/6000 workstations
■Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHD L, and other inter faces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
■Programming support with Altera’s Master Programming Unit
(MPU), BitBlasterTM ser ial download cable, ByteBlasterTM parallel
port do wnload cable, and ByteBlasterMVTM parallel port download
cable, as well as programming hardware from third-party
manufacturers
■Offered in a variety of package options with 84 to 356 pins (see
Table 2)
Notes:
(1) MAX 9000 device package types include plastic J-lead chip carrier (PLCC), power
quad fla t pack (RQFP ), cera mic pin-g ri d ar ra y (P GA), and bal l-g r id ar r ay (B GA )
packages.
(2) Perform a complete thermal analysis before committing a design to this device
package. See Application Note 74 (Evaluating Power for Altera Devices).
Table 2. MAX 9000 Package Options & I/O Counts Note (1)
Device 84-Pin
PLCC 208-Pin
RQFP 240-Pin
RQFP 280-Pin
PGA 304-Pin
RQFP 356-Pin
BGA
EPM9320 60 (2) 132 – 168 – 168
EPM9320A 60 (2) 132–––168
EPM9400 59 (2) 139 159 – – –
EPM9480 – 146 175 – – –
EPM9560 – 153 191 216 216 216
EPM9560A – 153 191 – – 216
Altera Corporation 3
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
General
Description
The MAX 9000 family of in-system-programmable, high-density, high-
performance EPLDs is based on Altera’s third-generation MAX
archit ecture. Fabr icated on an adva nced CMOS technolog y, the EEPROM -
based MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin
delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed
grade of the MAX 9000 family is compliant with the PCI Local Bus
Specification, Revision 2.2. Table 3 shows the speed grades available for
MAX 900 0 de vi c es .
Table 4 shows t he pe rfor mance o f MAX 9000 d evices f or typical f uncti ons.
Note:
(1) Intern al logic array block (LAB) perfo rman ce is show n. Nu mbers in pare nthese s sho w external delays from row
input pin to row I/O pin.
The MAX 9000 architecture supports high-density integration of system-
level logic functions. It easily integrates multiple programmable logic
devices ranging from PALs , GALs, and 22 V10s to field-programmable
gate arra y (FP G A) devices and EPLDs.
Table 3. MAX 90 00 Speed G rade Availability
Device Speed Grade
-10 -15 -20
EPM9320 vv
EPM9320A v
EPM9400 vv
EPM9480 vv
EPM9560 vv
EPM9560A v
Table 4. MAX 9000 Performance Note (1)
Application Macrocells Used Speed Grade Units
-10 -15 -20
16-bit loadable counter 16 144 118 100 MHz
16-bit up/down counter 16 144 118 100 MHz
16-bit prescaled counter 16 144 118 100 MHz
16-bit address decode 1 5.6 (10) 7.9 (15) 10 (20) ns
16-to -1 m ult iplex er 1 7.7 (12 .1) 10.9 (18) 16 (26) ns
4Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
All MAX 9000 device packages provide four dedicated inputs for global
contr ol sig nal s wi th l arg e fan-outs. Each I/O pin has an asso ciated I /O
cell regi ster with a clock enable cont rol on the per iphery of the device . As
outputs , the se r egist ers pr ovide f ast clock -to-out put ti mes; a s in puts, they
of fe r quick setup times.
MAX 9 000 EPLDs provide 5.0-V in-system programmability (ISP). This
feature allows the devices to be programmed and reprogrammed on the
printed circuit board (PCB) for quick and efficient iterations during design
deve lopment and debug cycles. MAX 9000 devi ces ar e guarant eed fo r 100
progr am and erase cycles.
MAX 9000 EPLDs contain 320 to 560 macrocells that ar e co mbined into
groups of 16 macrocel ls, ca lled logic arr ay blocks (LABs). Each macrocell
has a programmable-AND/fixed-OR arra y and a config urable regist er with
independently programmable clock, clock enable, clear, and preset
functions. For increased flexibility, each macrocell offers a dual-output
structure that allows the register and the product terms to be used
independently. This feature allows register-rich and combinatorial-
in ten sive desi gns to be impl emented eff iciently. The dual-o utput
structur e of the MAX 9000 macrocel l al so imp ro ves log ic u tiliz at ion, thus
increasing the effective capacity of the devices. To build complex logic
functions, each macrocell can be supplemented with both shareable
expa nder p roduct t erms a nd hi gh-spe ed pa rallel e xpan der prod uct te rms
to provide up to 32 product terms per macrocell.
The MAX 9000 family provides programmable speed/power
optimization. Speed-critical portions of a design can run at high
speed/full power, while the remaining portions run at reduced
speed/low power. This speed/power optimization feature enables the
user to configure one or more macrocells to operate at 50% or less power
while adding only a nominal timing delay. MAX 9000 devices also
provide an option that reduces the slew rate of the output buffers,
minimizing noise transients when non-speed-critical signals are
switching. MAX 9000 devices offer the MultiVolt feature, which allows
output drivers to be set for either 3.3-V or 5.0-V operation in mixed-
vo ltag e systems.
Altera Corporation 5
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
The MAX 9000 family is supported by Altera’s MAX+PLUS II
dev elo pment sy stem, a single , integrate d sof tware pa ckage th at o ffers
schematic, text—including VHDL, Verilog HDL, and the Altera
Hardware Description Lan guage (AHDL)—and waveform des i gn entry,
compilation and logic synthesis, simulation and timing analysis, and
device programming. The MAX+PLUS II software provides EDIF 2 0 0
and 3 0 0, LPM, and other interfaces for additional design entry and
simulation support from other industry-standard PC- and UNIX-
workstation-based EDA tools. The MAX+PLUS II software runs on
Windows-b a sed PCs as well as Sun SPARCstation, HP 9000 Serie s
700/800, and IBM RISC System/6000 workstations.
fFor more information on development tools, see the MAX+P LUS II
Programmable Logic Development System & Software Data Sheet.
Functional
Description
MAX 9000 devices use a third-generation MAX architecture that yields
both high performance and a high degree of utilization for most
applications. The MAX 9000 architecture includes the following elements:
■Logic array blo cks
■Macrocells
■Expander product terms (shareable and parallel)
■FastTrack Interc onnect
■Dedicat ed inputs
■I/O cells
Figure 1 shows a block diagram of the MAX 9000 architecture.
6Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
Figure 1. MAX 9000 Device Block Diagram
Logic Array Blocks
The MAX 9000 architecture is based on linking high-performance, flexible
logic array modules called logic array blocks (LABs). LABs consist of
16-macrocell arrays that are fed by the LAB local array, as shown in
Figure 2 on page 7. Multiple LABs are linked together via the FastTrack
Interconnect, a series of fast, continuous channels that run the entire
length and width of the device. The I/O pins are supported by I/O cells
(IOCs) located at the end of each row (horizontal) and column (vertical)
path of the FastTrack Interconnect.
Each LAB is fed by 33 inputs from the row interconnect and 16 feedback
signals from the macrocells within the LAB. All of these signals are
available within the LAB in their true and inverted form. In addition,
16 shared expander product terms (“expanders”) are available in their
inverted form, for a total of 114 signals that feed each product term in the
LAB. Each LAB is also fed by two low-skew global clocks and one global
clear that can be used for register control signals in all 16 macrocells.
IOCIOC
IO
C
IO
C
IO
C
IO
C
IOC
IOC
IOC
IOC
IOCIOC IOCIOC
I/O Cell
(IOC)
Logic Array
Block (LAB)
Macrocell
FastTrack
Interconnect
IOC IOC
LAB Local Array
Altera Corporation 7
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
LABs drive the row and colu mn inter connect d irectly. Ea ch macroce ll can
drive out of the L AB on to on e or b ot h r outi ng resou rces . Onc e on the row
or column interconnect, signals can traverse to other LABs or to the IOCs.
Figure 2. MAX 9000 Logic Array Block
Column FastTrac
k
Interconnect
Row FastTrack
Interconnect
33
48
To Peripheral Bus and
Other LABs in the Device
Global Control Select
DIN2
GCLR
16 16
48
See Figure 7
for details.
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
LAB Local Array
(114 Channels)
Shared Expander
Signals Local Feedback
16
16
16
GCLK1
GCLK2
16
DIN3
DIN4 GOE To Peripheral Bus
DIN1
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
8Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
Macrocells
The MAX 9000 macrocell consists of three functional blocks: the product
terms, the product-term select matrix, and the programmable register.
The macrocell can be individually configured for both sequential and
combinatorial logic operation. See Figure 3.
Figure 3. MAX 9000 Macrocell & Local Array
Combinatorial logic is implemented in the local array, which provides five
product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register clear, pre set , clock, and clo ck en able contr ol
functions. Two kinds of expander product terms (“expanders”) are
available to supplement macrocell logic resources:
■Sh areable expanders, which are i nver ted prod uct term s that are fed
back into the logic array
■Parallel expanders, which are product terms borrowed from adjacent
macrocells
The MAX+PLUS II software automatically optimizes product-term
allocation according to the logic requirements of the design.
VCC
Product-
Term
Select
Matrix
16 Local
Feedbacks 16 Shareable
Expander Product
LAB Local
Array
Parallel
Expanders
(from Other
Macrocells)
Clear
Select
Global
Clear Global
Clocks
Clock/
Enable
Select
2
PRN
CLRN
D/T Q
ENA
Register
Bypass
To Row or
Column
FastTrack
Interconnect
Programmable
Register
Macrocell
Input Select
Local Array
Feedback
33 Row
FastTrack
Interconnect
Inputs
Altera Corporation 9
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
For registered functions, each macrocell register can be individually
programmed for D, T, JK, or SR operation with programmable clock
control. The flipflop can also be bypassed for combinatorial operation.
During design entry, the user specifies the desired register type; the
MAX+PLUS II software then selects the most efficient register operation
for each registered function to optimize resource utilization.
Each programma bl e regist er c an be c locked in three different modes :
■By eithe r global clock signa l . This m od e ach ieves th e fast es t clock - to -
output performance.
■By a global clock signal and enabled by an act ive-high clo ck en ab le.
This mode provides an enable on each flipflop while still achieving
the fast clock-to-output performance of the global clock.
■By an array clock im plemente d with a product term. In this mode, th e
flipflop can be clocked b y signa ls from bu ried macroce lls or I /O pins.
Two glob al cloc k s ignals are availab le. As shown in Figure 2, th ese gl ob al
clock signals can be the true or the complement of either of the global clock
pins (DIN1 and DIN2).
Each register also supports asynchronous preset and clear functions. As
show n in Figure 3, the produ ct-term s elect ma trix a llocate s prod uct te rms
to cont rol the se operat ions. Although the product-term -driven preset and
clea r inputs to regi sters are act ive high, active -low control ca n be obta ined
by inverting the signal within the logic array. In addition, each register
clear function can be ind ividually dr iven by t he dedi cated g lobal clear pin
(DIN3). The g lobal cl ear can b e prog rammed for a ctive-high or act ive-low
operation.
All MAX 9000 macrocells offer a dual-output structure that provides
independent register and combinatorial logic output within the same
macrocell. This function is implemented by a process called register
packing. When register packing is used, the product-term select matrix
alloc ates one prod uct term to the D input of the register, whil e the
remaining product terms can be used to implement unrelated
combinatorial logic. Both the registered and the combinatorial output of
the macrocell can feed either the FastTrack Interconnect or the LAB local
array.
10 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
Expa nder Product Terms
Althoug h most l ogic functio ns can b e im ple ment ed w ith the f ive pr od uct
terms availa ble in each mac rocell, some logic function s are more comp lex
and require addi tiona l produ ct terms . Althoug h anothe r macroc ell can
supply the requ ired lo gic resour ces, the MAX 900 0 archite cture a lso offers
both shareable and parallel expander product terms that provide
additio nal product terms directly to any macrocel l in the same LAB. These
expanders help ensure that logic is synthesized with the fewest possible
logic resources to obtain the fastest possible speed.
Shareable Expanders
Each LAB has 16 shareable expanders that can be viewed as a pool of
uncommitted single product terms (one from each macrocell) with
inverted outputs that feed back into the LAB local array. Each shareable
expander can be used and shared by any or all macrocells in the LAB to
build complex logic functions. A small delay (tLOCAL + tSEXP) is incurred
when sh areabl e expanders are used. Figure 4 shows how shareable
expanders can feed multiple macrocells.
Figure 4. MAX 9000 Shareable Expanders
Macrocell
Product-Term
Logic
Product-Term Select Matrix
Macrocell
Product-Term
Logic
LAB Local Array
16 Local
Feedbacks 16 Shared
Expanders
33 Row
FastTrack
Interconnect
Signals
Shareable expanders can be shared by any or all macrocells in the LAB.
Altera Corporation 11
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Parallel Expanders
Parallel expand ers are unus ed pro du ct terms tha t can be alloca ted to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 20 product terms to directly feed the
macrocell OR logic, with five product terms provided by the macrocell and
15 parallel expanders provided by neighboring macrocells in the LAB.
Figure 5 shows how parallel expanders can feed the neighboring
macrocell.
Figure 5. MAX 9000 P aral l el Expanders
Preset
Clock
Clear
Product-
Term
Select
Matrix
Preset
Clock
Clear
Product-
Term
Select
Matrix
Macrocell
Product-
Term Logic
From
Previous
Macrocell
To Next
Macrocell
LAB Local
Array
Macrocell
Product-
Term Logic
33 Row
FastTrack
Interconnect
Signals
16 Local
Feedbacks 16 Shared
Expanders
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
12 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
The MAX+PL US II Compiler a utomatically alloca tes as many a s three sets
of up to five parallel expanders to macrocells that require additional
product terms. Each set of expanders incurs a small, incremental timing
delay (tPEXP). For example, if a macrocell requires 14 product terms, the
Compiler uses the five dedicat ed product terms within the macroc ell and
allocates tw o se ts of p aral l el ex pa nd ers; the f ir s t s et includes f ive prod uct
terms and the second set in cludes f our prod uct te rms, i ncreasin g the total
delay by 2 × tPEXP.
Two groups of eight macrocells within each LAB (e.g., macrocells 1
through 8 and 9 through 16) form two chains to lend or borrow parallel
expa nd er s . A macro c el l borrow s par allel ex pa nd er s f ro m lowe r -
numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can
only lend parallel expanders and the highest-numbered macrocell can
only borrow them.
FastTrack Interconnect
In the MAX 9000 architecture, connections between macrocel ls and device
I/O pins are provided by the FastTrack Interconnect, a series of
continuous horizontal and vertical routing channels that traverse the
entire device. This device-wide routing structure provides predictable
perfo rmance e ven in comp lex de signs. In contrast , the segme nted routing
in FPGAs requires switch matrices to connect a variable number of
routing paths, increasing the delays between logic resources and reducing
performance. Figure 6 shows the interconnection of four adjacent LABs
with row and column interconnects.
Altera Corporation 13
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Figure 6. MAX 9000 Device Intercon nec t R esourc es
The LABs within MAX 9000 devices are arranged into a matrix of columns
and r ows. Table 5 shows the number of columns and rows in each
MAX 900 0 devi c e.
Each LAB is named on the basis of its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device.
LAB
A1 LAB
A2
LAB
B1 LAB
B2
Column
FastTrack
Interconnect Row FastTrack
Interconnect
See Figure 8
for details.
See Figure 9
for details.
IOC1 IOC10 IOC1 IOC10
IOC1
IOC8
IOC1
IOC8
IOC1 IOC10
IOC1 IOC10
IOC1
IOC8
IOC1
IOC8
See Figure 7
for details.
Table 5. MAX 9000 Rows & Columns
Devices Rows Columns
EPM9320, EPM9320A 4 5
EPM9400 5 5
EPM9480 6 5
EPM9560, EPM9560A 7 5
14 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
Each row of LABs has a dedicated row interconnect that ro utes signals
both into and out of the LABs in the row. The row interconnect can then
drive I/O pins or feed other LABs in the device. Each row interconnect has
a total of 9 6 chann els. Figure 7 shows how a macrocell drives the row and
column interconnect.
Figure 7. MAX 9000 LAB Connect i ons to Row & Column I n t ercon nect
Each macrocell in the LAB can drive one of three separate column
interconnect channels. The column channels run vertically across the
enti re d evi c e, and ar e sha r ed by the macr o ce ll s in the sam e col um n. The
MAX+PLUS II Compiler optimizes connections to a column channel
automatically.
Macrocell 1
Macrocell 2
96 Row Channels
48 Column
Channels
Each macrocell drives one
of three column channels
.
To LAB
Local Array
Each macrocell drives
one row channel.
Additional multiplexer provides
column-to-row path if
macrocell drives row channel.
Dual-output
macrocell feeds
both FastTrack
Interconnect and
LAB local array.
LAB
Altera Corporation 15
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
A row interconnect channel can be fed by the output of the macrocell
throug h a 4-to -1 multi plexer that the macr ocell sha res wi th thr e e column
channe ls. If the multipl exer is used for a macrocell-to-r ow connection, the
three column signals can access another row channel via an additional
3-to-1 multiplexer. Within any LAB, the multiplexers provide all
48 column channels with access to 32 row channels.
Row-to-I/O Cell Connections
Figure 8 illustrates the connections between row interconnect channels
and IOCs. An input signal fro m an IOC can drive two separate row
channels. When an IOC is used as an output, the signal is driven by a
10-to-1 multiplexer that selects the row channels. Each end of the row
channel feeds up to eight IOCs on the periphery of the device.
Figure 8. MAX 9000 Row-t o-I O C Connections
Colu mn- to-I /O Cel l Conn ect ions
Each end of a column channel has up to 10 IOCs (see Figure 9). An input
signal from an IOC can drive two separate column channels. When an IOC
is used as an output, the signal is driven by a 17-to-1 multiplexer that
selects the column channels.
96
96
Each IOC is driven by
a 10-to-1 multiplexer.
Each IOC can drive up to
two row channels.
IOC8
IOC1
10
10
Row FastTrack
Interconnect
96
16 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
Figure 9. MAX 9000 Column-to-IOC Connections
Dedicated Inputs
In addition to the genera l-purpose I /O pins, MAX 9000 device s have four
dedica te d input pins. These dedica te d inputs provide low-s kew, device-
wide si gnal distribu tion to the LA Bs and IOCs in the dev i ce, and are
typically used for global clock, clear, and output enable control signals.
The global control signals can feed the macrocell or IOC clock and clear
inputs, as well as the IOC out put enable. The dedi cated inputs can also be
used as general-purpose data inputs because they can feed the row
FastTrack Interconnect (see Figure 2 on page 7).
I/O Cells
Figure 10 shows the I OC bl ock d iag r am. Signals enter th e MAX 9000
device from either the I/O pins that provide general-purpose input
capability or from the four dedicated inputs. The IOCs are located at the
ends of the row and column interconnect channels.
48
Each IOC is driven by
a 17-to-1 multiplexer .
Each IOC can drive u
p
to two column
channels.
17 17
Column FastT rack
Interconnect
IOC10
IOC1
48
48
Altera Corporation 17
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Figure 10. MAX 9000 IOC
I/O pins can be used as input, output, or bidirectional pins. Each IOC has
an IO C register with a clock e nable input. Th is regis te r ca n b e use d eit he r
as an input r egis ter for e xterna l data that re quire s fast se tup tim es, or as a n
output register for data that requires fast clock-to-output performance.
The IOC register clock enable allows the global clock to be used for fast
clock-to-output performance, while maintaining the flexibility required
for select ive clocki ng.
The clock , clock enable, clear, a nd output enab le controls for the IOCs are
provided by a network of I/O control signals. These signals can be
supplied by either the dedicated input pins or internal logic. The IOC
contr ol -signal paths a re d esigne d to mi nimi ze the skew acro ss the device.
All con trol-signal sou rces are buffe red onto hig h-speed drive rs that dr ive
the signals around the pe ri pher y of t he de vic e. This “p eriph er a l bus” c an
be configured to provide up to eight output enable signals, up to four
clock signals, up to six clock enable signals, and up to two clear signals.
Table 6 on page 18 shows the sources that drive the peripheral bus and
how the IOC control signals share the peripheral bus.
Slew-Rate
Control
From Row or
Column FastTrack
Interconnect
4
2
8
13
To Row or
Column FastTrack
Interconnect
OE [7..0]
CLK [3..0]
ENA [5..0]
CLR [1..0]
Peripheral Control
Bus [12..0]
CLRN
DQ
ENA
VCC
VCC
6
VCC
18 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
The out put buff er in eac h IOC ha s an adju stabl e output sl ew rate that can
be configured for low-noise or high-speed performance. A slower slew
rate reduces board-level noise and adds a nominal timing delay to the
output buffe r delay (tOD) param eter . The fast slew ra te s hould be use d fo r
speed-critical outputs in systems that are adequately protected against
noise. D e sig ners c a n sp eci fy t he sl ew r ate on a pi n-by-pin b asis d uring
design e ntr y or assig n a de fau lt slew ra te to all pins on a g lob al b as is. T he
slew rate c ontrol affects bo th rising and fallin g edges of the out put signals.
Output
Configuration
The MAX 9000 device architecture supports the MultiVolt I/O interface
feature, which allows MAX 9000 devices to interface with systems of
differin g supply volt ag es. T he 5.0- V devic es in all pa ck ag es can be se t for
3.3-V or 5.0-V I/O pin operation. These devices have one set of VCC pins
for internal operation and i nput buffers (VCCINT), and another set for I/O
output driv ers ( VCCIO).
The VCCINT pins must always be connected to a 5.0-V power supply.
With a 5.0-V VCCINT level, input voltages are at TTL levels and are
therefore compatible with 3.3-V and 5.0-V inputs.
Table 6. Per i pheral Bus Sources
Peri pheral Cont r ol
Signal Source
EPM9320
EPM9320A EPM9400 EPM9480 EPM9560
EPM9560A
OE0/ENA0 Row C Row E Row F Row G
OE1/ENA1 Row B Row E Row F Row F
OE2/ENA2 Row ARow ERow ERow E
OE3/ENA3 Row BRow BRow BRow B
OE4/ENA4 Row ARow ARow ARow A
OE5 Row DRow DRow DRow D
OE6 Row CRow CRow CRow C
OE7/CLR1 Row B/GOE Row B/GOE Row B/GOE Row B/GOE
CLR0/ENA5 Row A/GCLR Row A/GCLR Row A/GCLR Row A/GCLR
CLK0 GCLK1 GCLK1 GCLK1 GCLK1
CLK1 GCLK2 GCLK2 GCLK2 GCLK2
CLK2 Row DRow DRow DRow D
CLK3 Row CRow CRow CRow C
Altera Corporation 19
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
The VCCIO pins can be c onnecte d to e ither a 3.3- V or 5. 0-V powe r supp ly,
depending on the output requirements. When the VCCIO pins are
connected to a 5.0-V power supply, the output levels are compatible with
5.0-V systems. When the VCCIO pins are connected to a 3.3-V power
supp ly, the out put high is at 3.3 V and is there for e compati ble wit h 3.3-V
or 5.0-V systems. Devices operating with VCCIO levels lower than 4.75 V
incur a nominally greater timing delay of tOD2 instead of tOD1.
In-System
Programma-
bility (ISP)
MAX 9000 devices can be programmed in-system through a 4-pin JTAG
interface. ISP offers quick and efficient iterations during design
development and debug cycle s. The M AX 900 0 architecture intern ally
generates the 12.0-V programming voltage required to program EEPROM
cells, eliminating the need for an external 12.0-V power supply to program
the devices on the board. During ISP, the I/O pins are tri-stated to
eliminate board conflicts.
ISP simplifies the manufacturing flow by allowing the devices to be
mounted on a printed circuit board with standard pick-and-place
equipment bef ore they are pr og r amm ed . MAX 9000 dev ice s can be
programmed by downloading the information via in-circuit testers,
embedded processors, or the Altera BitBlaster, ByteBlaster, or
ByteBlasterMV download cable. (The ByteBlaster cable is obsolete and has
be en rep laced b y the ByteBl aster MV cab le, w hich c an int erface with 2 .5-V ,
3.3-V, and 5.0-V devices. ) Programm ing the devices after they are place d
on the board eliminates lead damage on high pin-count packages (e.g.,
QFP packages) due to device handling. MAX 9000 devices can also be
reprogrammed in the field (i.e., product upgrades can be performed in the
field via software or modem).
In-system programming can be accomplished with either an adaptive or
constant algo ri thm. An ada p tiv e a l go ri thm reads inform ati on from the
unit and adapts subsequent programming steps to achieve the fastest
possible programming time for that unit. Because some in-circuit testers
platforms have difficulties supporting an adaptive algorithm, Altera
offers devices tested with a constant algorithm. Devices tested to the
constant algorithm have an “F” suffix in the ordering code.
20 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
Progra mm ing S equence
During in-syst em p ro gra mming, instruct i ons , addresses, and da ta are
shifted into the MAX 9000 device through the TDI input pin. Data is
shifted out through the TDO output pin and compared against the
expected data.
Programming a pattern into the device requires the following six ISP
stage s. A stand-alon e verifica tion of a progra mmed patte rn involves only
stages 1, 2, 5, and 6.
1. Enter ISP. The enter ISP stage ensures that the I/O pins transition
smoothly from user mode to ISP mode. The enter ISP stage requires
1ms.
2. Check ID. Before any program or verify process, the silicon ID is
checked. The time required to read this silicon ID is relatively small
compar e d to the overall programmin g time.
3. Bulk Eras e. Erasing the device in-system involves shifting in the
instructions to erase the devi ce an d applying one er ase pulse of
100 ms.
4. Program. Programming the device in-system involves shifting in the
address and data and then applying the programming pu l se to
program the EEPROM cells. This process is repeated for each
EEPROM address.
5. Verify. Verifying an Altera device in-system involves shifting in
addresses, applying the read pulse to verify the EEPROM cells, and
shifting out the data for comparison. This process is repeated for
each EEPROM address.
6. Exit ISP. An exit ISP stage ensures that the I/O pins transition
smoothly from ISP mode to user mode. The exit ISP stage requires
1ms.
Progra mming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
■A pulse time to erase, program, or read the EEPROM cells.
■A shifting time based on the test clock (TCK) frequency and the
number of TCK cyc les to shift instr ucti ons, addr ess, an d data into th e
device.
Altera Corporation 21
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
By combining the pulse and shift times for each of the programming
stage s, the program or verify time can be derived as a function of the TCK
frequency, the n umber of devic e s, and sp ecif ic target de vi ce(s). B ecause
different ISP-ca pable devices have a different numbe r of EEPROM cells,
bot h the to tal fixed and tota l varia ble t imes are uniqu e for a single devic e.
Programming a Single MAX 9000 Device
The time required to progr am a single MAX 9000 devic e in-system can be
calculated from the following formula:
where: tPROG = Programming time
tPPULSE = Sum of the fixed times to erase, program, and
verify the EEPROM cells
CyclePTCK =Number of TCK cycles to program a device
fTCK =TCK frequency
The ISP times for a stand-alone verification of a single MAX 9000 device
can be calculated from the following formula:
where: tVER =Verify time
tVPULSE = Sum of the fixed times to verify the EEPROM cells
CycleVTCK =Number of TCK cycles to verify a device
t
PROG tPPULSE
Cycle
PTC
K
fTCK
-----------------------------
---
+=
t
VER tVPULSE
Cycle
VTC
K
fTCK
-----------------------------
---
+=
22 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
The programming times described in Tables 7 through 9 are associated
with the worst-case method using the ISP algorithm.
Tables 8 and 9 show the in-system programming and stand alone
verification times for several common test clock frequencies.
Table 7. MAX 9000 tPULSE & CycleTCK Values
Device Programming Stand-Alone Verific ation
tPPULSE (s) CyclePTCK tVPULSE (s) CycleVTCK
EPM9320
EPM9320A 11.79 2,966,000 0.15 1,806,000
EPM9400 12.00 3,365,000 0.15 2,090,000
EPM9480 12.21 3,764,000 0.15 2,374,000
EPM9560
EPM9560A 12.42 4,164,000 0.15 2,658,000
Table 8. MAX 9000 In-System Programming Times for Different Test Clock Frequencies
Device fTCK Units
10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz
EPM9320
EPM9320A 12.09 12.38 13.27 14.76 17.72 26.62 41.45 71.11 s
EPM9400 12.34 12.67 13.68 15.37 18.73 28.83 45.65 79.30 s
EPM9480 12.59 12.96 14.09 15.98 19.74 31.03 49.85 87.49 s
EPM9560
EPM9560A 12.84 13.26 14.50 16.59 20.75 33.24 54.06 95.70 s
Table 9. MAX 9 000 Stan d-Al one Verification T i mes f or Differ ent Test Clock Frequencies
Device fTCK Units
10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz
EPM9320
EPM9320A 0.33 0.52 1.06 1.96 3.77 9.18 18.21 36.27 s
EPM9400 0.36 0.57 1.20 2.24 4.33 10.60 21.05 41.95 s
EPM9480 0.39 0.63 1.34 2.53 4.90 12.02 23.89 47.63 s
EPM9560
EPM9560A 0.42 0.69 1.48 2.81 5.47 13.44 26.73 53.31 s
Altera Corporation 23
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Programming
with External
Hardware
MAX 9000 devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card , th e Master Programmin g U nit (MPU),
and the appropr iate devi ce ad apt er . Th e MPU pe rfo r ms continuity
checking to ensure ade qua te el ectrical conta ct be tween the adapter and
the device.
fFor more informati on, see the Altera Programming Hardware Data Sheet.
The MAX+PLUS II software can u se text- or waveform-format test vectors
created with the MAX+PLUS II Text Editor or Waveform Editor to test a
program m ed device. For added desi gn verification, designers c an
perform functional testing to compare the functional behavior of a
MAX 9000 device with the results of simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers also provi de pro gra mmi n g support for Altera devices.
fFor more informati on, see Programmi n g Hardware M anufactu rers.
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
MAX 9000 devices suppor t JTAG BST circuitry as sp ec ified by IE EE S td.
1149.1-1990. Table 10 describes the JTAG instructions supported by the
MAX 9000 family. The pin-out tables starting on page 38 show the
location of the JTAG control pins for each device. If the JTAG interface is
not required, the JTAG pins are available as user I/O pins.
Table 10. M AX 9000 JTAG Instructions
JTAG Instructio n Description
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during
normal devic e operation, and permits an init ial dat a pat te rn out put at the dev ic e pins .
EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a test
pattern at the out put pins and c apt uring test resu lts at the inp ut pin s.
BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation.
IDC OD E Select s the IDC OD E register and plac es it betw een TDI and TDO, allo wi ng th e IDC OD E
to be shifted out of TDO. Sup port ed by th e EPM9320A, EPM 9400, EPM 9480, and
EPM956 0A dev ic es only.
UE SC OD E Selects the us er elec t ronic s ignat ure (UESC OD E) regis t er and allows the U ESC OD E t o
be shifted ou t of TDO se rially . This ins tr uc tion is supported by MAX 9000A de vices only .
ISP Instructions These instructions are used when programming MAX 9000 devices via the JTAG ports
with the BitBlas t er or By te Blas t erM V dow nload cable, or us ing a Ja m File (.jam), Jam
Byte-Co de Fi le (.jbc), or Serial Vector Format (.svf) File via an embedded processor or
test equipment.
24 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
The instruction register length for MAX 9000 devices is 10 bits. EPM9320A
and EPM9560A devices support a 16-bit UESCODE register. Tables 11
and 12 show the bo undary-scan register leng th and device IDCOD E
information for MAX 9000 devices.
Notes:
(1) The IDCOD E ’s le ast signi fican t bi t (LS B) is alw ay s 1.
(2) The most sign ifi can t bit (MSB ) is on the left.
(3) Although the EPM9320A and EPM9560A devices support the IDCODE instruction,
the EPM9320 and E PM9560 devices d o n ot.
Figure 11 shows the timing r equirements for the JTAG sig nals.
Table 11. MAX 9000 Boundary-Scan Register Length
Device Boundary-Scan Register Length
EPM9320, EPM9320A 504
EPM9400 552
EPM9480 600
EPM9560, EPM9560A 648
Table 12. 32-Bit MAX 9000 Device IDCODE Note (1)
Device IDCODE (32 Bit s)
Version
(4 Bits) Part Number
(16 Bits) (2) Manufacturer’s
Identity (11 Bits) 1
(1 Bit)
EPM9320A (3) 0000 1001 0011 0010 0000 00001101110 1
EPM9400 0000 1001 0100 0000 0000 00001101110 1
EPM9480 0000 1001 0100 1000 0000 00001101110 1
EPM9560A (3) 0000 1001 0101 0110 0000 00001101110 1
Altera Corporation 25
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Figure 11. MAX 9000 JTAG Waveforms
Table 13 shows the JTAG timing parameters and values for MAX 9000
devices.
fFor detailed information on JTAG operation in MAX 9000 devices, refer to
Application Note 39 (IEEE 114 9.1 (JTAG) Boundar y-S can Testing in Altera
Devices).
Table 13. JTAG Timing Parameters & Values for M A X 9000 Devi ces
Symbol Parameter Min Max Unit
tJCP TCK clock period 100 ns
tJCH TCK clo ck high t im e 50 ns
tJCL TCK clock low time 50 ns
tJPSU JTAG port se tu p time 20 ns
tJPH JTAG port hold time 45 ns
tJPCO JTAG port clo ck to outp ut 25 ns
tJPZX JTAG port high impedanc e t o val id out put 25 ns
tJPXZ JTAG port va lid out put to hig h im pedance 25 ns
tJSSU Capture register setup time 20 ns
tJSH Capture register hold time 45 ns
tJSCO Update register clock to output 25 ns
tJSZX Update register high impedance to valid output 25 ns
tJSXZ Update register valid output to high impedance 25 ns
TDO
TCK
tJPZX tJPCO
tJPH
tJPXZ
tJCP
tJPSU
tJCL
tJCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
tJSZX
tJSSU tJSH
tJSCO tJSXZ
26 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
Programmable
Speed/Power
Control
MAX 9000 device s offe r a power-sav ing mod e that supports low-pow er
operation across user-defined signal paths or the entire device. Because
most logic app lications require only a small fraction of all gates to ope rate
at maximum frequency, this feature allows total power dissipation to be
reduced by 50% or more.
The designer can program each individual macrocell in a MAX 9000
device for either high-speed (i.e., with the Turbo Bit™ option t urned on) or
low-power (i.e., with the Turbo Bit option turned off) operation. As a
result, speed-critical paths in the design can run at high speed, while
remaining paths operate at reduced power. Macrocells that run at low
power incur a nominal timing delay adder (tLPA) for the LAB l ocal array
delay (tLOCAL).
Design Security All MAX 9000 EPLDs contain a programmable security bit that controls
access to the data programmed into the device. When this bit is
programmed, a pr opr ietary design implem ente d in the device cannot be
copied or retrieved. This feature provides a high level of design security,
becau se progr ammed data wit hin EEPROM cells is invisible . The secur ity
bit that controls this function, as well as all other programmed data, is
reset only when the devi ce is erased.
Generic Testing MAX 9000 EPLDs are fully function ally test ed. Comp lete te stin g of each
programmable EEPROM bit and all logic functionality ensures 100%
pr ogra mmi ng yield . AC test me as urem e nts are tak en unde r condit ions
equivalent to those shown in Figure 12. Te st patt erns c an be used and t hen
erased during the early stages of the production flow.
Figure 12. MAX 9000 AC Test Conditions
VCC
To Test
System
C1 (includes
JIG capacitance
)
Device input
rise and fall
times < 3 ns
Device
Output
464 Ω
(703 Ω)
250 Ω
(8.06 KΩ)
Power supply transients can affect AC
measurements. Simultaneous transitions of
multi ple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast gr ound-
current transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
thro ugh the paras itic inductance between
the dev ice ground pi n and the test system
ground, significant reductions in
obser vab le noise imm unit y can result.
Numb ers in parentheses are for 3.3-V
outpu ts. Numbers wit hou t parentheses are
for 5.0-V devices or outp uts.
Altera Corporation 27
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Operating
Conditions
Tables 14 through 20 provid e i nformat ion on absol ute maximum r ating s,
recommended operating conditions, operating conditions, and
capac ita nce for MAX 9000 devices .
Table 14. MAX 9000 Device Absolute Maximum Ratings Note (1)
Symbol Parameter Conditions Min Max Unit
VCC Supply voltage With respect to ground (2) –2.0 7.0 V
VIDC input voltage
–2.0 7.0 V
VCCISP Supply voltage during in-system
programming –2.0 7.0 V
IOUT DC output current, per pin –25 25 mA
TSTG S torage temperature No bias –65 150 ° C
TAMB A mbient temperature Under bias –65 135 ° C
TJJunction temperature Ceram ic packages, under bias 150 ° C
PQFP and RQFP package s, under bias 135 ° C
Table 15. MAX 9000 Device Recommended Operating Conditions
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage for internal logic and
input buffers (3), (4) 4.75
(4.50) 5.25
(5.50) V
VCCIO Supply voltage for output drivers,
5.0-V operation (3), (4) 4.75
(4.50) 5.25
(5.50) V
Supply voltage for output drivers,
3.3-V operation (3), (4) 3.00
(3.00) 3.60
(3.60) V
VCCISP Supply voltage during in-system
programming 4.75 5.25 V
VIInput voltage –0.5 VCCINT +
0.5 V
VOOutput voltage 0V
CCIO V
TAAmbient temperature For commercial use 0 70 ° C
For industrial use –40 85 ° C
TJJunction temperature For commercial use 0 90 ° C
For industrial use –40 105 ° C
tRInput rise time 40 ns
tFInput fall time 40 ns
28 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
Table 16. MAX 9000 Device DC Operating Conditions Notes (5), (6)
Symbol Parameter Conditions Min Max Unit
VIH High-level input voltage (7) 2.0 VCCINT +
0.5 V
VIL Low-level input voltage –0.5 0.8 V
VOH 5.0-V high-level TTL output voltage IOH = –4 mA DC, VCCIO = 4.75 V (8) 2.4 V
3.3-V high-level TTL output voltage IOH = –4 mA DC, VCCIO = 3.00 V (8) 2.4 V
3.3-V high-level CMOS output voltage IOH = –0.1 mA DC, VCCIO = 3.00 V (8) VCCIO –
0.2 V
VOL 5.0-V low level TTL output voltage IOL = 12 m A DC, V CCIO = 4.75 V (8) 0.45 V
3.3-V low-level TTL out put voltage IOL = 12 mA DC, V CCIO = 3.00 V (8) 0.45 V
3.3-V low-level CMOS output voltage IOL = 0.1 mA DC, VCCIO = 3.00 V (8) 0.2 V
III/O pin leakage current of dedicated input
pins VI = –0.5 to 5.5 V (9) –10 10 µA
IOZ Tri-state output off-state current VI = –0.5 to 5.5 V –40 40 µA
Tabl e 17. MAX 9000 Device C apacita nce: EP M9320, EPM94 00, EPM9 480 & E PM9560 Devices Note (10)
Symbol Parameter Conditions Min Max Unit
CDIN1 Dedicated input capacitance VIN = 0 V, f = 1.0 MH z 18 pF
CDIN2 Dedicated input capacitance VIN = 0 V, f = 1.0 MH z 18 pF
CDIN3 Dedicated input capacitance VIN = 0 V, f = 1.0 MH z 17 pF
CDIN4 Dedicated input capacitance VIN = 0 V, f = 1.0 MH z 20 pF
CI/O I/O pin capacitance VIN = 0 V, f = 1.0 M Hz 12 pF
Table 18. MAX 9000A Device Capacitance: EPM9320A & EPM9560A Devices Note (10)
Symbol Parameter Conditions Min Max Unit
CDIN1 Dedicated input capacitance VIN = 0 V, f = 1.0 MH z 16 pF
CDIN2 Dedicated input capacitance VIN = 0 V, f = 1.0 MH z 10 pF
CDIN3 Dedicated input capacitance VIN = 0 V, f = 1.0 MH z 10 pF
CDIN4 Dedicated input capacitance VIN = 0 V, f = 1.0 MH z 12 pF
CI/O I/O pin capacitance VIN = 0 V, f = 1.0 M Hz 8 p F
Table 19. MAX 9000 Device Typical ICC Supply Current Values
Symbol Parameter Conditions EPM9320 EPM9400 EPM9480 EPM9560 Unit
ICC1 ICC supply current (low-power mode,
standby, typical) VI = ground,
no load (11) 106 132 140 146 mA
Altera Corporation 29
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input on I/O pins is –0.5 V and on the four dedicated input pins is –0.3 V. During transitions, the
inputs may undershoot to –2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.
(3) VCC must rise monotonically.
(4) Numbers in parenthes es are for industri al-t e mperatur e-ra nge devices.
(5 ) T ypical values ar e f or TA = 25° C and VCC = 5.0 V.
(6) These values are specified under the MAX 9000 recommended operating conditions, shown in Table 15 on page 27.
(7) During in-s y s te m p rogram min g, t he minimum VIH of the JTAG TCK pin is 3.6 V. Th e mi n imum VIH of this pin
during JTA G testing rema in s at 2.0 V. To atta in this 3.6-V VIH during programming, the ByteBlaster and
ByteBlast e rMV downl oad cables must have a 5.0-V V CC.
(8) This para meter is measured with 50% of the outputs each sinking 12 mA. The IOH parameter refers to high-level
TTL or CMOS output current; the IOL parameter refers to the low-level TTL or CMOS output current.
(9) JTAG pin input leakage is typically –60 µΑ.
(10) Capacitanc e is sample- te st ed on ly an d is measured at 25° C.
(11 ) Meas ure d wit h a 1 6- bit lo adable, enabled, up / d own cou nt er progra mmed in t o ea c h L A B . ICC is me as ured at 0° C.
Figure 13 shows typic al outpu t drive characteristics for MAX 9000 devices
with 5.0-V and 3.3-V VCCIO.
Figure 13. Output Drive Characteristics of MAX 9000 Devices Note (1)
Note:
(1) Output drive c ha racte r ist ic s in c lude the JTAG TDO pin.
Table 20. MAX 90 00A Device Typical ICC Supply Current Val ues
Symbol Parameter Conditions EPM9320A EPM9560A Unit
ICC1 ICC supply current (low-power mode,
standby, typical) VI = ground, no load (11) 99 174 mA
12345
30
60
90
150
120
V
CCIO
= 5.0 V
IOL
IOH
Room Temperature
12345
30
60
90
150
120
V
CCIO
= 3.3 V
IOL
IOH
Room Temperature
3.3
T
ypical I
O
utput
C
urrent (mA)
Output Voltage (V) Output Voltage (V)
OTypical I
Output
Current (mA)
O
5.0-V 3.3-V
30 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
T i mi ng Model The continuous, high-performance FastTrack Interconnect ensures
predictable performance and accurate simulation and timing analysis.
This predictable performance contrasts with that of FPGAs, which use a
seg mented conn ect ion scheme and hen ce have unpr e di cta b le
performance. Timing simulation and delay prediction are available with
the MAX+PLUS II Simulator and Timing Analyzer, or with industry-
standard EDA tools. The Simulator offers both pre-synthesis functional
simulation to evaluate logic design accuracy and post-synthesis timing
simulation with 0.1-ns resolution. The Timing Analyzer provides point-
to-point timing delay information, setup and hold time prediction, and
device-wide performance analysis.
The MAX 9000 timing model in Figure 14 shows the delays that
correspond to various paths and functions in the circuit. This model
contains three distinct parts: the macrocell, IOC, and interconnect,
including the row and column FastTrack Interconnect and LAB local array
paths. Each parameter shown in Figure 14 is expressed as a worst-case
value in the internal t im ing cha r ac ter is tic s tables in this d ata sh ee t. H an d -
calculations that use the MAX 9000 timing model and these timing
parameters can be used to estimate MAX 9000 device performance.
fFor more information on calculating MAX 9000 timing delays, see
Application Note 77 (Understanding MAX 9000 Timing).
Altera Corporation 31
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Fig ure 14. MAX 9000 Timing Model
Macrocell
tRD
tCOMB
tSU
tH
tPRE
tCLR
Macrocell/
Register
Delays
Logic Array
Delay
tLAD
Register
Control Delay
Shared Expander
Delay
tSEXP
Global Input
Delays
I/O Pi
n
tINREG
tIODR
tIODC
I/O Register
Delays
Output Data
Delay
I/O Cell
Control Delay
Input
Delay
Output
Delays
tIORD
tIOCOMB
tIOSU
tIOH
tIOCLR
tOD1
tOD2
tOD3
tXZ
tZX1
tZX2
tZX3
IOC
tCOL
tROW
tLOCAL
Parallel Expander
Delay
tPEXP
tDIN_D
tDIN_CLK
tDIN_CLR
tDIN_IO
tDIN_IOC
FastTrack
Drive Delay
tINCOMB
I/O Register
Feedback Delay
tIOFD
tLAC
tIC
tEN
tFTD
tIOC
32 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
Tables 21 through 24 sho w ti ming for MAX 9 000 devices.
Table 21. MAX 90 00 Ex t ernal Timing Character istics Note (1)
Symbol Par amet er Conditions Speed Gr ade Uni t
-10 -15 -20
Min Max Min Max Min Max
tPD1 Row I/O pin input to row I/O
pin output C1 = 35 pF (2) 10.0 15.0 20.0 ns
tPD2 Column I/O pin inpu t to
column I/O pin output C1 = 35 pF
(2) EPM9320A 10.8 ns
EPM9320 16.0 23.0 ns
EPM9400 16.2 23.2 ns
EPM9480 16.4 23.4 ns
EPM9560A 11.4 ns
EPM9560 16.6 23.6 ns
tFSU Global clock setup time for I/O
cell 3.0 5.0 6.0 ns
tFH Global clock hold time for I/O
cell 0.0 0.0 0.0 ns
tFCO Global clock to I/O cell output
delay C1 = 35 pF 1.0 (3) 4.8 1.0 (3) 7.0 1.0 (3) 8.5 ns
tCNT Minimum internal global clock
period (4) 6.9 8.5 10.0 ns
fCNT Maximum internal global clock
frequency (4) 144.9 117.6 100.0 MHz
Altera Corporation 33
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Table 22. MAX 9000 Internal Timing Characteristics No te (1)
Symbol Parameter Conditions Speed Grade Unit
-10 -15 -20
Min Max Min Max Min Max
tLAD Logic array delay 3.5 4.0 4.5 ns
tLAC Logic control array delay 3.5 4.0 4.5 ns
tIC Array clock delay 3.5 4.0 4.5 ns
tEN Register enable time 3.5 4.0 4.5 ns
tSEXP Shared expander delay 3.5 5.0 7.5 ns
tPEXP Parallel expander delay 0.5 1.0 2.0 ns
tRD Register delay 0.5 1.0 1.0 ns
tCOMB Combinatorial delay 0.4 1.0 1.0 ns
tSU Register setup time 2.4 3.0 4.0 ns
tHRegister hold time 2.0 3.5 4.5 ns
tPRE Register preset time 3.5 4.0 4.5 ns
tCLR Register clear time 3.7 4.0 4.5 ns
tFTD FastTrack drive delay 0.5 1.0 2.0 ns
tLPA Low-power adder (5) 10.0 15.0 20.0 ns
34 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
Table 23. IO C Del ays
Symbol Parameter Conditions Speed Grade Unit
-10 -15 -20
MinMaxMinMaxMinMax
tIODR I/O row output data delay 0.2 0.2 1.5 ns
tIODC I/O column output data delay 0.4 0.2 1.5 ns
tIOC I/O control delay (6) 0.5 1.0 2.0 ns
tIORD I/O register clock-to-output
delay 0.6 1.0 1.5 ns
tIOCOMB I/O combinatorial delay 0.2 1.0 1.5 ns
tIOSU I/O register setup time before
clock 2.0 4.0 5.0 ns
tIOH I/O register hold time after
clock 1.0 1.0 1.0 ns
tIOCLR I/O register clear delay 1.5 3.0 3.0 ns
tIOFD I/O register feedback delay 0.0 0.0 0.5 ns
tINREG I/O input pad and buffer to I/O
register delay 3.5 4.5 5.5 ns
tINCOMB I/O input pad and buffer to row
and column delay 1.5 2.0 2.5 ns
tOD1 Output buffer and pad delay,
Slow slew r ate = off,
VCCIO = 5.0 V
C1 = 35 pF 1.8 2.5 2.5 ns
tOD2 Output buffer and pad delay,
Slow slew r ate = off,
VCCIO = 3.3 V
C1 = 35 pF 2.3 3.5 3.5 ns
tOD3 Output buffer and pad delay,
Slow slew rate = on,
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF 8.3 10.0 10.5 ns
tXZ Output buffer disa ble delay C1 = 5 pF 2.5 2.5 2.5 ns
tZX1 Output buffer enable delay,
Slow slew r ate = off,
VCCIO = 5.0 V
C1 = 35 pF 2.5 2.5 2.5 ns
tZX2 Output buffer enable delay,
Slow slew r ate = off,
VCCIO = 3.3 V
C1 = 35 pF 3.0 3.5 3.5 ns
tZX3 Output buffer enable delay,
Slow slew rate = on,
VCCIO = 3.3 V or 5.0 V
C1 = 35 pF 9.0 10.0 10.5 ns
Altera Corporation 35
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Notes to tables:
(1) These values are specified under the MAX 9000 device recommended operating conditions, shown in Table 15 on
page 27.
(2) See Appli ca tio n Note 77 (Un der s tandi n g MAX 9000 T i ming) for more information on test conditions for tPD1 and tPD2
delays.
(3) This parameter is a guideline that is sample-tested only. It is based on extensive device characterization. This
parameter applies for both global and array clocking as well as both macrocell and I/O cell registers.
(4) Me as ure d wit h a 16-b it loadable, enabled, up/do wn c ounter pro gr ammed in each LAB .
(5) The tLPA parameter must be added to the tLOCAL parameter for macrocells running in low-power mode.
(6) The tROW , tCOL, and tIOC d e lays ar e wors t-cas e v alue s fo r typical app licat io n s . Pos t - c omp ilatio n t iming s imu lat ion
or timing analysis is required to determine actual worst-case performance.
Power
Consumption
The supply power (P) versus fr equency (fMAX) for MAX 9000 devices can
be calculated with the following equation:
P = PINT + PIO = ICCINT × VCC + PIO
The P IO value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
Application Note 74 (Evaluating Power for Altera Devices). The ICCINT valu e
depends on the switching frequency and the application logic.
The ICCINT value is calculated with the following equation:
ICCINT = (A × MCTON) + [B × (MCDEV – MCTON)] + (C × MCUSED
× fMAX × togLC)
Table 24. Int er con nect Delays
Symbol Parameter Conditions Speed Grade Unit
-10 -15 -20
MinMaxMinMaxMinMax
tLOCAL LAB local array delay 0.5 0.5 0.5 ns
tROW FastTrack row dela y (6) 0.9 1.4 2.0 ns
tCOL FastTrack column de lay (6) 0.9 1.7 3.0 ns
tDIN_D Dedicated input data delay 4.0 4.5 5.0 ns
tDIN_CLK Dedicated input clock delay 2.7 3.5 4.0 ns
tDIN_CLR Dedicated input clear delay 4.5 5.0 5.5 ns
tDIN_IOC Dedicated input I/O register
clock delay 2.5 3.5 4.5 ns
tDIN_IO Dedicated input I/O register
control delay 5.5 6.0 6.5 ns
36 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
The parameters in this equation are shown below:
MCTON = Number of macrocells with the Turbo Bit option turned on,
as reported in the MAX+PLUS II Report File (.rpt)
MCDEV = Number of macrocells in the device
MCUSED = Number of macrocells used in the design, as reported in the
MAX+PLUS II Re port File
fMAX = Highest clock frequency to the device
togLC = Average percentage of logic cells toggling at each clock
(typically 12.5%)
A, B, C = Constants, shown in Table 25
This calculation provides an ICC estimate based on typical conditions with
no output load, using a typical pattern of a 16-bit, loadable, enabled
up/down counter in each LAB. Actual ICC values should be verified
during operation, because the measurement is sensitive to the actual
pattern in the device and the environmental operating conditions.
Figure 15 shows typical supply current versus frequency for MAX 9000
devices.
Table 25 . MAX 9000 ICC Equatio n Con st a nt s
Devi ce Constant A Constant B Const ant C
EPM9320 0.81 0.33 0.056
EPM9320A 0.56 0.31 0.024
EPM9400 0.60 0.33 0.053
EPM9480 0.68 0.29 0.064
EPM9560 0.68 0.26 0.052
EPM9560A 0.56 0.31 0.024
Altera Corporation 37
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Figure 15. I CC vs. Frequency for MAX 900 0 D evice s (P art 1 of 2)
0
Frequency (MHz)
1000
200
400
600
800
50 75 100 12525
EPM9320
118 MHz
Turbo
Frequency (MHz)
0
1000
200
400
600
800
50 75 100 12525
EPM9320A
144 MH
z
Turbo
59 MHz
42 MHz
Non-Turbo
Non-Turbo
Typical
ICC Active
(mA)
Typical
ICC Active
(mA)
0
Frequency (MHz)
42 MHz 42 MHz
1000
200
400
600
800
50 75 100 12525
EPM9400
118 MHz
Turbo
0
Frequency (MHz)
1000
200
400
600
800
50 75 100 12525
EPM9480
118 MHz
Turbo
Non-Turbo
Non-Turbo
Typical
ICC Active
(mA)
Typical
ICC Active
(mA)
38 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
Figu re 15. ICC vs. Frequency for MAX 9000 Devices (Part 2 of 2)
Device
Pin-Outs
Tables 26 through 29 show the dedicated pin names and numbers for each
EPM9320, EPM 9320A, EPM9 400, E PM9480, EPM 9560, and EP M 9560A
device package.
0
Frequency (MHz)
42 MHz 59 MHz
1000
200
400
600
800
50 75 100 12525
EPM9560
118 MHz
Turbo
0
Frequency (MHz)
1000
200
400
600
800
50 75 100 12525
EPM9560A
144 MHz
Turbo
Non-Turbo
Non-Turbo
Typical
ICC Active
(mA)
Typical
ICC Active
(mA)
Table 26. EPM9320 & EPM9320A Dedicated Pin-Outs (Part 1 of 2) Note (1)
Pin Name 84-Pin PLCC (2) 208-Pin RQFP 280-Pin PGA (3) 356-Pin BGA
DIN1
(GCLK1)1 182 V10 AD13
DIN2
(GCLK2)84 183 U10 AF14
DIN3 (GCLR) 13 153 V17 AD1
DIN4 (GOE)72 4 W2 AC24
TCK 43 78 A9 A18
TMS 55 49 D6 E23
TDI 42 79 C11 A13
TDO 30 108 A18 D3
Altera Corporation 39
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
GND 6, 18, 24, 25, 48,
61, 67, 70 14, 20, 24, 31, 35,
41, 42 , 43, 44, 46,
47, 66 , 85, 102,
110, 113, 114, 115,
116, 118, 121, 122,
132, 133, 143, 152,
170, 189, 206
D4, D5, D16, E4, E5, E6,
E15, E16, F5, F15, G5,
G15, H5, H15, J5, J15, K5,
K15, L5, L15, M5, M15, N5,
N15, P4, P5, P15, P16, R4,
R5, R15, R 16, T4, T5 , T16
A9, A22, A25, A26, B25,
B26, D2 , E1, E26, F2 , G1 ,
G25, G26, H2, J1, J25, J26,
K2, L26, M26, N1, N25,
P 2 6 , R2 , T1, U2, U26, V 1,
V25, W25, Y26, AA2, AB1,
AB26, AC26, AE1, AF1,
AF2 , AF4, AF 7, AF20
VCCINT
(5.0 V only) 14, 21, 28, 57 ,
64, 71 10, 19, 30, 45, 112,
128, 139, 148 D15, E8, E10, E12, E14,
R7, R9, R11, R13, R14,
T14
D26, F1, H1, K26 , N26, P1,
U1, W 26, AE26, AF25,
AF26
VCCIO
(3.3 or 5.0 V) 15, 37, 60, 79 5, 25, 36, 55, 72 ,
91, 11 1, 12 7, 13 8,
159, 176, 195
D14, E7, E9, E11, E13, R6,
R8, R10, R12, T13, T15 A1, A2, A21, B1, B10, B24,
D1, H26, K1, M25, R1, V26,
AA1, AC 25, AF5 , AF8,
AF19
No Connec t
(N.C.) 29 6, 7, 8, 9, 11, 12,
13, 15 , 16, 17, 18,
109, 140, 141, 142,
144, 145, 146, 147,
149, 150, 151
B6, K19, L2, L4, L18, L19,
M1, M2, M3, M4, M16, M17,
M18, M19, N1, N2, N3, N4 ,
N16, N17 , N18, N1 9, P1 ,
P2, P3, P17, P18, P19, R1,
R2, R3, R17, R18, R19, T 1,
T2, T3, T17, T18, T19, U1,
U2, U3, U17, U18, U19, V1,
V2, V19, W 1
B4, B5, B6, B7, B8, B9,
B11, B12, B13, B14, B15,
B16, B18, B19, B20, B21,
B22, B23, C4 , C23, D4,
D23, E4, E 22, F4 , F23, G4,
H4, H 23, J23 , K4, L4, L23,
N4, P4, P23, R3 , R26, T2 ,
T3, T4, T5, T22, T23, T24,
T25, T26, U3, U4, U5, U22,
U23, U24, U25, V2, V3, V4,
V5, V22, V23, V24, W1,
W2, W3, W4, W5, W22,
W23, W24, Y1, Y2, Y3, Y4,
Y5, Y22, Y23, Y24, Y25,
AA3, AA4, AA5, AA22,
AA23, AA24, AA25, AA26,
AB2, AB3, AB4, AB5,
AB23, AB24, AB25, AC 1,
AC 2, AC23, AD4, AD 23,
AE4, AE5, AE6, AE7, AE9,
AE11, AE12, AE14, AE15,
AE16, AE18, AE19, AE20,
AE21, AE22, AE23
VPP (4) 56 48 C4 E25
Total User
I/O Pins (5) 60 132 168 168
Table 26. EPM9320 & EPM9320A Dedicated Pin-Outs (Part 2 of 2) Note (1)
Pin Nam e 84-Pin PLCC (2) 208-Pin RQFP 280-Pin PGA (3) 356-Pin BGA
40 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
Notes:
(1) All pins no t li st ed ar e user I/O pins.
(2) Perform a complete thermal analysis before committing a design to this device package. See Application Note 74
(Ev al uati ng Powe r f o r Altera De vices).
(3) EPM9320A devices are not offered in this package.
(4) During in-system programming, each device’s VPP pin must be connected to the 5.0-V power supply. During
normal de v ice op er at ion, th e VPP pin is pulle d up inte rn ally a n d can be co nn ecte d to th e 5. 0 -V sup ply or left
unconnected.
(5) The user I/O pin count includes dedicated input pins and all I/O pins.
Notes:
(1) All pins no t li st ed ar e user I/O pins.
(2) Perform a complete thermal analysis before committing a design to this device package. See Application Note 74
(Ev al uati ng Powe r f o r Altera De vices) for more information.
(3) During in-system programming, each device’s VPP pin must b e c o n necte d to the 5. 0 -V power s upply. Du ring
normal de v ice op er at ion, th e VPP pin is pull ed up int er nall y and ca n be co n nect ed to the 5. 0 -V su pply o r le ft
unconnected.
(4) The user I/O pin count includes dedicated input pins and all I/O pins.
Table 27. EPM9400 Dedicated Pin-Outs Note (1)
Pin Name 84-Pin PLCC (2) 208-Pin RQFP 240-Pin RQFP
DIN1 (GCLK1) 2 182 210
DIN2 (GCLK2) 1 183 211
DIN3 (GCLR) 12 153 187
DIN4 (GOE) 74 4 234
TCK 43 78 91
TMS 54 49 68
TDI 42 79 92
TDO 31 108 114
GND 6, 13, 20, 26 , 27, 47, 60,
66, 69, 73 14, 20 , 24, 31, 35, 41 , 42,
43, 44, 46, 47, 66, 85, 102,
110, 113, 114, 115, 116,
118, 121, 122, 132, 133,
143, 152, 170, 189, 206
5, 14, 25, 34, 45, 54, 65,
66, 81, 96, 110, 115, 126,
127, 146, 147, 166, 167,
186, 200, 216, 229
VCCINT (5.0 V only ) 16, 23, 30, 56, 63, 70 10, 19, 30, 45, 112, 128,
139, 148 4, 24, 44, 64, 117, 137,
157, 177
VCCIO (3.3 or 5.0 V) 17, 37, 59, 80 5, 25, 36, 55, 72, 91, 111,
127, 138, 159, 176, 195 15, 35, 55, 73, 86, 101,
116, 136, 156, 176, 192,
205, 220, 235
No Connec t (N. C.) – 6, 7, 8, 9, 11, 12, 13, 109,
144, 145, 146, 147, 149,
150, 151
1, 2, 3, 6, 7, 8, 9, 10, 11,
12, 13, 168, 169, 170,
171, 172, 173, 174, 175,
178, 179, 180, 181, 182,
183, 184, 185, 236, 237,
238, 239, 240
VPP (3) 55 48 67
Total Us e r I/O P i n s (4) 59 139 159
Altera Corporation 41
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Notes:
(1) All pins not listed are user I/O pins.
(2) During in-system programming, each device’s VPP pin must be connected to the
5.0-V power supply. During normal device operation, the VPP pin is pulled up
internally and can be connected to the 5.0-V supply or left unconnected.
(3) The user I/O pin count includes dedicated input pins and all I/O pins.
Tabl e 28 . EPM9 48 0 De di ca te d Pi n - Ou t s Note (1)
Pin Name 208-Pin RQFP 240-Pin RQFP
DIN1 (GCLK1) 182 210
DIN2 (GCLK2) 183 211
DIN3 (GCLR) 153 187
DIN4 (GOE)4 234
TCK 78 91
TMS 49 68
TDI 79 92
TDO 108 114
GND 14, 20, 24, 31, 35, 41, 42,
43, 44, 46, 47, 66, 85,
102, 110, 113, 114, 115,
116, 118, 121, 122, 132,
133, 143, 152, 170, 189,
206
5, 14, 25, 34, 45, 54, 65,
66, 81, 96, 110, 115, 126,
127, 146, 147, 166, 167,
186, 20 0, 21 6, 22 9
VCCINT (5.0 V only) 10, 19, 30, 45, 112, 128,
139, 14 8 4, 24, 44, 64, 117, 137,
157, 177
VCCIO (3.3 or 5.0 V) 5, 25, 36, 55, 72, 91, 111,
127, 13 8, 15 9, 176, 195 15, 35, 55, 73, 86, 1 01,
116, 136, 156, 176, 192,
205, 22 0, 23 5
No Connect (N.C. ) 6, 7, 8, 9, 109, 149, 150,
151 1, 2, 3, 178, 179, 180,
181, 182, 183, 184, 185,
236, 237, 238, 239, 240
VPP (2) 48 67
Total User I/O Pins (3) 146 175
42 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
Table 29. EPM9560 & EPM9560A Dedicated Pin-Outs (Part 1 of 2) Note (1)
Pin N ame 208-Pin RQFP 240 -Pi n R Q FP 280-Pin PGA (2) 304-Pi n R QF P (2) 35 6-Pi n BGA
DIN1
(GCLK1)182 210 V10 266 AD13
DIN2
(GCLK2)183 211 U10 267 AF14
DIN3 (GCLR) 153 187 V17 237 AD1
DIN4 (GOE) 4 234 W2 296 AC24
TCK 78 91 A9 114 A18
TMS 49 68 D6 85 E23
TDI 79 92 C11 115 A13
TDO 108 114 A18 144 D3
GND 14, 20, 24, 31, 35,
41, 42, 43, 44, 46,
47, 66, 85, 102,
110, 113 , 114 ,
115, 116 , 118 ,
121, 122 , 132 ,
133, 143 , 152 ,
170, 189 , 206
5, 14, 25, 34, 45,
54, 65, 66, 81, 96,
110, 115, 126,
127, 146, 147,
166, 167, 186,
200, 216, 229
D4, D5, D16, E4,
E5, E6, E15, E16,
F5, F15, G5, G15,
H5, H15, J5, J15,
K5, K15, L5, L15,
M5, M15, N5,
N15, P4, P5, P15,
P16, R4, R5, R15,
R16, T4, T5, T1 6
13, 22, 33, 42, 53,
62, 73, 74, 102,
121, 13 8, 15 5,
166, 16 7, 18 6,
187, 20 6, 20 7,
226, 25 4, 27 3,
290
A9, A22, A25,
A26, B25 , B26 ,
D2 , E 1, E 2 6, F 2 ,
G1, G25, G26,
H2, J1, J25, J26,
K2, L26, M26, N1,
N25, P26, R2, T1,
U2, U26, V1, V25,
W25, Y26, AA2,
AB1, AB2 6,
AC26, AE1, AF 1,
AF2, AF4, AF7,
AF20
VCCINT
(5.0 V only) 10, 19, 30, 45,
112, 128 , 139 ,
148
4, 24, 44, 64, 117,
137, 157, 177 D15 , E8, E10,
E12, E14, R7, R9,
R11, R13, R14,
T14
12, 32, 52, 72,
157, 17 7, 19 7,
217
D26, F1, H1, K26,
N26, P1, U1 ,
W26, AE26,
AF25, AF 26
VCCIO
(3.3 or 5. 0 V) 5, 25, 36, 55, 72,
91, 111, 127, 138,
159, 176 , 195
15, 35, 55, 73, 86,
101, 116, 136,
156, 176, 192,
205, 220, 235
D14, E7, E9, E11,
E13, R6, R8, R10,
R12 , T13, T15
3, 23, 43, 63 , 91,
108, 12 7, 15 6,
176, 19 6, 21 6,
243, 26 0, 27 9
A1, A2, A21 , B1,
B10, B24 , D1,
H26, K1, M25,
R1, V26, AA1,
AC25, AF 5, AF8 ,
AF19
Altera Corporation 43
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Notes:
(1) Al l pins not listed are user I/O pins.
(2) EPM95 60A d evi c es ar e n ot offer ed in this pa ckag e.
(3) During in-system programming, each device’s VPP pin must be connected to the 5.0-V power supply. During
normal device operatio n, the VPP pin is pul led up int ernally and c an be con nect ed t o t he 5.0 -V supply o r left
unconnected.
(4) The user I/O pin count includes dedicated input pins and all I/O pins.
No Connec t
(N.C.) 1 09 – B6, W1 1, 2, 76, 77, 78 ,
79, 80, 81, 82, 83,
84, 145, 146, 147,
148, 149, 150,
151, 152, 153,
154, 227, 228,
229, 230, 231,
232, 233, 234,
235, 236, 297,
298, 299, 300,
301, 302, 303,
304
B4, B5 , B6, B7,
B8, B9, B11, B12,
B13, B14, B15,
B16, B18, B19,
B20, B21, B22,
B23, C4, C23, D4,
D23, E4, E22, F4,
F23, G4, H4, H23,
J23, K4, L4, L23,
N4, P4, P23, T4 ,
T23, U4, V4, V23,
W4, Y4, AA4,
AA23, AB4,
AB23, AC 23,
AD 4, AD23, AE4,
AE5, AE 6, AE 7,
AE9, AE11,
AE12, AE14,
AE15, AE16,
AE18, AE19,
AE20, AE21,
AE22, AE23
VPP (3) 48 67 C4 75 E25
Total User
I/O Pins (4) 153 191 216 216 216
Table 29. EPM9560 & EPM9560A Dedicated Pin-Outs (Part 2 of 2) Note (1)
Pin N ame 2 08-Pin RQ FP 240-Pin RQFP 280-Pin PGA (2) 304-Pin RQFP (2) 356-Pin BGA
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®
MAX 9000 Pr o grammabl e Log ic Dev ice Fam ily D ata Sh eet
44 Altera Corporation
Printed on Recycled Paper.
Revision
History
Informat ion c onta ine d in the M AX 9000 Programmabl e L og i c Device F am il y
Data Sheet versi o n 6.5 superse des inform ation pub lis hed in previous
versions.
Version 6.5
Version 6.6 of the MAX 9000 Programmable Logic Device Family Data Sheet
contains the following change:
■Added Tables 7 through 9.
■Added “Programming Sequence” on page 20 and “Programming
Time s ” on pa g e 20
Version 6.4
Version 6.4 of the MAX 9000 Programmable Logic Device Family Data Sheet
contains the following change: Updated text on page 23.
Version 6.3
Version 6.3 of the MAX 9000 Programmable Logic Device Family Data Sheet
contains the following change: added Note (7) to Table 16.
Altera Corporation 45
MAX 9000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
46 Altera Corporation
MAX 9000 Progr ammable Logic D evi ce F ami l y Da ta Sh eet
