MAX14983EETJ+ - Maxim Integrated

General Description

The MAX14983E integrates high-bandwidth analog switches,

level-translating buffers, and 5V power switches to

implement a complete 1:2 multiplexer for VGA monitors.

The device switches graphics signals between a control-

ler and two outputs. Integrated pullup resistors (2.2kΩ,

typ) are provided on the monitor-side display data channel

(DDC) signal lines.

The device features a simple power interface that

operates with a single +5V supply input. Two integrated

power switches with current limiting and reverse-current

protection pass the +5V supply to external loads with

minimal voltage drop.

The horizontal and vertical synchronization (HSYNC/

VSYNC) buffers shift logic levels to support +2.5V to

+5.0V CMOS or TTL-compatible graphics controllers

while meeting the VESA drive capability requirement of

±8mA. An internal 2.5V regulator translates the DDC

voltage levels to be compatible with low-voltage graphics

controllers.

The device also features monitor-detect outputs and

enable inputs that allow monitor switching to operate either

automatically or with inputs from the graphics controller.

The MAX14983E is available in a 32-pin (5mm x 5mm)

TQFN package, and is specified over the -40°C to +85°C

extended temperature range.

Applications

●Servers

●KVM Switches

●Computing

●Graphics Cards

Benets and Features

●Design Flexibility

• Graphics Controller Port is Protected when

VCC = 0V

• DDC Switches Limit Voltage to Low-Voltage Supply

• Internal +2.5V Regulator

●High Level of Integration for Enhanced Performance

• Low 5.5pF (typ) RGB Capacitance

• 2.0ns (typ) tR/tF with 10pF, 2.2kΩ Load on Monitor-

Side SYNC Signals

• Source and Sink 8mA While Meeting Speed

Requirements

• ±11kV Human Body Model (HBM)

●Saves Space on Board

• Internal Power Switches

• Pass +5V with 300mV (max) IR Drop

• Short-Circuit/Thermal/Reverse-Current

Protection

• 5mm x 5mm, 32-Pin TQFN Package

19-5935; Rev 1; 9/17

Ordering Information appears at end of data sheet.

R0, G0, B0 R1, G1, B1

HSYNC1, VSYNC1

SCL1, SDA1

1µF

S5V1

HSYNC0, VSYNC0

SCL0, SDA0

MDOR

MD1

MD2

EN1

EN2

GRAPHICS

CONTROLLER

VGA

PORT 1

+2.5V

+5V

R2, G2, B2

HSYNC2, VSYNC2

SCL2, SDA2

1µF

105Ω

S5V2

GND

VGA

PORT 2

REF

VCC

+5V

0.1µF

MAX14983E

MAX14983E Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

Typical Application Circuit

EVALUATION KIT AVAILABLE

(Voltages referenced to GND.)

VCC, S5V1, S5V2, SDA_, SCL_, REF, MD_,

EN_, MDOR .........................................................-0.3V to +6V

HSYNC_, VSYNC_, R_, G_, B_ .............. -0.3V to (VCC + 0.3V)

Continuous Current Through R_, G_, B_ Switches .........±50mA

Continuous Current Through SDA_, SCL_ Switches .......±50mA

Continuous Current Through S5V_ ................................ ±750mA

Peak Current Through R_, G_, B_, SDA_, SCL_

(10% duty cycle)........................................................ ±100mA

Continuous Power Dissipation (TA = +70°C)

TQFN (derate 34.5mW/°C above +70°C)...............2758.6mW

Operating Temperature Range ........................... -40°C to +85°C

Junction Temperature ...................................................... +150°C

Storage Temperature Range ............................ -65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

(Note 1)

TQFN

Junction-to-Ambient Thermal Resistance (θJA) ..........29°C/W

Junction-to-Case Thermal Resistance (θJC) ..............1.7°C/W

(VCC = +5V ±5%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +5V, TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLY

Quiescent Current IQ

VCC = 5.25V, VEN1 = VEN2 = VCC, REF

unconnected 50 150 µA

Operating Current ICC

HSYNC0 = 50kHz, VSYNC0 = 60Hz 10%

duty cycle, RL on SYNC outputs = 2kΩ, REF

unconnected

1.5 2.7 mA

5V SWITCH (S5V1, S5V2 OUTPUTS)

S5V_ Voltage Drop VS5V IOUT = 55mA 0.3 V

Reverse Leakage Current IL

VCC = 0V, VEN1 = VEN2 = 0V, VS5V1 =

VS5V2 = 5.25V, no load on S5V1 or S5V2 10 µA

Pulldown Resistor RS5V1,

RS5V2

VS5V1 = VS5V2 = 1V, VEN1 = VEN2 = VCC 250 Ω

Output Current Limit ILIM 55 300 500 mA

Thermal-Shutdown Threshold TSHDN +150 °C

Thermal-Shutdown Hysteresis TSHDN_

HYS

25 °C

MAX14983E Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

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Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Electrical Characteristics

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Package Thermal Characteristics

(VCC = +5V ±5%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +5V, TA = +25°C.) (Note 2)

Note 2: All units are production tested at TA = +25°C. Specifications over temperature are guaranteed by design.

Note 3: VPU is the pullup voltage.

Note 4: See the Pin Description section for the ESD status of each pin.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DDC SWITCHES (SDA_, SCL_ INPUTS/OUTPUTS)

Input Leakage Current ILVEN1 = VCC, VEN2 = VCC, VIN = 0V or 5.25V -1 +1 µA

Off-Leakage Current ILOFF VIN = +5.25V, VCC = 0V 10 µA

On-Resistance RON VIN = 0.8V, ISDA_ = ISCL_ = ±10V 25 Ω

SDA1, SDA2, SCL1, SCL2

Internal Pullup Resistance RPULLUP VSDA_ = VSCL_ = 4V 2.2 kΩ

CONTROL SIGNALS (HSYNC_, VSYNC_, EN_ INPUTS/OUTPUTS)

Input Logic-Low Voltage VIL HSYNC0, VSYNC0, EN1, EN2 0.8 V

Input Logic-High Voltage VIH HSYNC0, VSYNC0, EN1, EN2 2 V

Output Logic-Low Voltage VOL

HSYNC1, HSYNC2, VSYNC1, VSYNC2,

ISINK = 8mA 0.5 V

Output Logic-High Voltage VOH

HSYNC1, HSYNC2, VSYNC1, VSYNC2,

ISOURCE = 8mA 2.4 V

Rise Time/Fall Time tR, tFHSYNC0 input tR/tF < 5ns, 10% to 90% 2 ns

MONITOR DETECTION OUTPUTS (MD_, MDOR)

Output-Voltage Low VOL RPULLUP = 3.3kΩ, VPU = 3.3V (Note 3) 0.3 V

Input Leakage Current ILOD VIN = 3.3V, MD_ and MDOR deasserted 1 µA

R_, G_, B_ SWITCH PERFORMANCE

Bandwidth fMAX Figure 1, RS = RL = 50Ω 800 MHz

On-Loss ILOSS Figure 1, f = 50MHz, RS = RL = 50Ω -0.6 dB

On-Resistance RON IIN = ±10mA, VIN = 0.7V 5 8 Ω

On-Resistance Matching ΔRON IIN = ±10mA, VIN = 0 to 0.7V 1 Ω

On-Resistance Flatness RFLAT(ON) IIN = ±10mA, VIN = 0 to 0.7V 0.5 1 Ω

B1, B2 Internal Pullup Resistance RB2.5 kΩ

Off-Leakage Current ILOFF VR_ = VG_ = VB0 = 0V or VCC -1 +1 µA

Off-Capacitance COFF f = 1MHz; R0, G0, B0 to R_, G_, B_ 2.5 pF

On-Capacitance CON f = 1MHz; R0, G0, B0 to R_, G_, B_ 5.5 pF

ESD PROTECTION

High-ESD Pins ESD Protection Human Body Model (Note 4) ±11 kV

All Other Pins ESD Protection Human Body Model (Note 4) ±2 kV

MAX14983E Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

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Electrical Characteristics (continued)

(VCC = +5.0V, TA = +25°C, unless otherwise noted.)

Figure 1. On-Loss

RGB ON-RESISTANCE

vs. ANALOG SIGNAL VOLTAGE

MAX14983E toc02

VR0 (V)

0 54321

RON (Ω)

IRO = 10mA

TA = -40°C

TA = +85°C TA = +25°C

DDC ON-RESISTANCE

vs. ANALOG SIGNAL VOLTAGE

MAX14983E toc01

VSDA0 (V)

RON (Ω)

1.51.00.5

0 2.0

ISDA0 = 10mA

TA = -40°C

TA = +85°C TA = +25°C

MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.

ON-LOSS IS MEASURED BETWEEN R0 AND R1 ON EACH SWITCH.

SIGNAL DIRECTION THROUGH IS REVERSED; WORST VALUES ARE RECORDED.

+5V

0.1µF

VOUT

EN1,

EN2

R1, G1, B1

GND

VCC

R0, G0, B0

R2, G2, B2

VIN ON-LOSS = 20log VOUT

VIN

NETWORK

ANALYZER

50Ω

50Ω50Ω

50Ω

MEAS REF

0V OR VCC

50I

MAX14983E

MAX14983E Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

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Typical Operating Characteristics

(VCC = +5.0V, TA = +25°C, unless otherwise noted.)

HSYNC_/ VSYNC_ OUTPUT VOLTAGE

vs. TEMPERATURE

MAX14983E toc04

TEMPERATURE (°C)

VOH / VOL (V)

-40 85

6035-10-15

ISOURCE /ISINK = 8mA

VOL

VOH

100E+610E+61E+6100E+3 1E+9

FREQUENCY RESPONSE

MAX14983E toc03

FREQUENCY (Hz)

FREQUENCY RESPONSE (dB)

-9

-8

-7

-6

-5

-4

-3

-2

-1

-10

G0 TO G1

MAX14983E

TQFN

TOP VIEW

HSYNC0

VSYNC0

SDAO

GND

HSYNC1

REF

GND

VSYNC2

HSYNC2

1 2

SDA1

4 5 6 7

2324 22 20 19 18

S5V1

*CONNECT EP TO GND.

*EP

SCL2

SDA2

S5V2

VCC

G0 VSYNC1

31 10

32 9

SCL1

26 15 R2

25 16 G2

SCLO B2

EN2

MDOR

EN1

MD1

MD2

MAX14983E Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

Maxim Integrated

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Typical Operating Characteristics (continued)

Pin Conguration

PIN NAME FUNCTION ESD

1, 20 GND Ground —

2 R0 RGB Analog Input Standard

3 G0 RGB Analog Input Standard

4 B0 RGB Analog Input Standard

5 HSYNC0 Horizontal Sync Input Standard

6 VSYNC0 Vertical Sync Input Standard

7 SDA0 DDC Input/Output Standard

8 SCL0 DDC Input/Output Standard

9EN2 Active-Low Enable Input 2. Assert EN2 to connect the graphics controller to the monitor on port 2

(see Table 1). Standard

10 MDOR Logic NOR Output of MD1 and MD2. MDOR asserts whenever a monitor is detected on either

port. MDOR is an active-low, open-drain output. Standard

11 VCC

Supply Voltage. VCC = +5.0V ±5%. Bypass VCC to GND with a 1µF or larger ceramic capacitor

as close as possible to VCC.Standard

12 S5V2 Switched 5V Out 2. S5V2 is internally pulled down when not connected. Bypass S5V2 to GND

with a 1µF or larger capacitor as close as possible to S5V2. High

13 SDA2 DDC Input/Output. SDA2 has a 2.2kΩ (typ) internal pullup resistor to S5V2. High

14 SCL2 DDC Input/Output. SCL2 has a 2.2kΩ (typ) internal pullup resistor to S5V2. High

15 R2 RGB Analog Output for Port 2 High

16 G2 RGB Analog Output for Port 2 High

17 B2 RGB Analog Output for Port 2 High

18 HSYNC2 Horizontal Sync Output for Port 2 High

19 VSYNC2 Vertical Sync Output for Port 2 High

21 REF Monitor-Detection Reference. Connect a 105Ω ±1% resistor from REF to ground. Standard

22 VSYNC1 Vertical Sync Output for Port 1 High

23 HSYNC1 Horizontal Sync Output for Port 1 High

24 B1 RGB Analog Output for Port 1 High

25 G1 RGB Analog Output for Port 1 High

26 R1 RGB Analog Output for Port 1 High

27 SCL1 DDC Input/Output. SCL1 has a 2.2kΩ (typ) internal pullup resistor to S5V1. High

28 SDA1 DDC Input/Output. SDA1 has a 2.2kΩ (typ) internal pullup resistor to S5V1. High

29 S5V1 Switched 5V Out 1. S5V1 is internally pulled down when not connected. Bypass S5V1 to GND

with a 1µF or larger capacitor as close as possible to S5V1. High

30 MD2 Monitor-Detect Output 2. MD2 asserts when a monitor is detected on port 2. MD2 is an active-

low, open-drain output. Standard

31 MD1 Monitor-Detect Output 1. MD1 asserts when a monitor is detected on port 1. MD1 is an active-

low, open-drain output. Standard

32 EN1 Enable Input 1. Assert EN1 to connect the graphics controller to the monitor on port 1 (see Table 1). Standard

— EP Exposed Pad. Connect exposed pad to GND. —

MAX14983E Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

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Pin Description

250Ω

MONITOR

DETECTION

THERMAL

PROTECTION

2.5V

REGULATOR

INTERNAL VL

CONTROL

LOGIC

GND

2.2kΩS5V1

2.2kΩ

2.2kΩS5V2

2.2kΩ

S5V1

S5V2

SDA1

SCL1

SDA2

SCL2

HSYNC1

VSYNC1VSYNC0

HSYNC0

SCL0

SDA0

HSYNC2

VSYNC2

VCC

EN2

EN1

MD2

MD1

MDOR

MAX14983E

MAX14983E Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

www.maximintegrated.com Maxim Integrated

│

Functional Diagram

Detailed Description

The MAX14983E integrates high-bandwidth analog

switches and level-translating buffers to implement a

complete 1:2 multiplexer for VGA signals. The device

provides switching for red-green-blue (RGB) signals,

horizontal and vertical synchronization (HSYNC/VSYNC)

pulses, display data channel (DDC) signals, and 5V

power supplies. The power switches provide +5V power

with current limiting and reverse-voltage protection.

The device uses a simplified power-supply interface that

operates from a single +5V supply. An internal 2.5V

regulator limits the voltage passed by the DDC switches to

provide compatibility with low-voltage graphics controllers.

The device features two enable inputs and three monitor-

detection outputs. This interface signals to the graphics

controller when a monitor is inserted or removed from

either of the VGA ports and allows it to switch between

them. Alternatively, these signals can be connected

together to automatically select the port when a monitor is

plugged in. A dedicated output (MDOR) signals the graph-

ics controller when any monitor is detected.

5V Power Switches (S5V1, S5V2)

The device provides a switched +5V output in addition to

the regular VGA signals (S5V1 and S5V2). Each output

can supply 55mA with less than 300mV drop from VCC.

The S5V_ outputs tolerate +5V while turned off.

The power switches are protected against overcur-

rent and overtemperature faults. The device limits cur-

rent supplied to each monitor side to 300mA (typ).

Thermalprotection circuitry shuts off the switch when the

temperature exceeds +150°C. The device is re-enabled

once the temperature has fallen below +125°C.

Each power switch output has a 250Ω (typ) pulldown resis-

tor to discharge filter capacitors when the switch is off.

RGB Switches

The device provides three single-pole/double-throw

(SPDT) high-bandwidth switches to route the standard

VGA R, G, and B signals (Table 1). The R, G, and B ana-

log switches are identical, and any of the three switches

can be used to route red, green, or blue video signals.

Horizontal/Vertical Sync Multiplexer

The HSYNC_/VSYNC_ signals are buffered to provide

level shifting and drive capability to meet the VESA speci-

fication. HSYNC_/VSYNC_ signals are only routed to the

port selected by EN2 and EN1 (Table 1). HSYNC_ and

VSYNC_ are not interchangeable.

Display Data Channel Multiplexer

(SDA_, SCL_)

The device provides two voltage-limited SPDT switches

to route DDC signals (SDA_, SCL_). These switches limit

the voltage that can be passed through to the graphics

controller to less than 2.5V. Internal pullup resistors on

the monitor side of the switches translate the graphics

controller signals to 5V compatible logic. Connect pullup

resistors on SCL0 and SDA0 to define the logic level of

the graphics controller.

The SDA_ and SCL_ switches are identical, and either

of these two switches can be used to route SDA or SCL

I2C signals.

Note: The B_ switches are unconnected if the HSYNC_ input

is idle.

Note: MD1, MD2, and MDOR function regardless of the state

of the EN_ inputs.

Table 1. Channel Selection

Table 2. Monitor Detection

EN1 EN2 VGA CONTROLLER

CONNECTED TO

0 0 Port 1

0 1 Port 1

1 0 Port 2

1 1 Not Connected

MONITOR 1

DETECTED

MONITOR 2

DETECTED MD1 MD2 MDOR

No No 1 1 1

No Yes 1 0 0

Yes No 0 1 0

Yes Yes 0 0 0

MAX14983E Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

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Truth Tables

Applications Information

1:2 Multiplexer for Low-Voltage

Graphics Controllers

The device provides the level shifting necessary to drive

two standard VGA ports using a single graphics controller.

Internal buffers drive the HSYNC_ and VSYNC_ signals to

VGA standard TTL levels. The DDC multiplexer provides

level shifting by limiting signal levels to less than 2.5V.

Power-Supply Decoupling

Bypass VCC to ground with a 1µF or larger ceramic

capacitor as close as possible to the device.

PCB Layout

High-speed switches such as the MAX14983E require

proper PCB layout for optimum performance. Ensure that

impedance-controlled PCB traces for high-speed signals

are matched in length and as short as possible. Connect

the exposed pad to a solid ground plane.

High-ESD Protection

Electrostatic discharge (ESD)-protection structures are

incorporated on all pins to protect against electrostatic

discharges up to ±2kV Human Body Model (HBM)

encountered during handling and assembly. All outputs

are further protected against ESD up to ±11kV (HBM)

without damage (see the Pin Description).

The ESD structures withstand high ESD both in normal

operation and when the device is powered down. After

an ESD event, the device continues to function without

latchup.

ESD Test Conditions

ESD performance depends on a variety of conditions.

Contact Maxim for a reliability report that documents test

methodology and results.

Human Body Model

Figure 2 shows the Human Body Model. Figure 3 shows

the current waveform it generates when discharged into a

low impedance. This model consists of a 100pF capacitor

charged to the ESD voltage of interest that is then dis-

charged into the device through a 1.5kΩ resistor.

Figure 2. Human Body ESD Test Model Figure 3. Human Body Current Waveform

CHARGE CURRENT-

LIMIT RESISTOR

DISCHARGE

RESISTANCE

STORAGE

CAPACITOR

100pF

1MΩ

1.5kΩ

HIGH-

VOLTAGE

SOURCE

DEVICE

UNDER

TEST

36.8%

tRL

TIME

tDL

PEAK-TO-PEAK RINGING

(NOT DRAWN TO SCALE)

10%

AMPERES

100%

IPEAK (AMPS)

90%

MAX14983E Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

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+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed paddle.

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

32 TQFN-EP T3255+4 21-0140 90-0012

PART TEMP RANGE PIN-PACKAGE

MAX14983EETJ+ -40°C to +85°C 32 TQFN-EP*

MAX14983E Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

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Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

Chip Information

PROCESS: BiCMOS

Ordering Information

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 6/11 Initial release —

1 9/17 Updated Typical Operating Circuit and Pin Description table 1, 6

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

MAX14983E Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

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Revision History

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.