TL/F/11522
74VHC244 #74VHCT244 Octal Buffer/Line Driver with TRI-STATE Outputs
October 1995
74VHC244 #74VHCT244
Octal Buffer/Line Driver with TRI-STATEÉOutputs
General Description
The ’VHC/’VHCT244 is an advanced high speed CMOS oc-
tal bus buffer fabricated with silicon gate C2MOS technolo-
gy. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low pow-
er dissipation. The ’VHC/’VHCT244 is a non-inverting
TRI-STATE buffer having two active-low output enables.
These devices are designed to be used as TRI-STATE
memory address drivers, clock drivers, and bus oriented
transmitter/receivers.
An input protection circuit ensures that 0V–7V can be ap-
plied to the input pins without regard to the supply voltage.
This device can be used to interface 5V to 3V systems and
two supply systems such as battery back up. This circuit
prevents device destruction due to mismatched supply and
input voltages.
Features
YHigh noise immunity:
VHC VNIH eVNIL e28% VCC (min)
VHCT VIH e2.0V, VIL e0.8V
YPower down protection:
VHC inputs only
VHCT inputs and outputs
YLow noise:
VHC VOLP e0.6V (typ)
VHCT VOLP e0.7V (typ)
YLow power dissipation:
ICC e4mA (max) @TAe25§C
YBalanced propagation delays: tPLH jtPHL
YPin and function compatible with 74HC/HCT244
NOTE: ADD EXTERNAL PULL UP RESISTOR TO VHCT OUTPUTS TO
DRIVE CMOS INPUTS
Commercial Package Number Package Description
74VHC244M M20B 20-Lead Molded JEDEC SOIC
74VHC244SJ M20D 20-Lead Molded EIAJ SOIC
74VHC244MSC MSC20 20-Lead Molded EIAJ Type 1 SSOP
74VHC244MTC MTC20 20-Lead Molded JEDEC Type 1 TSSOP
74VHC244N N20A 20-Lead Molded DIP
74VHCT244M M20B 20-Lead Molded JEDEC SOIC
74VHCT244SJ M20D 20-Lead Molded EIAJ SOIC
74VHCT244MTC MTC20 20-Lead Molded JEDEC Type 1 TSSOP
74VHCT244N N20A 20-Lead Molded DIP
Note: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter ‘‘X’’ to the ordering code.
EIAJ Type 1 SSOP available on Tape and Reel only, order MSCX.
Logic Symbol
IEEE/IEC
TL/F/11522–3
Connection Diagram
Pin Assignment for DIP,
SSOP, TSSOP and SOIC
TL/F/11522– 1
Truth Tables
Inputs Outputs
OE1In(Pins 12, 14, 16, 18)
LL L
LH H
HX Z
Inputs Outputs
OE2In(Pins 3, 5, 7, 9)
LL L
LH H
HX Z
H
e
HIGH Voltage Level I eImmaterial
LeLOW Voltage Level ZeHigh
Impedance
Pin Names Description
OE1,OE
2TRI-STATE Output Enable Inputs
I0–I7Inputs
O0–O7TRI-STATE Outputs
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation RRD-B30M125/Printed in U. S. A.