74HC164D,652 - NXP Semiconductors

1. General description

The 74HC164; 74HCT164 ar e hig h-sp eed Si-g ate CMOS d evices and ar e pin compatible

with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC164; 74HCT164 are 8-bit edge-triggered shift registers with serial data entry

and an output from each of the eight stages. Data is entered serially through one of two

inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry

through the other input. Both inputs must be connected togethe r or an unu se d inpu t must

be tied HIGH.

Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input

and enters into Q0, which is the logical AND of the two data inputs (DSA and DSB) that

existed one set-up time prior to the rising clock edge.

A LOW level on the master reset (MR) input overrides all other inputs and clears the

2. Features and benefits

Input levels:

For 74HC164: CMOS level

For 74HCT164: TTL level

Gated serial data inputs

Asynchronous master reset

Complies with JEDEC standard no. 7A

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD2 2 -A115-A exceeds 2 0 0 V.

Multiple package options

Specified from 40 C to +85 C and 40 C to +125 C.

74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

Rev. 6 — 12 December 2011 Product data sheet

Product data sheet Rev. 6 — 12 December 2011 2 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

3. Ordering information

4. Functional diagram

Table 1. Ordering information

Type number Package

Temperatur e range Name Description Version

74HC164N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74HCT164N

74HC164D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width

3.9 mm SOT108-1

74HCT164D

74HC164DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body

width 5.3 mm SOT337-1

74HCT164DB

74HC164PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm SOT402-1

74HCT164PW

74HC164BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5 30.85 mm

SOT762-1

74HCT164BQ

Fig 1. Logic symbol Fig 2. IEC logic symbol

001aac423

DSB

DSA

001aac424

C1/

SRG8

Fig 3. Logic diagra m

001aac425

310136412511

Q0 Q1 Q2

8-BIT SERIAL−IN/PARALLEL−OUT

SHIFT REGISTER

Q3 Q4 Q5 Q6 Q7

DSB

DSA

Product data sheet Rev. 6 — 12 December 2011 3 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

5. Pinning information

5.1 Pinning

Fig 4. Functional diagram

001aac616

FF1

DSB

DSA

FF2

FF3

FF4

FF5

FF6

FF7

FF8

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land sho uld remain

floating or be connected to GND.

Fig 5. Pin configuration DIP14, SO14, (T)SSOP14 Fig 6. Pin configuration DHVQFN14

74HC164

74HCT164

DSA V

DSB Q7

Q0 Q6

Q1 Q5

Q2 Q4

Q3 MR

GND CP

001aal390

001aal391

74HC164

74HCT164

GND

(1)

Transparent top view

Q3 MR

Q2 Q4

Q1 Q5

Q0 Q6

DSB Q7

GND

DSA

6 9

5 10

4 11

3 12

2 13

terminal 1

index area

Product data sheet Rev. 6 — 12 December 2011 4 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

5.2 Pin description

6. Functional description

[1] H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition

L = LOW voltage level

I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition

q = lower case letters indicate the state of the referenced input one set-up time prior to the LOW-to-HIGH clock transition

= LOW-to-HIGH clock transition

7. Limiting values

Table 2. Pin description

Symbol Pin Description

DSA 1 data input

DSB 2 data input

Q0 to Q7 3, 4, 5, 6, 10, 11, 12, 13 output

GND 7 ground (0 V)

CP 8 clock input (LOW-to-HIGH, edge-triggered)

MR 9 master reset input (active LOW)

VCC 14 positive supply voltage

Table 3. Function table[1]

Operating

modes Input Output

MR CP DSA DSB Q0 Q1 to Q7

Reset (clear)LXXXLLtoL

Shift H llLq0to q6

HlhLq0to q6

Hhl Lq0to q6

HhhHq0to q6

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +7 V

IIK input clamping current VI < 0.5 V or VI>V

CC +0.5 V [1] -20 mA

IOK output clamping current VO<0.5 V or VO>V

CC +0.5V [1] -20 mA

IOoutput curren t 0.5 V < VO < VCC +0.5V - 25 mA

ICC supply current - 50 mA

IGND ground current 50 - mA

Tstg storage temperature 65 +150 C

Product data sheet Rev. 6 — 12 December 2011 5 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.

For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.

For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.

For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.

8. Recommended operating conditions

9. Static characteristics

Ptot total power dissipation [2]

DIP14 package - 750 mW

SO14, (T)SSOP14 and

DHVQFN14 packages - 500 mW

Table 4. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

Table 5. Recommended operating con ditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions 74HC164 74HCT164 Unit

Min Typ Max Min Typ Max

VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V

VIinput voltage 0 - VCC 0- V

CC V

VOoutput voltage 0 - VCC 0- V

CC V

Tamb ambient temperature 40 +25 +125 40 +25 +125 C

t/V i nput transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V

VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V

VCC = 6.0 V--83---ns/V

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

74HC164

VIH HIGH-level

input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V

VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V

VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V

VIL LOW-level

input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V

VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V

VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V

Product data sheet Rev. 6 — 12 December 2011 6 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

VOH HIGH-level

output voltage VI = VIH or VIL

IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V

IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V

IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V

VOL LOW-level

output voltage VI = VIH or VIL

IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V

IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI = VCC or GND;

VCC =6.0V --0.1 - 1-1A

ICC supply current VI = VCC or GND; IO=0A;

VCC =6.0V - - 8.0 - 80 - 160 A

CIinput

capacitance -3.5- - - - -pF

74HCT164

VIH HIGH-level

input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2 .0 - 2.0 - V

VIL LOW-level

input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V

VOH HIGH-level

output voltage VI = VIH or VIL; VCC = 4.5 V

IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V

IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V

VOL LOW-level

output voltage VI = VIH or VIL; VCC = 4.5 V

IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO = 5.2 mA; VCC = 6.0 V - 0.15 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI = VCC or GND;

VCC =6.0V --0.1 - 1-1A

ICC supply current VI = VCC or GND; IO=0A;

VCC =6.0V --8 - 80 - 160A

ICC additional

supply current per input pin;

VI=V

CC 2.1 V; IO=0A;

other inputs at VCC or GND;

VCC = 4.5 V to 5.5 V

- 100 360 - 450 - 490 A

CIinput

capacitance -3.5- - - - -pF

Table 6. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

Product data sheet Rev. 6 — 12 December 2011 7 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

10. Dynamic characteristics

Table 7. Dynamic characteristics

GND = 0 V; tr= tf= 6 ns; CL= 50 pF; test circuit see Figure 10; unless otherwise specifi ed

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

74HC164

tpd propagation

delay CP to Qn; see Figure 7 [1]

VCC = 2.0 V - 41 170 - 215 - 255 ns

VCC = 4.5 V - 15 34 - 43 - 51 ns

VCC = 5.0 V; CL=15pF - 12 - - - - - ns

VCC = 6.0 V - 12 29 - 37 - 43 ns

tPHL HIGH to LOW

propagation

delay

MR to Qn; see Figure 8

VCC = 2.0 V - 39 140 - 175 - 210 ns

VCC = 4.5 V - 14 28 - 35 - 42 ns

VCC = 5.0 V; CL=15pF - 11 - - - - - ns

VCC = 6.0 V - 11 24 - 30 - 36 ns

tttransition time see Figure 7 [2]

VCC = 2.0 V - 19 75 - 95 - 110 ns

VCC = 4.5 V - 7 15 - 19 - 22 ns

VCC = 6.0 V - 6 13 - 16 - 19 ns

tWpulse width CP HIGH or LOW;

see Figure 7

VCC = 2.0 V 80 14 - 100 - 120 - ns

VCC = 4.5 V 16 5 - 20 - 24 - ns

VCC = 6.0 V 14 4 - 17 - 20 - ns

MR LOW; see Figure 8

VCC = 2.0 V 60 17 - 75 - 90 - ns

VCC = 4.5 V 12 6 - 15 - 18 - ns

VCC = 6.0 V 10 5 - 13 - 15 - ns

trec recovery time MR to CP; see Figure 8

VCC = 2.0 V 60 17 - 75 - 90 - ns

VCC = 4.5 V 12 6 - 15 - 18 - ns

VCC = 6.0 V 10 5 - 13 - 15 - ns

tsu set-up time DSA, and DSB to CP;

see Figure 9

VCC = 2.0 V 60 8 - 75 - 90 - ns

VCC = 4.5 V 12 3 - 15 - 18 - ns

VCC = 6.0 V 10 2 - 13 - 15 - ns

thhold time DSA, and DSB to CP;

see Figure 9

VCC = 2.0 V +4 6- 4 - 4 - ns

VCC = 4.5 V +4 2- 4 - 4 - ns

VCC = 6.0 V +4 2- 4 - 4 - ns

Product data sheet Rev. 6 — 12 December 2011 8 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

fmax maximum

frequency for Cp, see Figure 7

VCC = 2.0 V 6 23 - 5 - 4 - MHz

VCC = 4.5 V 30 71 - 24 - 20 - MHz

VCC = 5.0 V; CL=15pF - 78 - - - - - MHz

VCC = 6.0 V 35 85 - 28 - 24 - MHz

CPD power

dissipation

capacitance

per package;

VI=GNDtoV

[3] -40- - - - - pF

74HCT164

tpd propagation

delay CP to Qn; see Figure 7 [1]

VCC = 4.5 V - 17 36 - 45 - 54 ns

VCC = 5.0 V; CL=15pF - 14 - - - - - ns

tPHL HIGH to LOW

propagation

delay

MR to Qn; see Figure 8

VCC = 4.5 V - 19 38 - 48 - 57 ns

VCC = 5.0 V; CL=15pF - 16 - - - - - ns

tttransition time see Figure 7 [2]

VCC = 4.5 V - 7 15 - 19 - 22 ns

tWpulse width CP HIGH or LOW;

see Figure 7

VCC = 4.5 V 18 7 - 23 - 27 - ns

MR LOW; see Figure 8

VCC = 4.5 V 18 10 - 23 - 27 - ns

trec recovery time MR to CP; see Figure 8

VCC = 4.5 V 16 7 - 20 - 24 - ns

tsu set-up time DSA, and DSB to CP;

see Figure 9

VCC = 4.5 V 12 6 - 15 - 18 - ns

thhold time DSA, and DSB to CP;

see Figure 9

VCC = 4.5 V +4 2- 4 - 4 - ns

fmax maximum

frequency for Cp, see Figure 7

VCC = 4.5 V 27 55 - 22 - 18 - MHz

VCC = 5.0 V; CL=15pF - 61 - - - - - MHz

Table 7. Dynamic characteristics …continued

GND = 0 V; tr= tf= 6 ns; CL= 50 pF; test circuit see Figure 10; unless otherwise specifi ed

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

Product data sheet Rev. 6 — 12 December 2011 9 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in W):

PD=C

PD VCC2fiN+ (CLVCC2fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(CLVCC2fo) = sum of outputs.

CPD power

dissipation

capacitance

per package;

VI=GNDtoV

CC 1.5 V [3] -40- - - - - pF

Table 7. Dynamic characteristics …continu ed

GND = 0 V; tr= tf= 6 ns; CL= 50 pF; test circuit see Figure 10; unless otherwise specifi ed

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

(1) Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 7. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output

transition times and the maximum clock frequency

001aal392

CP input

Qn output

tPHL tPLH

tTHL tTLH

VOH

GND

VOL

1/fmax

Table 8. Measurement points

Type Input Output

VMVMVXVY

74HC164 0.5VCC 0.5VCC 0.1VCC 0.9VCC

74HCT164 1.3 V 1.3 V 0.1VCC 0.9VCC

Product data sheet Rev. 6 — 12 December 2011 10 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

(1) Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 8. Waveforms showing the master re set (MR) pulse width, the master reset to output (Qn) propagation

delays and the master reset to clock (CP) re moval time

001aac427

MR input

CP input

Qn output

tPHL

tWfrec

GND

VOH

VOL

GND

(1) Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 9. Waveforms showing the data set-up and hold times for Dn inputs

001aac428

GND

Qn output

CP input

Dn input

Product data sheet Rev. 6 — 12 December 2011 11 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

Test data is given in Table 9.

Definitions test circuit:

RT = termination resistance should be equal to output impedance Zo of the pulse generator.

CL = load capacitance including jig and probe capacitance.

Fig 10. Test circuit for measuring switching times

001aah768

negative

pulse

GND

positive

pulse

GND

10 %

90 %

10 % VMVM

VCC

DUT

VIVO

Table 9. Test data

Type Input Load Test

VItr, tfCL

74HC164 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL

74HCT164 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL

Product data sheet Rev. 6 — 12 December 2011 12 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

11. Package outline

Fig 11. Package outline SOT27-1 (DIP14)

UNIT A

max. 1 2 (1) (1)

b1cD (1)

Ee M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT27-1 99-12-27

03-02-13

min. A

max. bmax.

1.73

1.13 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 2.24.2 0.51 3.2

0.068

0.044 0.021

0.015 0.77

0.73

0.014

0.009 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0870.17 0.02 0.13

050G04 MO-001 SC-501-14

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

Product data sheet Rev. 6 — 12 December 2011 13 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

Fig 12. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 6 — 12 December 2011 14 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

Fig 13. Package outline SOT337-1 (SSOP14)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25 0.2

7.9

7.6 1.03

0.63 0.9

0.7 1.4

0.9 8

0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT337-1 99-12-27

03-02-19

(1)

vMA

14 8

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1

max.

Product data sheet Rev. 6 — 12 December 2011 15 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

Fig 14. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 6 — 12 December 2011 16 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

Fig 15. Package outline SOT762-1 (DHVQFN14)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.65

1.35

2.6

2.4 1.15

0.85

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT762-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT762-1

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 9

02-10-17

03-01-27

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 6 — 12 December 2011 17 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

12. Abbreviations

13. Revision history

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

LSTTL Low-power Schottky Transistor-Transistor Logic

MM Machine Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT164 v.6 20111212 Product data sheet - 74HC_HCT 164 v.5

Modifications: •Legal pages updated.

74HC_HCT164 v.5 20101125 Product data sheet - 74HC_HCT164 v.4

74HC_HCT164 v.4 20100202 Product data sheet - 74HC_HCT164 v.3

74HC_HCT164 v.3 20050404 Product data sheet - 74HC_HCT164_ CNV v.2

74HC_HCT164_CNV v.2 19901201 Product specification - -

Product data sheet Rev. 6 — 12 December 2011 18 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

14. Legal information

14.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

14.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

14.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be lia ble for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulat ive liability t owards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or cust omer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from competent authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 6 — 12 December 2011 19 of 20

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equ ipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting f rom customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

14.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

15. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74HC164; 74HCT164

8-bit serial-in, parallel-out shift register

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 December 2011

Document identifier: 74HC_HCT164

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

16. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 4

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Recommended operating conditions. . . . . . . . 5

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12

12 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17

13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17

14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18

14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18

14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

15 Contact information. . . . . . . . . . . . . . . . . . . . . 19

16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20