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ML145106
PLL Frequency Synthesizer
CMOS
Legacy Device: Motorola MC145106
The ML145106 is a phase–locked loop (PLL) frequency synthesizer
constructed in CMOS on a single monolithic structure. This synthesizer
finds applications in such areas as AM radio, shortwave, amateur radio,
CB and FM transceivers. The device contains an oscillator/amplifier, a
210 or 211 divider chain for the oscillator signal, a programmable
divider chain for the input signal, and a phase detector. The ML145106
has circuitry for a 10.24 MHz oscillator or may operate with an exter-
nal signal. The circuit provides a 5.12 MHz output signal, which can be
used for frequency tripling. A 29programmable divider divides the
input signal frequency for channel selection. The inputs to the program-
mable divider are standard ground–to–supply binary signals. Pull–down
resistors on these inputs normally set these inputs to ground enabling
these programmable inputs to be controlled from a mechanical switch
or electronic circuitry.
The phase detector may control a VCO and yields a high level signal
when input frequency is low, and a low level signal when input fre-
quency is high. An out–of–lock signal is provided from the on–chip
lock detector with a “0” level for the out–of–lock condition.
• Single Power Supply
• Wide Supply Range: 4.5 to 12 V
• Provision for 10.24 MHz Crystal Oscillator
• 5.12 MHz Output
• Programmable Division Binary Input Selects up to 29
• On–Chip Pull–Down Resistors on Programmable Divider Inputs
• Selectable Reference Divider, 210 or 211 (Including ÷ 2)
• Three–State Phase Detector
• See Application Note AN535 and Article Reprint AR254
• Chip Complexity: 880 FETs or 220 Equivalent Gates
BLOCK DIAGRAM
fin
OSCin
OSCout
DIVIDE–BY–N COUNTER 29 – 1
REFERENCE
DIVIDE 29 OR 210
÷
2
PHASE
DETECTOR
÷
2out FS
φ
Detout
LD
P0 P1 P2 P3 P4 P5 P6 P7 P8
P DIP 18 = VP
PLASTIC DIP
CASE 707
SOG 20W = -6P
SOG PACKAGE
CASE 751D
18
1
20
1
CROSS REFERENCE/ORDERING INFORMATION
MOTOROLA
P DIP 18 MC145106P ML145106VP
SOG 20W MC145106DW ML145106-6P
LANSDALE
PACKAGE
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
INTERFACES WITH DUAL–MODULUS PRESCALERS
Issue bBCC
Page 2 of 8
LANSDALE Semiconductor, Inc.ML145106
÷2out
OSCin
fin
VDD
P8
LD
φ
Detout
FS
OSCout P2
P1
P0
VSS
P7
P6
P5
P4
P3
14
15
16
17
18
10
11
12
13
5
4
3
2
1
9
8
7
6
PLASTIC DIP
SOG PACKAGE
PIN ASSIGNMENTS
NC = NO CONNECTION
FS
OSCout
OSCin
fin
VDD
P7
P8
LD
φ
Detout
÷2out 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
P2
P1
NC
P0
VSS
P6
P5
NC
P4
P3
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter Symbol Value Unit
DC Supply Voltage VDD – 0.5 to + 12 V
Input Voltage, All Inputs Vin – 0.5 to VDD + 0.5 V
DC Input Current, per Pin I ± 10 mA
Operating Temperature Range TA– 40 to + 85 °C
Storage Temperature Range Tstg – 65 to + 150 °C
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised that
normal precautions be taken to avoid application
of any voltage higher than maximum rated
voltages to this high impedance circuit. For
proper operation it is recommended that Vin and
Vout be constrained to the range VSS° (Vin or
Vout)°≤ VDD.
≤
B
www.lansdale.com Issue b B
www.lansdale.comPage 3 of 8
LANSDALE Semiconductor, Inc.ML145106
ELECTRICAL CHARACTERISTICS (TA = 25°C Unless Otherwise Stated, Voltages Referenced to VSS)
V
DD
All Types
Characteristic Symbol
VDD
Vdc Min Typ* Max Unit
Power Supply Voltage Range VDD – 4.5 – 12 V
Supply Current IDD 5.0
10
12
–
–
–
6
20
28
10
35
50
mA
Input Voltage “0” Level VIL 5.0
10
12
–
–
–
–
–
–
1.5
3.0
3.6
V
“1” Level VIH 5.0
10
12
3.5
7.0
8.4
–
–
–
–
–
–
Input Current “0” Level
FS, Pull–Up Resistor Source Current)
Iin 5.0
10
12
– 5.0
– 15
– 20
– 20
– 60
– 80
– 50
– 150
– 200
µA
(P0 – P8) 5.0
10
12
–
–
–
–
–
–
– 0.3
– 0.3
– 0.3
(FS) “1” Level 5.0
10
12
–
–
–
–
–
–
0.3
0.3
0.3
(P0 – P8, Pull–Down Resistor Sink Current) 5.0
10
12
7.5
22.5
30
30
90
120
75
225
300
(OSCin, fin) “0” Level 5.0
10
12
– 2.0
– 6.0
– 9.0
– 6.0
– 25
– 37
– 15
– 62
– 92
(OSCin, fin) “1” Level 5.0
10
12
2.0
6.0
9.0
6.0
25
37
15
62
92
Output Drive Current
(VO = 4.5 V) Source
(VO = 9.5 V)
(VO = 11.5 V)
IOH
5.0
10
12
– 0.7
– 1.1
– 1.5
– 1.4
– 2.2
– 3.0
–
–
–
mA
(VO = 0.5 V) Sink
(VO = 0.5 V)
(VO = 0.5 V)
IOL 5.0
10
12
0.9
1.4
2.0
1.8
2.8
4.0
–
–
–
Input Amplitude
(fin @ 4.0 MHz)
(OSCin @ 10.24 MHz)
–
–
–
1.0
1.5
0.2
0.3
–
–
V p–p
Sine
Input Resistance
(OSCin, fin)
Rin
5.0
10
12
–
–
–
1.0
0.5
–
–
–
–
MΩ
Input Capacitance
(OSCin, fin)
Cin – – 6.0 – pF
Three–State Leakage Current
(φDetout)
IOZ 5.0
10
12
–
–
–
–
–
–
1.0
1.0
1.0
µA
Input Frequency
(– 40 to + 85°C)
fin 4.5
12
0
0
–
–
4.0
4.0
MHz
Oscillator Frequency
(– 40 to + 85°C)
OSCin 4.5
12
0.1
0.1
–
–
10.24
10.24
MHz
*Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC's potential performance.
Issue Bb
www.lansdale.comPage 4 of 8
LANSDALE Semiconductor, Inc.ML145106
TYPICAL CHARACTERISTICS*
* Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC's potential performance.
OSCin, MAXIMUM FREQUENCY (MHz)fin, MAXIMUM FREQUENCY (MHz)
50403020100
0
5.0
10
15
20
25
+ 85°C– 40°C
+ 25°C
50403020100
0
5.0
10
15
20
25
+ 85°C– 40°C
+ 25°C
V , POSITIVE POWER SUPPLY (V)
DD
V , SUPPLY VOLTAGE (V)
DD
Figure 1. Maximum Divider Input Frequency
versus Supply Voltage
Figure 2. Maximum Oscillator Input Frequency
versus Supply Voltage
PIN DESCRIPTIONS
P0 – P8
Programmable Inputs (PDIP – Pins 17 – 9; SOG – Pins 19,
17 – 14, 12 – 9)
Programmable divider inputs (binary).
fin
Frequency Input (PDIP, SOG – Pin 2)
Frequency input to programmable divider (derived
fromVCO).
OSCin, OSCout
Oscillator Input and Oscillator Output (PDIP, SOG –
Pins 3, 4)
Oscillator/amplifier input and output terminals.
LD
Lock Detector (PDIP, SOG – Pin 8)
LD is high when loop is locked, pulses low when
out–of–lock.
φDetout (PDIP, SOG – Pin 7)
Signal for control of external VCO, output high when fin/N
is less than the reference frequency; output low when fin/N is
greater than the reference frequency. Reference frequency is
the divided down oscillator–input frequency typically 5.0 or 10
kHz.
NOTE
Phase Detector Gain = VDD/4π.
FS
Reference Oscillator Frequency Division Select (PDIP,SOG
– Pin 6)
When using 10.24 MHz OSC frequency, this control selects
10 kHz, a “0” selects 5.0 kHz.
÷2out (PDIP, SOG – Pin 5)
Reference OSC frequency divided by 2 output; when using
10.24 MHz OSC frequency, this output is 5.12 MHz for fre-
quency tripling applications.
VDD
Positive Power Supply (PDIP, SOG – Pin 1)
VSS
Ground (PDIP – Pin 18, SOG – Pin 20)
TRUTH TABLE
Selection
P8 P7 P6 P5 P4 P3 P2 P1 P0 Divide by N
0 0 0 0 0 0 0 0 0 2*
0 0 0 0 0 0 0 0 1 3*
0 0 0 0 0 0 0 1 0 2
0 0 0 0 0 0 0 1 1 3
0 0 0 0 0 0 1 0 0
•••••••••
4
•
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
0 1 1 1 1 1 1 1 1 255
1 1 1 1 1 1 1 1 1 511
1: Voltage level = VDD.
0: Voltage level = 0 or open circuit input.
* The binary setting of 00000000 and 00000001 on P8 to P0 results
in a 2 and 3 division which is not in the 2N – 1 sequence. When pin
is not connected the logic signal on that pin can be treated as a “0”.
Issue b
www.lansdale.comPage 5 of 8
LANSDALE Semiconductor, Inc.ML145106
Figure 3. Single Crystal CB Synthesizer Featuring On–Frequency VCO During Transmit
26.965 – 27.405 MHz
(TRANSMIT)
26.510 – 26.950 MHz
(RECEIVE)
RECEIVER 1ST
LOCAL OSC SIGNAL
TO RECEIVER
2ND MIXER
25.6 MHz
X 5 MIXER
16.270 – 16.710 MHz10.24 MHz
MIXERBUFFER
GND
VDD
5.0 kHz BUFFERVCO
LOOP
FILTER
PHASE
DETECTOR
LD
R/T
SWITCH WAFERS
ML145106
PROGRAMMABLE
DIVIDER
29/210
2
OSC
10.24
MHz
1.365 – 1.805 MHz (TRANSMIT)
0.91 – 1.35 MHz (RECEIVE)
Legacy Applications Information
PLL SYNTHESIZER APPLICATIONS
The ML145106 is well suited for applications in CB radios
because of the channelized frequency requirements. A typical
40 channel CB transceiver synthesizer, using a single crystal
reference, is shown in Figure 3 for receiver IF values of 10.695
MHz and 455 kHz.
In addition to applications in CB radios, the MC145106 can
be used as a synthesizer for several other systems. Various fre-
quency spectrums can be achieved through the use of proper
offset, prescaling, and loop programming techniques. In gener-
al, 300 – 400 channels can be synthesized using a single loop,
with many additional channels available when multiple loop
approaches are employed. Figures 4 and 5 are examples of
some possibilities.
In the aircraft synthesizer of Figure 5, the VHF loop (top)
will provide a 50 kHz, 360 channel system with 10.7 MHz R/T
offset when only the 11.0500 MHz (transmit) and 12.1200
MHz (receive) frequencies are provided to mixer #1. When
these signals are provided with crystal oscillators, the result is
a three crystal 360 channel, 50 kHz step synthesizer. When
using the offset loop (bottom) in Figure 5 to provide the indi-
cated injection frequencies for mixer #1 (two for transmit and
two for receive) 360 additional channels are possible. This
results in a 720–channel, 25 kHz step synthesizer which
requires only two crystals and provides R/T offset capability.
The receive offset value is determined by the 11.31 MHz crys-
tal frequency and is 10.7 MHz for the example.
The VHF marine synthesizer in Figure 4 depicts a single
loop approach for FM transceivers. The VCO operates on fre-
quency during transmit and is offset downward during receive.
The offset corresponds to the receive IF (10.7 MHz) for chan-
nels having identical receive/transmit frequencies (simplex),
and is (10.7 – 4.6 = 6.1) MHz for duplex channels. Carrier
modulation is introduced in the loop during transmit.
Issue b
www.lansdale.comPage 6 of 8
LANSDALE Semiconductor, Inc.ML145106
Figure 4. VHF Marine Transceiver Synthesizer
LOCK DETECT
VDD
GND
0.2425 – 0.3825
(0.4850 – 0.7650)
*0.3800
TRANSMIT RANGE
156.025 – 157.425 MHz
*157.4
RECEIVER L.O. RANGE
145.575 – 152.575 MHz
*151.3
MODULATION
5.12 MHz
(10.24 MHz) VCO AND
BUFFER
LOOP
FILTER
14.29
(28.58)
SIMPLEX
14.75#
(29.50)
DUPLEX
RECEIVETRANSMIT
15.36 (30.72) RECEIVE OFFSET
OSCILLATOR
10 ( 5)
MIXER
TRIPLER
BUFFER
FILTER
PROGRAMMABLE INPUTS
N = 97 TO 153 *152
N 29 – 1
2.5 kHz
(5.0 kHz)
ML145106
PHASE
DETECTOR
29, 210
DIVIDER
2
REF
OSC
TRANSMIT
MODULATION
CIRCUIT
NOTES:
• Receiver IF = 10.7 MHz.
• Low Side Injection.
• Duplex Offset = 4.6 MHz.
• Step Size = 25 kHz.
• Frequencies in MHz unless noted.
• Values in parentheses are for a 5.0 kHz reference frequency.
• Example frequencies for Channel 28 shown by *.
N for Duplex Channels.
Legacy Applications Information
#Can be eliminated by adding 184 to
Issue b
www.lansdale.comPage 7 of 8
LANSDALE Semiconductor, Inc.ML145106
Figure 5. VHF Aircraft 720 Channel Two Crystal Frequency Synthesizer
5.12 MHz
VDD GND
RECEIVE
11.31 MHz
(SELECT FREQUENCY TO
GIVE DESIRED R/T OFFSET)
TRANSMIT
10.24 MHz
TRANSMIT
11.0500 MHz
11.0525 MHz
RECEIVE
12.1200 MHz
12.1225 MHz
01000101
810 kHz – 812.5 kHz
N = 324 – 325
LOCK DETECT
AMP
OSC
MIXER
#2
VDD GND
OFFSET LOOP
PROGRAMMING
÷
N 29 – 1
2.5 kHz
MC145106
REF OSC
AND
÷
2
÷
10
MIXER
#1
LOCK DETECT
TRANSMIT
118.000 – 135.975 MHz
(25 kHz STEPS)
RECEIVE
128.700 – 146.675 MHz
10.24 MHz VCO AND
BUFFER
LOOP
FILTER
VHF LOOP
PROGRAMMING
750 kHz – 2545 kHz
N = 150 – 509
÷
N 29 – 1
5.0 kHz
MC145106
PHASE
DETECTOR
29, 210
DIVIDER
÷
2
REF
OSC
LOOP
FILTER
VCO AND
BUFFER
PHASE
DETECTOR
29, 210
DIVIDER
Legacy Applications Information
Issue b
www.lansdale.comPage 8 of 8
LANSDALE Semiconductor, Inc.ML145106
OUTLINE DIMENSIONS
P DIP 18 = VP
(ML145106VP)
CASE 707–02
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
22.22
6.10
3.56
0.36
1.27
1.02
0.20
2.92
23.24
6.60
4.57
0.56
1.78
1.52
0.30
3.43
0°
0.51
0.875
0.240
0.140
0.014
0.050
0.040
0.008
0.115
0.915
0.260
0.180
0.022
0.070
0.060
0.012
0.135
15°
1.02
2.54 BSC
7.62 BSC
0.100 BSC
0.300 BSC
0°
0.020
15°
0.040
A
B
C
D
F
G
H
J
K
L
M
N
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
19
1018
B
A
H
F
G
D
SEATING
PLANE
NK
MJ
L
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
–B–
20
1
11
10
S
A
M
0.010 (0.25) B
S
T
D20X
M
B
M
0.010 (0.25)
P10X
J
F
G
18X K
C
–T–
SEATING
PLANE
M
RX 45°
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A12.65 12.95 0.499 0.510
B7.40 7.60 0.292 0.299
C2.35 2.65 0.093 0.104
D0.35 0.49 0.014 0.019
F0.50 0.90 0.020 0.035
G1.27 BSC 0.050 BSC
J0.25 0.32 0.010 0.012
K0.10 0.25 0.004 0.009
M0° 7° 0° 7°
P10.05 10.55 0.395 0.415
R0.25 0.75 0.010 0.029
SOG 20W = -6P
(ML145106-6P)
CASE 751D–04
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabil-
ity, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the cus-
tomer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Issue b
