1
Features
•Single Volt age Operation
–5V Read
– 5V Reprogramming
•Fast Re ad Access Time – 55 ns
•Internal Program Control and Timer
•Sector Architecture
– One 16K Bytes Boot Block with Programming Lockout
– Two 8K Bytes Parameter Blocks
– Two Main Memory Blocks (32K, 64K Bytes)
•Fast Erase Cycle Time – 10 Seconds
•Byte-by-byte Programming – 10 µs/Byte Typical
•Hardware Data Protection
•DATA Polling for End of Program Detection
•Low Power Dissipation
– 50 mA Active Current
– 100 µA CMOS Standby Current
•Typical 10,000 Write Cycles
Description
The AT49F001(N)(T) is a 5-volt only in-system reprogrammable Flash memory. Its
1 megabit of memor y is organized as 131,072 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to
1-megabit
(128K x 8)
5-vo lt Only
Flash Memory
AT49F001
AT49F001N
AT49F001T
AT49F001NT
Rev. 1008D– FLAS H– 2/0 3
PLCC Top View
Pin Configurations
Pin Name Function
A0 - A16 Address es
CE Chip Enable
OE Out put Enable
WE Write Enable
RESET RESET
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
4
3
2
1
32
31
30
14
15
16
17
18
19
20
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A12
A15
A16
RESET *
VCC
WE
NC
DIP Top View
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
* RESET
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
WE
VCC
* RESET
A16
A15
A12
A7
A6
A5
A4
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Note: *This pin is a DC on the AT49F001N(T).
2AT49F001(N(T) 1008D–FLASH–2/03
55 ns with power dissipation of just 275 mW over the commercial temperature range. When
the device is deselected, the CMOS standby current is less than 100 µA. For the
AT49F0 01N(T) pin 1 for the D IP and PLCC packag es and pin 9 for the T SOP package a re
don’t co nnect pin s.
To allow for simple in-sys tem reprogrammability, the AT49F001(N) (T) does not require high
input voltages for programmi ng. Five-volt-only commands determine the read and program-
ming operation of the device. Reading data out of the device is similar to reading from an
EPROM; it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the
AT49F001 (N )(T ) is per fo rmed by er asi ng a b loc k of data and the n programming o n a by te -b y-
byte bas is. The byte pro gramming tim e is a fast 50 µs. Th e end of a program c ycle can be
option ally detec ted by th e DATA po lling feature. Once the end of a byte program cyc le has
been detected, a new access for a read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles.
The device is erased by executing the erase command sequence; the device internally con-
trols th e erase oper ations. Th ere are two 8K bytes parame ter block sec tions and tw o main
memory blocks.
The devi ce has the c apa bil ity to pr ot ec t the da ta in th e boo t blo ck; thi s fe atur e is en abl ed by a
command sequence. The 16-Kbyte boot block section includes a reprogramming lock out fea-
ture to pr ovide data int egrity. The boot sector is designe d to contain user se cure code , and
when the feature is enabled, the boot sector is protected from being reprogrammed.
In the AT49F0 01( N)( T), on ce the boot bloc k progr amm ing locko ut fea tur e is enab le d, the c on-
tents of the boo t block are p erma nent a nd ca nnot be chang ed. In the AT49F 001( T), on ce th e
boot block programming lockout feature is enabled, the contents of the boot block cannot be
changed with input voltage levels of 5.5 volts or less.
Block Diag ram
CONTROL
LOGIC
Y DECODER
PARAMETER
BLOCK 1
(8K BYTES)
BOOT BLOCK
(16K BYTES)
OE
WE
CE
RESET
ADDRESS
INPUTS
VCC
GND
AT49F001(N)T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
X DECODER
PARAMETER
BLOCK 2
(8K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
MAIN MEMORY
BLOCK 2
(64K BYTES)
PROGRAM
DATA LATCHES
Y-GATING
INPUT/OUTPUT
BUFFERS
1FFFF
1C000
1BFFF
1A000
19FFF
18000
17FFF
10000
0FFFF
00000
PARAMETER
BLOCK 1
(8K BYTES)
BOOT BLOCK
(16K BYTES)
AT49F001(N)
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
PARAMETER
BLOCK 2
(8K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
MAIN MEMORY
BLOCK 2
(64K BYTES)
PROGRAM
DATA LATCHES
Y-GATING
INPUT/OUTPUT
BUFFERS
1FFFF
10000
0FFFF
08000
07FFF
06000
05FFF
04000
03FFF
00000
3
AT49F001(N(T)
1008D–FLASH–2/03
Device
Operation READ: The AT49 F001( N) (T ) is ac ce ss ed li k e an EP RO M. Wh en C E a nd OE are low and WE
is high , the data st or ed a t the memory loc at ion det er min ed by the a ddr ess pi ns is as se r ted o n
the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This
dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: Wh en the devi ce is first powe red on, it wil l be reset to the r ead or
standby mode depending upon the state of th e control line inputs. In or der to perform other
device fu nctio n s, a s er i es o f com mand se que nce s are entered i nto th e dev ic e. T he command
sequences are shown in the Command Definitions table. The command sequences are written
by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high.
The addres s is la tched on th e falling edge of CE or WE, w hichever occu rs last. T he data is
latched b y the firs t rising edge of CE or W E. Stand ard micr opr ocess or write timing s are u sed.
The addres s lo ca tions used in the command sequ ences are not affe cte d by enter ing the c om-
mand sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halt s the present de vice opera tion and puts the outputs of the de vice in a high inp endance
state. If the RESET pin makes a high-to-low transition during a program or erase operation,
the operation may not be successfully completed and the operation will have to be repeated
after a hi gh level is app lied to the RES ET pin. When a hig h leve l is rea sser ted on the RES ET
pin, the device returns to the read or standby mode, depending upon the state of the control
inputs. By applying a 12V ± 0.5V input signal to the RESET pin, the boot block array can be
reprogrammed even if the boot block lockout feature has been enabled (see Boot Block Pro-
gramming Lockout Override section). The RESET feature is not available for the
AT49F001N(T).
ERASURE: Befo re a byte can b e repro gramm ed, th e main memo ry b lock or param eter block
which c ontains the by te must be era sed. The erased stat e of the memor y bits is a lo gical “1”.
The entire device can be erased at one time by using a 6-byte software code. The software
chip erase code consists of 6-byte load commands to specific address locations with a specific
data pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device will internally time the erase opera-
tion so that no external clocks are requ ired. The maximu m time ne eded to e rase the w hole
chip is tEC. If t he bo ot bl ock l ockou t feat ure has been enab led, the data in the b oot sec tor will
not be erased.
CHIP ERASE : If the boot block lockout has been enabled, the Chip Erase function will erase
Parameter Block 1, Parameter Block 2, Main Memory Block 1, and Main Memory Block 2 but
not the boot block. If the Boot Block Lockout has not been enabled, the Chip Erase function
will erase the entire chip. After the full chip erase the device will return back to read mode. Any
command during chip erase will be ignored.
4AT49F001(N(T) 1008D–FLASH–2/03
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into sectors
that can be individually erased. There are two 8-Kbyte parameter block sections and two main
memory blocks. The 8-Kbyte p arameter bloc k sections c an be indepe ndently erased and
reprogr ammed. Th e two main memory sections are de signed to be used as alterna tive mem-
ory sectors. That is, whenever one of the blocks has been erased and reprogrammed, the
other block sho uld be erased and reprogrammed before the first block is again erased. The
Sect or Er as e command i s a six bus c ycle op er ati on. Th e s ec tor ad dres s i s lat che d o n the fal l-
ing WE edge of the sixth cycle while the 30H data input command is latched at the rising edge
of WE. The sector erase starts after the rising edge of WE of the sixt h cyc l e. Th e er as e op e ra -
tion is internally controlled; it will automatically time to completion.
BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a
logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to
a “1” ; only erase op eratio ns can conve rt “0”s t o “1”s . Prog ramming is ac compli shed v ia the
internal device command register and is a 4 bus cycle operation (please refer to the Command
Definitions table). The device will automatically generate the required internal program pulses.
The prog ram cycle has add resses latch ed on the fal ling edge of WE or CE, whic hever oc curs
last, and the data l atched on the rising edge of WE or CE, whichever occurs fir st. Program-
ming is co mpleted after the sp ecified tBP cyc le time. The DATA polling fea ture may also be
used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The devic e has one desi gnated bl ock that has
a progra mmin g lockou t feature. This fe ature pre vents pr ogrammi ng of data in the des ignate d
block once the feature has been enab led. The size of the block is 16K bytes. This block,
refer red to as th e boot block , can cont ain secur e code that i s used to bri ng up the s ystem.
Enabling the lockout feature will allow the boot code to stay in the device while data in the rest
of the device is updated. This feature does not have to be activated; the boot block’s usage as
a write pr otected reg ion is opt ional to the use r. The addr ess range of the boot block is 00000
to 03FFF for the AT49F001(N) while the address range of the boot block is 1C000 to 1FFFF
for the AT49F001(N)T.
Once the feature is enabled, the data in the boot block can no longer be erased or pro-
grammed with inp ut volt age level s of 5.5V or less . Data in th e main m emory bl ock can s till be
changed through the regular programming method. To activate the lockout feature, a series of
six pro gram commands to specific addresses with specific data must b e performed. Pl ease
refer to the Command Definitions table.
BOOT BLOCK LO CKOUT DETECTIO N: A software method is available to determine if pro-
gramm ing of th e boot bl ock sec tion i s locke d out. Wh en th e device is in th e softwa re produ ct
identification mode (see Software Product Identification Entry and Exit sections) a read from
address location 00002H will show if programming the boot block is locked out for the
AT49F0 01(N) a nd a r ead from addr ess 1C00 2H wil l show if prog ramming the bo ot blo ck is
locked out for the AT49F001(N)T. If the data on I/O0 is low, the boot block can be pro-
grammed ; if t he dat a on I /O0 i s high , the p rogram loc kout featu re h as be en acti vated and th e
block c annot be prog ramme d. The softwa re produc t identi fica tion exit co de shou ld be use d to
return to standard operation.
5
AT49F001(N(T)
1008D–FLASH–2/03
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot
block progr ammi ng lock out by taking the RES ET pin to 12 v olts. By doi ng thi s , p rot ected bo ot
block d ata ca n be al ter ed through a ch ip er ase, s ec tor e rase or word pr ogr am mi ng. Whe n th e
RESET pin i s b rough t back to T TL le ve ls the bo ot bl ock pr ogram mi ng l oc k out featu re is a gai n
active. This feature is not available on the AT49F001N(T).
PRODUCT IDENTIFICATION: The pr odu ct identificatio n mode ident ifi es the device and m an-
ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.
For deta ils, see Ope rating Mod es (for hardwar e operation) or Software Pr oduct Ide ntificatio n.
The manufacturer and device code is the same for both modes.
DATA POLLING: The AT49F001(N)(T) features DATA polling to indicat e the end of a pr o-
gram cycl e. Du ring a p ro gr am cyc le an att empted read of the las t by te loade d wil l res ul t in th e
complem ent of the loaded d ata on I/O 7. Once the program cycle h as been completed, true
data is va li d on al l o utp uts an d th e next cy cle may b egi n. DAT A po ll ing ma y begin a t an y time
during the program cycle.
TOGGLE BIT: In addition to DATA polling the AT49F001(N)(T) provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc-
cessive attempts to read data from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION : Hardware featur es pr otect agai nst inad verte nt pro grams
to the AT 49 F 001 (N)( T) in the fo ll owin g w a ys: (a ) VCC se ns e: i f VCC i s bel ow 3.8V (ty pi cal) , th e
program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE
high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or
CE inputs will not initiate a program cycle.
6AT49F001(N(T) 1008D–FLASH–2/03
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex)
2. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F001(N) and
1C000H to 1FFFFH for the AT49F001(N)T.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses
For the AT49F001(N ):
SA = 00000 to 03FFF for BOOT BLOCK
Nothing will happen and the device goes back to the read mode in 100 ns
SA = 04000 to 05FFF for PARAMETER BLOCK 1
SA = 06000 to 07FFF for PARAMETER BLOCK 2
SA = 08000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 1
This command will erase - PB1, PB2 and MMB1
SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2
For the AT49F001(N )T:
SA = 1C000 to 1FFFF for BOOT BLOCK
Nothing will happen and the device goes back to the read mode in 100 ns
SA = 1A000 to 1BFFF for PARAMETER BLOCK 1
SA = 18000 to 19FFF for PARAMETER BLOCK 2
SA = 10000 to 17FFF for MAIN MEMORY ARRAY BLOCK 1
This command will erase - PB1, PB2 and MMB1
SA = 00000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 2
Absolute Maxim u m Ratings*
Command Definition (in Hex)(1)
Command
Sequence Bus
Cycles
1st Bus
Cycle 2nd Bus
Cycle 3rd Bus
Cycle 4th Bu s
Cycle 5th Bu s
Cycle 6th Bu s
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read 1 Addr DOUT
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA(4) 30
Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr DIN
Boot Block Lockout(2) 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
Product ID Entr y 3 5555 AA 2AAA 55 5555 90
Product ID Exit(3) 3 5555 AA 2AAA 55 5555 F0
Product ID Exit(3) 1 XXXX F0
Temperature Under Bias................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device rel iab ili ty.
Storage Te mperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground................................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground................................... -0.6V to +13.5V
7
AT49F001(N(T)
1008D–FLASH–2/03
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programm i ng Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 05H - AT49F001(N), 04H - AT49F001(N)T
5. See details under Software Product Identification Entry/Exit.
6. This pin is not availa ble on the AT49F001N(T).
Note: 1. In the erase mode, ICC is 90 mA.
DC and AC Oper ating Rang e
AT49F001(N)(T)-55 AT49F001(N)(T)-70 AT49F001(N)(T)-90 AT49F001(N)(T)-12
Operating
Temperature (Case) Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C
Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C
VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%
Operating Modes
Mode CE OE WE RESET(6) Ai I/O
Read VIL VIL VIH VIH Ai DOUT
Program/Erase(2) VIL VIH VIL VIH Ai DIN
Standby/Write Inhibit VIH X(1) XV
IH X High Z
Program Inhibit X X VIH VIH
Program Inhibit X VIL XV
IH
Output Disable X VIH XV
IH High Z
Reset X X X VIL X High Z
Product Identification
Hardware VIL VIL VIH A1 - A16 = VIL, A9 = VH,(3) A0 = VIL Manufacturer Code(4)
A1 - A16 = VIL, A9 = VH,(3) A0 = VIH Device Code(4)
Software(5) A0 = VIL, A1 - A16=VIL Manufacturer Code(4)
A0 = VIH, A1 - A16=VIL Device Code(4)
DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC 10 µA
ILO Output Leakage Current VI/O = 0V to VCC 10 µA
ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC Com. 100 µA
Ind. 300 µA
ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3mA
ICC(1) VCC Active Current f = 5 MHz; IOUT = 0 mA 50 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 2.1 mA 0.45 V
VOH1 Output High Voltage IOH = -400 µA 2.4 V
VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V
8AT49F001(N(T) 1008D–FLASH–2/03
AC Read Waveforms (1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be de layed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
AC Read Characteristics
Symbol Parameter
AT49F001(N)(T)-55 AT49F001(N)(T)-70 AT49F001(N)(T)-90 AT49F001(N)(T)-12
UnitsMin Max Min Max Min Max Min Max
tACC Addr ess to Output Delay 55 70 90 120 ns
tCE(1) CE to Output Delay 55 70 90 120 ns
tOE(2) OE to Output Delay 0 30 0 35 0 40 0 50 ns
tDF(3)(4) CE or OE to Output Float 0 25 0 25 0 25 0 30 ns
tOH
Output Hold from OE, CE
or Address, whichever
occurred first 0000ns
ADDRESS
OUTPUT
HIGH Z
OUTPUT
OE
CE
tACC
tOE
tDF
tOH
tCE
VALID
ADDRESS VALID
9
AT49F001(N(T)
1008D–FLASH–2/03
Input Test Waveform and Measurement Le vel
tR, tF < 5 ns
Output Load Test
Note: 1. This parameter is characterized and is not 100% tested.
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol Typ Max Units Conditions
CIN 46pFV
IN = 0V
COUT 812pFV
OUT = 0V
5.0V
1.8K
100 pF
30 pF 1.3K
5.0V
1.8K
OUTPUT
PIN
1.3K
OUTPUT
PIN
55 ns 70/90/120 ns
10 AT49F001(N(T) 1008D–FLASH–2/03
AC Byte Load W aveforms
WE Controlled
CE Controlled
AC Byte Load Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Set-up Time 0 ns
tAH Address H old Time 50 ns
tCS Chip Select Set-up Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE)90ns
tDS Data Set-up Time 50 ns
tDH, tOEH Data, OE Hold Time 0ns
tWPH Write Pulse Width High 90 ns
tDH
tDS
tAS tAH
tWP
CE
ADDRESS
DATA IN
OE tOES tOEH
WE tCS
tCH
tWPH
t
DH
t
DS
t
AS
t
AH
t
WP
WE
ADDRESS
DATA IN
OE t
OES
t
OEH
CE t
CS
t
CH
t
WPH
11
AT49F001(N(T)
1008D–FLASH–2/03
Program Cycle Waveforms
Sector or Chip Erase Cycle Waveforms
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased.
(See note 4 under command definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
Program Cycle Characteristics
Symbol Parameter Min Typ Max Units
tBP Byte Progr am mi ng Time 10 50 µ s
tAS Address Set-u p Time 0 ns
tAH Address H old Time 50 ns
tDS Data Set-up Time 50 ns
tDH Data Hold Time 0 ns
tWP Write Pulse Widt h 90 ns
tWPH Write Pulse Width High 90 ns
tEC Erase Cyc le Tim e 10 seconds
OE
PROGRAM CYCLE
INPUT
DATA
ADDRESS
A0
55
5555 5555
AA
2AAA
t
BP
t
WPH
t
WP
CE
WE
A0-A16
DATA
t
AS
tAH tDH
tDS
OE
(1)
AA
80 Note 3
55 55
5555 5555 Note 2
AA
BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5
2AAA 2AAA
t
WPH
t
WP
CE
WE
A0-A16
DATA
t
AS
t
AH
t
EC
t
DH
t
DS
5555
12 AT49F001(N(T) 1008D–FLASH–2/03
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteri stics.
Data Polling Waveforms
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteri stics.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
Data Polling Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tWR Write Recov ery Time 0 ns
Toggle Bit Character istics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tOEHP OE High Pulse 150 ns
tWR Write Recov ery Time 0 ns
HIGH Z
An An An An An
WE
CE
OE
I/O7
A0-A16
t
OEH
t
OE
t
DH
t
WR
WE
CE
OE
I/O6
t
OEH
HIGH Z
t
DH
t
OE
t
WR
t
OEHP
13
AT49F001(N(T)
1008D–FLASH–2/03
Software Product Identification Entry(1)
Software Product Identification Exit(1)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A16 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
pow e red do w n .
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 05H - AT49F001(N)
04H - AT49F001(N)T
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE
(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE
(4)
OR
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE
(4)
Boot Block Lockout
Feature Enable Algorithm(1)
Notes: 1. Data For mat: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enable d.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 40
TO
ADDRESS 5555
PAUSE 1 second(2)
14 AT49F001(N(T) 1008D–FLASH–2/03
AT49F001 Ordering Information
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
55 50 0.1 AT49F001-55JC
AT49F001-55PC
AT49F001-55TC
AT49F001-55VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001-55JI
AT49F001-55PI
AT49F001-55TI
AT49F001-55VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
70 50 0.1 AT49F001-70JC
AT49F001-70PC
AT49F001-70TC
AT49F001-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001-70JI
AT49F001-70PI
AT49F001-70TI
AT49F001-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
90 50 0.1 AT49F001-90JC
AT49F001-90PC
AT49F001-90TC
AT49F001-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001-90JI
AT49F001-90PI
AT49F001-90TI
AT49F001-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
120 50 0.1 AT49F001-12JC
AT49F001-12PC
AT49F001-12TC
AT49F001-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001-12JI
AT49F001-12PI
AT49F001-12TI
AT49F001-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J 32-lead, Plastic, J-leaded Ch ip Carrier Package (PLCC)
32P6 32-lead, 0.600" Wide, Plast ic Dual In-line Package (PDIP)
32T 32-lead, Plastic Thin Small Outline Package (TSOP)
32V 32-lead, Plastic Thin Sma ll Outline Package (VSOP) (8 x 14 mm)
15
AT49F001(N(T)
1008D–FLASH–2/03
AT49F001N Ordering Information
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
55 50 0.1 AT49F001N-55JC
AT49F001N-55PC
AT49F001N-55TC
AT49F001N-55VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001N-55JI
AT49F001N-55PI
AT49F001N-55TI
AT49F001N-55VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
70 50 0.1 AT49F001N-70JC
AT49F001N-70PC
AT49F001N-70TC
AT49F001N-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001N-70JI
AT49F001N-70PI
AT49F001N-70TI
AT49F001N-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
90 50 0.1 AT49F001N-90JC
AT49F001N-90PC
AT49F001N-90TC
AT49F001N-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001N-90JI
AT49F001N-90PI
AT49F001N-90TI
AT49F001N-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
120 50 0.1 AT49F001N-12JC
AT49F001N-12PC
AT49F001N-12TC
AT49F001N-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001N-12JI
AT49F001N-12PI
AT49F001N-12TI
AT49F001N-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J 32-lead, Plastic, J-leaded Ch ip Carrier Package (PLCC)
32P6 32-lead, 0.600" Wide, Plast ic Dual In-line Package (PDIP)
32T 32-lead, Plastic Thin Small Outline Package (TSOP)
32V 32-lead, Plastic Thin Sma ll Outline Package (VSOP) (8 x 14 mm)
16 AT49F001(N(T) 1008D–FLASH–2/03
AT49F001T Ordering Information
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
55 50 0.1 AT49F001T-55JC
AT49F001T-55PC
AT49F001T-55TC
AT49F001T-55VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001T-55JI
AT49F001T-55PI
AT49F001T-55TI
AT49F001T-55VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
70 50 0.1 AT49F001T-70JC
AT49F001T-70PC
AT49F001T-70TC
AT49F001T-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001T-70JI
AT49F001T-70PI
AT49F001T-70TI
AT49F001T-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
90 50 0.1 AT49F001T-90JC
AT49F001T-90PC
AT49F001T-90TC
AT49F001T-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001T-90JI
AT49F001T-90PI
AT49F001T-90TI
AT49F001T-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
120 50 0.1 AT49F001T-12JC
AT49F001T-12PC
AT49F001T-12TC
AT49F001T-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001T-12JI
AT49F001T-12PI
AT49F001T-12TI
AT49F001T-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J 32-lead, Plastic, J-leaded Ch ip Carrier Package (PLCC)
32P6 32-lead, 0.600" Wide, Plast ic Dual Inline Package (PDIP)
32T 32-lead, Plastic Thin Small Outline Package (TSOP)
32V 32-lead, Plastic Thin Sma ll Outline Package (VSOP) (8 x 14 mm)
17
AT49F001(N(T)
1008D–FLASH–2/03
AT49F001NT Ordering Inf ormation
tACC
(ns) ICC (mA) Ordering Code Package Operation Range
55 50 0.1 AT49F001NT-55JC
AT49F001NT-55PC
AT49F001NT-55TC
AT49F001NT-55VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001NT-55JI
AT49F001NT-55PI
AT49F001NT-55TI
AT49F001NT-55VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
70 50 0.1 AT49F001NT-70JC
AT49F001NT-70PC
AT49F001NT-70TC
AT49F001NT-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001NT-70JI
AT49F001NT-70PI
AT49F001NT-70TI
AT49F001NT-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
90 50 0.1 AT49F001NT-90JC
AT49F001NT-90PC
AT49F001NT-90TC
AT49F001NT-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001NT-90JI
AT49F001NT-90PI
AT49F001NT-90TI
AT49F001NT-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
120 50 0.1 AT49F001NT-12JC
AT49F001NT-12PC
AT49F001NT-12TC
AT49F001NT-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50 0.3 AT49F001NT-12JI
AT49F001NT-12PI
AT49F001NT-12TI
AT49F001NT-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J 32-lead, Plastic, J-leaded Ch ip Carrier Package (PLCC)
32P6 32-lead, 0.600" Wide, Plast ic Dual In-line Package (PDIP)
32T 32-lead, Plastic Thin Small Outline Package (TSOP)
32V 32-lead, Plastic Thin Sma ll Outline Package (VSOP) (8 x 14 mm)
18 AT49F001(N(T) 1008D–FLASH–2/03
Packaging Informa t ion
32J – PLCC
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
R
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B
32J
10/04/01
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER 1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1 E2
B
e
E1 E
D1
D
D2
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 3.175 – 3.556
A1 1.524 – 2.413
A2 0.381 – –
D 12.319 – 12.573
D1 11.354 – 11.506 Note 2
D2 9.906 – 10.922
E 14.859 – 15.113
E1 13.894 – 14.046 Note 2
E2 12.471 – 13.487
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
19
AT49F001(N(T)
1008D–FLASH–2/03
32P6 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP) B
32P6
09/28/01
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
0º ~ 15º
D
e
eB
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 4.826
A1 0.381 – –
D 41.783 – 42.291 Note 1
E 15.240 – 15.875
E1 13.462 – 13.970 Note 1
B 0.356 – 0.559
B1 1.041 – 1.651
L 3.048 – 3.556
C 0.203 – 0.381
eB 15.494 – 17.526
e 2.540 TYP
Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
20 AT49F001(N(T) 1008D–FLASH–2/03
32T – TSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP) B
32T
10/18/01
PIN 1
D1 D
Pin 1 Identifier
b
e
EA
A1
A2
0º ~ 8º c
L
GAGE PLANE
SEATING PLANE
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 19.80 20.00 20.20
D1 18.30 18.40 18.50 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
21
AT49F001(N(T)
1008D–FLASH–2/03
32V – VSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP) B
32V
10/18/01
PIN 1
D1 D
Pin 1 Identifier
b
e
EA
A1
A2
0º ~ 8º c
L
GAGE PLANE
SEATING PLANE
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MO-142, Variation BA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 13.80 14.00 14.20
D1 12.30 12.40 12.50 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
Printed on recycled paper.
Atmel® is the registered trademark of Atmel.
Other terms and product names may be the trademarks of others.
© Atmel Corporation 2003.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reser ves the right to change devices or specifications detailed herein at any tim e without notice, and does
not make any com mitment to update the infor mation contained herein. No licenses to patents or other intellectual proper ty of Atmel are granted
by the Company in connection with the s ale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life suppor t devices or systems.
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1008D–FLASH–2/03 xM
