KSZ8041TL/FTL
10Base-T/100Base-TX/100Base-FX
Physical Layer Transceiver
Data Sheet Rev. 1.1
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
April 2007 M9999-042707-1.1
General Description
The KSZ8041TL is a single supply 10Base-T/100Base-TX
Physical Layer Transceiver, which provides MII/RMII/SMII
interfaces to transmit and receive data. It utilizes a unique
mixed-signal design to extend signaling distance while
reducing power consumption.
HP Auto MDI/MDI-X provides the most robust solution for
eliminating the need to differentiate between crossover
and straight-through cables.
Micrel LinkMD® TDR-based cable diagnostics permit
identification of faulty copper cabling.
The KSZ8041TL represents a new level of features and
performance and is an ideal choice of physical layer
transceiver for 10Base-T/100Base-TX applications.
The KSZ8041FTL has all the identical rich features of the
KSZ8041TL plus 100Base-FX support for fiber and media
converter applications.
Both KSZ8041TL and KSZ8041FTL are available in 48-
pin, lead-free TQFP packages (See Ordering Informat ion).
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Diagram
Micrel, Inc. KSZ8041TL/FTL
April 2007 2 M9999-042707-1.1
Features
Single-chip 10Base-T/100Base -TX physical layer
solution
Fully compliant to IEEE 802.3u Standard
Low power CMOS design, power consumption of
<180mW
HP auto MDI/MDI-X for reliable detection and corre ction
for straight-through and crossover cables with disa ble
and enable option
Robust operation over standard cables
LinkMD® TDR-based cabl e diagnostics for identification
of faulty copper cabling
Fiber support: 100Base-FX (KSZ8041 FTL only), Back-
to-Back mode (KSZ8041FTL and KSZ8 041TL)
MII interface support
RMII interface support with external 50MHz system
clock
SMII interface support with external 125MHz system
clock and 12.5MHz syn c clock from MAC
MIIM (MDC/MDIO) manageme nt bus to 12.5MHz for
rapid PHY register configu ration
Interrupt pin option
Programmable LED outputs for link, activity and speed
Power down and power saving modes
Single power supply (3.3V)
Built-in 1.8V regulator for core
Available in 48-pin TQFP package
Applications
Printer
LOM
Game Console
IPTV
IP Phone
IP Set-top Box
Media Converter
Ordering Information
Part Number Temp. Range Package Lead Finish
KSZ8041TL 0°C to 70°C 48-Pin TQFP Pb-Free
KSZ8041TLI(1) -40°C to 85°C 48-Pin TQFP Pb-Free
KSZ8041FTL 0°C to 70°C 48-Pin TQFP Pb-Free
KSZ8041FTLI(1) -40°C to 85°C 48-Pin TQFP Pb-Free
Note:
1. Contact factory for lead time.
Micrel, Inc. KSZ8041TL/FTL
April 2007 3 M9999-042707-1.1
Revision History
Revision Date Summary of Changes
1.0 12/21/06 Data sheet created.
1.1 4/27/07 Added maximum MDC clock speed.
Added 40K +/-30% to note 1 of Pin Descri pti on and Strapping Options tables for interna l pull-ups/pull-
downs.
Changed Model Number in Register 3 h – PHY Identifier 2.
Changed polarity (swapped definition) of DUPLEX strapping pin.
Removed DUPLEX strapping pin update to Register 4h – Auto-Negotiation Advertisement bits [8, 6].
Added Back-to-Back mode for KSZ8041TL.
Added Symbol Error to MII/RMII Receive Error description and Register 15h – RXER Counter.
Added a 100pF capacitor on REXT (pin 16) in Pin Description table.
Micrel, Inc. KSZ8041TL/FTL
April 2007 4 M9999-042707-1.1
Contents
Pin Configuration..................................................................................................................................................................8
Pin Description....................................................................................................................................................................10
Strapping Options...............................................................................................................................................................15
Functional Description.......................................................................................................................................................17
100Base-TX Transmit.......................................................................................................................................................17
100Base-TX Receive........................................................................................................................................................17
PLL Clock Synthesizer......................................................................................................................................................17
Scrambler/De-scrambler (100Base-TX only)....................................................................................................................17
10Base-T Transmit...........................................................................................................................................................17
10Base-T Receive............................................................................................................................................................18
SQE and Jabber Function (10Base-T only)......................................................................................................................18
Auto-Negotiation...............................................................................................................................................................18
MII Management (MIIM) Interface....................................................................................................................................20
Interrupt (INTRP)..............................................................................................................................................................20
MII Data Interface.............................................................................................................................................................20
MII Signal Definition..........................................................................................................................................................21
Transmit Clock (TXC).................................................................................................................................................21
Transmit Enable (TXEN).............................................................................................................................................21
Transmit Data [3:0] (TXD[3:0])...................................................................................................................................21
Receive Clock (RXC)..................................................................................................................................................21
Receive Data Valid (RXDV)........................................................................................................................................22
Receive Data [3:0] (RXD[3:0])....................................................................................................................................22
Receive Error (RXER).................................................................................................................................................22
Carrier Sense (CRS) ...................................................................................................................................................22
Collision (COL) ...........................................................................................................................................................22
Reduced MII (RMII) Data Interface...................................................................................................................................22
RMII Signal Definition.......................................................................................................................................................23
Reference Clock (REF_CLK) .....................................................................................................................................23
Transmit Enable (TX_EN)...........................................................................................................................................23
Transmit Data [1:0] (TXD[1:0])...................................................................................................................................23
Carrier Sense/Receive Data Valid (CRS_DV)...........................................................................................................23
Receive Data [1:0] (RXD[1:0])....................................................................................................................................23
Receive Error (RX_ER)...............................................................................................................................................23
Collision Detection.....................................................................................................................................................24
Serial MII (SMII) Data Interface........................................................................................................................................24
SMII Signal Definition .......................................................................................................................................................24
Clock Reference (CLOCK).........................................................................................................................................24
Sync Pulse (SYNC).....................................................................................................................................................24
Transmit Data and Control (TX) ................................................................................................................................24
Receive Data and Control (RX)..................................................................................................................................25
Collision Detection.....................................................................................................................................................26
HP Auto MDI/MDI-X..........................................................................................................................................................27
Straight Cable .............................................................................................................................................................27
Crossover Cable.........................................................................................................................................................28
LinkMD® Cable Diagnostics..............................................................................................................................................29
Access.........................................................................................................................................................................29
Usage...........................................................................................................................................................................29
Micrel, Inc. KSZ8041TL/FTL
April 2007 5 M9999-042707-1.1
Power Management..........................................................................................................................................................29
Power Saving Mode....................................................................................................................................................29
Power Down Mode......................................................................................................................................................29
Reference Clock Connection Options ..............................................................................................................................30
Reference Circuit for Power and Ground Connections....................................................................................................31
100Base-FX Fiber Operation (KSZ8041FTL only)...........................................................................................................32
Fiber Signal Detect.....................................................................................................................................................32
Far-End Fault...............................................................................................................................................................32
Back-to-Back Media Converter.........................................................................................................................................33
MII Back-to-Back Mode..............................................................................................................................................33
RMII Back-to-Back Mode............................................................................................................................................34
Register Map........................................................................................................................................................................35
Register Description...........................................................................................................................................................35
Absolute Maximum Ratings(1) ............................................................................................................................................43
Operating Ratings(2) ............................................................................................................................................................43
Electrical Characteristics(3) ................................................................................................................................................43
Timing Diagrams.................................................................................................................................................................45
MII SQE Timing (10Base-T) .............................................................................................................................................45
MII Transmit Timing (10Base-T).......................................................................................................................................46
MII Receive Timing (10Base-T)........................................................................................................................................47
MII Transmit Timing (100Base-TX) ..................................................................................................................................48
MII Receive Timing (100Base-TX) ...................................................................................................................................49
RMII Timing.......................................................................................................................................................................50
Auto-Negotiation Timing...................................................................................................................................................51
MDC/MDIO Timing ...........................................................................................................................................................52
Reset Timing.....................................................................................................................................................................53
Reset Circuit........................................................................................................................................................................54
Selection of Isolation Transformer....................................................................................................................................56
Selection of Reference Crystal..........................................................................................................................................56
Package Information...........................................................................................................................................................57
Micrel, Inc. KSZ8041TL/FTL
April 2007 6 M9999-042707-1.1
List of Figures
Figure 1. Auto-Negotiation Flow Chart.................................................................................................................................19
Figure 2. SMII Transmit Data/Control Segment...................................................................................................................25
Figure 3. SMII Receive Data/Control Segment....................................................................................................................26
Figure 4. Typical Straight Cable Connection .......................................................................................................................27
Figure 5. Typical Crossover Cable Connection ...................................................................................................................28
Figure 6. 25MHz Crystal / Oscillator Reference Clock for MII Mode...................................................................................30
Figure 7. 50MHz Oscillator Reference Clock for RMII Mode...............................................................................................30
Figure 8. 125MHz Oscillator Reference Clock for SMII Mode.............................................................................................30
Figure 9. KSZ8041TL/FTL Power and Ground Connections...............................................................................................31
Figure 10. KSZ8041FTL / KSZ8041TL Back-to-Back Media Converter..............................................................................33
Figure 11. MII SQE Timing (10Base-T) ...............................................................................................................................45
Figure 12. MII Transmit Timing (10Base-T).........................................................................................................................46
Figure 13. MII Receive Timing (10Base-T)..........................................................................................................................47
Figure 14. MII Transmit Timing (100Base-TX).....................................................................................................................48
Figure 15. MII Receive Timing (100Base-TX)......................................................................................................................49
Figure 16. RMII Timing – Data Received from RMII............................................................................................................50
Figure 17. RMII Timing – Data Input to RMII.......................................................................................................................50
Figure 18. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................................................................51
Figure 19. MDC/MDIO Timing..............................................................................................................................................52
Figure 20. Reset Timing.......................................................................................................................................................53
Figure 21. Recommended Reset Circuit..............................................................................................................................54
Figure 22. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output .....................................................54
Figure 23. Reference Circuits for LED Strapping Pins.........................................................................................................55
Micrel, Inc. KSZ8041TL/FTL
April 2007 7 M9999-042707-1.1
List of Tables
Table 1. MII Management Frame Format............................................................................................................................20
Table 2. MII Signal Definition...............................................................................................................................................21
Table 3. RMII Signal Description..........................................................................................................................................23
Table 4. SMII Signal Description..........................................................................................................................................24
Table 5. SMII TX Bit Description..........................................................................................................................................25
Table 6. SMII TXD[0:7] Encoding Table ..............................................................................................................................25
Table 7. SMII RX Bit Description..........................................................................................................................................26
Table 8. SMII RXD[0:7] Encoding Table..............................................................................................................................26
Table 9. MDI/MDI-X Pin Definition.......................................................................................................................................27
Table 10. KSZ8041TL/FTL Power Pin Description..............................................................................................................31
Table 11. Copper and Fiber Mode Selection.......................................................................................................................32
Table 12. MII Signal Connection for MII Back-to-Back Mode..............................................................................................33
Table 13. RMII Signal Connection for RMII Back-to-Back Mode.........................................................................................34
Table 14. MII SQE Timing (10Base-T) Parameters.............................................................................................................45
Table 15. MII Transmit Timing (10Base-T) Parameters ......................................................................................................46
Table 16. MII Receive Timing (10Base-T) Parameters .......................................................................................................47
Table 17. MII Transmit Timing (100Base-TX) Parameters..................................................................................................48
Table 18. MII Receive Timing (100Base-TX) Parameters...................................................................................................49
Table 19. RMII Timing Parameters......................................................................................................................................50
Table 20. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters...............................................................................51
Table 21. MDC/MDIO Timing Parameters...........................................................................................................................52
Table 22. Reset Timing Parameters ....................................................................................................................................53
Table 23. Transformer Selection Criteria.............................................................................................................................56
Table 24. Qualified Single Port Magnetics...........................................................................................................................56
Table 25. Typical Reference Crystal Characteristics...........................................................................................................56
Micrel, Inc. KSZ8041TL/FTL
April 2007 8 M9999-042707-1.1
Pin Configur ation
1
NC
NC
TXC
RST#
INTRP
REXT
GND
RXER / RX_ER /
ISO
GND
VDD_1.8
GND
GND
GND
GND
XO
VDDA_3.3
NC
TXD1 / TXD[1] /
SYNC
TXD0 / TXD[0] /
TX
TXEN /
TX_EN
LED1 /
SPEED
LED0 /
NWAYEN
CRS /
CONFIG1
NC
2
3
8
13 14 16 17
29
30
31
32
33
34
35
36
4142434445464748
RX+
TX-
RX-
9
10
11
GND
24
TXD3
TXD2
GND
COL /
CONFIG0
37383940
RXC
VDDIO_3.3
VDDIO_3.3
RXDV / CRSDV /
CONFIG2
25
26
27
28
RXD2 /
PHYAD1
RXD1 / RXD[1] /
PHYAD2
RXD0 / RXD[0] / RX
DUPLEX
21 22 23
MDIO
MDC
RXD3 /
PHYAD0
18 19 20
XI / REFCLK /
CLOCK
15
TX+
12
VDDA_1.8
VDDA_1.8
4
5
V1.8_OUT
VDDA_3.3
6
7
KSZ8041TL
48-Pin TQFP
Micrel, Inc. KSZ8041TL/FTL
April 2007 9 M9999-042707-1.1
1
NC
NC
TXC
RST#
INTRP
REXT
GND
RXER / RX_ER /
ISO
GND
VDD_1.8
GND
GND
GND
GND
XO
VDDA_3.3
FXSD /
FXEN
TXD1 / TXD[1] /
SYNC
TXD0 / TXD[0] /
TX
TXEN /
TX_EN
LED1 /
SPEED / no FEF
LED0 /
NWAYEN
CRS /
CONFIG1
NC
2
3
8
13 14 16 17
29
30
31
32
33
34
35
36
4142434445464748
RX+
TX-
RX-
9
10
11
GND
24
TXD3
TXD2
GND
COL /
CONFIG0
37383940
RXC
VDDIO_3.3
VDDIO_3.3
RXDV / CRSDV /
CONFIG2
25
26
27
28
RXD2 /
PHYAD1
RXD1 / RXD[1] /
PHYAD2
RXD0 / RXD[0] / RX
DUPLEX
21 22 23
MDIO
MDC
RXD3 /
PHYAD0
18 19 20
XI / REFCLK /
CLOCK
15
TX+
12
VDDA_1.8
VDDA_1.8
4
5
V1.8_OUT
VDDA_3.3
6
7
KSZ8041FTL
48-Pin TQFP
Micrel, Inc. KSZ8041TL/FTL
April 2007 10 M9999-042707-1.1
Pin Description
Pin Number Pin Name Type(1) Pin Function
1 GND Gnd Ground
2 GND Gnd Ground
3 GND Gnd Ground
4 VDDA_1.8 P 1.8V analog VDD
5 VDDA_1.8 P 1.8V analog VDD
6 V1.8_OUT P 1.8V output voltage from chip
7 VDDA_3.3 P 3.3V analog VDD
8 VDDA_3.3 P 3.3V analog VDD
9 RX- I/O Physical receive or transmit signal (- differential)
10 RX+ I/O Physical receive or transmit signal (+ differential)
11 TX- I/O Physical transmit or receive signal (- differential)
12 TX+ I/O Physical transmit or receive signal (+ differential)
13 GND Gnd Ground
14 XO O Crystal feedback
This pin is used only in MII mode when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or if RMII
mode or SMII mode is selected.
15 XI /
REFCLK /
CLOCK
I Crystal / Oscillator / External Clock Input
MII Mode: 25MHz +/-50ppm (crystal, oscillator, or external clock)
RMII Mode: 50MHz +/-50ppm (oscillator, or external clock only)
SMII Mode: 125MHz +/-100ppm (oscillator, or external clock only)
16 REXT I/O Set physical transmit output current
Connect a 6.49K resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041TL-FTL reference schematics.
17 GND Gnd Ground
18 MDIO I/O Management Interface (MII) Data I/O
This pin requires an external 4.7K pull-up resistor.
19 MDC I Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
20 RXD3 /
PHYAD0 Ipu/O MII Mode: Receive Data Output[3](2) /
Config Mode: The pull-up/pull-down value is latched as PHYADDR[0] during
power-up / reset. See “Strapping Options” section for details.
21 RXD2 /
PHYAD1 Ipd/O MII Mode: Receive Data Output[2](2) /
Config Mode: The pull-up/pull-down value is latched as PHYADDR[1] during
power-up / reset. See “Strapping Options” section for details.
22 RXD1 /
RXD[1] /
PHYAD2
Ipd/O MII Mode: Receive Data Output[1](2) /
RMII Mode: Receive Data Output[1](3) /
Config Mode: The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
Micrel, Inc. KSZ8041TL/FTL
April 2007 11 M9999-042707-1.1
Pin Number Pin Name Type(1) Pin Function
23 RXD0 /
RXD[0] /
RX
DUPLEX
Ipu/O MII Mode: Receive Data Output[0](2) /
RMII Mode: Receive Data Output[0](3) /
SMII Mode: Receive Data and Control(4) /
Config Mode: Latched as DUPLEX (register 0h, bit 8) during po wer-up /
reset. See “Strapping Options” section for details.
24 GND Gnd Ground
25 VDDIO_3.3 P 3.3V digital VDD
26 VDDIO_3.3 P 3.3V digital VDD
27 RXDV /
CRSDV /
CONFIG2
Ipd/O MII Mode: Receive Data Valid Output /
RMII Mode: Carrier Sense/Receive Data Valid Output /
Config Mode: The pull-up/pull-down value is latched as CONFIG2 during
power-up / reset. See “Strapping Options” section for details.
28 RXC O MII Mode: Receive Clock Output
29 RXER /
RX_ER /
ISO
Ipd/O MII Mode: Receive Error Output /
RMII Mode: Receive Error Output /
Config Mode: The pull-up/pull-down value is latched as ISOLATE during
power-up / reset. See “Strapping Options” section for details.
30 GND Gnd Ground
31 VDD_1.8 P 1.8V digital VDD
32 INTRP Opu Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for programming the
interrupt conditions and readi ng the interrupt status. Register 1Fh bit 9 sets the
interrupt output to active low (default) or active high.
33 TXC I/O MII Mode: Transmit Clock Output
MII Back-to Back Mode: Transmit Clock Input
34 TXEN /
TX_EN I MII Mode: Transmit Enable Input /
RMII Mode: Transmit Enable Input
35 TXD0 /
TXD[0] /
TX
I MII Mode: Transmit Data Input[0](5) /
RMII Mode: Transmit Data Input[0](6) /
SMII Mode: Transmit Data and Control(7)
36 TXD1 /
TXD[1] /
SYNC
I MII Mode: Transmit Data Input[1](5) /
RMII Mode: Transmit Data Input[1](6) /
SMII Mode: SYNC Clock Input
37 GND Gnd Ground
38 TXD2 I
MII Mode: Transmit Data Input[2](5) /
39 TXD3 I
MII Mode: Transmit Data Input[3](5) /
40 COL /
CONFIG0 Ipd/O MII Mode: Collision Detect Output /
Config Mode: The pull-up/pull-down value is latched as CONFIG0 during
power-up / reset. See “Strapping Options” section for details.
41 CRS /
CONFIG1 Ipd/O MII Mode: Carrier Sense Output /
Config Mode: The pull-up/pull-down value is latched as CONFIG1 during
power-up / reset. See “Strapping Options” section for details.
Micrel, Inc. KSZ8041TL/FTL
April 2007 12 M9999-042707-1.1
Pin Number Pin Name Type(1) Pin Function
42
(KSZ8041TL) LED0 /
NWAYEN Ipu/O LED Output: Programmable LED0 Output /
Config Mode: Latche d as Auto-Negotiation Enable (register 0h, bit 12)
during power-up / reset. See “Strapping Options” section for
details.
The LED0 pin is programmable via register 1Eh bits [15:14], and is define d as
follows.
LED mode = [00]
Link/Activity Pin State LED Definition
No Link H OFF
Link L ON
Activity Toggle Blinking
LED mode = [01]
Link Pin State LED Definition
No Link H OFF
Link L ON
LED mode = [10]
Reserved
LED mode = [11]
Reserved
42
(KSZ8041FTL) LED0 /
NWAYEN Ipu/O LED Output: Programmable LED0 Output /
Config Mode: If copper mode (F XEN=0), latched as Auto-Negotiation
Enable (register 0h, bit 12) during power-up / reset.
If fiber mode (FXEN=1), this pin configuration is always
strapped to disable Auto-Neg otiation.
See “Strapping Options” section for details.
The LED0 pin is programmable via register 1Eh bits [15:14], and is define d as
follows.
LED mode = [00]
Link/Activity Pin State LED Definition
No Link H OFF
Link L ON
Activity Toggle Blinking
LED mode = [01]
Link Pin State LED Definition
No Link H OFF
Link L ON
LED mode = [10]
Reserved
LED mode = [11]
Reserved
Micrel, Inc. KSZ8041TL/FTL
April 2007 13 M9999-042707-1.1
Pin Number Pin Name Type(1) Pin Function
43
(KSZ8041TL) LED1 /
SPEED Ipu/O LED Output: Programmable LED1 Output /
Config Mode: Latche d as SPEED (register 0h, bit 13) during power-up /
reset. See “Strapping Options” section for details.
The LED1 pin is programmable via register 1Eh bits [15:14], and is define d as
follows.
LED mode = [00]
Speed Pin State LED Definition
10BT H OFF
100BT L ON
LED mode = [01]
Activity Pin State LED Definition
No Activity H OFF
Activity Toggle Blinking
LED mode = [10]
Reserved
LED mode = [11]
Reserved
43
(KSZ8041FTL) LED1 /
SPEED /
no FEF
Ipu/O LED Output: Programmable LED1 Output /
Config Mode: If copper mode (FXEN=0), latched as SPEED (register 0h, bit
13) during power-up / reset.
If fiber mode (FXEN=1), latched as no FEF (no Far-End Fault)
during power-up / reset.
See “Strapping Options” section for details.
The LED1 pin is programmable via register 1Eh bits [15:14], and is define d as
follows.
LED mode = [00]
Speed Pin State LED Definition
10BT H OFF
100BT L ON
LED mode = [01]
Activity Pin State LED Definition
No Activity H OFF
Activity Toggle Blinking
LED mode = [10]
Reserved
LED mode = [11]
Reserved
44 NC - No connect
45 NC - No connect
46 NC - No connect
Micrel, Inc. KSZ8041TL/FTL
April 2007 14 M9999-042707-1.1
Pin Number Pin Name Type(1) Pin Function
47 RST# I Chip Reset (active low)
48
(KSZ8041TL)
NC - No connect
48
(KSZ8041FTL) FXSD /
FXEN Ipd FXSD: Signal Detect for 100Base-FX fiber mode
FXEN: Fiber Enable for 100Base-FX fiber mode
If FXEN=0, fiber mode is disabled. PHY is in copper mode. The default is “0”.
See “100Base-FX Operation” section for details.
Notes:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipd = Input with internal pull-down (40K +/-30%).
Ipu = Input with internal pull-up (40K +/-30%).
Opu = Output with internal pull-up (40K +/-30%).
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC through the MII.
RXD[3..0] is invalid when RXDV is de-asserted.
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of recovered
data are sent from the PHY.
4. SMII Rx Mode: Receive data and control information are sent in 10 bit segments. In 100MBit mode, each segment represents a new byte of
data. In 10MBit mode, each segment is repeated ten times; therefore, every ten segments represent a new byte of data. The MAC can sample
any one of every 10 segments in 10MBit mode.
5. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC through
the MII. TXD[3..0] has no effect when TXEN is de-asserted.
6. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are
received by the PHY from the MAC.
7. SMII Tx Mode: Transmit data and control information are received in 10 bit segments. In 100MBit mode, each segment represents a new byte
of data. In 10MBit mode, each segment is repeated ten times; therefore, ever y ten segments represent a new byte of data. The P H Y can
sample any one of every 10 segments in 10MBit mode.
Micrel, Inc. KSZ8041TL/FTL
April 2007 15 M9999-042707-1.1
Strapping Options
Pin Number Pin Name Type(1) Pin Function
22
21
20
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipd/O
Ipu/O
The PHY Address is latched at power-up / reset and is con figurable to any value from
1 to 7.
The default PHY Address is 00001.
PHY Address bits [4:3] are always set to ‘00’.
27
41
40
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as
follows:
CONFIG[2:0] Mode
000 MII (default)
001 RMII
010 SMII
011 Reserved – not used
100 PCS Loopback
101 RMII back-to-back
110 MII back-to-back
111 Reserved – not used
29 ISO Ipd/O ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
During power-up / reset, this pin value is latched into register 0h bit 10.
43
(KSZ8041TL) SPEED Ipu/O SPEED mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
During power-up / reset, this pin value is latched i nto register 0h bit 13 as the Speed
Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the
Speed capability support.
43
(KSZ8041FTL) SPEED /
no FEF
Ipu/O If copper mode (FXEN= 0), pin strap-in is SPEED mode.
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
During power-up / reset, this pin value is latched i nto register 0h bit 13 as the Speed
Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the
Speed capability support.
If fiber mode (FXEN=1), pin strap-in is no FEF.
Pull-up (default) = Enable Far-End Fault
Pull-down = Disable Far-End Fault
This pin value is latched during power-up / reset.
Micrel, Inc. KSZ8041TL/FTL
April 2007 16 M9999-042707-1.1
Pin Number Pin Name Type(1) Pin Function
23 DUPLEX Ipu/O DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
During power-up / reset, this pin value is latched i nto register 0h bit 8 as the Duplex
Mode.
42
(KSZ8041TL) NWAYEN Ipu/O Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiati on
During power-up / reset, this pin value is latched into register 0h bit 12.
42
(KSZ8041FTL) NWAYEN Ipu/O If copper mode (FXEN=0), pin strap-in is Nway Auto-Negotiation Enable.
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiati on
During power-up / reset, this pin value is latched into register 0h bit 12.
If fiber mode (FXEN=1), this pin configuration is always strapped to disable Auto-
Negotiation.
Note:
1. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII/SMII signals to be latched high. In this
case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to
ISOLATE or PCS Loopback mode, or is not co nfigured with an incorrect PHY Address.
Micrel, Inc. KSZ8041TL/FTL
April 2007 17 M9999-042707-1.1
Functional Description
The KSZ8041TL is a single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3u Specification.
On the media side, the KSZ8041TL supports 10Base-T and 100Base-TX with HP auto MDI/MDI-X for reliable detection of
and correction for straight-through and crossover cables.
The KSZ8041TL offers a choice of MII, RMII, or SMII data interface connection to a MAC processor. The MII management
bus option gives the MAC processor complete access to the KSZ8041TL control and status registers. Additionally, an
interrupt pin eliminates the need for the processor to poll for PHY status change.
Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the
design more efficient and allow for lower power consumption and smaller chip die size.
The KSZ8041FTL has all the identical rich featu res of the KSZ8041TL plus 100Base -FX fiber support.
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is
further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output.
The output current is set by an external 6.49 K 1% resistor for the 1:1 transformer ratio. It has typical rise/fall times of 4
ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The wave-
shaped 10Base-T output drivers are al so incorporated into the 100Base-TX drivers.
100Base-TX Receiv e
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based upon
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KSZ8041TL/FTL generates 125 MΗz, 25 MΗz and 20 MΗz clocks for system timing. Internal clocks are generated
from an external 25 MHz crystal or oscillator. In RMII mode, these internal clocks are generated from an external 50 MHz
oscillator or system clock.
Scrambler/De-scrambler (100Base-TX only )
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.
10Base-T Transmit
The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.
The drivers also perform internal wave-shaping and pre-emphasize, and output 10Base-T signals with a typical amplitude
of 2.5V peak. The 10Base-T signals have harmonic contents that are at least 27dB below the fundamental frequency
when driven by an all-ones Manchester-encoded signal.
Micrel, Inc. KSZ8041TL/FTL
April 2007 18 M9999-042707-1.1
10Base-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and
a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data.
A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to prevent noise at the RX+ and
RX- inputs from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming
signal and the KSZ8041TL/FTL decodes a data frame. The receive clock is kept active during idle periods in between
data reception.
SQE and Jabber Function (10Bas e-T only)
In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE Test is required
as a test of the 10Base-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the
10Base-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the 10Base-
T transmitter is re-enabled and COL is de-asserted (returns to low).
Auto-Negotiation
The KSZ8041TL/FTL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification.
Auto-negotiation is enabled by either hardware pin strapping (pin 30) or software (regi ster 0h bit 12).
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link
partners advertise their capabilities to each other, and then compare their own capabilities with those they received from
their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode
of operation.
The following list shows the spe ed and duplex operation mode from highe st to lowest.
Priority 1: 100Base-TX, full-duplex
Priority 2: 100Base-TX, half-duplex
Priority 3: 10Base-T, full-duplex
Priority 4: 10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ8041TL/FTL link partner is forced to bypass auto-negotiation, the
KSZ8041TL/FTL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and
allows the KSZ8041TL/FTL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation
advertisement protocol.
The auto-negotiation link up proce ss is shown in the following flow chart.
Micrel, Inc. KSZ8041TL/FTL
April 2007 19 M9999-042707-1.1
Start Auto Negotiat ion
Force Link Setting
Listen for 10BASE-T
Link Pulses
Listen for 100BASE-TX
Idles
A
ttempt Auto
Negotiation
Link Mode Set
Bypass Auto Negotiation
and Set Link Mode
Link Mode Set ?
Parallel
Operation
Join
Flow
N
o
Yes
Yes
No
Figure 1. Auto-Negotiation Flow Chart
Micrel, Inc. KSZ8041TL/FTL
April 2007 20 M9999-042707-1.1
MII Management (MIIM) Interface
The KSZ8041TL/FTL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input /
Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the
KSZ8041TL/FTL. An external device with MIIM capability is used to read the PHY status and/or configure the PHY
settings. Further detail on the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3u Specification.
The MIIM interface consists of the following:
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with one or more KSZ8041TL/FTL devices. Each KSZ8041TL/FTL device is assigned a PHY
address between 1 and 7 by the PHYAD[2:0] strappin g pins.
An internal addressable set of thirteen 16-bit MDIO registers. Register [0:6] are required, and their functions are
defined by the IEEE 802.3u Specification. The additional registers are provided for expanded functionality.
The KSZ8041TL/FTL supports MIIM in MII mode, RMII mode and SMII mode.
The following table shows the MII Manag ement frame format for the KSZ8041TL/FTL.
Preamble
Start of
Frame Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA Data
Bits [15:0]
Idle
Read 32 1’s 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z
Table 1. MII Management Frame Format
Interrupt (INTRP)
INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status
update in the KSZ8041TL/FTL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits, and are used to
enable and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits, and
are used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register
1Bh.
Bit 9 of register 1Fh sets the interrupt level to active high or active low.
MII Data Interface
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Specification. It provides a common
interface between physica l layer and MAC layer devices, and has the following key characteristics:
Supports 10Mbps and 100Mbps data rates.
Uses a 25 MHz reference clo ck, sourced by the PHY.
Provides independent 4-bit wide (nibble) transmit and receive data paths.
Contains two distinct groups of signals: one for transmission an d the other for reception.
By default, the KSZ8041TL/FTL is configured in MII mode after it is power-up or reset with the following:
A 25 MHz crystal connected to XI, XO (pins 15, 14), or an external 25MHz clock source (oscillator) connected to
XI.
CONFIG[2:0] (pins 27, 41, 40) set to ‘000’ (default setting).
Micrel, Inc. KSZ8041TL/FTL
April 2007 21 M9999-042707-1.1
MII Signal Definition
The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3u Specification for detailed information.
MII
Signal Name
Direction
(with respect to PHY,
KSZ8041TL/FTL signal)
Direction
(with respect to MAC) Description
TXC Output Input Transmit Clock
(2.5 MHz for 10Mbps; 25 MHz for 100Mbps)
TXEN Input Output Transmit Enable
TXD[3:0] Input Output Transmit Data [3:0]
RXC Output Input Receive Clock
(2.5 MHz for 10Mbps; 25 MHz for 100Mbps)
RXDV Output Input Receive Data Valid
RXD[3:0] Output Input Receive Data [3:0]
RXER Output Input, or (not required) Receive Error
CRS Output Input Carrier Sense
COL Output Input Collision Detection
Table 2. MII Signal Definition
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provide s the timing refe rence for TXEN and TXD[3:0].
TXC is 2.5MHz for 10Mbps ope ration and 25MHz for 100Mbps operation.
Transmit Enable (TXEN)
TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated
prior to the first TXC following the final nibble of a fram e.
TXEN transitions synchronously with respect to TXC.
Transmit Data [3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmission
by the PHY. TXD[3:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[3:0] while TXEN
is de-asserted are ignored by the PHY.
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
In 10Mbps mode, RXC is recovered from the line while carrier is active. RXC is derived from the PHY’s reference
clock when the line is idle, or link is down.
In 100Mbps mode, RXC is continuously recovered from the line. If link is down, RXC is derived from the PHY’s
reference clock.
RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbp s operation.
Micrel, Inc. KSZ8041TL/FTL
April 2007 22 M9999-042707-1.1
Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nib bles on RXD[3:0].
In 10Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), “5D”, and remains
asserted until the end of the frame.
In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
Receive Data [3:0] (RXD[3:0])
RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recov ered data from the PHY.
Receive Error (RXER)
RXER is asserted for one or more RXC periods to indicate that a Symbol Error (e.g. a coding error that a PHY is capable
of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame
presently being transferred from the PHY.
RXER transitions synchron ously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC.
Carrier Sense (CRS)
CRS is asserted and de-a sserted as follows:
In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the
reception of an end-of-frame (EOF) marker.
In 100Mbps mode, CRS is asserted when a start-of-stream delimiter, or /J/K symbol pair is detected. CRS is de-
asserted when an end-of-stream delimiter, or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts
CRS if IDLE symbols are received without /T/R.
Collision (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This is
used to inform the MAC that a collision has occurred during its transmission to the PHY.
COL transitions asynchronously with respect to TXC and RXC.
Reduced MII (RMII) Data Interface
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides
a common interface between physical layer and MAC layer devices, and has the following key characteristics:
Supports 10Mbps and 100Mbps data rates.
Uses a single 50 MHz reference clock provided by the MAC or the system board.
Provides independent 2-bit wide (di-bit) transmit and receive data paths.
Contains two distinct groups of signals: one for transmission an d the other for reception.
The KSZ8041TL/FTL is configured in RMII mode after it is power-u p or reset with the following:
A 50 MHz reference clock connected to REFCLK (pin 15).
CONFIG[2:0] (pins 27, 41, 40) set to ‘001’.
In RMII mode, unused MII signals, TXD[3:2] (pins 3 9, 38), are tied to ground.
Micrel, Inc. KSZ8041TL/FTL
April 2007 23 M9999-042707-1.1
RMII Signal Definition
The following table describes the RMII signals. Refer to RMII Specification for detailed information.
RMII
Signal Name
Direction
(with respect to PHY,
KSZ8041TL/FTL signal)
Direction
(with respect to MAC) Description
REF_CLK Input Input, or Output Synchronous 50 MHz clock reference for
receive, transmit and control interface
TX_EN Input Output Transmit Enable
TXD[1:0] Input Output Transmit Data [1:0]
CRS_DV Output Input Carrier Sense/Receive Data Valid
RXD[1:0] Output Input Receive Data [1:0]
RX_ER Output Input, or (not requir ed) Receive Error
Table 3. RMII Signal Description
Reference Clock (REF_C LK)
REF_CLK is sourced by the MAC or system board. It is a continuous 50 MHz clock that provides the timing reference for
TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and RX_ER.
Transmit Enable (TX_EN)
TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is negated
prior to the first REF_CLK following the final di-bit of a frame.
TX_EN transitions synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for
transmission by the PHY. TXD[1:0] is ”00” to indicate idle when TX_EN is de-asserted. Values other than “00” on TXD[1:0]
while TX_EN is de-asserted are ignored by the PHY.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of
carrier. This is when squelch is passed in 10Mbps mode, and when 2 non-contiguous zeroes in 10 bits are detected in
100Mbps mode. Loss of carrier results in the de-assertion of CRS _DV.
So long as carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered di-bit of the
frame through the final recovered di-bit, and it is negated prior to the first REF_CLK that follows the final di-bit. The data
on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] is "00" until proper receive signal decoding takes p lace.
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers
two bits of recovered data from the PHY. RXD[1:0] is "00" to indicate idle when CRS_DV is de-asserted. Values other
than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored b y the MAC.
Receive Error (RX_ER)
RX_ER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (e.g. a coding error that a PHY is
capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the
frame presently being transferred from the PHY.
RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the
MAC.
Micrel, Inc. KSZ8041TL/FTL
April 2007 24 M9999-042707-1.1
Collision Detection
The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV.
Serial MII (SMII) Data Interface
The Serial Media Independent Interface (SMII) is the lowest pin count Media Independent Interface (MII). It provides a
common interface between physical layer and MAC layer devices, and has the following key characteristics:
Supports 10Mbps and 100Mbps data rates.
Uses 125 MHz reference clock provided by the MAC or the system board.
Uses 12.5 MHz sync pulse provided by the MAC.
Provides independent single-bit wide transmit and receive data paths for data and control information.
The KSZ8041TL/FTL is configured in SMII mode after it is power-u p or reset with the following:
A 125 MHz reference clock connecte d to CLOCK (pin 15).
A 12.5 MHz sync pulse connected to SYNC (pin 36).
CONFIG[2:0] (pins 27, 41, 40) set to ‘010’.
In SMII mode, unused MII signals, TXD[3:2] (pins 39, 38), are tied to grou nd.
SMII Signal Definition
The following table describes the SMII signals. Refer to SMII Specification for detailed information.
SMII
Signal Name
Direction
(with respect to PHY,
KSZ8041TL/FTL signal)
Direction
(with respect to MAC) Description
CLOCK Input Input, or Output 125 MHz clock reference for receive and
transmit data and control
SYNC Input Output 12.5 MHz sync pulse from MAC
TX Input Output Transmit Data and Control
RX Output Input Receiv e Data and Control
Table 4. SMII Signal Description
Clock Reference (CLOCK)
CLOCK is sourced by the MAC or system board. It is a continuous 125 MHz clock that provides the timing reference for
SYNC, TX, and RX.
Sync Pulse (SYNC)
SYNC is a 12.5 MHz synchronized pulse derived from CLOCK by the MAC. It is used to indicate the segment boundary
for each transmit data/control segment, or receive data/ control segment. Each segment is comprised of ten bits.
SYNC is generated continuou sly by the MAC at every ten cycles of CLOCK.
Transmit Data and Control (TX)
TX provides transmit data and control information from MAC-to -PHY in 10-bit segments.
In 10Mbps mode, each segment is repeated ten times. Therefore, every ten segments represent a new byte of
data. The PHY can sample any one of every ten segments.
In 100Mbps mode, each segment represents a new byte of data.
Micrel, Inc. KSZ8041TL/FTL
April 2007 25 M9999-042707-1.1
The following figure and table shows the transmit data/control format for each segment:
TX_ER TX_EN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7
CLOCK
SYNC
TX
Figure 2. SMII Transmit Data/Control Segment
SMII TX Bit Description
TX_ER Transmit Error
TX_EN Transmit Enable
TXD[0:7] Encoded Data
See SMII TXD[0:7] Encoding Table (below)
Table 5. SMII TX Bit Description
TX_ER TX_EN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7
X 0 Use to
force an
error in a
direct
MAC-to-
MAC
connection
Speed
0=10M
1=100M
Duplex
0=Half
1=Full
Link
0=Down
1=Up
Jabber
0=No
1=Yes
1 1 1
X 1 One Data Byte
Table 6. SMII TXD[0:7] Encoding Table
Receive Data and Control (RX)
RX provides receive data and control information from PHY-to-MAC in 10-bit segments.
In 10Mbps mode, each segment is repeated ten times. Therefore, every ten segments represent a new byte of
data. The MAC can sample any one of every ten segments.
In 100Mbps mode, each segment represents a new byte of data.
Micrel, Inc. KSZ8041TL/FTL
April 2007 26 M9999-042707-1.1
The following figure and table shows the receive data/control format for each segment:
CRS RX_DV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7
CLOCK
SYNC
RX
Figure 3. SMII Receive Data/Cont rol Segment
SMII RX Bit Description
CRS Carrier Sense
RX_DV Receive Data Valid
RXD[0:7] Encoded Data
See SMII RXD[0:7] Encoding Table (below)
Table 7. SMII RX Bit Description
CRS RX_DV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7
X 0 RX_ER
from
pervious
frame
Speed
0=10M
1=100M
Duplex
0=Half
1=Full
Link
0=Down
1=Up
Jabber
0=No
1=Yes
Upper
Nibble
0=Invalid
1=Valid
False
Carrier
Detected
1
X 1 One Data Byte
Table 8. SMII RXD[0:7] Encoding Table
Collision Detection
Collisions occur when CRS and TX_EN are simultaneously asserted. The MAC regenerates the MII collision signal from
CRS and TX_EN.
Micrel, Inc. KSZ8041TL/FTL
April 2007 27 M9999-042707-1.1
HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable
between the KSZ8041TL/FTL and its link partner. This feature allows the KSZ8041TL/FTL to use either type of cable to
connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive
pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8041TL/FTL accordingly.
HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a one to register 1F bit 13. MDI and MDI-X mode is
selected by register 1F bit 14 if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support auto MDI/MDI-X.
The IEEE 802.3u Standard defines MDI and MDI-X as follow:
MDI MDI-X
RJ-45 Pin Signal RJ-45 Pin Signal
1 TD+ 1 RD+
2 TD- 2 RD-
3 RD+ 3 TD+
6 RD- 6 TD-
Table 9. MDI/MDI-X Pin Definition
Straight Cable
A straight cable connects a MDI device to a MDI-X device, or a MDI-X device to a MDI device. The following diagram
depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
Receive PairTransmit Pair
Receive Pair
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Transmit Pair
Modular Connector
(RJ-45)
NIC
Straight
Cable
10/100 Ethernet
Media Dependent Interface 10/100 Ethernet
Media Dependent Interface
Modular Connector
(RJ-45)
HUB
(Repeater or Switch)
Figure 4. Typical Straight Cable Connection
Micrel, Inc. KSZ8041TL/FTL
April 2007 28 M9999-042707-1.1
Crossover Cable
A crossover cable connects a MDI device to another MDI device, or a MDI-X device to another MDI-X device. The
following diagram depict s a typical crossover cable connect ion between two switches or hu bs (two MDI-X devices).
Receive Pair Receive Pair
Transmit Pair
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Transmit Pair
10/100 Ethernet
Media Dependent Interface 10/100 Ethernet
Media Dependent Interface
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
Crossover
Cable
Figure 5. Typical Crossover Cable Connection
Micrel, Inc. KSZ8041TL/FTL
April 2007 29 M9999-042707-1.1
LinkMD® Cable Diagnostics
The LinkMD® feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems,
such as open circuits, short circuits and im pedance mismatches.
LinkMD® works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs, and then analyzing
the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with
maximum distance of 200m and accuracy of +/-2m. Internal circuitry computes the TDR information and presents it in a
user-readable digital format.
Note: Cable diagnostics are only valid for copper connections and do not support fiber o ptic operation.
Access
LinkMD® is initiated by accessing register 1Dh, the LinkMD® Control/Status Register, in conjunction with register 1Fh, the
PHY Control 2 Register.
Usage
The following test procedure demon strates how to use LinkMD® for cable diagn ostic:
1. Disable auto MDI/MDI-X by writing a ‘1’ to register 1Fh bit 13 to enable manual control over the differential pair
used to transmit the LinkMD® pulse.
2. Select the differential pair to transmit the LinkMD® pulse with register 1Fh bit 14.
3. Start cable diagnostic test by writing a ‘1’ to register 1Dh bit 15. This enable bit is self-clea ring.
4. Wait (poll) for register 1Dh bit 15 to return a ‘0’, indicating cable dia gnostic test is completed.
5. Read cable diagnostic test results in register 1Dh bits [14:13]. The results are a s follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs if the KSZ8041TL/FTL is unable to shut down the link partner. In this instance,
the test is not run, since it would be impossible for the KSZ8041TL/FTL to determine if the detected signal is a
reflection of the signal generated by the KSZ8041TL/FTL, or a si gnal from its link partner.
6. Get distance to fault by multiplying the decimal value in register 1Dh bits [8:0] by a constant of 0.4. The distance,
D (expressed in meters), to the cable fault is determined by the following formula:
D (distance to cable fault) = 0.4 x {decimal value of register 1Dh bits [8:0]}
The 0.4 constant can be calibrated for different cable types and cabling conditions, such a s cables with velocity of
propagation that varies significantly fro m the norm.
Power Management
The KSZ8041TL/FTL offers the following power man agement modes:
Power Saving Mode
This mode is used to reduce power consumption when the cable is unplugged. It is in effect when auto-negotiation mode
is enabled, cable is disconnected, and register 1Fh bit 10 is set to 1 (default setting). Under power saving mode, the
KSZ8041TL/FTL shuts down all transceiver blocks, except for energy detect and PLL circuits. Additionally, in MII mode,
the RXC clock output is disabled. RXC clock is enabled after the cable is conn ected and link is established.
Power saving mode is disabled by writing a zero to register 1Fh bit 10.
Power Down Mode
This mode is used to power down the entire KSZ8041TL/FTL device when it is not in use. Power down mode is enabled
by writing a one to register 0h bit 11. In the power down state, the KSZ8041TL/FTL disables all internal functions, except
for the MII management interface.
Micrel, Inc. KSZ8041TL/FTL
April 2007 30 M9999-042707-1.1
Reference Clock Connection Options
A crystal or clock source, such as an oscillator, is used to provide the reference clock for the KSZ8041TL/FTL. The
reference clock is 25 MHz for MII mode, 50 MHz for RMII mode, and 125 MHz for SMII mode. The following three figures
illustrate how to connect the referen ce clock to XI / REFCLK / CLOCK (pin 9) and XO (pin 8) of the KSZ8041TL/FTL.
25MHz OSC
+/-50ppm
NC
NC
XI
XO
XI
XO
22pF
22pF
22pF
22pF
25MHz XTAL
+/-50ppm
Figure 6. 25MHz Crystal / Oscillator Reference Clock for MII Mode
Figure 7. 50MHz Oscillator Reference Clock for RMII Mode
125MHz OSC
+/-100ppm
NC
NC
CLOCK
XO
Figure 8. 125MHz Oscillator Reference Clock for SMII Mode
Micrel, Inc. KSZ8041TL/FTL
April 2007 31 M9999-042707-1.1
Reference Circuit for Power and Ground Connections
The KSZ8041TL/FTL is a single 3.3V supply device with a built-in 1.8V low noise regulator. The power and ground
connections are shown in the following figure and table.
Figure 9. KSZ8041TL/FTL Power and Ground Connections
Power Pin Pin Number Pin Type Description
V1.8_OUT 6 Output 1.8V supply output from KSZ8041TL/FTL
Decouple with 22uF and 0.1uF capacitors-to-ground.
VDD_1.8 31 Input Connect to V1.8_OUT (pin 6) thru ferrite bead.
Decouple with 0.1uF capacitor-to-ground.
VDDA_1.8 4, 5 Input Connect to V1.8_OUT (pin 6) thru ferrite bead.
Decouple with 0.1uF capacitor on each pin-to-ground.
VDDIO_3.3 25, 26 Input Connect to board’s 3.3V supply.
Decouple with 22uF and 0.1uF capacitors-to-ground.
VDDA_3.3 7, 8 Input Connect to board’s 3.3V supply thru ferrite bead.
Decouple with 22uF and 0.1uF capacitors-to-ground.
Table 10. KSZ8041TL/FTL Power Pin Description
Micrel, Inc. KSZ8041TL/FTL
April 2007 32 M9999-042707-1.1
100Base-FX Fiber Operation (KSZ8041FTL only)
100Base-FX fiber operation is similar to 100Base-TX copper operation with the differences being that the scrambler/de-
scrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In addition, auto-negotiation is
bypassed, auto MDI/MDI-X is disabled, and speed is set to 100Mbps. The duplex can be set to either half or full. Usually,
it is set to full-duplex.
Fiber Signal Detect
In 100Base-FX operation, FXSD (fiber signal detect), input pin 48, is usually connected to the fiber transceiver SD (signal
detect) output pin. 100Base-FX mode is activated when the FXSD input pin is greater than 1V. When FXSD is between
1V and 1.8V, no fiber signal is detected and a Far-End Fault is generated. When FXSD is over 2.2V, the fiber signal is
detected.
100Base-FX mode and signal detection is summarized in the following table:
FXSD Input Voltage Mode
Less than 0.2V Copper mode
Greater than 1V, but less than 1.8V Fiber mode
No signal detected
Far-End Fault generated (if enabl ed)
Greater than 2.2V Fiber mode
Signal detected
Table 11. Copper and Fiber Mode Selection
To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD (signal detect)
output voltage swing to match the FXSD pin’s input voltage threshold.
Alternatively, the Far-End Fault feature can be disabled. In this case, the FXSD input pin is tied high to 3.3V to force
100Base-FX mode.
Far-End Fault
A Far-End Fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The
KSZ8041FTL detects a FEF when its FXSD input (pin 48) is between 1V and 1.8V. When a FEF is detected, the
KSZ8041FTL signals its fiber link partner that a FEF has occurred by transmitting a repetitive pattern of 84-ones and 1-
zero. This pattern is used to inform the fiber link partner that there is a faulty link on its transmit side.
By default, FEF is enabled. FEF is disabled by strapping “no FEF (pin 43) low. See “Strapping Options” section for detail.
Micrel, Inc. KSZ8041TL/FTL
April 2007 33 M9999-042707-1.1
Back-to-Back Media Converter
A KSZ8041FTL and a KSZ8041TL can be connected back-to-back to provide a low cost media converter solution. In
back-to-back mode, media conversion is between 100Base-FX fiber and 100Base-TX copper. On the copper side, link up
at 10Base-T is not allowed, and is bloc ked during auto-negotiation.
Figure 10. KSZ8041FTL / KSZ8041TL Back-to-Back Media Converter
The KSZ8041FTL and KSZ8041TL support MII Back-to-Ba ck mode and RMII Back-to-Back mode for me dia conversion.
MII Back-to-Back Mode
The KSZ8041FTL and KSZ8041TL are configure d in MII Back-to-Back mode after it is power-up or reset with the following:
CONFIG[2:0] (pins 27, 41, 40) set to ‘110’ for both KSZ8041FTL and KSZ8041T L.
A common 25 MHz reference clock connected to XI (pin 15) of both KSZ8041FTL and KSZ8041TL.
MII signals connected as shown in the following table between KSZ8041FTL in fiber mode and KSZ8041TL in
copper mode.
KSZ8041FTL in fiber mode KSZ8041TL in copper mode
Pin Name Pin Number Pin Type Pin Name Pin Number Pin Type
RXC 28 Output TXC 33 Input
RXDV 27 Output TXEN 34 Input
RXD3 20 Output TXD3 39 Input
RXD2 21 Output TXD2 38 Input
RXD1 22 Output TXD1 36 Input
RXD0 23 Output TXD0 35 Input
TXC 33 Input RXC 28 Output
TXEN 34 Input RXDV 27 Output
TXD3 39 Input RXD3 20 Output
TXD2 38 Input RXD2 21 Output
TXD1 36 Input RXD1 22 Output
TXD0 35 Input RXD0 23 Output
Table 12. MII Signal Connection for MII Back-to-Back Mode
Micrel, Inc. KSZ8041TL/FTL
April 2007 34 M9999-042707-1.1
RMII Back-to-Back M ode
The KSZ8041FTL and KSZ8041TL are configured in RMII Back-to-Back mode after it is power-up or reset with the
following:
CONFIG[2:0] (pins 27, 41, 40) set to ‘101’ for both KSZ8041FTL and KSZ8041T L.
A common 50 MHz reference clock connected to REFCLK (pin 15) of both KSZ8041FTL and KSZ8041TL.
RMII signals connected as shown in the following table between KSZ8041FTL in fiber mode and KSZ8041TL in
copper mode.
KSZ8041FTL in fiber mode KSZ8041TL in copper mode
Pin Name Pin Number Pin Type Pin Name Pin Number Pin Type
CRSDV 27 Output TXEN 34 Input
RXD1 22 Output TXD1 36 Input
RXD0 23 Output TXD0 35 Input
TXEN 34 Input CRSDV 27 Output
TXD1 36 Input RXD1 22 Output
TXD0 35 Input RXD0 23 Output
Table 13. RMII Signal Connection for RMII Back-to-Back Mode
RMII Back-to-Back mode provides the option to disable and tri-state the transmitter on both copper and fiber sides if the
cable is disconnected on the copper side. On the copper side, RXD2 (pin 21) indicates if there is energy detected at the
receive inputs of the UTP port. RXD2 outputs a low if there is no energy detected (cable disconnected), and outputs a
high if the re is energy detec ted (cable connected) . The RXD2 output is connec ted thru an inverter to drive T XD2 (pin 38)
input high to disable and tri-state the transmitters for both copper and fiber sides.
The TXD3 and TXD2 pins should be pulled down with 1K resistors, and RXD3 and RXD2 pins should be left floating, if
they are not used.
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April 2007 35 M9999-042707-1.1
Register Map
Register Number (Hex) Description
0h Basic Control
1h Basic Status
2h PHY Identifier 1
3h PHY Identifier 2
4h Auto-Negotiation Advertisement
5h Auto-Negotiation Link Partner Ability
6h Auto-Negotiation Expansion
7h Auto-Negotiation Next Page
8h Link Partner Next Page Ability
9h – 14h Reserved
15h RXER Counter
16h – 1Ah Reserved
1Bh Interrupt Control/Status
1Ch Reserved
1Dh LinkMD® Control/Status
1Eh PHY Control 1
1Fh PHY Control 2
Register Description
Address Name Description Mode(1) Default
Register 0h – Basic Cont ro l
0.15 Reset 1 = Software reset
0 = Normal operation
This bit is self-cleared after a ‘1’ is written to it.
RW/SC 0
0.14 Loop-back 1 = Loop-back mode
0 = Normal operation RW 0
0.13 Speed Select
(LSB) 1 = 100Mbps
0 = 10Mbps
This bit is ignored if auto-negotiation is enabled
(register 0.12 = 1).
RW Set by SPEED strapping pin.
See “Strapping Options” section
for details.
0.12 Auto-
Negotiation
Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
If enabled, auto-negotiation result overrides
settings in register 0.13 and 0.8.
RW Set by NWAYEN strapping pin.
See “Strapping Options” section
for details.
0.11 Power Down 1 = Power do wn mode
0 = Normal operation RW 0
0.10 Isolate 1 = Electrical isolation of PHY from MII and
TX+/TX-
0 = Normal operation
RW Set by ISO strapping pin.
See “Strapping Options” section
for details.
0.9 Restart Auto-
Negotiation 1 = Restart auto-negotiation process
0 = Normal operation.
This bit is self-cleared after a ‘1’ is written to it.
RW/SC 0
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April 2007 36 M9999-042707-1.1
Address Name Description Mode(1) Default
0.8 Duplex Mode 1 = Full-duplex
0 = Half-duplex RW Set by DUPLEX strapping pin.
See “Strapping Options” section
for details.
0.7 Collision Test 1 = Enable COL test
0 = Disable COL test RW 0
0.6:1 Reserved RO 000_000
0.0 Disable
Transmitter 0 = Enable transmitter
1 = Disable transmitter RW 0
Register 1h – Basic Status
1.15 100Base-T4 1 = T4 capable
0 = Not T4 capable RO 0
1.14 100Base-TX
Full Duplex 1 = Capable of 100Mbps full-duplex
0 = Not capable of 100Mbps full-duplex RO 1
1.13 100Base-TX
Half Duplex 1 = Capable of 100Mbps half-duplex
0 = Not capable of 100Mbps half-duplex RO 1
1.12 10Base-T Full
Duplex 1 = Capable of 10Mbps full-duplex
0 = Not capable of 10Mbps full-duplex RO 1
1.11 10Base-T Half
Duplex 1 = Capable of 10Mbps half-duplex
0 = Not capable of 10Mbps half-duplex RO 1
1.10:7 Reserved RO 0000
1.6 No Preamble 1 = Preamble s uppression
0 = Normal preamble RO 1
1.5 Auto-
Negotiation
Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed RO 0
1.4 Remote Fault 1 = Remote fault
0 = No remote fault RO/LH 0
1.3 Auto-
Negotiation
Ability
1 = Capable to perform auto-negoti ation
0 = Not capable to perform auto-negotiation RO 1
1.2 Link Status 1 = Link is up
0 = Link is down RO/LL 0
1.1 Jabber Detect 1 = Jabber detected
0 = Jabber not detected (default is low) RO/LH 0
1.0 Extended
Capability 1 = Supports extended capabi lities registers RO 1
Register 2h – PHY Identifier 1
2.15:0 PHY ID
Number Assigned to the 3rd through 18th bits of the
Organizationally Unique Identifier (OUI).
Kendin Communication’s OUI is 0010A1 (hex)
RO 0022h
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April 2007 37 M9999-042707-1.1
Address Name Description Mode(1) Default
Register 3h – PHY Identifier 2
3.15:10 PHY ID
Number Assigned to the 19th through 24th bits of the
Organizationally Unique Identifier (OUI).
Kendin Communication’s OUI is 0010A1 (hex)
RO 0001_01
3.9:4 Model Number Six bit manufacturer’s model number RO 01_0001
3.3:0 Revision
Number Four bit manufacturer’s model number RO 0010
Register 4h – Auto-Negotiatio n Advertisement
4.15 Next Page 1 = Next page capable
0 = No next page capabi lity. RW 0
4.14 Reserved RO 0
4.13 Remote Fault 1 = Remote fault supported
0 = No remote fault RW 0
4.12:11 Reserved RO 00
4.10 Pause 1 = PAUSE function supported
0 = No PAUSE function supported RW 0
4.9 100Base-T4 1 = T4 capable
0 = No T4 capability RO 0
4.8 100Base-TX
Full-Duplex 1 = 100Mbps full-dupl ex capable
0 = No 100Mbps full-duple x capability RW Set by SPEED strapping pin.
See “Strapping Options” section
for details.
4.7 100Base-TX
Half-Duplex 1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duple x capability RW Set by SPEED strapping pin.
See “Strapping Options” section
for details.
4.6 10Base-T
Full-Duplex 1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex cap ability RW 1
4.5 10Base-T
Half-Duplex 1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability RW 1
4.4:0 Selector Field [00001] = IEEE 802.3 RW 0_0001
Register 5h – Auto-Negotiation Link Partner Ability
5.15 Next Page 1 = Next page capable
0 = No next page capability RO 0
5.14 Acknowledge 1 = Link code word received from partner
0 = Link code word not yet received RO 0
5.13 Remote Fault 1 = Remote fault detected
0 = No remote fault RO 0
5.12 Reserved RO 0
5.11:10 Pause [00] = No PAUSE
[10] = Asymmetric PAUSE
[01] = Symmetric PAUSE
[11] = Asymmetric & Symmetric PAUSE
RO 00
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April 2007 38 M9999-042707-1.1
Address Name Description Mode(1) Default
5.9 100Base-T4 1 = T4 capable
0 = No T4 capability RO 0
5.8 100Base-TX
Full-Duplex 1 = 100Mbps full-dupl ex capable
0 = No 100Mbps full-duple x capability RO 0
5.7 100Base-TX
Half-Duplex 1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duple x capability RO 0
5.6 10Base-T
Full-Duplex 1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex cap ability RO 0
5.5 10Base-T
Half-Duplex 1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability RO 0
5.4:0 Selector Field [00001] = IEEE 802.3 RO 0_0001
Register 6h – Auto-Negotiation Expansion
6.15:5 Reserved RO 0000_0000_000
6.4 Parallel
Detection Fault 1 = Fault detected by parallel detection
0 = No fault detected by parallel detection. RO/LH 0
6.3 Link Partner
Next Page
Able
1 = Link partner has next page capa bility
0 = Link partner does not have next page
capability
RO 0
6.2 Next Page
Able 1 = Local device has next page capa bility
0 = Local device does not have next page
capability
RO 1
6.1 Page Received 1 = New page received
0 = New page not received yet RO/LH 0
6.0 Link Partner
Auto-
Negotiation
Able
1 = Link partner has auto-negotiation capa bility
0 = Link partner does not have auto-neg otiation
capability
RO 0
Register 7h – Auto-Negotiatio n Next Page
7.15 Next Page 1 = Additional next page(s) will follow
0 = Last page RW 0
7.14 Reserved RO 0
7.13 Message Page 1 = Message page
0 = Unformatted page RW 1
7.12 Acknowledge2 1 = Will comply with message
0 = Cannot comply with message RW 0
7.11 Toggle 1 = Previous value of the transmitted link code
word equaled logic one
0 = Logic zero
RO 0
7.10:0 Message Field 11-bit wide field to encode 2048 messages RW 000_0000_0001
Register 8h – Link Partn er Next Pag e Ability
8.15 Next Page 1 = Additional Next Page(s) will follow
0 = Last page RO 0
Micrel, Inc. KSZ8041TL/FTL
April 2007 39 M9999-042707-1.1
Address Name Description Mode(1) Default
8.14 Acknowledge 1 = Successful receipt of link word
0 = No successful receipt of link word RO 0
8.13 Message Page 1 = Message page
0 = Unformatted page RO 0
8.12 Acknowledge2 1 = Able to act on the information
0 = Not able to act on the information RO 0
8.11 Toggle 1 = Previous value of transmitted link code
word equal to logic zero
0 = Previous value of transmitted link code
word equal to logic one
RO 0
8.10:0 Message Field RO 000_0000_0000
Register 15h – RXER Counter
15.15:0 RXER Counter Receive error counter for Symbol Error frame s RO/SC 0000h
Register 1Bh – Interrup t Con t rol/Status
1b.15 Jabber
Interrupt
Enable
1 = Enable Jabber Interrupt
0 = Disable Jabber Interrupt RW 0
1b.14 Receive Error
Interrupt
Enable
1 = Enable Receive Error Interrupt
0 = Disable Receive Error Interrupt RW 0
1b.13 Page Received
Interrupt
Enable
1 = Enable Page Received Interrupt
0 = Disable Page Receive d Interrupt RW 0
1b.12 Parallel Detect
Fault Interrupt
Enable
1 = Enable Parallel Detect Fault Interrupt
0 = Disable Parallel Detect Fault Interrupt RW 0
1b.11 Link Partner
Acknowledge
Interrupt
Enable
1 = Enable Link Partner Acknowledge Interrupt
0 = Disable Link Partner Acknowledge
Interrupt
RW 0
1b.10 Link Down
Interrupt
Enable
1 = Enable Link Down Interrupt
0 = Disable Link Do wn Interrupt RW 0
1b.9 Remote Fault
Interrupt
Enable
1 = Enable Remote Fault Interrupt
0 = Disable Remote Fault Interrupt RW 0
1b.8 Link Up
Interrupt
Enable
1 = Enable Link Up Interrupt
0 = Disable Link Up Interrupt RW 0
1b.7 Jabber
Interrupt 1 = Jabber occurred
0 = Jabber did not occurred RO/SC 0
1b.6 Receive Error
Interrupt 1 = Receive Error occurred
0 = Receive Error did not occurred RO/SC 0
1b.5 Page Receive
Interrupt 1 = Page Receive occurred
0 = Page Receive did not occurred RO/SC 0
1b.4 Parallel Detect
Fault Interrupt 1 = Parallel Detect Fault occurred
0 = Parallel Detect Fault did not occurred RO/SC 0
Micrel, Inc. KSZ8041TL/FTL
April 2007 40 M9999-042707-1.1
Address Name Description Mode(1) Default
1b.3 Link Partner
Acknowledge
Interrupt
1 = Link Partner Acknowledge occurred
0 = Link Partner Acknowledge did not occurred RO/SC 0
1b.2 Link Down
Interrupt 1 = Link Down occurred
0 = Link Down did not occurred RO/SC 0
1b.1 Remote Fault
Interrupt 1 = Remote F ault occurred
0 = Remote Fault did not occurred RO/SC 0
1b.0 Link Up
Interrupt 1 = Link Up occurred
0 = Link Up did not occurred RO/SC 0
Register 1Dh – LinkMD® Control/Status
1d.15 Cable
Diagnostic
Test Enable
1 = Enable cable diagnostic test. After test
has completed, this bit is self-cleared.
0 = Indicates cable diagnostic test (if enable d)
has completed and the status information
is valid for read.
RW/SC 0
1d.14:13 Cable
Diagnostic
Test Result
[00] = normal condition
[01] = open condition has been detected in
cable
[10] = short condition has been detected in
cable
[11] = cable diagnostic test has failed
RO 00
1d.12:9 Reserved 0000
1d.8:0 Cable Fault
Counter Distance to fault; it’s approximatel y
0.4m*(Cable Fault Counter value in decimal) RO 0_0000_0000
Register 1Eh – PHY Con t rol 1
1e.15:14 LED mode [00] = LED1 : Speed
LED0 : Link/Activity
[01] = LED1 : Activity
LED0 : Link
[10] = Reserved
[11] = Reserved
RW 00
1e.13 Polarity 0 = Polarity is not reversed
1 = Polarity is reversed RO
1e.12 Far-End Fault
Detect 0 = Far-End Fault not detected
1 = Far-End Fault detected
This bit applies to KSZ8041FTL fiber on ly.
RO 0
1e.11 MDI/MDI-X
State 0 = MDI
1 = MDI-X RO
1e.10:8 Reserved
1e.7 Remote
loopback 0 = Normal mode
1 = Remote (analog) loop back is enab le RW 0
1e.6:0 Reserved
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April 2007 41 M9999-042707-1.1
Address Name Description Mode(1) Default
Register 1Fh – PHY Cont rol 2
1f.15 HP_MDIX 0 = Micrel Auto MDI/MDI-X mode
1 = HP Auto MDI/MDI-X mode RW 1
1f.14 MDI/MDI-X
Select When Auto MDI/MDI-X is disabled,
0 = MDI Mode
Transmit on TX+/- (pins 12,11) and
Receive on RX+/ - (pins 10,9)
1 = MDI-X Mode
Transmit on RX+/- (pins 10,9) and
Receive on TX+/- (pins 12,11)
RW 0
1f.13 Pairswap
Disable 1 = Disable auto MDI/MDI-X
0 = Enable auto MDI/MDI-X RW 0
1f.12 Energy Detect
1 = Presence of signal on RX+/- analo g wire
pair
0 = No signal detected on RX+/ -
RO 0
1f.11 Force Link 1 = Force link pass
0 = Normal link operation
This bit bypasses the control logic and allow
transmitter to send pattern even if there is no
link.
RW 0
1f.10 Power Saving 1 = Enable power saving
0 = Disable power saving
If power saving mode is enabled and the cable
is disconnected, the RXC clock output (in MII
mode) is disabled. RXC clock is enable d afte r
the cable is connected and link is established.
RW 0
1f.9 Interrupt Level 1 = Interrupt pin active high
0 = Interrupt pin active low RW 0
1f.8 Enable Jabber 1 = Enable jabber counter
0 = Disable jabber counter RW 1
1f.7 Auto-
Negotiation
Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed RO 0
1f.6 Enable Paus e
(Flow Control) 1 = F low control capable
0 = No flow control capabilit y RO 0
1f.5 PHY Isolate 1 = PHY in isolate mode
0 = PHY in normal operation RO 0
1f.4:2 Operation
Mode
Indication
[000] = still in auto-negotiation
[001] = 10Base-T half-duplex
[010] = 100Base-TX half-dupl ex
[011] = reserved
[101] = 10Base-T full-duplex
[110] = 100Base-TX full-duplex
[111] = reserved
RO 000
1f.1 Enable SQE
test 1 = Enable SQE test
0 = Disable SQE test RW 0
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April 2007 42 M9999-042707-1.1
Address Name Description Mode(1) Default
1f.0 Disable Data
Scrambling 1 = Disable scrambler
0 = Enable scrambler RW 0
Note:
1. RW = Read/Write.
RO = Read only.
SC = Self-cleared.
LH = Latch high.
LL = Latch low.
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April 2007 43 M9999-042707-1.1
Absolute Maximum Ratings(1)
Supply Voltage
(VDD_1.8, VDDA_1.8, V1.8_OUT)........................-0.5V to +2.4V
(VDDIO_3.3, VDDA_3.3) ...................................-0.5V to +4.0V
Input Voltage (all inputs) ...............................-0.5V to +4.0V
Output Voltage (all outputs) ..........................-0.5V to +4.0V
Lead Temperature (solderi ng, 10sec. ).......................260°C
Storage Temperature (Ts)..........................-55°C to +150°C
Operating Ratings(2)
Supply Voltage
(VDDIO_3.3, VDDA_3.3) ..........................+3.135V to +3.465V
Ambient Temperature (TA)..............................0°C to +70°C
Maximum Junction Temperature (TJ Max).................125°C
Thermal Resistance (θJA)....................................69.64°C/W
Electrical Characteristics(3)
Symbol Parameter Condition Min Typ Max Units
Supply Current(4)
IDD1 100Base-TX Chip only (no transformer);
Full-duplex traffic @ 100% util ization 53 mA
IDD2 10Base-T Chip only (no transformer);
Full-duplex traffic @ 100% util ization 38 mA
IDD3 Power Saving Mode Ethernet cable disconnected (reg. 1F.10 = 1) 32 mA
IDD4 Power Down Mode Software power down (reg. 0.11 = 1) 4 mA
TTL Inputs
VIH Input High Voltage 2.0 V
VIL Input Low Voltage 0.8 V
IIN Input Current VIN = GND ~ VDDIO -10 10
µA
TTL Outputs
VOH Output High Voltage IOH = -4mA 2.4 V
VOL Output Low Voltage IOL = 4mA 0.4 V
|Ioz| Output Tri-State Leakage 10 µA
100Base-TX Transmit (me asured differentially after 1:1 t ran sformer)
VO Peak Differential Output Voltage 100 terminati on across differential output 0.95 1.05 V
VIMB Output Voltage Imbalanc e 100 termination across differential output 2 %
tr, tf Rise/Fall Time 3 5 ns
Rise/Fall Time Imbalance 0 0.5
ns
Duty Cycle Distortion ± 0.25
ns
Overshoot 5 %
VSET Refere nce Voltage of ISET 0.65 V
Output Jitter Peak-to-peak 0.7 1.4 ns
10Base-T Transmit (measured differentially after 1:1 transformer)
VP Peak Differential Output Voltage 100 termination across differential output 2.2 2.8 V
Jitter Added Peak-to-peak 3.5
ns
tr, tf Rise/Fall Time 25 ns
10Base-T Receive
VSQ Squelch Threshold 5MHz square wave 400 mV
Micrel, Inc. KSZ8041TL/FTL
April 2007 44 M9999-042707-1.1
Notes:
1. Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent
damage to the device. Operation of the device at these or any othe r conditions above those specified in the operating sections of this specification
is not implied. Maximum conditions for extended periods may affect reliability.
2. The device is not guaranteed to function outside its operating rating.
3. TA = 25°C. Specification for packaged product only.
4. Current consumption is for the single 3.3V supply KSZ8041TL/FTL device only, and includes the 1.8V supply voltage (VDD_1.8, VDDA_1.8, V1.8_OUT) that is
provided by the KSZ8041TL/FTL. The PHY port’s transformer consumes an additional 45mA @ 3.3V for 100Base-TX and 70mA @ 3.3V for
10Base-T.
Micrel, Inc. KSZ8041TL/FTL
April 2007 45 M9999-042707-1.1
Timing Diagrams
MII SQE Timing (10Base-T)
TXC
tSQE
COL tSQEP
TXEN
tWL tWH
tP
Figure 11. MII SQE Timing (10Base-T)
Timing Parameter Description Min Typ Max Unit
tP TXC period 400 ns
tWL TXC pulse width low 200 ns
tWH TXC pulse width high 200 ns
tSQE COL (SQE) delay after TXEN de-asserted 2.5 µs
tSQEP COL (SQE) pulse duration 1.0 µs
Table 14. MII SQE Timing (10Base-T) Parameters
Micrel, Inc. KSZ8041TL/FTL
April 2007 46 M9999-042707-1.1
MII Transmit Timing (10Base-T)
TXC
tHD2
tSU2
TXEN
TXD[3:0] tSU1 tHD1
CRS tCRS2
tCRS1
tWH
tWL
tP
Figure 12. MII Transmit Ti ming (10Base-T)
Timing Parameter Description Min Typ Max Unit
tP TXC period 400 ns
tWL TXC pulse width low 200 ns
tWH TXC pulse width high 200 ns
tSU1 TXD[3:0] setup to rising edge of TXC 10 ns
tSU2 TXEN setup to rising edge of TXC 10 ns
tHD1 TXD[3:0] hold from rising edge of TXC 0 ns
tHD2 TXEN hold from rising edge of TXC 0 ns
tCRS1 TXEN high to CRS asserted l atency 4 Bit
Time
tCRS2 TXEN low to CRS de-asserted latency 8 Bit
Time
Table 15. MII Transmit Timing (10Base-T ) Parameters
Micrel, Inc. KSZ8041TL/FTL
April 2007 47 M9999-042707-1.1
MII Receive Timing (10Base-T)
Figure 13. MII Receive Timing (10Base-T)
Timing Parameter Description Min Typ Max Unit
tP RXC period 400 ns
tWL RXC pulse width low 200 ns
tWH RXC pulse width high 200 ns
tOD (RXD[3:0], RXER, RXDV) output
delay from rising edge of RXC 182 225 ns
tRLAT CRS to (RXD[3:0], RXER, RXDV)
latency 6.5 µs
Table 16. MII Receive Timing (10Base-T) Parameters
Micrel, Inc. KSZ8041TL/FTL
April 2007 48 M9999-042707-1.1
MII Transmit Timing (100Base-TX)
Figure 14. MII Transmit Ti ming (100Base-TX)
Timing Parameter Description Min Typ Max Unit
tP TXC period 40 ns
tWL TXC pulse width low 20 ns
tWH TXC pulse width high 20 ns
tSU1 TXD[3:0] setup to rising edge of TXC 10 ns
tSU2 TXEN setup to rising edge of TXC 10 ns
tHD1 TXD[3:0] hold from rising edge of TXC 0 ns
tHD2 TXEN hold from rising edge of TXC 0 ns
tCRS1 TXEN high to CRS asserted l atency 4 Bit
Time
tCRS2 TXEN low to CRS de-asserted latency 4 Bit
Time
Table 17. MII Transmit Timing (100Base-TX) Parameter s
Micrel, Inc. KSZ8041TL/FTL
April 2007 49 M9999-042707-1.1
MII Receive Timing (100Base-TX)
Figure 15. MII Receive Timing (100Base- TX)
Timing Parameter Description Min Typ Max Unit
tP RXC period 40 ns
tWL RXC pulse width low 20 ns
tWH RXC pulse width high 20 ns
tOD (RXD[3:0], RXER, RXDV) output
delay from rising edge of RXC 19 25 ns
tRLAT CRS to (RXD[3:0], RXER, RXDV)
latency 1 2 3
Bit
Time
Table 18. MII Receive Timing (100Base-TX) Parameters
Micrel, Inc. KSZ8041TL/FTL
April 2007 50 M9999-042707-1.1
RMII Timing
REFCLK
tcyc
TX_EN
TXD[1:0]
t1
t2
Transmit
Timing
Figure 16. RMII Timing – Data Received from RMII
REFCLK
tcyc
tod
CRSDV
RXD[1:0]
Receive
Timing
Figure 17. RMII Timing – Data Input to RMII
Timing Parameter Description Min Typ Max Unit
tcyc Clock cycle 20 ns
t1 Setup time 4 ns
t2 Hold time 2 ns
tod Output delay 2.8 10 ns
Table 19. RMII Timing Parameters
Micrel, Inc. KSZ8041TL/FTL
April 2007 51 M9999-042707-1.1
Auto-Negotiation Timing
Auto-Negotiation
Fast Link Pulse (FL P) Timin g
tPW
TX+/TX-
Clock
Pulse Data
Pulse Clock
Pulse
tPW
tCTD
tCTC
tFLPW
tBTB
TX+/TX-
Data
Pulse
FLP
Burst FLP
Burst
Figure 18. Auto-Negotiation Fast Link Pulse (FLP) Timing
Timing Parameter Description Min Typ Max Units
tBTB FLP Burst to FLP Burst 8 16 24 ms
tFLPW FLP Burst width 2 ms
tPW Clock/Data Pulse width 100 ns
tCTD Clock Pulse to Data Pulse 55.5 64 69.5 µs
tCTC Clock Pulse to Clock Pulse 111 128 139 µs
Number of Clock/Data Pulse per
FLP Burst 17 33
Table 20. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
Micrel, Inc. KSZ8041TL/FTL
April 2007 52 M9999-042707-1.1
MDC/MDIO Timing
tMD1
Valid
Data
MDIO
(PHY input) Valid
Data
MDC
tMD2
MDIO
(PHY output) Valid
Data
tMD3
tP
Figure 19. MDC/MDIO Timing
Timing Parameter Description Min Typ Max Unit
tP MDC period 400 ns
t1MD1 MDIO (PHY input) setup to rising edge of MDC 10 ns
tMD2 MDIO (PHY input) hold from rising edge of MDC 10 ns
tMD3 MDIO (PHY output) delay from rising edge of MDC 222 ns
Table 21. MDC/MDIO Timing Parameters
Micrel, Inc. KSZ8041TL/FTL
April 2007 53 M9999-042707-1.1
Reset Timing
The KSZ8041TL/FTL reset timing requirement is summarized in the following figure and table.
tsr
tcs tch
trc
Supply
Voltage
RST#
Strap-In
Value
Strap-In /
Output Pi n
Figure 20. Reset Timing
Parameter Description Min Max Units
tsr Stable supply voltage to reset high 10 ms
tcs Configuration setup time 5 ns
tch Configuration hold time 5 ns
trc Reset to strap-in pin output 6 ns
Table 22. Reset Timing Parameters
After the de-assertion of reset, it is recommended to wait a minimum of 100µs before starting programming on the MIIM
(MDC/MDIO) Interface.
Micrel, Inc. KSZ8041TL/FTL
April 2007 54 M9999-042707-1.1
Reset Circuit
The following reset circuit is recommended for powering up the KSZ8041TL/FTL if reset is triggered by the power supply.
KSZ8041TL/FTL
3.3V
D1
D1: 1N 4148
R 10K
C 10uF
RST#
Figure 21. Recommended Reset Circuit
The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or FPGA).
At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ8041TL/FTL device. The
RST_OUT_n from CPU/FPGA provides the warm reset after power up.
KSZ8041TL/FTL CPU/FPGA
3.3V
C 10uF
R 10K
RST_OUT_n
D1
D2
D1, D2: 1N4148
RST#
Figure 22. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output
Micrel, Inc. KSZ8041TL/FTL
April 2007 55 M9999-042707-1.1
The following figure shows the reference circuits for pull-up, float and pull-down on the LED1 and LED0 strapping pins.
LED pin
3.3V
Pull-up
KSZ8041TL/FTL
3.3V
Float
KSZ8041TL/FTL
LED pin
3.3V
Pull-down
KSZ8041TL/FTL
LED pin
Figure 23. Reference Circuits for LED Strapping Pins
Micrel, Inc. KSZ8041TL/FTL
April 2007 56 M9999-042707-1.1
Selection of Isolation Transformer
A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode chokes
is recommended for exceeding FCC requirements.
The following table gives recommen ded transformer characteristics.
Parameter Value Test Condition
Turns ratio 1 CT : 1 CT
Open-circuit inductance (min.) 350µH 100mV, 100kHz, 8mA
Leakage inductance (max.) 0.4µH 1MHz (min.)
Inter-winding capacitance (max.) 12pF
D.C. resistance (max.) 0.9
Insertion loss (max.) 1.0dB 0MHz – 65MH z
HIPOT (min.) 1500Vrms
Table 23. Transformer Selection Criteria
Magnetic Manufacturer Part Number Auto MDI-X Number of Port
Bel Fuse S558-5999-U7 Yes 1
Bel Fuse (Mag Jack) SI-46001 Yes 1
Bel Fuse (Mag Jack) SI-50170 Yes 1
Delta LF8505 Yes 1
LanKom LF-H41S Yes 1
Pulse H1102 Yes 1
Pulse (low cost) H1260 Yes 1
Transpower HB726 Yes 1
TDK (Mag Jack) TLA-6T718 Yes 1
Table 24. Qualified Single Port Magnetics
Selection of Reference Crystal
Characteristics Value Units
Frequency 25 MHz
Frequency tolerance (max) ±50 ppm
Load capacitance (max) 20 pF
Series resistance 40
Table 25. Typical Reference Crystal Characteristics
Micrel, Inc. KSZ8041TL/FTL
April 2007 57 M9999-042707-1.1
Package Information
,SNOISURTORPROHSALFDLOMEDULCNITONSEODNOISNEMID .MM452.0DEECXETONLLAHSHCIHWFOREHTIE .NOISURTORPRABMADEDU
LCNITONSEODNOISNEMIDDAEL MOTTOBNAHTRELLAMSERASNOISNEMIDDLOMPOTEGAKCAP GNAHREVOTONLLIWEGAKCAPFOPOTDNASNO
ISNEMIDDLOM .EGAKCAPFOMOTTOB
:SETON
.1
.2.3.4
48-Pin (7mm x 7mm) TQFP Package
Note: ALL DIMENSIONS ARE IN MILLIMETERS.
Micrel, Inc. KSZ8041TL/FTL
April 2007 58 M9999-042707-1.1
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its
use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical
implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user.
A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to
fully indemnify Micrel for any damages resulting from such use or sale.
© 2007 Micrel, Incor
p
orated.
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