AD9460-105LVDS/PCB - Analog Devices

16-Bit, 80 / 105 MSPS ADC

Preliminary Technical Data AD9460

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

105 MSPS guaranteed sampling rate (AD9460-105)

78.3 dBFS SNR with 30 MHz input (3.4 V p-p input, 80 MSPS)

76.6 dBFS SNR with 170 MHz input (3.4V p-p input, 80 MSPS)

90 dBc SFDR with 30 MHz input (3.4V p-p input, 105 MSPS)

83dBc SFDR with 225 MHz input (3.4V p-p input, 105 MSPS)

60 fsec rms jitter

Excellent linearity

DNL = ±0.6 LSB typical

INL = ±4.0 LSB typical

2.0 V p-p to 4.0 V p-p differential full-scale input

Buffered analog inputs

LVDS outputs (ANSI-644 compatible) or CMOS outputs

Data format select (offset binary or twos complement)

Output data capture clock available

3.3 V and 5 V supply operation

APPLICATIONS

MRI receivers

Multicarrier, multimode cellular receivers

Antenna array positioning

Power amplifier linearization

Broadband wireless

Radar

Infrared imaging

Communications instrumentation

GENERAL DESCRIPTION

The AD9460 is a 16-bit, monolithic, sampling analog-to-digital

converter (ADC) with an on-chip track-and-hold circuit. It is

optimized for performance, small size, and ease of use. The

product operates up to 105 MSPS, providing superior SNR for

instrumentation, medical imaging, and radar receivers

employing baseband (<100 MHz) and IF frequencies.

The ADC requires 3.3 V and 5.0 V power supplies and a low

voltage differential input clock for full performance operation.

No external reference or driver components are required for

many applications. Data outputs are CMOS or LVDS

compatible (ANSI-644 compatible) and include the means to

reduce the overall current needed for short trace distances.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Optional features allow users to implement various selectable

operating conditions, including input range, data format select,

and output data mode.

The AD9460 is available in a Pb-free, 100-lead, surface-mount,

plastic package (100-lead TQFP/EP) specified over the

industrial temperature range −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. True 16-bit linearity.

2. High performance: outstanding SNR performance for

baseband IFs in data acquisition, instrumentation,

magnetic resonance imaging, and radar receivers.

3. Ease of use: on-chip reference and high input impedance

track-and-hold with adjustable analog input range and an

output clock simplifies data capture.

4. Packaged in a Pb-free, 100-lead TQFP/EP package.

5. Clock duty cycle stabilizer (DCS) maintains overall ADC

performance over a wide range of clock pulse widths.

6. OR (out-of-range) outputs indicate when the signal is

beyond the selected input range.

CMOS

LVDS

OUTPUT

STAGING

CLOCK

AND TIMING

MANAGEMENT

AGND DRGND DRVDD

VREF

CLK+

VIN+

AD9460

VIN–

CLK–DCO

AVDD1 AVDD2

DCS MODE

DFS

OUTPUT MODE

T/H

BUFFER 16

PIPELINE

ADC 2

D15 TO D0

REF

REFBSENSE REFT

AD9460 Preliminary Technical Data

Rev. PrA| Page 2 of 28

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications .................... Error! Bookmark not defined.

AC Specifications..................... Error! Bookmark not defined.

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Terminology ...................................................................................... 9

Pin Configurations and Function Descriptions......................... 10

Equivalent Circuits......................................................................... 15

Typical Performance Characteristics ........ Error! Bookmark not

defined.

Theory of Operation ...................................................................... 16

Analog Input and Reference Overview ................................... 16

Clock Input Considerations...................................................... 18

Power Considerations................................................................ 19

Digital Outputs ........................................................................... 19

Timing ......................................................................................... 19

Operational Mode Selection..................................................... 20

Evaluation Board ............................................................................ 21

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 28

REVISION HISTORY

10/05—Revision 0: Initial Version

Preliminary Technical Data AD9460

Rev.PrA | Page 3 of 28

DC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.4 V p-p differential input, internal

trimmed reference (1.0 V mode), AIN = −1.0 dBFS, DCS on, unless otherwise noted. RF ENABLE = AGND.

Table 1.

AD9460BSVZ-80 AD9460BSVZ-105

Parameter Temp Min Typ Max Min Typ Max Unit

RESOLUTION Full 16 16 Bits

ACCURACY

No Missing Codes Full Guaranteed

Offset Error Full mV

25°C ±3 ±3 mV

Gain Error Full % FSR

25°C % FSR

Differential Nonlinearity (DNL)1 Full ±0.6 ±0.6 LSB

Integral Nonlinearity (INL)1 25°C ±4.0 ±4.0 LSB

Full LSB

VOLTAGE REFERENCE

Output Voltage VREF = 1.7V Full 1.7 1.7 V

Load Regulation @ 1.0 mA Full ±2 ±2 mV

Reference Input Current (External VREF = 1.7 V) Full µA

INPUT REFERRED NOISE 25°C LSB rms

ANALOG INPUT

Input Span

VREF = 1.7V Full 3.4 3.4 V p-p

VREF = 1.0 V Full 2.0 2.0 V p-p

Internal Input Common-Mode Voltage Full 3.5 3.5 V

External Input Common-Mode Voltage Full 3.2 3.9 3.2

3.9 V

Input Resistance2 Full 1 1 kΩ

Input Capacitance2 Full 6 6 pF

POWER SUPPLIES

Supply Voltage

AVDD1 Full 3.14 3.3 3.46 3.14 3.3 3.46 V

AVDD2 Full 4.75 5.0 5.25 4.75 5.0 5.25 V

DRVDD—LVDS Outputs Full 3.0 3.6 3.0 3.6 V

DRVDD—CMOS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V

Supply Current1

AVDD1 Full 270 310 mA

AVDD21, 3 Full

103

120 mA

IDRVDD1—LVDS Outputs Full 63 63 mA

IDRVDD1—CMOS Outputs Full 14 14 mA

PSRR

Offset Full 1 1 mV/V

Gain Full 0.2 0.2 %/V

POWER CONSUMPTION

LVDS Outputs Full 1.6

1.8 W

CMOS Outputs (DC Input) Full 1.4

1.6 W

1 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and

approximately 5 pF loading on each output bit for CMOS output mode.

2 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.

3 For RF ENABLE = AVDD1, IAVDD2 increases by ~30 mA, which increases power dissipation.

AD9460 Preliminary Technical Data

Rev. PrA| Page 4 of 28

AC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.4 V p-p differential input, internal

trimmed reference (1.7 V mode), AIN = −1.0 dBFS, DCS on, RF ENABLE = ground, unless otherwise noted.

Table 2.

AD9460BSVZ-80 AD9460BSVZ-105

Parameter Temp

Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 10 MHz 25°C 78.3 77.9 dB

fIN = 30 MHz 25°C 77.7 77.8 dB

Full dB

fIN = 170 MHz 25°C 76.6 76.2 dB

fIN = 225 MHz1 25°C 75.5 75.4 dB

Full dB

fIN = 300 MHz2 25°C dB

fIN = 400 MHz2 25°C dB

fIN = 450 MHz2 25°C dB

fIN = 10 MHz (2.0 V p-p Input) 25°C dB

fIN = 30 MHz (2.0 V p-p Input) 25°C dB

fIN = 170 MHz (2.0 V p-p Input) 25°C dB

fIN = 225 MHz (2.0 V p-p Input)1 25°C dB

fIN = 300 MHz (2.0 V p-p Input)2 25°C dB

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 10 MHz 25°C 78.1 77.8 dB

fIN = 30 MHz 25°C 77.1 dB

Full dB

fIN = 170 MHz 25°C 75.9 75.4 dB

fIN = 225 MHz1 25°C 73.3 74.3 dB

Full dB

fIN = 300 MHz2 25°C dB

fIN = 400 MHz2 25°C dB

fIN = 450 MHz2 25°C dB

fIN = 10 MHz(2.0 V p-p Input) 25°C dB

fIN = 30 MHz (2.0 V p-p Input) 25°C dB

fIN = 170 MHz (2.0 V p-p Input) 25°C dB

fIN = 225 MHz (2.0 V p-p Input) 25°C dB

fIN = 300 MHz (2.0 V p-p Input) 25°C dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 10 MHz 25°C 12.8 12.7 Bits

fIN = 30 MHz 25°C 12.7 Bits

fIN = 170 MHz 25°C 12.5 12.4 Bits

fIN = 225 MHz1 25°C 12.0 12.2 Bits

fIN = 300 MHz2 25°C Bits

fIN = 400 MHz2 25°C Bits

fIN = 450 MHz2 25°C Bits

Preliminary Technical Data AD9460

Rev.PrA | Page 5 of 28

AD9460BSVZ-80 AD9460BSVZ-105

Parameter Temp

Min Typ Max Min Typ Max Unit

SPURIOUS-FREE DYNAMIC RANGE

(SFDR, Second or Third Harmonic)

fIN = 10 MHz 25°C 93 90 dBc

fIN = 30 MHz 25°C 87 90 dBc

Full dBc

fIN = 170 MHz 25°C 84 84 dBc

fIN = 225 MHz1 25°C 80 83 dBc

Full dBc

fIN = 300 MHz2 25°C dBc

fIN = 400 MHz2 25°C dBc

fIN = 450 MHz2 25°C dBc

fIN = 10 MHz(2.0 V p-p Input) 25°C dBc

fIN = 30 MHz (2.0 V p-p Input) 25°C dBc

fIN = 170 MHz (2.0 V p-p Input) 25°C dBc

fIN = 225 MHz (2.0 V p-p Input) 25°C dBc

fIN = 300 MHz (2.0 V p-p Input) 25°C dBc

WORST SPUR EXCLUDING SECOND OR

THIRD HARMONICS

fIN = 10 MHz 25°C 97 92 dBc

fIN = 30 MHz 25°C 97 dBc

Full dBc

fIN = 170 MHz 25°C 96 92 dBc

fIN = 225 MHz1 25°C 96 86 dBc

Full dBc

fIN = 300 MHz2 25°C dBc

fIN = 400 MHz2 25°C dBc

fIN = 450 MHz2 25°C dBc

fIN = 10 MHz(2.0 V p-p Input) 25°C dBc

fIN = 30 MHz (2.0 V p-p Input) 25°C dBc

fIN = 170 MHz (2.0 V p-p Input) 25°C dBc

fIN = 225 MHz (2.0 V p-p Input) 25°C dBc

fIN = 300 MHz (2.0 V p-p Input) 25°C dBc

TWO-TONE SFDR

fIN = 30.3 MHz @ −7 dBFS,

31.3 MHz @ −7 dBFS

25°C dBFS

fIN = 170.3 MHz @ −7 dBFS,

171.3 MHz @ −7 dBFS

25°C dBFS

ANALOG BANDWIDTH Full MHz

1TBD

2 RF ENABLE = high (AVDD1).

AD9460 Preliminary Technical Data

Rev. PrA| Page 6 of 28

DIGITAL SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIA S = 3.74 kΩ, unless otherwise noted.

Table 3.

AD9460BSVZ-80

Parameter Temp Min Typ Max Unit

CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)

High Level Input Voltage Full 2.0 V

Low Level Input Voltage Full 0.8 V

High Level Input Current Full 200 µA

Low Level Input Current Full −10 +10 µA

Input Capacitance Full 2 pF

DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR)1

DRVDD = 3.3 V

High Level Output Voltage Full 3.25 V

Low Level Output Voltage Full

0.2 V

DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR)

VOD Differential Output Voltage2 Full 247 545 mV

VOS Output Offset Voltage Full 1.125 1.375 V

CLOCK INPUTS (CLK+, CLK−)

Differential Input Voltage Full 0.2 V

Common-Mode Voltage Full 1.3 1.5 1.6 V

Input Resistance Full 1.1 1.4 1.7 kΩ

Input Capacitance Full 2 pF

1 Output voltage levels measured with 5 pF load on each output.

2 LVDS RTERM = 100 Ω.

SWITCHING SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.

Table 4.

AD9460BSVZ-80

Parameter Temp Min Typ Max Unit

CLOCK INPUT PARAMETERS

Maximum Conversion Rate Full 80 MSPS

Minimum Conversion Rate Full 1 MSPS

CLK Period Full 12.5 ns

CLK Pulse Width High1 (tCLKH) Full 5.0 ns

CLK Pulse Width Low1 (tCLKL) Full 5.0 ns

DATA OUTPUT PARAMETERS

Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+) Full 3.35 ns

Output Propagation Delay—LVDS (tPD)3 (Dx+), (tCPD)3 (DCO+) Full 2.1 3.6 4.8 ns

Pipeline Delay (Latency) Full 13 Cycles

Aperture Delay (tA) Full ns

Aperture Uncertainty (Jitter, tJ) Full 60

fsec

rms

1 With duty cycle stabilizer (DCS) enabled.

2 Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.

3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

Preliminary Technical Data AD9460

Rev.PrA | Page 7 of 28

TIMING DIAGRAMS

N – 13 N–12 NN + 1

AIN

CLK+

CLK–

DATA OUT

DCO+

DCO–

N + 1

N–1

CLKH

CLKL

13 CLOCK CYCLES

CPD

05490-002

Figure 2. LVDS Mode Timing Diagram

N + 1

N + 2

N–1

CLKL

13 CLOCK CYCLES

05490-003

CLKH

VIN

CLK+

CLK–

DCO+

DCO–

N – 13 N – 12 N – 1 N

Figure 3. CMOS Timing Diagram

AD9460 Preliminary Technical Data

Rev. PrA| Page 8 of 28

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter

With

Respect

to Rating

ELECTRICAL

AVDD1 AGND −0.3 V to +4 V

AVDD2 AGND −0.3 V to +6 V

DRVDD DGND −0.3 V to +4 V

AGND DGND −0.3 V to +0.3 V

AVDD1 DRVDD −4 V to +4 V

AVDD2 DRVDD −4 V to +6 V

AVDD2 AVDD1 −4 V to +6 V

D0± to D15± DGND –0.3 V to DRVDD + 0.3 V

CLK+/CLK− AGND –0.3 V to AVDD1 + 0.3 V

OUTPUT MODE,

DCS MODE, DFS

AGND –0.3 V to AVDD1 + 0.3 V

VIN+, VIN− AGND –0.3 V to AVDD2 + 0.3 V

VREF AGND –0.3 V to AVDD1 + 0.3 V

SENSE AGND –0.3 V to AVDD1 + 0.3 V

REFT, REFB AGND –0.3 V to AVDD1 + 0.3 V

ENVIRONMENTAL

Storage Temperature

Range

–65°C to +125°C

Operating Temperature

Range

–40°C to +85°C

Lead Temperature

(Soldering 10 sec)

300°C

Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

The heat sink of the AD9460 package must be soldered to

ground.

Table 6.

Package Type θJA θ

JB θ

JC Unit

100-lead TQFP/EP 19.8 8.3 2 °C/W

Typical θJA = 19.8°C/W (heat sink soldered) for multilayer

board in still air.

Typical θJB = 8.3°C/W (heat sink soldered) for multilayer board

in still air.

Typical θJC = 2°C/W (junction to exposed heat sink) represents

the thermal resistance through heat sink path.

Airflow increases heat dissipation, effectively reducing θJA. Also,

more metal directly in contact with the package leads from

metal traces through holes, ground, and power planes reduces

the θJA. It is required that the exposed heat sink be soldered to

the ground plane.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Preliminary Technical Data AD9460

Rev.PrA | Page 9 of 28

TERMINOLOGY

Analog Bandwidth (Full Power Bandwidth)

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

Aperture Delay (tA)

The delay between the 50% point of the rising edge of the clock

and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter, tJ)

The sample-to-sample variation in aperture delay.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that the

clock pulse should be left in the Logic 1 state to achieve rated

performance. Pulse width low is the minimum time the clock

pulse should be left in the low state. At a given clock rate, these

specifications define an acceptable clock duty cycle.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Guaranteed

no missing codes to 16-bit resolution indicates that all 65,536

codes must be present over all operating ranges.

Effective Number of Bits (ENOB)

The effective number of bits for a sine wave input at a given

input frequency can be calculated directly from its measured

SINAD using the following formula:

()

6.02

1.76−

=SINAD

ENOB

Gain Error

The first code transition should occur at an analog value of

½ LSB above negative full scale. The last transition should occur

at an analog value of 1½ LSB below the positive full scale. Gain

error is the deviation of the actual difference between first and

last code transitions and the ideal difference between first and

last code transitions.

Integral Nonlinearity (INL)

The deviation of each individual code from a line drawn from

negative full scale through positive full scale. The point used as

negative full scale occurs ½ LSB before the first code transition.

Positive full scale is defined as a level 1½ LSB beyond the last

code transition. The deviation is measured from the middle of

each particular code to the true straight line.

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

Minimum Conversion Rate

The clock rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the guaranteed

limit.

Offset Error

The major carry transition should occur for an analog value of

½ LSB below VIN+ = VIN−. Offset error is defined as the

deviation of the actual transition from that point.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input

after a transition from 10% above positive full scale to 10%

above negative full scale, or from 10% below negative full scale

to 10% below positive full scale.

Output Propagation Delay (tPD)

The delay between the clock rising edge and the time when all

bits are within valid logic levels.

Power-Supply Rejection Ratio

The change in full scale from the value with the supply at the

minimum limit to the value with the supply at the maximum

limit.

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms input signal amplitude to the rms value of

the sum of all other spectral components below the Nyquist

frequency, including harmonics but excluding dc.

Signal-to-Noise Ratio (SNR)

The ratio of the rms input signal amplitude to the rms value of

the sum of all other spectral components below the Nyquist

frequency, excluding the first six harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the

peak spurious spectral component. The peak spurious component

may be a harmonic. SFDR can be reported in dBc (that is, degrades

as signal level is lowered) or dBFS (always related back to converter

full scale).

Temperature Drift

The temperature drift for offset error and gain error specifies

the maximum change from the initial (25°C) value to the value

at TMIN or TMAX.

Total Harmonic Distortion (THD)

The ratio of the rms input signal amplitude to the rms value of

the sum of the first six harmonic components.

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value

of the peak spurious component. The peak spurious component

may or may not be an IMD product.

AD9460 Preliminary Technical Data

Rev. PrA| Page 10 of 28

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

D10+

D10–

D9+

D8–

D8+

D9–

DRGND

DCO+

DCO–

D7+

DRVDD

DRGND

D6+

D6–

D5+

D5–

D4+

D4–

D3+

D3–

D2+

D2–

D1+

D1–

D7–

PIN 1

DNC = DO NOT CONNECT

100

AGND

AVDD1

AGND

OR+

OR–

DRVDD

DRGND

D15+ (MSB)

D15–

D14+

D14–

D13+

D13–

D12+

D12–

D11+

D11–

DRVDD

AVDD2

AVDD1

AVDD2

AVDD1

AVDD2

AVDD1

AGND

CLK+

CLK–

AGND

AVDD1

AGND

DRGND

DRVDD

D0– (LSB)

D0+

DNC

OUTPUT MODE

DFS

SENSE

AVDD1

LVDS_BIAS

DCS MODE

VREF

AGND

REFT

AVDD2

AVDD1

AGND

VIN+

VIN–

AGND

AVDD2

REFB

AD9446

LVDS MODE

TOP VIEW

(Not to Scale)

05490-004

Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode

AD9460

Preliminary Technical Data AD9460

Rev.PrA | Page 11 of 28

Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode

Pin No. Mnemonic Description

1 DCS MODE

Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable

DCS (recommended); DCS = high (AVDD1) to disable DCS.

2 DNC Do Not Connect. These pins should float.

3 OUTPUT

MODE

CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;

OUTPUT MODE = 1 (AVDD1) for LVDS outputs.

4 DFS

Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS =

high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.

5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.

6, 18 to 20, 32 to 34, 36, 38,

43 to 45, 92 to 97

AVDD1 3.3 V (±5%) Analog Supply.

7 SENSE

Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog

input range); connect to AVDD1 for external reference.

8 VREF

1.7 V Reference I/O. Function dependent on SENSE and external programming resistors.

Decouple to ground with 0.1 µF and 10 µF capacitors.

9, 21, 24, 39, 42, 46, 91, 98,

99, 100, Exposed Heat Sink

AGND Analog Ground. The exposed heat sink on the bottom of the package must be connected to

AGND.

10 REFT

Differential Reference Output. Decoupled to ground with 0.1 µF capacitor and to REFB (Pin 11)

with 0.1 µF and 10 µF capacitors.

11 REFB

Differential Reference Output. Decoupled to ground with a 0.1 µF capacitor and to REFT

(Pin 10) with 0.1 µF and 10 µF capacitors.

12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%).

22 VIN+ Analog Input—True.

23 VIN− Analog Input—Complement.

40 CLK+ Clock Input—True.

41 CLK− Clock Input—Complement.

47, 63, 75, 87, DRGND Digital Output Ground.

48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).

49 D0− (LSB) D0 Complement Output Bit (LVDS Levels).

50 D0+ D0 True Output Bit.

51 D1− D1 Complement Output Bit.

52 D1+ D1 True Output Bit.

53 D2− D2 Complement Output Bit.

54 D2+ D2 True Output Bit.

55 D3− D3 Complement Output Bit.

56 D3+ D3 True Output Bit.

57 D4− D4 Complement Output Bit.

58 D4+ D4 True Output Bit.

59 D5− D5 Complement Output Bit.

60 D5+ D5 True Output Bit.

61 D6− D6 Complement Output Bit.

62 D6+ D6 True Output Bit.

65 D7− D7 Complement Output Bit.

66 D7+ D7 True Output Bit.

67 DCO− Data Clock Output—Complement.

68 DCO+ Data Clock Output—True.

69 D8− D8 Complement Output Bit.

70 D8+ D8 True Output Bit.

71 D9− D9 Complement Output Bit.

72 D9+ D9 True Output Bit.

73 D10− D10 Complement Output Bit.

74 D10+ D10 True Output Bit.

77 D11− D11 Complement Output Bit.

78 D11+ D11 True Output Bit.

AD9460 Preliminary Technical Data

Rev. PrA| Page 12 of 28

Pin No. Mnemonic Description

79 D12− D12 Complement Output Bit.

80 D12+ D12 True Output Bit.

81 D13− D13 Complement Output Bit

82 D13+ D13 True Output Bit.

83 D14− D14 Complement Output Bit

84 D14+ D14 True Output Bit.

85 D15− D15 Complement Output Bit.

86 D15+ (MSB) D15 True Output Bit.

89 OR− Out-of-Range Complement Output Bit.

90 OR+ Out-of-Range True Output Bit.

Preliminary Technical Data AD9460

Rev.PrA | Page 13 of 28

D4+

D3+

D2+

DNC

D0+ (LSB)

D1+

DRGND

DCO+

DCO–

DNC

DRVDD

DRGND

DNC

PIN 1

DNC = DO NOT CONNECT

100

AGND

AVDD1

AGND

OR+

D15+ (MSB)

DRVDD

DRGND

D14+

D13+

D12+

D11+

D10+

D9+

D8+

D7+

D6+

D5+

DRVDD

AVDD2

AVDD1

AVDD2

AVDD1

AVDD2

AVDD1

AGND

CLK+

CLK–

AGND

AVDD1

AGND

DRGND

DRVDD

DNC

OUTPUT MODE

DFS

SENSE

AVDD1

LVDS_BIAS

DCS MODE

VREF

AGND

REFT

AVDD2

AVDD1

AGND

VIN+

VIN–

AGND

AVDD2

REFB

AD9446

CMOS MODE

TOP VIEW

(Not to Scale)

05490-005

Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode

AD9460

AD9460 Preliminary Technical Data

Rev. PrA| Page 14 of 28

Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode

Pin No. Mnemonic Description

1 DCS MODE

Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to

enable DCS (recommended); DCS = high (AVDD1) to disable DCS.

2, 49 to 62, 65 to 66, 69, DNC Do Not Connect. These pins should float.

3 OUTPUT MODE

CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;

OUTPUT MODE = 1 (AVDD1) for LVDS outputs.

4 DFS

Data Format Select Pin. CMOS control pin that determines the format of the output data.

DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.

5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.

6, 18 to 20, 32 to 34, 36,

38, 43 to 45, 92 to 97

AVDD1 3.3 V (±5%) Analog Supply.

7 SENSE

Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog

input range); connect to AVDD1 for external reference.

8 VREF

1.7 V Reference I/O. Function dependent on SENSE and external programming resistors.

Decouple to ground with 0.1 µF and 10 µF capacitors.

9, 21, 24, 39, 42, 46, 91, 98,

99, 100, Exposed Heat

Sink

AGND Analog Ground. The exposed heat sink on the bottom of the package must be connected to

AGND.

10 REFT

Differential Reference Output. Decoupled to ground with 0.1 µF capacitor and to REFB (Pin 11)

with 0.1 µF and 10 µF capacitors.

11 REFB

Differential Reference Output. Decoupled to ground with a 0.1 µF capacitor and to REFT (Pin 10)

with 0.1 µF and 10 µF capacitors.

12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%).

22 VIN+ Analog Input—True.

23 VIN− Analog Input—Complement.

40 CLK+ Clock Input—True.

41 CLK− Clock Input—Complement.

47, 63, 75, 87, DRGND Digital Output Ground.

48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).

67 DCO− Data Clock Output—Complement.

68 DCO+ Data Clock Output—True.

70 D0+ (LSB) D0 True Output Bit (CMOS levels).

71 D1+ D1 True Output Bit.

72 D2+ D2 True Output Bit.

73 D3+ D3 True Output Bit.

74 D4+ D4 True Output Bit.

77 D5+ D5 True Output Bit.

78 D6+ D6 True Output Bit.

79 D7+ D7 True Output Bit.

80 D8+ D8 True Output Bit.

81 D9+ D9 True Output Bit.

82 D10+ D10 True Output Bit.

83 D11+ D11 True Output Bit.

84 D12+ D12 True Output Bit.

85 D13+ D13 True Output Bit.

86 D14+ D14 True Output Bit.

89 D15+ (MSB) D15 True Output Bit.

90 OR+ Out-of-Range True Output Bit.

Preliminary Technical Data AD9460

Rev.PrA | Page 15 of 28

EQUIVALENT CIRCUITS

3.5V

AVDD2

VIN+

VIN–

T/H

AVDD2

05490-006

6pF

Figure 6. Equivalent Analog Input Circuit

05490-007

1.2V

DRVDD DRVDD

3.74k

LVDSOUT

LVDSBIAS

Figure 7. Equivalent LVDS_BIAS Circuit

DRVDD

DX– DX+

05490-008

Figure 8. Equivalent LVDS Digital Output Circuit

DRVDD

05490-009

Figure 9. Equivalent CMOS Digital Output Circuit

DCS MODE,

OUTPUT MODE,

DFS

VDD

30kΩ

05490-010

Figure 10. Equivalent Digital Input Circuit,

DFS, DCS MODE, OUTPUT MODE

Figure 11. Equivalent Sample Clock Input Circuit

CLK+

3kΩ

2.5kΩ

3kΩ

2.5kΩ

AVDD1

CLK–

05490-011

AD9460 Preliminary Technical Data

Rev. PrA| Page 16 of 28

THEORY OF OPERATION

The AD9460 architecture is optimized for high speed and ease

of use. The analog inputs drive an integrated, high bandwidth

track-and-hold circuit that samples the signal prior to quantization

by the 16-bit pipeline ADC core. The device includes an on-board

reference and input logic that accepts TTL, CMOS, or LVPECL

levels. The digital output logic levels are user selectable as standard

3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT

MODE pin.

ANALOG INPUT AND REFERENCE OVERVIEW

A stable and accurate 0.5 V band gap voltage reference is built

into the AD9460. The input range can be adjusted by varying

the reference voltage applied to the AD9460, using either the

internal reference or an externally applied reference voltage.

The input span of the ADC tracks reference voltage changes

linearly.

Internal Reference Connection

A comparator within the AD9460 detects the potential at the

SENSE pin and configures the reference into three possible states,

which are summarized in Table 9. If SENSE is grounded, the

reference amplifier switch is connected to the internal resistor

divider (see Figure 12), setting VREF to ~1.7 V. If a resistor

divider is connected as shown in Figure 13, the switch again sets

to the SENSE pin. This puts the reference amplifier in a

noninverting mode with the VREF output defined as

⎟

⎠

⎞

⎜

⎝

⎛+×= R1

VVREF 15.0

In all reference configurations, REFT and REFB drive the

analog-to-digital conversion core and establish its input span.

The input range of the ADC always equals twice the voltage at

the reference pin for either an internal or an external reference.

Internal Reference Trim

The internal reference voltage is trimmed during the production

test; therefore, there is little advantage to the user supplying an

external voltage reference to the AD9460. The gain trim is per-

formed with the AD9460 input range set to 3.4 V p-p nominal

(SENSE connected to AGND). Because of this trim and the

maximum ac performance provided by the 3.4 V p-p analog

input range, there is little benefit to using analog input ranges

<2 V p-p. However, reducing the range can improve SFDR

performance in some applications. Likewise, increasing the

range up to 3.4 V p-p can improve SNR. Users are cautioned

that the differential nonlinearity of the ADC varies with the

reference voltage. Configurations that use <2.0 V p-p may

exhibit missing codes and therefore degraded noise and

distortion performance.

10μF+0.1μF

VREF

SENSE

0.5V

AD9446

VIN–

VIN+

REFT

0.1μF

0.1μF 10μF

0.1μF

REFB

SELECT

LOGIC

ADC

CORE +

05490-052

Figure 12. Internal Reference Configuration

05490-053

10μF+0.1μF

VREF

SENSE

R1 0.5V

AD9446

VIN–

VIN+

REFT

0.1μF

0.1μF 10μF

0.1μF

REFB

SELECT

LOGIC

ADC

CORE +

Figure 13. Programmable Reference Configuration

AD9460

Preliminary Technical Data AD9460

Rev.PrA | Page 17 of 28

Table 9. Reference Configuration Summary

Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)

External Reference AVDD N/A 2 × external reference

Programmable Reference 0.2 V to VREF ⎟

⎠

⎞

⎜

⎝

⎛+× R1

10.5 (See Figure 13) 2 × VREF

Programmable Reference

(Set for 2 V p-p)

0.2 V to VREF ⎟

⎠

⎞

⎜

⎝

⎛+× R1

10.5 , R1 = R2 = 1 kΩ 2.0

Internal Fixed Reference AGND to 0.2 V 1.7 3.4

External Reference Operation

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7 kΩ load. The internal buffer still generates the positive and

negative full-scale references, REFT and REFB, for the ADC

core. The input span is always twice the value of the reference

voltage; therefore, the external reference must be limited to a

maximum of 2.0 V. See Error! Reference source not found. for

gain variation vs. temperature.

Analog Inputs

As with most new high speed, high dynamic range ADCs, the

analog input to the AD9460 is differential. Differential inputs

improve on-chip performance because signals are processed

through attenuation and gain stages. Most of the improvement

is a result of differential analog stages having high rejection of

even-order harmonics. There are also benefits at the PCB level.

First, differential inputs have high common-mode rejection of

stray signals, such as ground and power noise. Second, they

provide good rejection of common-mode signals, such as local

oscillator feedthrough. The specified noise and distortion of the

AD9460 cannot be realized with a single-ended analog input, so

such configurations are discouraged. Contact sales for

recommendations of other 16-bit ADCs that support single-

ended analog input configurations.

With the 1.7 V reference, which is the nominal value (see the

Internal Reference Trim section), the differential input range of

the AD9460 analog input is nominally 3.4 V p-p or 1.7 V p-p on

each input (VIN+ or VIN−).

Figure 14. Differential Analog Input Range for VREF = 1.7 V

The AD9460 analog input voltage range is offset from ground

by 3.5 V. Each analog input connects through a 1 kΩ resistor to

the 3.5 V bias voltage and to the input of a differential buffer. The

internal bias network on the input properly biases the buffer for

maximum linearity and range (see the Equivalent Circuits

section). Therefore, the analog source driving the AD9460

should be ac-coupled to the input pins. The recommended

method for driving the analog input of the AD9460 is to use an

RF transformer to convert single-ended signals to differential

(see Figure 15). Series resistors between the output of the

transformer and the AD9460 analog inputs help isolate the

analog input source from switching transients caused by the

internal sample-and-hold circuit. The series resistors, along

with the 1 kΩ resisters connected to the internal 3.5 V bias,

must be considered in impedance matching the transformer

input. For example, if RT is set to 51 Ω, RS is set to 33 Ω and

there is a 1:1 impedance ratio transformer, the input will match a

50 Ω source with a full-scale drive of 16.0 dBm. The 50 Ω

impedance matching can also be incorporated on the secondary

side of the transformer, as shown in the evaluation board

schematic (see Figure 18).

3.5V

VIN+

VIN–

1.7V p-p

DIGITAL OUT = ALL 1s DIGITAL OUT = ALL 0s

05490-054

AD9460 Preliminary Technical Data

Rev. PrA| Page 18 of 28

05490-055

0.1

μF

AD9446

VIN+

VIN–

ADT1–1WT

ANALOG

INPUT

SIGNAL

Figure 15. Transformer-Coupled Analog Input Circuit

CLOCK INPUT CONSIDERATIONS

Any high speed ADC is extremely sensitive to the quality of the

sampling clock provided by the user. A track-and-hold circuit is

essentially a mixer, and any noise, distortion, or timing jitter on

the clock is combined with the desired signal at the analog-to-

digital output. For that reason, considerable care was taken in

the design of the clock inputs of the AD9460, and the user is

advised to give careful thought to the clock source.

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals and, as a result, may be sensitive

to the clock duty cycle. Commonly a 5% tolerance is required on

the clock duty cycle to maintain dynamic performance charac-

teristics. The AD9460 contains a clock duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal ~50% duty cycle. Noise and distortion per-

formance are nearly flat for a 30% to 70% duty cycle with the DCS

enabled. The DCS circuit locks to the rising edge of CLK+ and

optimizes timing internally. This allows for a wide range of input

duty cycles at the input without degrading performance. Jitter in

the rising edge of the input is still of paramount concern and is

not reduced by the internal stabilization circuit. The duty cycle

control loop does not function for clock rates of less than 30 MHz

nominally. The loop is associated with a time constant that

should be considered in applications where the clock rate can

change dynamically, requiring a wait time of 1.5 μs to 5 μs after a

dynamic clock frequency increase or decrease before the DCS

loop is relocked to the input signal. During the time that the

loop is not locked, the DCS loop is bypassed, and the internal

device timing is dependent on the duty cycle of the input clock

signal. In such an application, it may be appropriate to disable the

duty cycle stabilizer. In all other applications, enabling the DCS

circuit is recommended to maximize ac performance.

The DCS circuit is controlled by the DCS MODE pin; a CMOS

logic low (AGND) on DCS MODE enables the duty cycle stabilizer,

and logic high (AVDD1 = 3.3 V) disables the controller.

The AD9460 input sample clock signal must be a high quality,

extremely low phase noise source to prevent degradation of per-

formance. Maintaining 16-bit accuracy places a premium on the

encode clock phase noise. SNR performance can easily degrade

by 3 dB to 4 dB with 70 MHz analog input signals when using a

high jitter clock source. (See the AN-501 Application Note,

“Aperture Uncertainty and ADC System Performance.”) For

optimum performance, the AD9460 must be clocked differentially.

The sample clock inputs are internally biased to ~1.5 V, and the

input signal is usually ac-coupled into the CLK+ and CLK− pins

via a transformer or capacitors. Figure 16 shows one preferred

method for clocking the AD9460. The clock source (low jitter)

is converted from single-ended to differential using an RF trans-

former. The back-to-back Schottky diodes across the secondary

of the transformer limit clock excursions into the AD9460 to

approximately 0.8 V p-p differential. This helps prevent the large

voltage swings of the clock from feeding through to other portions

of the AD9460 and limits the noise presented to the sample

clock inputs.

If a low jitter clock is available, it may help to band-pass filter

the clock reference before driving the ADC clock inputs. Another

option is to ac couple a differential ECL/PECL signal to the encode

input pins, as shown in Figure 17.

05490-056

0.1

μF

AD9446

CLK+

CLK–

HSMS2812

DIODES

CRYSTAL

SINE

SOURCE

ADT1–1WT

Figure 16. Crystal Clock Oscillator, Differential Encode

05490-057

0.1

μF

AD9446

ENCODE

0.1μF

ECL/

PECL

Figure 17. Differential ECL for Encode

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR at a given input

frequency (fINPUT) and rms amplitude due only to aperture jitter

(tJ) can be calculated using the following equation:

SNR = 20 log[2πfINPUT × tJ]

In the equation, the rms aperture jitter represents the root-mean-

square of all jitter sources, which includes the clock input, analog

input signal, and ADC aperture jitter specification. IF under-

sampling applications are particularly sensitive to jitter

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9460.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter crystal-controlled oscillators make

the best clock sources. If the clock is generated from another type

of source (by gating, dividing, or another method), it should be

synchronized by the original clock during the last step.

AD9460

Preliminary Technical Data AD9460

Rev.PrA | Page 19 of 28

POWER CONSIDERATIONS

Care should be taken when selecting a power source. The use of

linear dc supplies is highly recommended. Switching supplies

tend to have radiated components that may be received by the

AD9460. Each of the power supply pins should be decoupled as

closely to the package as possible using 0.1 μF chip capacitors.

The AD9460 has separate digital and analog power supply pins.

The analog supplies are denoted AVDD1 (3.3 V) and AVDD2

(5 V), and the digital supply pins are denoted DRVDD. Although

the AVDD1 and DRVDD supplies can be tied together, best per-

formance is achieved when the supplies are separate. This is

because the fast digital output swings can couple switching

current back into the analog supplies. Note that both AVDD1

and AVDD2 must be held within 5% of the specified voltage.

The DRVDD supply of the AD9460 is a dedicated supply for the

digital outputs in either LVDS or CMOS output mode. When in

LVDS mode, the DRVDD should be set to 3.3 V. In CMOS mode,

the DRVDD supply can be connected from 2.5 V to 3.6 V for

compatibility with the receiving logic.

DIGITAL OUTPUTS

LVDS Mode

The off-chip drivers on the chip can be configured to provide

LVDS-compatible output levels via Pin 3 (OUTPUT MODE).

LVDS outputs are available when OUTPUT MODE is CMOS

logic high (or AVDD1 for convenience) and a 3.74 kΩ RSET

resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic

performance, including both SFDR and SNR, is maximized

when the AD9460 is used in LVDS mode; designers are

encouraged to take advantage of this mode. The AD9460

outputs include complimentary LVDS outputs for each data bit

(Dx+/Dx−), the overrange output (OR+/OR−), and the output

data clock output (DCO+/DCO−). The RSET resistor current is

multiplied on-chip, setting the output current at each output

equal to a nominal 3.5 mA (11 × IRSET). A 100 Ω differential

termination resistor placed at the LVDS receiver inputs results

in a nominal 350 mV swing at the receiver. LVDS mode

facilitates interfacing with LVDS receivers in custom ASICs and

FPGAs that have LVDS capability for superior switching

performance in noisy environments. Single point-to-point net

topologies are recommended, with a 100 Ω termination resistor

located as close to the receiver as possible. It is recommended to

keep the trace length less than 2 inches and to keep differential

output trace lengths as equal as possible.

CMOS Mode

In applications that can tolerate a slight degradation in dynamic

performance, the AD9460 output drivers can be configured to

interface with 2.5 V or 3.3 V logic families by matching

DRVDD to the digital supply of the interfaced logic. CMOS

outputs are available when OUTPUT MODE is CMOS logic

low (or AGND for convenience). In this mode, the output data

bits, Dx, are single-ended CMOS, as is the overrange output,

OR+. The output clock is provided as a differential CMOS

signal, DCO+/DCO−. Lower supply voltages are recommended

to avoid coupling switching transients back to the sensitive

analog sections of the ADC. The capacitive load to the CMOS

outputs should be minimized, and each output should be

connected to a single gate through a series resistor (220 Ω) to

minimize switching transients caused by the capacitive loading.

TIMING

The AD9460 provides latched data outputs with a pipeline delay

of 13 clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and

Figure 3 for detailed timing diagrams.

AD9460 Preliminary Technical Data

Rev. PrA| Page 20 of 28

OPERATIONAL MODE SELECTION

Data Format Select

The data format select (DFS) pin of the AD9460 determines

the coding format of the output data. This pin is 3.3 V CMOS

compatible, with logic high (or AVDD1, 3.3 V) selecting twos

complement and DFS logic low (AGND) selecting offset binary

format. Table 10 summarizes the output coding.

Output Mode Select

The OUPUT MODE pin controls the logic compatibility,

as well as the pinout of the digital outputs. This pin is a CMOS-

compatible input. With OUTPUT MODE = 0 (AGND), the

AD9460 outputs are CMOS compatible, and the pin assignment

for the device is as defined in Table 8. With OUTPUT MODE = 1

(AVDD1, 3.3 V), the AD9460 outputs are LVDS compatible, and

the pin assignment for the device is as defined in Table 7.

Duty Cycle Stabilizer

The DCS circuit is controlled by the DCS MODE pin; a CMOS

logic low (AGND) on DCS MODE enables the DCS, and logic

high (AVDD1, 3.3 V) disables the controller.

Table 10. Digital Output Coding

Code

VIN+ − VIN−

Input Span = 3.4 V p-p (V)

VIN+ − VIN−

Input Span = 2 V p-p (V)

Digital Output

Offset Binary (D15••••••D0)

Digital Output

Twos Complement (D15••••••D0)

65,536 +1.700 +1.000 1111 1111 1111 1111 0111 1111 1111 1111

32,768 0 0 1000 0000 0000 0000 0000 0000 0000 0000

32,767 −0.000052 −0.000031 0111 1111 1111 1111 1111 1111 1111 1111

0 −1.70 −1.00 0000 0000 0000 0000 1000 0000 0000 0000

Preliminary Technical Data AD9460

Rev.PrA | Page 21 of 28

EVALUATION BOARD

Evaluation boards are offered to configure the AD9460 in either

CMOS or LVDS mode only. This design represents a recom-

mended configuration for using the device over a wide range of

sampling rates and analog input frequencies. These evaluation

boards provide all the support circuitry required to operate

the ADC in its various modes and configurations. Complete

schematics are shown in Figure 18 through Figure 21. Gerber

files are available from engineering applications demonstrating

the proper routing and grounding techniques that should be

applied at the system level.

It is critical that signal sources with very low phase noise

(<60 fsec rms jitter) be used to realize the ultimate performance

of the converter. Proper filtering of the input signal to remove

harmonics and lower the integrated noise at the input is also

necessary to achieve the specified noise performance.

The evaluation boards are shipped with a 115 V ac to 6 V dc

power supply. The evaluation boards include low dropout

regulators to generate the various dc supplies required by the

AD9460 and its support circuitry. Separate power supplies are

provided to isolate the DUT from the support circuitry. Each

input configuration can be selected by proper connection of

various jumpers (see Figure 18).

The LVDS mode evaluation boards include an LVDS-to-CMOS

translator, making them compatible with the high speed ADC

FIFO evaluation kit (HSC-ADC-EVALA-SC). The kit includes a

high speed data capture board that provides a hardware solution

for capturing up to 32 kB samples of high speed ADC output

data in a FIFO memory chip (user upgradeable to 256 kB

samples). Software is provided to enable the user to download

the captured data to a PC via the USB port. This software also

includes a behavioral model of the AD9460 and many other

high speed ADCs.

Behavioral modeling of the AD9460 is also available at

www.analog.com/ADIsimADC. The ADIsimADC™ software

supports virtual ADC evaluation using ADI proprietary behavioral

modeling technology. This allows rapid comparison between the

AD9460 and other high speed ADCs with or without hardware

evaluation boards.

The user can choose to remove the translator and terminations

to access the LVDS outputs directly.

AD9460 Preliminary Technical Data

Rev. 0 | Page 22 of 28

OPTIONAL

81 45

100

89 36

101

R11

1kΩ

VCC

GND

3.74kΩ

DRGND

DRVDD

E24

EXTREF

D0_C (LSB)

D0_T

D1_C

D1_T

D3_C

D3_T

D4_C

D4_T

D5_C

D5_T

D7_C

D7_T

D8_C/D0_Y

D8_T/D1_Y

D9_C/D2_Y

D9_T/D3_Y

D10_C/D4_Y

C98

DNP

GND

D15_C/D14_Y

E41

E25

E27

E26

VCC

GND

E6 E5

GND

0.1μF

C86

0.1μF

DNP

GND

VCC

D14_C/D12_Y

DRGND

D6_T

D2_T

DRGND

D13_T/D11_Y

D10_T/D5_Y

DRB

D6_C

D2_C

DRVDD

D14_T/D13_Y

GND

VCC

D13_C/D10_Y

D12_T/D9_Y

D12_C/D8_Y

D11_T/D7_Y

D11_C/D6_Y

DRVDD

VCC

GND

VCC

ENCB

GND

ENC

GND

VCC

GND

VCC

5V 5V

GND

SCLK

VCC

GND

VCC

GND

C13

DNP

R35

33Ω

R28

33Ω

DNP

C91

0.1μF

GND

VCC

GND

VCC

EPAD

AD9445/AD9446

36Ω

P22

PTMICRO4

VCC

GND

P21

PTMICRO4

EXTREF

DRVDD

XTALPWR

DRGND

DCS MODE

DNC

OUTPUT MODE

DFS

LVDSBIAS

AVDD1

SENSE

VREF

AGND

REFT

REFB

AVDD2

AVDD1

AGND

VIN+

VIN–

AGND

AVDD2

VCC

DRGND

DOR_C

DOR_T/DOR_Y

GND

VCC

DRVDD

(MSB) D15_T/D15_Y

E1 E9

E10

GND

VCC

E14 E2

GND

VCC

E66 E18

E19

GND

VCC

C12

0.1μF

SMBMST

DNP

GND

TINB

GND

ANALOG

10nH

E15 R6

36Ω

DNP C51

10μFC2

0.1μF

C40

0.1μF

GND

05490-059

DRGND

D10_T

D10_C

D9_T

D9_C

D8_T

D8_C

DCO

DCOB

D7_T

D7_C

DRVDD

DRGND

D6_T

D6_C

D5_T

D5_C

D4_T

D4_C

D3_T

D3_C

D2_T

D2_C

D1_T

D1_C

D12_T

D12_C

D11_T

D11_C

DRVDD

AGND

AVDD1

OR_C

OR_T

AGND

AVDD1

DRVDD

DRGND

D15_T

D15_C

D14_T

D14_C

D13_T

D13_C

AVDD2

AVDD1

AVDD2

AVDD1

AVDD2

AVDD1

ENC

AGND

ENCB

AGND

AVDD1

AGND

DRGND

DRVDD

D0_C

D0_T

MTHOLE6

GND

DRGND

MTHOLE6

GND C39

10μF

TOUT

TOUTB

0.1μF

PRI SEC

GND

ADT1-1WT

GND

TINB TOUTB

TOUT

PRI SEC

ETC1-1-13

PRI SEC

ETC1-1-13

Figure 18. AD9460 Evaluation Board Schematic

AD9460

Preliminary Technical Data AD9460

Rev. 0 | Page 23 of 28

OUT OUT1

C34

10μF

C89

10μF

ADP3338

U14

GND

5VX

5VX5V

GND

VIN

GND

OUT OUT1

3.3V

FERRITE

10μF

C87

10μF

ADP3338

GND

VCCX

GND

VIN

GND

OUT OUT1

3.3V

10μF

C88

10μF

ADP3338

DRGND

DRVDD

DRVDDX

DRGND

VIN

GND

PJ-102A

C33

10μF

GND

VIN

POWER OPTIONS

ADT1-1WT

PRI SEC

ENC

ENCB

GND

SMBMST

DNP

R39

0Ω

50Ω

C26

0.1μF

C36

DNP

CR2

CR1

C42

0.1μFGND

XTALINPUT

GND

CR2 TO MAKE LAYOUT AND PARASITIC

LOADING SYMMETRICAL

SMBMST

ENCODE

GND

OUTVCC

VEE ~OUT

GND

XTALINPUT

E30

10μF

E31

ECLOSC

E20

VXTAL

GND

XTALPWR

VXTAL

+C44

10μF

C41

0.1μF

OPTIONAL ENCODE CIRCUITS

VCCXVCC

FERRITE

DRVDDXDRVDD

FERRITE

DRGNDGND

DNP

05490-060

Figure 19. AD9460 Evaluation Board Schematic (Continued)

AD9460 Preliminary Technical Data

Rev. 0 | Page 24 of 28

C96

0.1μFC97

0.1μFC84

0.1μFC46

0.1μF

C22

0.1μFC59

0.1μFC93

0.1μF

C94

0.1μFC95

0.1μF

GND

C60

0.1μFC10

0.1μFC61

0.1μFC75

0.1μF

C27

0.1μFC90

0.1μFC50

0.1μF

C30

0.01μFC28

0.1μF

C35

0.1μFC32

0.1μF

VCC

BYPASS CAPACITORS

GND

C31

XX C38

XX C29

XX C19

C17

XX C16

XX C15

C11

XX C14

VCC

GND

C37

0.1μFC48

0.1μFC18

0.1μF

C53

0.1μFC52

0.1μFC58

0.01μF

C56

10μF

+C85

0.1μF

GND

C110

C108

XX C109

C72

XX C73

GND

C21

0.1μFC20

0.1μF

C65

10μF

+C47

0.1μFC23

0.1μF

DRVDD

DRGND

C64

10μF

+C43

0.1μF

C45

XX C49

C69

XX C70

DRVDD

DRGND

C55

10μF

EXTREF

GND

05490-061

Figure 20. AD9460 Evaluation Board Schematic (Continued)

Preliminary Technical Data AD9460

Rev. 0 | Page 25 of 28

05490-062

RSO16ISO

220

RSO16ISO

220

RZ4

RZ5

D1O

D0O

D2O

D4O

D5O

D6O

D7O

D3O

D8O

D9O

D10O

D11O

D12O

D13O

D14O

D15O

GND5

VCC6

VCC5

GND4

END

D4Y

D3Y

D2Y

D1Y

ENC

C4Y

C3Y

C2Y

C1Y

GND3

VCC4

VCC3

GND2

B4Y

B3Y

B2Y

B1Y

ENB

A4Y

A3Y

A2Y

A1Y

ENA

GND1

VCC2

VCC1

GND

D4B

D4A

D3B

D3A

D2B

D2A

D1B

D1A

C4B

C4A

C3B

C3A

C2B

C2A

C1B

C1A

B4B

B4A

B3B

B3A

B2B

B2A

B1B

B1A

A4B

A4A

A3B

A3A

A2B

A2A

A1B

A1A

SN75LVDS386

D15_C/D14_Y

D14_C/D12_Y

D13_C/D10_Y

D12_C/D8_Y

D11_C/D6_Y

D10_C/D4_Y

D9_C/D2_Y

D3_C

D15_T/D14_Y

D14_T/D13_Y

D13_T/D11_Y

D12_T/D9_Y

D11_T/D7_Y

D10_T/D5_Y

D9_T/D3_Y

D8_T/D1_Y

D8_C/D0_Y

D7_T

D7_C

D6_T

D6_C

D5_C

D5_T

D4_T

D4_C

D3_T

D2_T

D2_C

D1_T

D1_C

D0_T

D0_C

DRVDD

DRGND

DRVDD

DRGND

DRVDD

DRGND

DRVDD

DRGND

P11

P13

P15

P17

P19

P21

P23

P25

P27

P29

P31

P33

P35

P37

P39

P10

P12

P14

P16

P18

P20

P22

P24

P26

P28

P30

P32

P34

P36

P38

P40

C40MS

D14_C/D12_Y

D12_C/D8_Y

D10_C/D4_Y

D8_C/DO_Y

DRB

D7_C

D4_C

D3_C

D2_C

D5_C

D6_C

D9_C/D2_Y

D11_C/D6_Y

D13_C/D10_Y

D1_C

DOR_C

DRGND

D15_C/D14_Y

DRGND

D0_C

D14_T/D13_Y

D12_T/D9_Y

D10_T/D5_Y

D8_T/D1_Y

D7_T

D4_T

D3_T

D2_T

D5_T

D6_T

D9_T/D3_Y

D11_T/D7_Y

D13_T/D11_Y

D1_T

DOR_T/DOR_Y

DRGND

D15_T/D15_Y

DRGND

D0_T R8

EN_3_4

GND

VCC

EN_1_2

U15

SN75LVDT390

R19

0Ω

R20

0Ω

DRB

DOR_C

DRO_T/DOR_Y

DRO

DRVDD

DRGND

ORO

DRVDD

C76

0.1μFC82

0.1μFC77

0.1μFC78

0.1μF

GND

P11

P13

P15

P17

P19

P21

P23

P25

P27

P29

P31

P33

P35

P37

P39

P10

P12

P14

P16

P18

P20

P22

P24

P26

P28

P30

P32

P34

P36

P38

P40

C40MS

D15O

D13O

D11O

D9O

D8O

D7O

D4O

D3O

D2O

D5O

D6O

D10O

D12O

D14O

D1O

DRO

DRGND DRGND

GND??

DRGND

ORO

DRGND

D0O

Figure 21. AD9460 Evaluation Board Schematic (Continued)

AD9460 Preliminary Technical Data

Rev. 0 | Page 26 of 28

Table 11. AD9460 Customer Evaluation Board Bill of Material

Item Qty.

Reference

Designator Description Package Value Manufacturer Mfg. Part No.

1 7

C4, C6, C33, C34, C87,

C88, C89

Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2

2 44

C2, C3, C5, C7, C8,

C9, C10, C11, C12,

C15, C20, C21, C22,

C23, C26, C27, C28,

C32, C35, C38, C40,

C42, C43, C46, C47,

C48, C50, C52, C53,

C59, C60, C76, C77,

C78, C82, C84, C85,

C86, C90, C91, C94,

C95, C96, C97

Capacitor 402 0.1 F Digi-Key Corporation PCC2146CT-ND

3 2 C30, C58 Capacitor 201 0.01 F Digi-Key Corporation 445-1796-1-ND

4 4 C39, C56, C64, C65 Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2

5 1 C51 Capacitor 805 10 F Digi-Key Corporation 490-1717-1-ND

6 1 CR1 Diode SOT23M5 Digi-Key Corporation

MA3X71600LCT-

7 1 CR2 Diode SOT23M5 Digi-Key Corporation

MA3X71600LCT-

8 20

E1, E2, E3, E4, E5, E6,

E9, E10, E14, E18, E19,

E20, E24, E25, E26, E27,

E30, E31, E36, E41

Header EHOLE Mouser Electronics 517-6111TG

9 2 J1, J4 SMA SMA Digi-Key Corporation ARFX1231-ND

10 1 L1 Inductor 0603A 10 nH Coilcraft, Inc. 0603CS-10NXGBU

11 3 L3, L4, L5 EMIFIL®

BLM31PG500SN1L

1206MIL Mouser Electronics 81-BLM31P500S

12 1 P4 PJ-002A PJ-002A Digi-Key Corporation CP-002A-ND

13 1 P7 Header C40MS Samtec, Inc. TSW-120-08-L-D-

14 1 R3 Resistor 402 3.74 kΩ Digi-Key Corporation P3.74KLCT-ND

15 1 R8 Resistor 402 50 Ω Digi-Key Corporation P49.9LCT-ND

16 4 R10, R19, R39, L2 Resistor 402 0 Ω Digi-Key Corporation P0.0JCT-ND

17 1 R11 BRES402 402 1 kΩ Digi-Key Corporation P1.0KLCT-ND

18 2 R28, R35 Resistor 402 33 Ω Digi-Key Corporation P33JCT-ND

19 2 RZ4, RZ5 Resistor array 16PIN 22 Ω Digi-Key Corporation 742C163220JCT-

20 2 T3, T5 Transformer ADT1-1WT Mini-Circuits ADT1-1WT

21 1 U1 AD9445BSVZ-125 SV-100-3 Analog Devices, Inc. AD9460BSVZ

22 1 U14 ADP3338-5 SOT-

223HS

Analog Devices, Inc. ADP3338-5

23 2 U3, U7 ADP3338-3.3 SOT-

223HS

Analog Devices, Inc. ADP3338-33

24 1 U8 SN75LVDT386 TSSOP64 Arrow Electronics, Inc. SN75LVDT386

25 1 U15 SN75LVDT390 SOIC16PW Arrow Electronics, Inc. SN75LVDT390

26 2 R4, R6 Resistor 402 36 Ω Digi-Key Corporation P36JCT-ND

27 2 C1, C44, C551 Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2

28 23

C13, C14, C16, C17,

C18, C19, C29, C31,

C36, C37, C41, C45,

C49, C61, C69, C70,

C72, C73, C75, C93,

C108, C109, C1101

CAP402 402 XX

29 1 C981 Capacitor 805 10 F Digi-Key Corporation 490-1717-1-ND

Preliminary Technical Data AD9460

Rev. 0 | Page 27 of 28

Item Qty.

Reference

Designator Description Package Value Manufacturer Mfg. Part No.

30 E151 Header EHOLE Mouser Electronics 517-6111TG

31 J51 SMA SMA Digi-Key Corporation ARFX1231-ND

32 P61 Header C40MS Samtec, Inc.

TSW-120-08-L-D-

33 2 R1, R21 BRES402 402 XX

34 3 R5, R7, R91 BRES402 402 XX

35 1 U21 ECLOSC DIP4(14)

36 4 H1, H2, H3, H41 MTHOLE6 MTHOLE6

37 2 T1, T21 Balun transformer SM-22 M/A-COM ETC1-1-13

38 2 P21, P221 Term strip PTMICRO4 Newark Electronics

1 Parts not populated.

AD9460 Preliminary Technical Data

Rev. 0 | Page 28 of 28

OUTLINE DIMENSIONS

COMP LIANT TO JEDEC S TANDARDS MS-026-AE D- HD

0.27

0.22

0.17

2526 49

76100 75

14.00 BSC SQ

16.00 BS C S Q

0.50 BS C

LEAD P ITCH

0.75

0.60

0.45

1.20

MAX

2650

76 100

1.05

1.00

0.95

0.20

0.09

0.08 M A X

COPLANARITY

VIEW A

RO TATE D 9 0

CCW

SEATING

PLANE

0° M IN

7°

3.5°

0°

0.15

0.05 VIEW A

PIN 1

TOP V IEW

(PINS DOWN)

BO T TOM V IEW

(PINS UP)

9.50 SQ

EXPOSED

PAD

NOTES

1. CENTER FIGURES ARE T Y P ICAL UNL E S S OTHERWISE NOTE D.

2. THE PACKAGE HAS A CO NDUCTIV E HEAT SLUG TO HELP DI S S IPATE HEAT AND ENSURE RELIABLE OPERATIO N OF

THE DE V ICE O V ER THE FULL INDUSTRIA L TEMP E RATURE RANG E. T HE SLUG IS EX P OSED ON THE BOTTOM OF

THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMME NDED THAT NO P CB S IGNAL

TRACE S OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE

SL UG.ATTACHING THE SLUG TO A GROUND PLANE W ILL REDUCE THE JUNCTION TE M PERATURE O F THE

DEVICE W HICH MAY BE BE NE FICIAL IN HIGH TEMP E RAT URE E NV IRONM E NTS.

Figure 22. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-100-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9460BSVZ-801 –40°C to +85°C 100-Lead TQFP_EP SV-100-3

AD9460-80LVDS/PCB AD9460-80LVDS Mode Evaluation Board

AD9460-105LVDS/PCB AD9460-105LVDS Mode Evaluation Board

1 Z = Pb-free part.

registered trademarks are the property of their respective owners.

PR06006-0-3/06(PrA)