Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6 1Publication Order Number:
SN74LS299/D
SN74LS299
8-Bit Shift/Storage Register
with 3-State Outputs
The SN74LS299 is an 8-Bit Universal Shift/Storage Register with
3-state outputs. Four modes of operation are possible: hold (store),
shift left, shift right and load data.
The parallel load inputs and flip-flop outputs are multiplexed to
reduce the total number of package pins. Separate outputs are provided
for flip-flops Q0 and Q7 to allow easy cascading. A separate active
LOW Master Reset is used to reset the register.
•Common I/O for Reduced Pin Count
•Four Operation Modes: Shift Left, Shift Right, Load and Store
•Separate Shift Right Serial Input and Shift Left Serial Input for Easy
Cascading
•3-State Outputs for Bus Oriented Applications
•Input Clamp Diodes Limit High-Speed Termination Ef fects
•ESD > 3500 Volts
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient
Temperature Range 0 25 70 °C
IOH Output Current – High
Q0, Q7–0.4 mA
IOL Output Current – Low
Q0, Q78.0 mA
IOH Output Current – High
I/O0 – 1/O7–2.6 mA
IOL Output Current – Low
I/O0 – 1/O724 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS299N 16 Pin DIP 1440 Units/Box
SN74LS299DW 16 Pin
SOIC
DW SUFFIX
CASE 751D
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 738
20
1
20
1
SN74LS299
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2
CONNECTION DIAGRAM DIP (TOP VIEW)
Clock Pulse (Active Positive–Going Edge) Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Parallel Data Input or
Parallel Output (3–State)
3–State Output Enable (Active LOW) Inputs
Serial Outputs
Asynchronous Master Reset (Active LOW) Input
Mode Select Inputs
CP
DS0
DS7
I/On
OE1, OE2
Q0, Q7
MR
S0, S1
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.5 U.L.
10 U.L.
0.5 U.L.
1 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
0.25 U.L.
5 U.L.
0.25 U.L.
0.5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
HIGH LOW
(Note a)LOADING
PIN NAMES
18 17 16 15 14 13
1234567
20 19
8
VCC
S0
S1Ds7 Q7I/O7I/O3
I/O5I/O1
OE1OE2I/O6I/O4I/O2I/O0Q0
910
MR GND
12 11
CP DS0
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
S1S0
DS0
CLOCK
Q0
MR
OE1
OE2
D
CLRQCK
I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7
DS7
Q7
VCC = PIN 20
GND = PIN 10
= PIN NUMBERS
14
1
2
67
3
8
45
9
11
12
13 15 16
17
18
19
D
CLRQCK D
CLRQCK D
CLR
QCK D
CLR
QCK D
CLR
QCK D
CLR
QCK D
CLRQCK
LOGIC DIAGRAM
SN74LS299
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3
FUNCTION TABLE
INPUTS RESPONSE
MR S1S0OE1OE2CP DS0DS7
L X X H X X X X
Asynchronous Reset
;
Q0=Q
7= LOW
L X X X H X X X
Asynchronous
Reset
Q0
=
Q7
=
LOW
I/O Voltage Undetermined
L H H X X X X X
I/O
Voltage
Undetermined
L L X L L X X X Asynchronous Reset; Q0 = Q7 = LOW
L X L L L X X X I/O Voltage LOW
H L H X X D X Shift Right; D
³
Q0; Q0
³
Q1; etc.
H L H L L D X Shift Right; D
³
Q0 & I/O0; Q0
³
O1 & I/O1; etc.
H H L X X X D Shift Left; D
³
Q7; Q7
³
Q6; etc.
H H L L L X D Shift Left; D
³
Q7 & I/O7; Q7
³
Q6 & I/O6; etc.
H H H X X X X Parallel Load; I/On
³
Qn
H L L H X X X X
Hold: I/O Voltage undetermined
H L L X H X X X
Hold:
I/O
Voltage
undetermined
H L L L L X X X Hold: I/On = Qn
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
SN74LS299
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4
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage 0.8 VGuaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage
I/O0–I/O72.4 3.1 V VCC = MIN, IOH = MAX
VOH Output HIGH Voltage
Q0, Q72.7 3.4 V VCC = MIN, IOH = MAX
VO
Output LOW Voltage 0.25 0.4 V IOL = 12 mA VCC = VCC MIN,
VIN =V
IL or VIH
V
OL
g
I/O0–I/O70.35 0.5 V IOL = 24 mA
V
IN =
V
IL
or
V
IH
per T ruth Table
VO
Output LOW Voltage 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN =V
IL or VIH
V
OL
g
I/O0–I/O70.5 V IOL = 8.0 mA
V
IN =
V
IL
or
V
IH
per T ruth Table
IOZH Output Off Current HIGH
I/O0–I/O740 µA VCC = MAX, VOUT = 2.7 V
IOZL Output Off Current LOW
I/O0–I/O7–400 µA VCC = MAX, VOUT = 0.4 V
Others 20 µA
I
I t HIGH C t
S0, S1,
I/O0–I/O740 µAVCC = MAX, VIN = 2.7 V
IIH Input HIGH Current Others 0.1 mA
VCC = MAX V =70V
S0, S10.2 mA
V
CC =
MAX
,
V
IN =
7
.
0
V
I/O0–I/O70.1 mA VCC = MAX, VIN = 5.5 V
I
In
p
ut LOW Current
Others –0.4 mA
VCC = MAX V =04V
I
IL
Inp
u
t
LOW
C
u
rrent
S0, S1–0.8 mA
V
CC =
MAX
,
V
IN =
0
.
4
V
IOS Short Circuit Current Q0, Q7–20 –100 mA VCC = MAX
(Note 1) I/O0–I/O7–30 –130 mA VCC = MAX
ICC Power Supply Current 53 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
SN74LS299
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5
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
fMAX Maximum Clock Frequency 25 35 MHz
tPHL
tPLH Propagation Delay, Clock
to Q0 or Q726
22 39
33 ns CL = 15 pF
tPHL Propagation Delay, Clear
to Q0 or Q727 40 ns
tPHL
tPLH Propagation Delay, Clock
to I/O0–I/O726
17 39
25 ns
tPHL Propagation Delay, Clear
to I/O0–I/O726 40 ns CL = 45 pF,
RL = 667 Ω
tPZH
tPZL Output Enable T ime 13
19 21
30 ns
tPHZ
tPLZ Output Disable T ime 10
10 15
15 ns CL = 5.0 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tWClock Pulse Width HIGH 25 ns
tWClock Pulse Width LOW 13 ns
tWClear Pulse Width LOW 20 ns
tsData Setup T ime 20 ns
VCC =50V
tsSelect Setup T ime 35 ns
V
CC =
5
.
0
V
thData Hold T ime 0 ns
thSelect Hold T ime 10 ns
trec Recovery Time 20 ns
SN74LS299
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6
1.3 V
1.3 V 1.3 V
1.3 V
VIN
VOUT
tPLH tPHL
1.3 V
1.3 V
VIN
VOUT 1.3 V
tPLH tPHL
1.3 V
Figure 1. Figure 2.
Figure 3. Figure 4.
1.5 V 1.5 V
1.5 V ≈ 1.5 V
1.5 V 1.5 V
1.5 V ≈ 1.5 V
VE
VE
VOUT
tPZL tPLZ
VOL
0.5 V
VE
VE
VOUT
tPZH tPHZ
0.5 V
≥ VOH
3-STATE WAVEFORMS
AC LOAD CIRCUIT
SW2CL*
5 kΩ
SW1
VCC
RL
TO OUTPUT
UNDER TEST
* Includes Jig and Probe Capacitance.
SWITCH POSITIONS
Closed
Open
Closed
Closed
Open
Closed
Closed
Closed
tPZH
tPZL
tPLZ
tPHZ
SW2SW1SYMBOL
Figure 5.
SN74LS299
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7
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J20 PL M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A25.66 27.171.010 1.070
B6.10 6.600.240 0.260
C3.81 4.570.150 0.180
D0.39 0.550.015 0.022
G2.54 BSC0.100 BSC
J0.21 0.380.008 0.015
K2.80 3.550.110 0.140
L7.62 BSC0.300 BSC
M0 15 0 15
N0.51 1.010.020 0.040
____
E1.27 1.770.050 0.070
1
11
10
20
–A–
SEATING
PLANE
K
N
FG
D20 PL
–T–
M
A
M
0.25 (0.010) T
E
B
C
F1.27 BSC0.050 BSC
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
20
1
11
10
B20X
H10X
C
L
18X A1
A
SEATING
PLANE
q
hX 45
_
E
D
M
0.25 M
B
M
0.25 S
AS
B
T
eT
B
A
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D12.65 12.95
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q
0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
__
SN74LS299
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8
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