MAX19527EVKIT+ - Maxim Integrated

EVALUATION KIT

AVAILABLE

_______________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Ultra-Low-Power, Octal, 12-Bit, 50Msps,

1.8V ADC with Serial LVDS Outputs

MAX19527

19-5309; Rev 0; 6/10

General Description

The MAX19527 is an octal, 12-bit analog-to-digital

converter (ADC), optimized for the low-power and

high-dynamic performance requirements of medical

imaging instrumentation and digital communications

applications. The device operates from a single 1.8V

supply and consumes 440mW (55mW per channel),

while providing a 69dBFS signal-to-noise ratio (SNR) at

a 5.3MHz input frequency. In addition to low operating

power, the device features programmable power man-

agement for idle states and reduced-channel operation.

An internal 1.25V precision bandgap reference sets the

full-scale range of the ADC to 1.5VP-P. A flexible refer-

ence structure allows the use of an external reference

for applications requiring greater gain accuracy or a

different input voltage range. A programmable common-

mode voltage reference output is provided to enable

DC-coupled input applications.

Various adjustments and feature selections are avail-

able through programmable registers that are accessed

through the 3-wire serial peripheral interface (SPIK).

A flexible clock input circuit allows for a single-ended,

logic-level clock or a differential clock signal. An on-chip

PLL generates the multiplied (6x) clock required for

the serial LVDS digital outputs. The serial LVDS output

provides programmable test patterns for data timing

alignment and output drivers with programmable current

drive and programmable internal termination.

The device is available in a small, 10mm x 10mm x

1.2mm, 144-lead thin chip ball grid array (CTBGA) pack-

age and is specified for the extended industrial (-40NC to

+85NC) temperature range.

Applications

Ultrasound and Medical Imaging

Instrumentation

Multichannel Communications

ZIF GSM and TD-SCDMA Transceivers

Features

S Ultra-Low-Power Operation

55mW per Channel at 50Msps

S Single 1.8V Power Supply

S Excellent Dynamic Performance

69dBFS SNR at 5.3MHz

140dBc/Hz Near-Carrier SNR at 1kHz Offset

from a 5.3MHz Tone

84dBc SFDR at 5.3MHz

90dB Channel Isolation at 5.3MHz

S User-Programmable Adjustment and Feature

Selection through an SPI Interface

S Serial LVDS Outputs with Programmable Current

Drive and Internal Termination

S Programmable Power Management

S Internal or External Reference Operation

S Single-Ended or Differential Clock Input

S Programmable Output Data Format

S Built-In Output Data Test Patterns

S Small, 10mm x 10mm, 144-Lead CTBGA Package

S Evaluation Kit Available (Order MAX19527EVKIT+)

Ordering Information

SPI is a trademark of Motorola, Inc.

+Denotes a lead(Pb)-free/RoHS-compliant package.

PART TEMP RANGE PIN-PACKAGE

MAX19527EXE+ -40NC to +85NC144 CTBGA

Ultra-Low-Power, Octal, 12-Bit, 50Msps,

1.8V ADC with Serial LVDS Outputs

MAX19527

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

AVDD, OVDD to GND ......................................... -0.3V to +2.1V

OGND to GND ......................................................-0.3V to +0.3V

IN_+, IN_-, CMOUT, REFIO, REFH,

REFL, CLKIN+, CLKIN- to GND ..............-0.3V to the lower of

(VAVDD + 0.3V) and +2.1V

OUT_+, OUT_-, FRAME+,

FRAME-, CLKOUT+, CLKOUT-,

SHDN, CS, SCLK, SDIO to GND .............-0.3V to the lower of

(VOVDD + 0.3V) and +2.1V

Continuous Power Dissipation (TA = +70NC)

144-Lead CTBGA (derate 37mW/NC above +70NC)

Multilayer Board ...................................................... 2963mW

Operating Temperature Range ......................... -40NC to +85NC

Junction Temperature ....................................................+150NC

Storage Temperature Range .......................... -65NC to +150NC

Lead Temperature (soldering, 10s) ................................+300NC

Soldering Temperature (reflow) ......................................+260NC

ELECTRICAL CHARACTERISTICS

(VAVDD = 1.8V, VOVDD = 1.8V, internal reference, AIN = -0.5dBFS, differential clock, VCLKD = 1.5VP-P, fCLK = 50MHz, programmable

registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted.) (Note 1)

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY

Resolution 12 Bits

Integral Nonlinearity INL fIN = 5.3MHz Q0.5 Q1.7 LSB

Differential Nonlinearity DNL fIN = 5.3MHz, no missing codes Q0.3 Q1.0 LSB

Offset Error OE Internal reference Q0.07 Q0.7 %FS

Gain Error GE External reference = 1.25V Q0.2 Q3.0 %FS

ANALOG INPUTS (IN_+, IN_-) (Figure 2)

Input Differential Range VDIFF IN_+ - IN_- 1.5 VP-P

Common-Mode Input Voltage

Range VCM Q50mV tolerance 1050 mV

Input Resistance RIN

Fixed resistance to GND > 100

Differential input resistance, common

mode connected to inputs 4

Input Current IIN Switched capacitance input current,

each input, VCM = 1.050V 36 FA

Input Capacitance

CINS Fixed capacitance to GND, each input 1

pFCIND Fixed differential capacitance 0.2

CSAMPLE Switched capacitance, each input 1.5

CONVERSION RATE

Maximum Clock Frequency fCLK 50 MHz

Minimum Clock Frequency fCLK 25 MHz

Data Latency Figure 5 8.5 Clock

Cycles

Ultra-Low-Power, Octal, 12-Bit, 50Msps,

1.8V ADC with Serial LVDS Outputs

MAX19527

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = 1.8V, VOVDD = 1.8V, internal reference, AIN = -0.5dBFS, differential clock, VCLKD = 1.5VP-P, fCLK = 50MHz, programmable

registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DYNAMIC PERFORMANCE

Small-Signal Noise Floor SSNF Analog input < -35dBFS, fIN = 5.3MHz -69.5 dBFS

Near-Carrier Signal-to-Noise

Ratio NCSNR

1kHz offset from 5.3MHz full-scale tone,

CREFIO = CREFH/REFL = 0.1FF

(Figure 3)

140 dBc/Hz

8-channel coherent sum 147

Signal-to-Noise Ratio SNR fIN = 5.3MHz at -0.5dBFS 67.0 68.5 dB

fIN = 19.3MHz at -0.5dBFS 68.5

Signal-to-Noise and Distortion

Ratio SINAD fIN = 5.3MHz at -0.5dBFS 66.6 68.2 dB

fIN = 19.3MHz at -0.5dBFS 68.2

Spurious-Free Dynamic Range SFDR fIN = 5.3MHz at -0.5dBFS 70.0 84 dBc

fIN = 19.3MHz at -0.5dBFS 84

Total Harmonic Distortion THD fIN = 5.3MHz at -0.5dBFS -81 -72 dBc

fIN = 19.3MHz at -0.5dBFS -81

Intermodulation Distortion IMD fIN1 = 5.15MHz at -6.5dBFS,

fIN2 = 5.45MHz at -6.5dBFS -83 dB

Full-Power Bandwidth FPBW RSOURCE = 50I differential > 500 MHz

Overdrive Recovery Time 6dB beyond full scale (recover accuracy

to < 1% of full scale) < 1 Clock

Cycles

INTERCHANNEL CHARACTERISTICS

Crosstalk fIN = 5.3MHz at -0.5dBFS -90 dB

Gain Matching fIN = 5.3MHz Q0.1 dB

Phase Matching fIN = 5.3MHz Q0.25 Degrees

ANALOG OUTPUT (CMOUT)

CMOUT Output Voltage VCMOUT Default programming state 1.05 1.10 1.15 V

INTERNAL REFERENCE

REFIO Output Voltage VREFIO Bypass only, no DC load 1.22 1.25 1.28 V

REFIO Temperature Coefficient TCREF < Q60 ppm/NC

REFH Voltage VREFH Bypass only, no DC load 1.61 V

REFL Voltage VREFL Bypass only, no DC load 0.86 V

EXTERNAL REFERENCE

REFIO Input Voltage Range VREFIN +5%/-15% tolerance 1.25 V

REFIO Input Resistance RREFIN 10 Q 20% kI

Ultra-Low-Power, Octal, 12-Bit, 50Msps,

1.8V ADC with Serial LVDS Outputs

MAX19527

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = 1.8V, VOVDD = 1.8V, internal reference, AIN = -0.5dBFS, differential clock, VCLKD = 1.5VP-P, fCLK = 50MHz, programmable

registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CLOCK INPUTS (CLKIN+, CLKIN-)—DIFFERENTIAL MODE (Figure 4)

Differential Clock Input Voltage VCLKD 0.4 to 2.0 VP-P

Common-Mode Voltage VCLKCM Self-biased 1.2 V

DC-coupled clock signal 1.0 to 1.4

Input Resistance RCLK

Differential, default setting 10

Differential, programmable internal

termination selected 0.1

Common mode to GND 9

Input Capacitance CCLK Capacitance to GND, each input 3 pF

CLOCK INPUTS (CLKIN+, CLKIN-)—SINGLE-ENDED MODE (CLKIN- < 0.1V) (Figure 4)

Single-Ended Mode Selection

Threshold (CLKIN-) VIL 0.1 V

Single-Ended Clock Input High

Threshold (CLKIN+) VIH 1.5 V

Single-Ended Clock Input Low

Threshold (CLKIN+) VIL 0.3 V

Input Leakage (CLKIN+) IIH VIH = 1.8V +5 FA

IIL VIH = 0V -5

Input Leakage (CLKIN-) IIL VIH = 0V -150 -50 FA

Input Capacitance (CLKIN+) 3 pF

DIGITAL INPUTS (SHDN, SCLK, SDIN, CS)

Input High Threshold VIH 1.5 V

Input Low Threshold VIL 0.3 V

Input Leakage IIH VIH = 1.8V +5 FA

IIL VIL = 0V -5

Input Capacitance CDIN 3 pF

DIGITAL OUTPUTS (SDIO)

Output Voltage Low VOL ISINK = 200FA0.2 V

Output Voltage High VOH ISOURCE = 200FAOVDD -

0.2 V

LVDS DIGITAL OUTPUTS (OUT_+/OUT_-, CLKOUT+/CLKOUT-, FRAME+/FRAME-)

Differential Output Voltage |VOD|External RLOAD = 100I250 450 mV

Output Offset Voltage VOS External RLOAD = 100I1.125 1.375 V

POWER-MANAGEMENT CHARACTERISTICS (Figure 3)

Wake-Up Time from Sleep Mode tSWAKE

Internal reference, CREFIO = 0.1FF,

CREFH/REFL = 0.1FF; Q1% gain error,

with respect to steady-state gain

10 ms

Wake-Up Time from Nap Mode tNWAKE

Internal reference, CREFIO = 0.1FF,

CREFH/REFL = 0.1FF; Q1% gain error,

with respect to steady-state gain

2Fs