1999-2013 Microchip Technology Inc. DS41106C-page 1
PIC16C712/716
Devices included in thi s Data Sheet:
• PIC16C712 • PIC16C716
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single-word instructions to learn
• All single-c ycle instructions except for program
branches which are two cycle
• Operating speed: DC – 20 MHz clock input
DC – 200 n s instruction cycle
• Interrupt capability
(up to 7 internal/external interrupt sources)
• Eight-level deep hardware stac k
• Direct, Indirect and Relative Addressing modes
• Pow er-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for r eliable operat ion
• Brown-out detection circuitry for
Brown-out Reset (BOR)
• Programmable code -protection
• Power- s aving Sleep mode
• Selectable osci llator opt ions
• Low-p ower, high-speed CMOS EPROM
technology
• Fully static design
•In-Circuit Serial Programming(ICSP™)
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
•Commercial , Industrial and Extended temperature
ranges
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 22.5 A, typical @ 3V, 32 kHz
-< 1 A, typical standby current
Pin Diagrams
Peripheral Feat ures:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler
can be increm ent ed duri ng Slee p via extern al
crystal/clock
• Timer2: 8-bit time r/counter with 8-bit period
register, prescaler and postscaler
• Capture , Comp a r e, PWM mo dul e
• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM ma ximum r esolution is 10-bit
• 8-bit multi-channel Analog-to-Digital converter
Device Program
Memory Data Memory
PIC16C712 1K 128
PIC16C716 2K 128
PIC16C712
RA2/AN2
RA4/T0CKI
RB0/INT
RB1/T1OSO/T1CKI
RA0/AN0
OSC1/CLKIN
RB7
RB6
1
2
3
4
5
6
7
18
17
16
15
14
13
12
8
9
11
10
18-pin PDIP, SOIC, Windowed CERDIP
MCLR/VPP
RA3/AN3/VREF
RB2/T1OSI
RB3/CCP1 RB4
RB5
RA1/AN1
VDD
OSC2/CLKOUT
VSS
PIC16C716
PIC16C712
RA2/AN2
RA4/T0CKI
RB0/INT
RB1/T1OSO/T1CKI
RA0/AN0
OSC1/CLKIN
RB7
RB6
1
2
3
4
5
6
7
20
19
18
17
16
15
14
8
9
13
12
20-pin SSOP
MCLR/VPP
RA3/AN3/VREF
RB2/T1OSI
RB3/CCP1 RB4
RB5
RA1/AN1
VDD
OSC2/CLKOUT
VSS
PIC16C716
10
VSS VDD
11
8-Bit CMOS Microcontrollers with A/D Conve rte r
and Capture/Compare/PWM
PIC16C712/716
DS41106C-page 2 1999-2013 Microchip Technology Inc.
PIC16C7XX FAMILY OF DEVICES
Key Feature s
PIC® Mid-Range Referen ce Ma nual (DS33023) PIC16C712 PIC16C716
Operating Frequency DC – 20 MHz DC – 20 MHz
Resets (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST)
Program Memory (14-bit words) 1K 2K
Data Memory (bytes) 128 128
Interrupts 7 7
I/O Ports Ports A,B Ports A, B
Timers 3 3
Capt ure/ Compare/PWM modules 1 1
8-bit Analog-to-Digital Module 4 input channels 4 input channels
PIC16C710 PIC16C71 PIC16C711 PIC16C712 PIC16C715 PIC16C716 PIC16C72A PIC16C73B
Clock Maximum Frequency
of Operation (MHz) 20 20 20 20 20 20 20 20
Memory
EPROM Program
Memory
(x14 words)
512 1K 1K 1K 2K 2K 2K 4K
Data Memory (bytes) 36 36 68 128 128 128 128 192
Peripherals
Timer Mo dul e (s) TMR0 TMR0 TMR0 TMR0
TMR1
TMR2
TMR0 TMR0
TMR1
TMR2
TMR0
TMR1
TMR2
TMR0
TMR1
TMR2
Capture/Compare/
PWM Module(s) ——— 1 — 1 1 2
Serial Port(s)
(SPI™/I2C™, USART) — — — — — — SPI/I2C SPI/I2C,
USART
A/D Converter (8-bit)
Channels 444 4 4 4 5 5
Features
Interrupt Sources 4 4 4 7 4 7 8 11
I/O Pins 13 13 13 13 13 13 22 22
Voltage Range (Volts) 2.5-6.0 3.0-6.0 2.5-6.0 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5
In-Circuit Serial
Programming™ Yes Yes Yes Yes Yes Yes Yes Yes
Brown-out Reset Yes — Yes Y es Yes Yes Yes Yes
Packages 18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC 18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
28-pin SDIP,
SOIC, SSOP 28-pin SDIP,
SOIC
1999-2013 Microchip Technology Inc. DS41106C-page 3
PIC16C712/716
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory O rganization................................................................................................................................................................... 9
3.0 I/O Ports......... ........... .......... ........... .......... ..................... ........... .......... ........... .......... . .................................................................. 21
4.0 Timer0 Module ........................................................................................................................................................................... 29
5.0 Timer1 Module ........................................................................................................................................................................... 31
6.0 Timer2 Module ........................................................................................................................................................................... 36
7.0 Capture/Compare/PWM (CCP) Module(s)................................................................ ................................................................. 39
8.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 45
9.0 Speci a l Features of the CPU.............. ........... ..................... .......... ........... ..................... .............................................................. 51
10.0 Instruction Set Summary............................................................................................................................................................ 67
11.0 Developm ent Suppor t. ................................................................................................................................................................ 69
12.0 Electrical Characteristics............................................................................................................................................................ 73
13.0 Packagin g In fo rmation................ .......... ........... ..................... .......... ........... ..................... ............................................................ 89
Revision History .................................................................................................................................................................................. 95
Conversi o n Co n side rations ............... ..................... .......... ..................... ..................... ........... .............................................................. 95
Migration from Base-line to Mid-Range Devices ..................................... .... ......... .... .... .... ........... .... .................................................... 95
Index ................................................................................................................................................................................................... 97
On-Line Support........................ .... ......... .... .... .... ......... .... .... .... ......... .... .... .... ......... .... .... .. ................................................................... 101
Reader Response.............................................................................................................................................................................. 102
PIC16C712/716 Product Identification System.................................. .... .... .... ........... .... .... ........... .... .................................................. 103
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PIC16C712/716
DS41106C-page 4 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41106C-page 5
PIC16C712/716
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PIC® Mid-
Range Reference Manual, (DS33023), which may be
obtained from your local Microchip Sales Representa-
tive or downloaded from the Microchip web site. The
Reference Manual should be considered a comple-
ment ary do cumen t to thi s dat a she et, and is hig hly re c-
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
There are two devices (PIC16C712, PIC16C716)
covered by this data sheet.
Figure 1-1 is the block diagram for both devices. The
pinouts are listed in Table 1-1.
FIGURE 1-1: PIC16C712/716 BLOCK DIAGRAM
EPROM
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction Reg
Progra m Counter
8 Level Sta c k
(13-bit)
RAM
File
Registers
Direct Addr 7
RAM Addr(1) 9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
RB0/INT
RB1/T1OSO/T1CKI
RB2/T1OSI
RB3/CCP1
RB4
RB5
RB6
RB7
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
CCP1 A/D
Timer0 Timer1 Timer2
RA4/T0CKI
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
8
3
1K X 14
128 x 8
or
2K x 14
PIC16C712/716
DS41106C-page 6 1999-2013 Microchip Technology Inc.
TABLE 1-1: PIC16C712/716 PINOUT DESCRIPTION
Pin PIC16C712/716 Pin Buffer
Name DIP, SOIC SSOP Type Type Description
MCLR/VPP
MCLR
VPP
44I
P
ST Master clear (Reset) input. This pin is
an active low Reset to the device.
Programmi ng vo lt age input
OSC1/CLKIN
OSC1
CLKIN
16 18 I
I
ST
CMOS
Oscillato r c ryst al i nput o r exte rnal c lock
source input. ST buffer when config-
ured in RC mode. CMOS otherwise.
External clock source in put.
OSC2/CLKOUT
OSC2
CLKOUT
15 17 O
O
—
—
Oscillator crystal output. Connects to
crystal or resonator in crystal oscillator
mode.
In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency
of OSC1, and denotes the instruction
cycl e rate.
PORTA is a bidi rectional I/O port.
RA0/AN0
RA0
AN0
17 19 I/O
ITTL
Analog Digital I/O
Analog input 0
RA1/AN1
RA1
AN1
18 20 I/O
ITTL
Analog Digital I/O
Analog input 1
RA2/AN2
RA2
AN2
11
I/O
ITTL
Analog Digital I/O
Analog input 2
RA3/AN3/VREF
RA3
AN3
VREF
22
I/O
I
I
TTL
Analog
Analog
Digital I/O
Analog input 3
A/D Reference Voltage input.
RA4/T0CKI
RA4
T0CKI
33
I/O
I
ST/OD
ST
Digital I/O. Open drain when conf igured
as output.
Timer0 external clock input
Legend: TTL = TTL-compatible inpu t CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
OD = Open drain output
SM = SMBus compatible input. An external resi stor is required if this pin is used as an output
NPU = N-channel pull-up PU = Weak internal pull-up
No-P diode = No P-diode to VDD AN = Analog input or output
I = input O = output
P = Power L = LCD Driver
1999-2013 Microchip Technology Inc. DS41106C-page 7
PIC16C712/716
PORTB is a bidirectional I/O port. PORTB
can be software programmed for internal
weak pull-u ps on all inputs.
RB0/INT
RB0
INT
67
I/O
ITTL
ST Digital I/O
External Interrupt
RB1/T1OSO/T1CKI
RB1
T1OSO
T1CKI
78
I/O
O
I
TTL
—
ST
Digital I/O
Timer1 oscillator output. Connects to
crystal in oscillator mode.
Timer1 external clock input.
RB2/T1OSI
RB2
T1OSI
89
I/O
ITTL
—Digital I/O
Timer1 oscillator inp ut. Connects to
crystal in oscillator mode.
RB3/CCP1
RB3
CCP1
910
I/O
I/O TTL
ST Digital I/O
Capture1 input, Compare1 output,
PWM1 output.
RB4 10 12 I/O TTL Digital I/O
Interrupt on change pin.
RB5 11 12 I/O TTL Digital I/O
Interrupt on change pin.
RB6 12 13 I/O
I
TTL
ST
Digital I/O
Interrupt on change pin.
ICSP programming clock.
RB7 13 14 I/O
I/O
TTL
ST
Digital I/O
Interrupt on change pin.
ICSP pro gramming data.
VSS 5 5, 6 P — Ground reference for logic and I/O pins.
VDD 14 15, 16 P — Positive supply for logic and I/O pins.
Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
OD = Open drain output
SM = SMBus compatible input. An external resi stor is required if this pin is used as an output
NPU = N-channel pull-up PU = Weak internal pull-up
No-P diode = No P-diode to VDD AN = Analog input or output
I = input O = output
P = Power L = LCD Driver
TABLE 1-1: PIC16C712/716 PINOUT DESCRIPTION (CONTINUED)
Pin PIC16C712/716 Pin Buffer
Name DIP, SOIC SSOP Type Type Description
PIC16C712/716
DS41106C-page 8 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41106C-page 9
PIC16C712/716
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these PIC®
microc ontroller d evices. Ea ch bloc k (Progra m Memo ry
and Data Memory) has its own bus so that concurrent
access can occur.
Addit ional informat ion on devi ce memory may be found
in the PIC® Mid-Range Reference M anual, (DS33 023).
2.1 Program Memory Organization
The PIC16C712/716 has a 13-bit Program Counter
(PC) capable of addressing an 8K x 14 program mem-
ory spac e. PI C16C7 12 has 1K x 14 w ords of prog ram
memory and PIC16C716 has 2K x 14 words of program
memory. Accessing a location above the physically
implemented address will cause a wraparound.
The Res et vector is at 000 0h and the interru pt vector is
at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK OF THE
PIC16C712
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK OF PIC16C716
PC<12:0>
13
0000h
0004h
0005h
03FFh
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
0400h
User Memory
Space
PC<12:0>
13
0000h
0004h
0005h
07FFh
0800h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Progra m
Memory
CALL, RETURN
RETFIE, RETLW
User Memory
Space
PIC16C712/716
DS41106C-page 10 1999-2013 Microchip Technology Inc.
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Sp ecia l Fu nct ion Re gis ters . Bi ts RP1 a nd R P0 are the
bank select bits.
= 00 Bank 0
= 01 Bank 1
= 10 Bank 2 (not implemented)
= 11 Bank 3 (not implemented)
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Funct ion Regi ste rs. S ome “hig h us e” Special Fun cti on
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly, or
indirectly through the File Select Register FSR (see
Section 2.5 “Indirect Addressing, INDF and FSR
Registers”).
FIGURE 2-3: REGISTER FILE MAP
RP1(1) RP0 (STATUS<6:5>)
Note 1: Maintain this bit clear to ensure upward
compatibility with future products.
Unimplemented data memory locations,
read as ‘0’.
Note 1: Not a physical register.
File
Address File
Address
00h INDF(1) INDF(1) 80h
01h TMR0 OPTION_REG 81h
02h PCL PCL 82h
03h STATUS STATUS 83h
04h FSR FSR 84h
05h PORTA TRISA 85h
06h PORTB TRISB 86h
07h DATACCP TRISCCP 87h
08h 88h
09h 89h
0Ah PCLATH PCLATH 8Ah
0Bh INTCON INTCON 8Bh
0Ch PIR1 PIE1 8Ch
0Dh 8Dh
0Eh TMR1L PCON 8Eh
0Fh TMR1H 8Fh
10h T1CON 90h
11h TMR2 91h
12h T2CON PR2 92h
13h 93h
14h 94h
15h CCPR1L 95h
16h CCPR1H 96h
17h CCP1CON 97h
18h 98h
19h 99h
1Ah 9Ah
1Bh 9Bh
1Ch 9Ch
1Dh 9Dh
1Eh ADRES 9Eh
1Fh ADCON0 ADCON1 9Fh
20h
General
Purpose
Registers
96 Bytes
General
Purpose
Registers
32 Bytes
A0h
BFh
C0h
7Fh FFh
Bank 0 Bank 1
1999-2013 Microchip Technology Inc. DS41106C-page 11
PIC16C712/716
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
give in Table 2-1.
The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in that
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi t 2 Bit 1 Bit 0 Value o n:
POR,
BOR
Value on
all other
Resets (4)
Bank 0
00h INDF(1) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 T imer0 Mod ule’s Register xxxx xxxx uuuu uuuu
02h PCL(1) Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS(1) IRP(4) RP1(4) RP0 TO PD ZDCCrr01 1xxx rr0q quuu
04h FSR(1) I ndir ect Data Memo ry Addr ess Po inter xxxx xxxx uuuu uuuu
05h PORTA(5,6) ———
(7) PORTA Data Latch when written: PORTA pins when read --xx xxxx --xu uuuu
06h PORTB(5,6) PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h DATACCP —(7) —(7) —(7) —(7) —(7) DCCP —(7) DT1CK xxxx xxxx xxxx xuxu
08h-09h —Unimplemented — —
0Ah PCLATH(1,2) — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh INTCON(1) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF—— — CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
0Dh —Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h-14h
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h-1Dh —Unimplemented — —
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’,
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: Other (non Power-up) Resets include: external Reset through MCLR and the Watc hdog Timer Reset.
4: The IRP and RP1 bits are reserved. Always maintain these bits clear.
5: On any device Reset, these pins are configured as inputs.
6: This is the value that will be in the port output latch.
7: Reserved bits; Do Not Use.
PIC16C712/716
DS41106C-page 12 1999-2013 Microchip Technology Inc.
Bank 1
80h INDF(1) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION_
REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL(1) Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS(1) IRP(4) RP1(4) RP0 TO PD ZDCCrr01 1xxx rr0q quuu
84h FSR(1) I ndir ect Data Memo ry Addr ess Po inter xxxx xxxx uuuu uuuu
85h TRISA ———
(7) PORTA Data Direction Register --x1 1111 --x1 1111
86h T RIS B PORTB Data Direct ion Regi st er 1111 1111 1111 1111
87h TRISCCP —(7) —(7) —(7) —(7) —(7) TCCP —(7) TT1CK xxxx x1x1 xxxx x1x1
88h-89h —Unimplemented — —
8Ah PCLATH(1,2) ——— Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh INTCON(1) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 —ADIE—— — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000
8Dh —Unimplemented — —
8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu
8Fh-91h —Unimplemented — —
92h P R2 Timer2 P eri o d Regi ste r 1111 1111 1111 1111
93h-9Eh —Unimplemented — —
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’,
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: Other (non Power-up) Resets include: external Reset through MCLR and the Watc hdog Timer Reset.
4: The IRP and RP1 bits are reserved. Always maintain these bits clear.
5: On any device Reset, these pins are configured as inputs.
6: This is the value that will be in the port output latch.
7: Reserved bits; Do Not Use.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi t 2 Bit 1 Bit 0 Value o n:
POR,
BOR
Value on
all other
Resets (4)
1999-2013 Microchip Technology Inc. DS41106C-page 13
PIC16C712/716
2.2.2.1 Status Register
The STATUS register, shown in Figure 2-4, contains
the arithmetic status of the ALU , the R eset status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabl ed. These bit s are set or clea red according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set t he Z bit. This leaves the STA T US register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affe ct the Z, C or D C bits from th e ST ATUS regist er . For
other inst ruct ions, not af fectin g any St atus bi ts, see th e
“Instructi on Set Summary.”
FIGURE 2-4: STATUS REGISTER (ADDRESS 03h, 83h)
Note 1: These devices do not use bits IRP and
RP1 (STATUS<7:6>). Maintain these bits
clear to ensure upward compatibility with
future products.
2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR Reset
bit7 bit0
bit 7: IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh) – not implemented, maintain clear
0 = Bank 0, 1 (00h-FFh) – not implemented, maintain clear
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh )
Each bank is 128 bytes
Note: RP1 = not implemented, maintain clear
bit 4: TO: Time-out bit
1 = After power-up, CLRWDT instructi on, or SLEEP instruction
0 = A WDT Time-out occurred
bit 3: PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By executi on of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructi ons) (fo r borrow t he p ola rity is re vers ed )
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instru ctions, this bit is loaded w i th either the high or low order bit of
the source register.
PIC16C712/716
DS41106C-page 14 1999-2013 Microchip Technology Inc.
2.2.2.2 OPTION_REG Register
The OPTION_REG register is a readable and writable
register, which cont ains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able re gister known a lso as the pres caler), t he Ext ernal
INT Int errupt, T MR0 and the w eak pul l-up s on POR TB.
FIGURE 2-5: OPTION_REG REGISTER (ADDRESS 81h)
Note: To achieve a 1:1 prescaler assignment for
the TMR 0 re gis ter, assign the p res ca ler to
the Watchdog Timer.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR Reset
bit7 bit0
bit 7: RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cyc le clo ck (CLK OUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on hi gh-to-low t ransitio n on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 modu le
bit 2-0: PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
1999-2013 Microchip Technology Inc. DS41106C-page 15
PIC16C712/716
2.2.2.3 INTCON Register
The INTCO N Register is a read able and writ able regis-
ter which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
FIGURE 2-6: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
Note: Interru pt flag bit s get set when an interru pt
conditi on occ urs, regar dless o f the s tate of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
war e shoul d ensu re the appro priat e inte r-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR Reset
bit7 bit0
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all inter rupts
bit 6: PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interru pts
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: IINTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3: RBIE: RB Port Change Inte rrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 Overflow Interrupt Flag bit
1 = TM R0 re gis ter has overf lowed (must be clear ed in software)
0 = TM R0 re gister did not overflow
bit 1: INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
PIC16C712/716
DS41106C-page 16 1999-2013 Microchip Technology Inc.
2.2.2.4 PIE1 Regi st er
This register contains the individual enable bits for the
peripheral interrupts.
FIGURE 2-7: PIE1 REGISTER (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIE — — — CCP1IE TMR2IE TMR1IE R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR Reset
bit7 bit0
bit 7: Unimplemented: Read as ‘0’
bit 6: ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5-3: Unimplemented: Read as ‘0’
bit 2: CCP1IE: CCP1 Interrupt E nable bit
1 = Enables the CCP1 interrupt
0 = Disables the C CP1 i nterru pt
bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 matc h interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0: TMR1IE: TMR1 Ov erfl ow Interru pt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
1999-2013 Microchip Technology Inc. DS41106C-page 17
PIC16C712/716
2.2.2.5 PIR1 Register
This register contains the individual flag bits for the
peripheral interrupts.
FIGURE 2-8: PIR1 REGISTER (ADDRESS 0Ch)
Note: Interru pt flag bit s get set when an interru pt
conditi on occ urs, regar dless o f the s tate of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
war e shoul d ensu re the appro priat e inte r-
rupt flag bits are clear prior to enabling an
interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIF — — — CCP1IF TMR2IF TMR1IF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR Reset
bit7 bit0
bit 7: Unimplemented: Read as ‘0’
bit 6: ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5-3: Unimplemented: Read as ‘0’
bit 2: CCP1IF: CCP1 Interrupt Flag bit
Capture Mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 r egister capture occurr ed
Compare Mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode:
Unused in this mode
bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurr ed (must be cleared in software )
0 = No TMR2 to PR2 match occurred
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TM R1 re gister did not overflow
PIC16C712/716
DS41106C-page 18 1999-2013 Microchip Technology Inc.
2.2.2.6 PCON Regi st er
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
These devices contain an additional bit to differentiate
a Brown-out Reset condition from a Power-on Reset
condition.
FIGURE 2-9: PCON REGISTER (ADDRESS 8Eh)
Note: If the BODEN Configuration bit is set, BOR
is ‘1’ on Power-on Reset. If the BODEN
Configuration bit is clear , BOR is unknown
on Power-on Reset.
The BOR Status bit is a “don’t care” and is
not necessarily predictable if the brown-out
circuit is disabled (the BODEN Configura-
tion bit is clear). BOR must then be set by
the user and checked on subsequent
resets to see if it is clear, indicating a
brown-out has occurred.
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q
— — — — — — POR BOR R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR Reset
bit7 bit0
bit 7-2: Unimplemented: Read as ‘0’
bit 1: POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0: BOR: Brown-ou t Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
1999-2013 Microchip Technology Inc. DS41106C-page 19
PIC16C712/716
2.3 PCL and PCLATH
The Progra m Counter (PC) specifies the address of th e
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits an d is no t directly readable or w ri t ab le. All updates
to the PCH register go through the PCLATH register.
2.3.1 STACK
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
Mid-range devices have an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the Stack Pointer is not
readable or writ able. The PC i s PUSHed on to the st ack
when a CALL instruction is executed or an interrupt
causes a bran ch . The st ac k i s PO Ped in the ev en t of a
RETURN, RETLW or a RETFIE instruction execution.
PCLAT H i s n o t mo di f ie d w h en th e s tac k i s PU SH ed o r
POPed.
Aft er the st ack has been PU SHed eigh t times , the nin th
push ov erwrit es the v alue tha t was stor ed fro m the first
push. The tenth push overw ri tes the second push (and
so on).
2.4 Program Memory Paging
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper bit of the address is provided by
PCLATH<3>. When doing a CALL or GOTO instru ct ion ,
the user must ensure that the page select bit is pro-
grammed so that the desired program memory page is
address ed. If a return from a CALL instru ction (or int er-
rupt) is executed, the entire 13-bit PC is pushed onto
the stack. Therefore, manipulation of the PCLATH<3>
bit is not required for the return instructions (which
POPs the address from the stack).
PIC16C712/716
DS41106C-page 20 1999-2013 Microchip Technology Inc.
2.5 Indirect Addressing, INDF and
FSR Registers
The INDF register is no t a physica l register. Addressing
INDF actu ally ad dress es the reg ister whos e addres s is
cont ained in the FSR regis ter (FSR is a pointer). This is
indirect addressing.
EXAMPLE 2-1: INDIRECT ADDRESSI NG
• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
• A read of the INDF reg ist er will return the value of
10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDR register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although Status bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
An eff ect ive 9-bit a ddress is obt ain ed by c oncatena tin g
the 8-bit FSR reg ister and the IRP bi t (ST A TU S<7>), as
shown in Figure 2-10. However, IRP is not used in the
PIC16C712/716.
FIGURE 2-10: DIRECT/INDI RECT ADDRESS ING
MOVLW 0x20 ;initialize pointer
MOVWF FSR ; to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;NO, clear next
CONTINUE
: ;YES, continue
Note 1: For register file map detail see Figure 2-3.
2: Maintain clear for upward compatibility with future products.
3: Not implemented.
Data
Memory(1)
Indirect AddressingDirect Addressing
bank select l ocation select
RP1:RP0 6 0
from opcode IRP FSR register
70
bank select location select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
(3) (3)
(2) (2)
1999-2013 Microchip Technology Inc. DS41106C-page 21
PIC16C712/716
3.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Addit ion al inf orm atio n o n I/O ports ma y b e f ound in the
PIC® Mid-Range Reference Manual, (DS33023).
3.1 PORTA and the TRISA Register
PORTA is a 5-bit wide bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make th e corresponding PORT A pin
an input, (i.e., put the corresponding output driver in a
High-Impe dance mode). Cle aring a TRISA bi t (= 0) will
make the corresponding PORT A pin an output, (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore , a write to a port implies that the port pins are
read, t he value is modified, and then written to the port
data l atc h.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schm itt Trigger inp ut a nd an open d rain ou tput.
All other RA port pins have TTL input levels and full
CMOS out put driv ers.
PORTA pins, RA3:0, are multiplexed with analog
inputs and analog VREF input. The operation of each
pin is se lec ted by c lea ring/setting the co ntrol bits in th e
ADCON1 register (A/D Control Register1).
The TRISA register controls the direction of the RA
pins, ev en w he n th ey a re being used as ana log inp ut s .
The user mu st ensure the bit s in the TRISA registe r are
maintained set when us ing them as analog inputs.
EXAMPLE 3-1: INITIALIZING PORTA
Note: On a Power-on Reset, these pins are
configured as analog inputs and read as
‘0’.
BCF STATUS, RP0 ;
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xEF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<4> as outputs
BCF STATUS, RP0 ; Return to Bank 0
PIC16C712/716
DS41106C-page 22 1999-2013 Microchip Technology Inc.
FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0
FIGURE 3-2: BLOCK DIAGRAM OF RA4/T0CKI PIN
DATA
BUS
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
PORT
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
VSS
VDD
I/O pin
Analog
input
mode
TTL
Input
Buffer
To A/D Converter
VSS
VDD
DATA
BUS
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
N
VSS
I/O Pin
TMR0 Clock Input
QD
Q
CK
QD
Q
CK
EN
QD
EN
VSS
1999-2013 Microchip Technology Inc. DS41106C-page 23
PIC16C712/716
TABLE 3-1: PORTA FUNCTIONS
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/AN0 bit 0 TTL Input/output or analog input
RA1/AN1 bit 1 TTL Input/output or analog input
RA2/AN2 bit 2 TTL Input/output or analog input
RA3/AN3/VREF bit 3 TTL Input/output or analog input or VREF
RA4/T0CKI bit 4 ST Input/output or external clock input for Timer0
Output is open drain type
Legend: TTL = TTL input, ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other Resets
05h PORTA — — —(1) RA4 RA3 RA2 RA1 RA0 --xx xxxx --xu uuuu
85h TRISA — — —(1) PORTA Data Direction Register --11 1111 --11 1111
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknow n, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTA.
Note 1: Reserved bits; Do Not Use.
PIC16C712/716
DS41106C-page 24 1999-2013 Microchip Technology Inc.
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an i nput, (i.e., pu t the correspo nding output driver in
a High-Impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output,
(i.e., pu t the co ntents o f the output latch on the selecte d
pin).
EXAMPLE 3-2: INITIALIZING PORTB
Each of the POR TB pins has a wea k inte rnal pul l-up. A
single control bit can turn on all the pull -ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull- up is au tomatica lly tur ned off when th e port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
FIGURE 3-3: BLOCK DIAGRAM OF RB0 PIN
BCF STATUS, RP0 ;
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Data Latch
RBPU(1) P
VDD
QD
CK
QD
CK
QD
EN
DATA BUS
WR PORT
WR TRIS
RD TRIS
RD PORT
weak
pull-up
RD PORT
RB0/INT
I/O
pin
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
VSS
VDD
1999-2013 Microchip Technology Inc. DS41106C-page 25
PIC16C712/716
PORTB pins RB3:RB1 are multiplexed with several
peripheral functions (Table 3-3). PORTB pins RB3:RB0
have Schmitt Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTB pin. Some
peripheral s override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISB as
dest ination shoul d be avoided. The user s hould refer to
the corresponding peripheral section for the correct
TRIS bit settings.
Four of POR TB’s pi ns, RB7:RB4, hav e an interrupt-o n-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-chan ge co mparison). The input pins, RB7:RB4, are
comp ared w ith the old value la tched on the last rea d of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interr upt in the foll owin g man ner:
a) Any read or write of PORTB will end the
mismatch condition.
b) Clear flag bit RBIF.
A mism at c h c ond it i on wi ll cont i n ue to s et f lag bi t RB IF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 3-4: BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN
0
1
QD
Q
CK
QD
Q
CK
QD
Q
CK
QD
Q
CK
0
1
0
1
TTL Buf fer
TRISB<1>
PORTB<1>
TRISCCP<0>
DATACCP<0>
RB1/T1OSO/T1CKI
RD
Data Bus
WR
WR
WR
WR TRISB
T1OSCEN
RD PORTB
TMR1CS
DATACCP
DATACCP
TRISCCP
PORTB
T1CLKIN ST
Buffer
P
VDD
Weak
Pull-up
RBPU(1)
T1OSCEN
T1CS
VSS
VDD
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
0
1
TMR1CS
PIC16C712/716
DS41106C-page 26 1999-2013 Microchip Technology Inc.
FIGURE 3-5: BLOCK DIAGRAM OF RB2/T1OSI PIN
FIGURE 3-6: BLOCK DIAGRAM OF RB3/CCP1 PIN
P
VDD
weak
pull-up
QD
Q
CK
QD
Q
CK
TTL Buffer
TRISB<2>
PORTB<2>
DATA BUS
WR PORTB
WR TRISB
T1OSCEN
RD PORTB
RB1/T1OSO/T1CKI
RBPU(1)
T1OSCEN
VSS
VDD
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
0
1
QD
Q
CK
QD
Q
CK
QD
Q
CK
QD
Q
CK
0
1
0
1
TRISB<3>
PORTB<3>
TRISCCP<2>
DATACCP<2>
RB3/CCP1
RD
DATA BUS
WR
WR
WR
WR
RD PORTB
CCPON
TTL Buffer
0
1
0
1
CCPOUT
CCPIN
CCPON
DATACCP
DATACCP
TRISCCP
PORTB
TRISB
CCP
Output
Mode
P
VDD
weak
pull-up
RBPU(1)
CCPON
VSS
VDD
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
1999-2013 Microchip Technology Inc. DS41106C-page 27
PIC16C712/716
FIGURE 3-7: BLOCK DIAGRAM OF RB7:RB4 PINS
TABLE 3-3: PORTB FUNCTIONS
Data Latch
From other
RBPU(1) P
VDD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
DATA BUS
WR PORT
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD PORT
RB7:RB4 pins
weak
pull-up
RD PORT
Latch
TTL
Buffer
pin
ST
Buffer
RB7:RB6 in Serial Programming mode Q3
Q1
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
VSS
VDD
Name Bit# Buffer Function
RB0/INT bit 0 TTL/ST(1) Input/output pin or external interrupt input. Internal software
programmable we ak pull-up.
RB1/T1OS0/
T1CKI bit 1 TTL/ST(1) Input/output pin or Timer1 oscillator output, or Timer1 clock input. Internal
so ftw are programmable weak pull -up. See Timer 1 section for detailed
operation.
RB2/T1OSI bit 2 TTL/ST(1) Input/output pin or Timer1 oscillator input. Internal software programmable
weak pull-up. See Timer1 section for detailed operation.
RB3/CCP1 bit 3 TTL/ST(1) Input/o utput pin or Captu re 1 input, or Comp are 1 outpu t, or PWM1 out put.
Internal software programmable weak pull-up. See CCP1 section for
detailed operation.
RB4 bit 4 TTL Input/output pin (wi th interru pt-on-change). Inter nal sof tware pro grammabl e
weak pull-up.
RB5 bit 5 TTL Input/output pin (wi th interru pt-on-change). Inter nal sof tware pro grammabl e
weak pull-up.
RB6 bit 6 TTL/ST(2) Inpu t/output pin (with interrupt-o n-change). Internal soft ware progra mmable
weak pull-up. Serial programming clock.
RB7 bit 7 TTL/ST(2) Inpu t/output pin (with interrupt-o n-change). Internal soft ware progra mmable
weak pull-up. Serial pr ogramming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note1: This buffer is a Schmitt Trigger input when configured as the external interrupt or peripheral input.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
PIC16C712/716
DS41106C-page 28 1999-2013 Microchip Technology Inc.
TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Re s e ts
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
1999-2013 Microchip Technology Inc. DS41106C-page 29
PIC16C712/716
4.0 T IMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• Internal or external clock select
• Edge select for external clock
• 8-bit software programmable prescaler
• Interrupt on overflow from FFh to 00h
Figure 4-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PIC® Mid-Range Reference Manual, (DS33023).
4.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 mod-
ule wi ll i ncr em en t ev ery instruction cycle (with ou t pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment on every rising or falling edge of pin RA4/
T0CKI. The incrementing edge is determined by the
Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the
rising edge. Res tricti ons on the external clo ck i nput a re
discussed bel ow.
When an external cl ock input i s used for T ime r0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the int ernal
phase clock (TOSC). Also, th ere is a delay in th e actual
incrementing of Timer0 after synchronization.
Additional information on external clock requirements
is avai lab le i n the PIC ® Mid-Range Reference Manual ,
(DS33023).
4.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer, respectively (Figure 4-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available, which is mutually exclusively shared
between the Timer0 module and the Watchdog Timer.
Thus, a prescaler assignment for the Timer0 module
means that there is no prescaler for the Watchdog
Timer and vice-versa.
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Clearing b it PSA will assign t he prescaler to the T imer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Setting bit PSA will assign the prescaler to th e Watch-
dog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 regi ster (e.g., CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.
FIGURE 4-1: TIMER0 BLOCK DIAGRAM
Note: Writing to TMR0 when the prescaler is
assign ed to Timer0 will clear th e prescal er
count, but will not change the prescaler
assignment.
Note1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detai led bloc k di agram).
RA4/T0CKI
T0SE(1)
0
1
1
0
pin
T0CS(1)
FOSC/4
Programmable
Prescaler(2)
Sync with
Internal
clocks TMR0
PSout
(2-cycle delay)
PSout
Data Bus
8
PSA(1)
PS2, PS1, PS0(1)Set Inte rrupt
Flag bit T0IF
on overflow
3
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4.2.1 SWITCHING PRESCALE R
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution).
4.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register ov erflows from FFh to 00h. This overflow sets
bit T0IF (INTCON<2>). Th e interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module Interrupt
Service Routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
Sleep since the timer is shut off during Sleep.
FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TABLE 4-1: REGISTERS ASSOCIATED WITH TIMER0
Note: To avoid an unintended device Reset, a
specific instruction sequence (shown in
the PIC® Mid-Range Reference Manual,
DS3302 3) must be e xecuted w hen chan g-
ing the prescaler assignment from Timer0
to the WDT. This sequence must be fol-
lowed even if the WDT is disabled.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA — — —(1) Bit 4 PORTA Data Direction Register --11 1111 --11 1111
Legend: x = unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
Note 1: Reserved bit; Do Not Use.
RA4/T0CKI
T0SE
pin
M
U
X
CLKOUT (=Fosc/4)
SYNC
2
Cycles TMR0 Reg
8-bit Prescaler
8-to-1 MUX
M
U
X
M U X
Watchdog
Timer
PSA
01
0
1
WDT
Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
PSA
WDT Enable bit
M
U
X
0
10
1
Data Bus
Set flag bit T0IF
on Overflow
8
PSA
T0CS
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5.0 T IMER1 MODULE
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter
(Two 8-bit registers; TMR1H and TM R1L)
• Readable and writable (Both registers)
• Internal or external clock select
•Interrupt on overflow from FFFFh to 0000h
• Reset from CCP module trigger
Timer1 has a control register, shown in Figure 5-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1O N (T1CON <0 >).
Figure 5-2 is a simplified block diagram of the Timer1
module.
Additional information on timer modules is available in
the PIC® Mid-Range Reference Manual, (DS33023).
5.1 Timer1 Operation
Timer1 can operate in one of these mo des :
•As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In timer mode, Timer1 increments every instruction
cycle. In co unter mode, it incre ments on every r ising
edge of the external clock input.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB2/T1OSI and RB1/T1OSO/T1CKI pins
become inputs. That is, the TRISB<2:1> value is
ignored.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see Section 7.0
“Capture/Compare/PWM (CCP) Module(s)”).
FIGURE 5-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR Reset
bit7 bit0
bit 7-6: Unimplemented: Read as ‘0’
bit 5-4: T1CKPS1:T1CKPS0: Timer1 In put Clock Prescale Select bits
11 = 1:8 P rescale value
10 = 1:4 P rescale value
01 = 1:2 P rescale value
00 = 1:1 P rescale value
bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain
bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1: TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB1/T 1O SO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0: TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
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DS41106C-page 32 1999-2013 Microchip Technology Inc.
FIGURE 5-2: TIMER1 BLOCK DIAGRAM
5.2 Timer1 Module and PORTB
Operation
When Timer1 is configured as timer running from the
main oscillator, PORTB<2:1> operate as normal I/O
lines. When Timer1 is configured to function as a
counter howe ver, the c lock s ource selec ti on may affect
the operation of PORTB<2:1>. Multiplexing details of
the Timer1 clock selection on PORTB are shown in
Figure 3-4 and Figure 3-5.
The clock source for Timer1 in the Counter mode can
be from one of the following:
1. External circuit connected to the RB1/T1OSO/
T1CKI pin
2. Firmware controlled DATACCP<0> bit, DT1CKI
3. Timer1 oscillator
Table 5-1 shows the det ails of T im er1 mode s elections,
control bit settings, TMR1 and PORTB operations.
TMR1H TMR1L
T1OSC T1SYNC
TMR1CS
T1CKPS1:T1CKPS0 Sleep input
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
clock input
2
RB1/T1OSO/T1CKI
RB2/T1OSI
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Set flag bit
TMR1IF on
Overflow TMR1
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TABLE 5-1: TMR1 MODULE AND PORTB OPERATION
TMR1
Module
Mode Clock Source Control Bits TMR1 Module Operation PORTB<2:1> Operation
Off N/A T1CON = --xx 0x00 Off PORTB<2:1> function as normal
I/O
Timer FOSC/4 T1CON = --xx 0x01 TMR1 module uses the main
oscillator as cl ock source.
TMR1 ON can tu rn on or t urn of f
Timer1.
PORTB< 2:1> function as normal
I/O
Counter External circuit T1CON = --xx 0x11
TR1SCCP = ---- -x-1 TMR1 module uses the exte rnal
signal on the RB1/T1OSO/
T1CKI pin as a clock source.
TMR1 ON can tu rn on or t urn of f
Timer1. DT1CK can read the
signal on the RB1/T1OSO/
T1CKI pi n.
PORTB<2> functions as normal
I/O. PORTB<1> always reads ‘0’
when configured as input. If
PORTB<1> is configured as out-
put, reading PORTB<1> will
read the data latch. Writing to
PORTB< 1> will always store the
result i n the dat a latch , but not t o
the RB1/T1OSO/T1CKI pin. If
the TMR1CS bit is cleared
(TMR1 reverts to the timer
mode), then pin PORTB<1> will
be driven with the value in the
data latch.
Firmware T1CON = --xx 0x11
TR1SCCP = ---- -x-0 DATACCP<0> bit drives RB1/
T1OSO/T1CKI and produces
the TMR1 clock source.
TMR1 ON can tu rn on or t urn of f
T i me r1. The DATACCP<0> bit,
DT1CK, can read and write to
the RB1/T1OSO/T1CKI pin.
Timer1 oscil lator T1CON = --xx 1x11 RB1/T1OSO/T1CKI and RB2/
T1OSI ar e conf igured as a 2 pin
crystal oscilla tor. RB1/ T1OS I/
T1CKI is the clock input for
TMR1. TMR1ON can turn on or
turn off Timer1. DATACCP<1>
bit, DT1CK, always reads ‘0’ as
input and can not write to the
RB1/T1OSO/ T1CK1 pin.
PORTB<2:1> always read ‘ 0’
when configured as inputs. If
PORTB<2:1> are configured as
outputs, reading PORTB<2:1>
will read the data latches. Writ-
ing to PORTB<2:1> will always
store the result in the data
latches, but not to the RB2/
T1OSI and RB1/T1OSO/T1CKI
pins. If the TMR1C S and
T1OSCEN bits are cleared
(TMR1 revert s to the timer mode
and TMR1 osci llator is disabled),
then pin PORTB<2:1> will be
driven with the value in the data
latches.
PIC16C712/716
DS41106C-page 34 1999-2013 Microchip Technology Inc.
5.3 Timer1 Oscillator
A cryst al oscillator circuit is built in be tween pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control b it T1OSCEN (T1CON<3>). The o scilla-
tor is a low-power oscillator rated up to 200 kHz. It will
continu e to run du ring Slee p. It i s prima rily in tended for
a 32 kHz crystal. Table 5-2 shows the capacitor
selection fo r the Timer1 oscillat or.
The Timer1 oscillator is identical to the LP oscillator.
The user m us t prov id e a so ftware time delay to en su re
proper oscillator start-up.
TABLE 5-2: CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
5.4 Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow
which is latched i n interrupt f lag bit TMR 1IF (PIR1<0>).
This in terrupt ca n be e nabled/di sabled by settin g/clear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.5 Resetti ng Timer1 using a CCP
Trigger Output
If the CCP module is configured in Compare mode to
generate a “Special Event T r igge r” (CCP1 M3:CCP1M 0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
T imer 1 must be c onfigured fo r either T ime r or Synch ro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L
registers pair effectively becomes the period register
for Timer1.
TABLE 5-3: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Osc Type Freq. C1 C2
LP 32 kHz 33 pF 33 pF
100 kHz 15 pF 15 pF
200 kHz 15 pF 15 pF
These values are for desi gn guida nce only.
Note1: Highe r capacitance increases the stability of
oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for
appropriate values of external components.
Note: The Special Event Triggers from the
CCP1 module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
Resets
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — — CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000
8Ch PIE1 —ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
07h DATACC
P— — — — — DCCP —DT1CK
---- -x-x ---- -u-u
87h TRISCCP — — — — — TCCP —TT1CK
---- -1-1 ---- -1-1
Legend: x = unk nown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module.
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NOTES:
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DS41106C-page 36 1999-2013 Microchip Technology Inc.
6.0 TIMER2 MODULE
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrup t on TMR2 match of PR2
Timer2 has a control register, shown in Figure 6-1.
Timer2 can be shu t off by clearing c on trol bit TMR2ON
(T2CON<2>) to minimize power consumption.
Figure 6-2 is a simplified block diagram of the Timer2
module.
Additional information on timer modules is available in
the PIC® Mid-Range Reference Manual, (DS33023).
FIGURE 6-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
FIGURE 6-2: TIMER2 BLOCK DIAGRAM
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 T OUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR Reset
bit7 bit0
bit 7: Unimplemented: Read as ‘0’
bit 6-3: TOUTPS3:TOUTPS0: Time r2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
0011 = 1:4 Postscale
0100 = 1:5 Postscale
0101 = 1:6 Postscale
0110 = 1:7 Postscale
0111 = 1:8 Postscale
1000 = 1:9 Postscale
1001 = 1:10 Postscale
1010 = 1:11 Postscale
1011 = 1:12 Postscale
1100 = 1:13 Postscale
1101 = 1:14 Postscale
1110 = 1:15 Postscale
1111 = 1:16 Postscale
bit 2: TMR2ON: Timer 2 On b it
1 = Timer2 is on
0 = Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Comparator
TMR2
Sets flag
TMR2 Reg
output
Reset
Postscaler
Prescaler
PR2 Reg
2
FOSC/4
1:1 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
to
1999-2013 Microchip Technology Inc. DS41106C-page 37
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6.1 Timer2 Operation
Timer2 can be used as the PWM time base for PWM
mode of the CCP module.
The TMR2 register is readable and writable, and is
cleared on any device Reset.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1: 0>).
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset, or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
6.2 Timer2 Interrupt
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then rese ts to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
Resets
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — —CCP1IF TMR2IF TMR1IF -00- -000 0000 -000
8Ch PIE1 —ADIE — — —CCP1IE TMR2IE TMR1IE -0-- -000 0000 -000
11h TM R2 Timer2 Mo dule ’s Register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h P R2 Timer2 Period Regi ste r 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module.
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PIC16C712/716
7.0 CAPTURE/COMPARE/PWM
(CCP) MODULE(S )
Each CCP (C apture/Compare/PWM) module contains
a 16-bit re gis ter, which can operate as a 16-bit captu r e
register, as a 16-bit compare register or as a PWM
master/s lave Duty Cycle register. Table 7-1 shows the
timer reso urces of the CCP module modes.
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
Additional information on the CCP module is available
in the PIC® Mid-Range Reference M anual, (DS33 023).
TABLE 7-1: CCP MODE – TIMER
RESOURCE
FIGURE 7-1: CCP1CON REGISTER (ADDRESS 17h)
FIGURE 7-2: TRISCCP REGISTER (ADDRESS 87H)
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 R = Readable bi t
W = Writable bit
U = Unimplem ented bit, read
as ‘0’
-n = Value at POR Reset
bit7 bit0
bit 7-6: Unimplemented: Read as ‘0’
bit 5-4: DC1B1:DC1B0: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bit s a re t he two LSbs of th e PWM duty cy cl e. The ei ght MSbs are found in C CP R1L.
bit 3-0: CCP1M3:CCP1M0: CCP1 Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP1 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Comp are mo de, clear outp ut on mat ch (C CP 1IF bit is set)
1010 = Com pare mode , generate sof tware inter rupt on match (CCP 1IF bit is set, C CP1 pin is unaf fected)
1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D
conversion (if A/D module is enabled))
11xx = PWM mode
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
———— —TCCP—TT1CKR =Readable bit
W =Writable bit
U = Unimplemente d bit, read
as ‘0’
-n = Value at POR Reset
bit7 bit0
bit 7-3: R eserved bits; Do Not Use
bit 2: TCCP – Tri-state control bit for CCP
0 = Output pin driven
1 = Output pin tristated
bit 1: Reserved bit; Do Not Use
bit 0: TT1CK – Tri-state control bit for T1CKI pin
0 = T1CKI pin is an output
1 = T1CKI pin is an input
PIC16C712/716
DS41106C-page 40 1999-2013 Microchip Technology Inc.
7.1 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit val ue of the TMR1 register when an event occurs
on pin RB3/CCP1. An event is defined as:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cle ared in so ftware. If a nother captu re occurs b efore
the value in register CCPR1 is read, the old captured
value wi ll be los t.
FIGURE 7-3: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
7.1.1 CCP PIN CONFIGURATION
In Capture mode, the CCP output must be disabled by
setting the TRISCCP<2> bit.
7.1.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture ope ration may not work.
7.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in Operating mode.
7.1.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 7-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 7-1: CHANGING BETWEEN
CAPTURE PRESCALERS
Note: If the RB3/CCP1 is configured as an out-
put by clearing the TRISCCP<2> bit, a
write to the DCCP bi t c an ca us e a capture
condition.
CCPR1H CCPR1L
TMR1H TMR1L
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s CCP1CON<3:0>
RB3/CCP1
Prescaler
1, 4, 16
and
edge det ect
Pin
CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; mode value and CCP ON
MOVWF CCP1CON ;Load CCP1CON with this
; value
1999-2013 Microchip Technology Inc. DS41106C-page 41
PIC16C712/716
7.2 Compare Mode
In C ompare mo de, t he 16 -bit CC PR1 r egist er va lue is
constantly compared against the TMR1 register pair
value. When a match occurs, the RB3/CCP1 pin is
either:
• driven High
• driven Low
• remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 7-4: COMPAR E MODE
OPERATION BLOCK
DIAGRAM
7.2.1 CCP PIN CONFIGURATION
The user must configure the RB3 /CCP1 pin as the CCP
output by clearing the TRISCCP<2> bit.
7.2.2 TIMER1 MODE SEL ECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
7.2.3 SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen the CCP1
pin is not af fected. On ly a CCP interrupt is generated (if
enabled).
7.2.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The Special Event Trigger output of CCP1 resets the
TMR1 re gist er pai r. Thi s al low s t he CC PR 1 re gis ter t o
ef fectively b e a 16-bit progra mmable pe riod registe r for
Timer1.
The Special Event Trigger output of CCP1 also starts
an A/D conversion (if the A/D module is enabled).
TABLE 7-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Event Trigger
Set flag bit CCP1IF
(PIR1<2>)
match
RB3/CCP1
TRISCCP<2> CCP1CON<3:0>
Mode Select
Output Enable
Pin
Special Event Trigger will:
Reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>)
which starts an A/D conversion
Note: Clearing the CCP1CON register will force
the RB3/CCP1 compare output latch to
the default low level. This is neither the
PORTB I/O data latch nor the DATACCP
latch.
Note: The Special Event Trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value o n
POR,
BOR
Value on
all other
Resets
07h DATACCP — — — — — DCCP —DT1CKxxxx xxxx xxxx xuxu
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — — CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h CCPR1L Capture/Compare/PWM Regis ter 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H C aptu re/Compare/PWM Regis ter 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
87h TRISCCP — — — — — TCCP — TT1CK xxxx x1x1 xxxx x1x1
8Ch PIE1 —ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.
PIC16C712/716
DS41106C-page 42 1999-2013 Microchip Technology Inc.
7.3 PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISCCP<2> bit must be cleared to make the
CCP1 pin an output.
Figure 7-5 shows a simplified block diagram of the
CCP module in PWM mode.
For a st ep by step pr ocedure on h ow to set up the CCP
module for PWM operation, see Section 7.3.3 “Set-
Up for PWM Operation”.
FIGURE 7-5: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 7-6) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period (1/
period).
FIGURE 7-6: PWM OUTPUT
7.3.1 PWM PERIO D
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TM R2 is equal to PR2, t he following three event s
occur on the next increment cycle:
•TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
7.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10- b i t re so l uti on is av ai l ab le. T he CC PR 1L c on tai ns
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to a t any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to dou ble buf fer th e PWM duty cycle. Thi s doubl e
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM r esolu tion (bits) for a given PWM
frequency:
For an example PWM period and duty cycle calcula-
tion, see the PIC® Mid-Range Reference Manual,
(DS33023).
Note: Clearing the CCP1CON register will force
the CCP1 PWM o utpu t la tch to th e de fau lt
low level. This is neither the PORTB I/O
data l atc h nor the DATACCP latc h.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty cycle registers CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISCCP<2>
RB3/CCP1
Note 1: 8-bit timer is con catenat ed with 2-bit int ernal Q clock
or 2 bits of the prescaler to create 10-bit time base.
Period = PR2+1
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle (CCPR1H)
TMR2 = PR2
Note: The Timer2 postscaler (see Section 6.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
Note: If the PWM duty cycle value is longer than
the P WM pe riod t he CC P1 pin will n ot be
cleared.
log( FPWM
log(2)
FOSC )bits
=
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7.3.3 SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISCCP< 2> bit.
4. Set the TMR2 prescale value and enable T imer2
by writing to T2CON.
5. Configure the CCP1 modu le for PWM operation.
TABLE 7-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
TABLE 7-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 5.5
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
Resets
07h DATACCP — — — — — DCCP — DT1CK xxxx xxxx xxxx xuxu
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF ———CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000
1 1h TMR2 T imer2 M odule’ s Regis ter 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Captur e/Comp ar e/PWM Registe r 1 ( LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Captur e/Comp ar e/PWM Registe r 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
87h TRISCCP — — — — — TCCP —TT1CK xxxx x1x1 xxxx x1x1
8Ch PIE1 —ADIE ———CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000
92h PR2 T imer 2 Module’s Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by PWM and T imer2.
PIC16C712/716
DS41106C-page 44 1999-2013 Microchip Technology Inc.
7.4 CCP1 Module and PORTB
Operation
When the CCP module is disabled, PORTB<3>
operates as a normal I/O pin. When the CCP module
is enabled, PORTB<3> operation is affected.
Multiplexing details of the CCP1 module are shown on
PORTB<3>, refer to Figure 3.6.
Table 7-5 below shows the effects of the CCP module
operation on PORTB<3> .
TABLE 7-5: CCP1 MODULE AND PORTB OPERATION
CCP1
Module
Mode Control Bits CCP1 Module Operation PORTB<3> Operation
Off CCP1CON = --xx 0000 Off PORTB<3> functions as normal I/O.
Capture CCP1CON = --xx 01xx
TRISCCP = ---- -1-x The CCP1 m odule wi ll cap ture an ev ent
on the RB3/C CP1 pin wh ich is driven by
an external circuit. The DCCP bit can
read the signal on the RB3/CCP1 pin.
PORTB<3> always reads ‘0’ when
configured as input. If PORTB<3> is
configured as output, reading
PORTB<3> will read the data latch.
Writing to PORTB<3> will always
store th e result in the d ata lat ch, but it
does not drive the RB3/CCP1 pin.
CCP1CON = --xx 01xx
TRISCCP = ---- -0-x The CCP1 m odule wi ll cap ture an ev ent
on the RB3/C CP1 pin wh ich is driven by
the DCCP bit. The DCCP bit can read
the signal on the RB3/CCP1 pin.
Compare CCP1CON = --xx 10xx
TRISCCP = ---- -0-x The CCP1 module produces an output
on the RB3/CCP1 pin when a compare
event occurs . The DCCP bit can read
the signal on the RB3/CCP1 pin.
PWM CCP1CON = --xx 11xx
TRISCCP = ---- -0-x The CCP1 module produces the PWM
signal on the RB3/CCP1 pin. The
DCCP bit can read the signal on the
RB3/CCP1 pin .
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8.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has four
inputs.
The A/D allo w s co nve rsi on of an analog input signal to
a corresponding 8-bit digital number (refer to Applica-
tion Note AN546 for use of A/D Converter). The output
of the sample and hold is the input into the converter,
which generates the result via successive approxima-
tion. The analog reference voltage is software select-
able t o either the devic e’s posi tive supply vol tage (VDD)
or the voltage level on the RA3/AN 3/VREF pin.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscill ator.
Addition al informatio n on the A/D m odule is avail able in
the PIC® Mid-Range Reference Manual, (DS33023).
The A/D module has three registers. These registers
are: • A/D Result Registe r (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off, and any
conversion is aborted.
The ADCON0 register, shown in Figure 8-1, controls
the operation of the A/D module. The ADCON1 regis-
ter , shown in Figure 8-2, configures the functions of the
port pins. The port pins can be configured as analog
inputs (RA3 can also be a voltage reference) or as
digital I/O.
FIGURE 8-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON R =Readable bit
W =Writa bl e bit
U =Unimplemented bit,
read as ‘0’
-n = Value at POR Reset
bit7 bit0
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from the internal ADC RC oscillator)
bit 5-3: CHS2:CHS0: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
1xx = reserved, do not use
bit 2: GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D
conver si on is comp lete)
bit 1: Unimplemented: Read as ‘0’
bit 0: ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
PIC16C712/716
DS41106C-page 46 1999-2013 Microchip Technology Inc.
FIGURE 8-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PCFG2 PCFG1 PCFG0 R =Readable bit
W =Writable bit
U =Unimplemented bit,
read as ‘0’
-n = Value at POR
Reset
bit7 bit0
bit 7-3: Unimplemented: Read as ‘0’
bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits
A = Analog input
D = Digital I/O
PCFG2:PCFG0 RA0 RA1 RA2 RA3 VREF
0x0 AAAA VDD
0x1 AAAVREF RA3
100 AADA V
DD
101 AADVREF RA3
11x DDDD VDD
1999-2013 Microchip Technology Inc. DS41106C-page 47
PIC16C712/716
The ADRES register contains the result of the A/D
conversion. When the A/D conversion is complete, the
result is loaded into th e ADRES register , the GO/DONE
bit (ADCON0<2>) is cleared and the A/D Interrupt Flag
bit ADIF i s set. The b lock d iagram of th e A/D m odule i s
shown in F igure 8-3.
The valu e tha t is in th e ADRES regi ste r is not m odifie d
for a Powe r-on Rese t. The AD RES registe r will cont ain
unknown data after a Power-on Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 8.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. The following steps should be followed for
doing an A/D conversion:
1. Configure the A/D module:
• Config ure ana log pins /vo lt age reference/
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversio n clock (A DCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
•Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
•Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result register (ADRES), clear bit
ADIF if required.
7. For the next conversion, go to step 1 or step 2
as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 8-3: A/D BLOCK DIAGRAM
(Input voltage)
VIN
VREF
(Reference
voltage)
VDD
PCFG2:PCFG0
CHS2:CHS0
000 or
010 or
110 or 111
001 or
011 or
101
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
011
010
001
000
A/D
Converter
100 or
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8.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the Ch arge Holdi ng cap acitor (CHOLD) must be al lowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figur e 8-4. The source
impeda nce (RS) and the inte rnal sam pling swi tch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the
analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 10 k. After the analog input channel is
selected (changed) this acquisition must be done
before the conversion can be started.
To calculate the minimum acquisition time, TACQ, see
the PIC® Mid-Range Reference Manual, (DS33023).
This equation calculates the acquisition time to within
1/2 LSb error (51 2 steps for the A/D) . The 1/2 LSb e rror
is the maximum error allowed for the A/D to meet its
specified accuracy.
FIGURE 8-4: ANALOG INPUT MODEL
Note: When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
CPIN
VA
Rs ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I leakage
RIC 1k
Sampling
Switch
SS RSS
CHOLD
= DAC capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
567891011
(k)
VDD
= 51.2 pF
500 nA
Legend: CPIN
VT
I leakage
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
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8.2 Selecti ng the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
•2T
OSC
•8TOSC
•32TOSC
• Internal RC oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
Table 8-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
sour ce se lec ted .
8.3 Configur ing Analog Port Pins
The ADCON1 and TRISA registers control the opera-
tion of the A/D port pins. The port pins that are desired
as analog inputs must have their corresponding TRIS
bits set (input). If the TRIS bit is cleared (output), the
digital output level (VOH or VOL) will be co nverted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
TABLE 8-1: TAD vs. DEVICE OPERATING FREQUENCIES
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins
configured as digital inputs, will convert
an analog input. Analog levels on a
digit ally configure d input will not af fect the
conversion accuracy.
2: Analog le vels on any pin that is defined a s
a digital input (including the AN3:AN0
pins), may cause the input buffer to
consum e current that is ou t of the device s
specification.
AD Clock Source (TAD) Device Frequency
Operation ADCS1:ADCS0 20 MHz 5 MHz 1.25 MHz 333.33 kHz
2T
OSC 00 100 ns(2) 400 ns(2) 1.6 s6 s
8TOSC 01 400 ns(2) 1.6 s6.4 s24 s(3)
32TOSC 10 1.6 s6.4 s25.6 s(3) 96 s(3)
RC(5) 11 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1)
Legend:Shaded cells are outside of recommended range.
Note 1: The RC source ha s a typical TAD time of 4 s.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for
Sleep operation only.
5: For extended voltage devices (LC), please refer to Electrical Specifications section.
PIC16C712/716
DS41106C-page 50 1999-2013 Microchip Technology Inc.
8.4 A/D Conversions
8.5 Use of the CCP Trigger
An A/D conversion c an be st arted by the “S pecial Event
Trigger” of the CCP1 module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be
programmed as 1011 and that the A/D module is
enabled (ADON bit is set). When th e trigger occurs, the
GO/DONE bit will be set, s tarting t he A/D conver sion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to au tomatical ly re peat th e A/D acquisi tion p eriod
with min imal so ftware ov erhead (mov ing the ADR ES to
the desired location). The appropriate analog input
channel must b e selecte d and the mi nimum ac quisitio n
done before the “Special Event Trigger” sets the GO/
DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “Special Event Trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
TABLE 8-2: SUMMARY OF A/D REGISTERS
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other Resets
05h PORTA — — —(1) RA4 RA3 RA2 RA1 RA0 --xx xxxx --xu uuuu
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — —— CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0
85h TRISA — — —(1) PORTA Data Direction Register ---1 1111 ---1 1111
8Ch PIE1 —ADIE — —— CCP1IE TMR2IE TMR1IE -0-- -000 -0-- 0000
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: Reserved bits; Do Not Use.
1999-2013 Microchip Technology Inc. DS41106C-page 51
PIC16C712/716
9.0 SPECIAL FEATURES OF THE
CPU
The PIC16C712/716 devices have a host of features
intended to maximize system reliability, minimize cost
through elimination of external components, provide
power-saving operating modes and offer code
protection. These are:
• OSC Selection
• Reset:
- Power -on R eset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Sleep
• Code protection
• ID locations
• In-Circuit Serial Programming™ (ICSP™)
These devices have a Watchdog Timer, which can be
shut off only through Configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers th at of fe r necessa ry delay s on po wer-up. O ne is
the Oscillator Start-up Timer (OST), intended to keep
the chip in Reset until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which
provides a fixed delay on power-up only and is
designed to keep the part in Reset while the power
supply stabilizes. With these two timers on-chip, most
applications need no ex ternal Reset circuitry.
Sleep mode is designed to offer a very low-current
Power-Down m ode . T he user can wake-up from Slee p
through external Reset, Watchdog Timer Wake-up, or
through a n inte rrupt. Se veral oscil lator options are a lso
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of Configuration
bits are used to select various options.
Additional information on special features is available
in the PIC® Mid-Range Reference M anual, (DS33 023).
9.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or lef t unprog rammed ( read as ‘ 1’) to se lect various
device configurations. These bits are mapped in
program memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to
the special test/configuration memory space
(2000h-3FFFh), which can be ac cessed only during
programming.
PIC16C712/716
DS41106C-page 52 1999-2013 Microchip Technology Inc.
FIGURE 9-1: CONFIGURATION WORD
CP1 CP0 CP1 CP0 CP1 CP0 —BODENCP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register:CONFIG
Address2007h
bit13 bit0
bit 13-8, 5-4: CP1:CP0: Code Protection bits (2)
Code Protection for 2K Program memory (PIC16C716)
11 = Programming code protection off
10 = 0400h-07FFh code protected
01 = 0200h-07FFh code protected
00 = 0000h-07FFh code protected
bit 13-8, 5-4:
Code Protection for 1K Program memory bits (PIC16C712)
11 = Programming code protection off
10 = Programming code protection off
01 = 0200h-03FFh code-protected
00 = 0000h-03FFh code-protected
bit 7: Unimplemented: Read as ‘1’
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown- out Reset automa tically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
1999-2013 Microchip Technology Inc. DS41106C-page 53
PIC16C712/716
9.2 Oscillator Configurations
9.2.1 OSCILLATOR TYPES
The PIC16CXXX can be operated in four different
Oscillator modes. The user can program two
Configuration bits (FOSC1 and FOSC0) to select one
of these four modes:
• LP Low-Power Crystal
• XT Crystal/Resonator
• HS High-Speed Crystal/Resonator
• RC Resistor/Capacitor
9.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes, a crys tal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 9-2). The
PIC16CXXX os cillator des ign requ ires the us e of a p ar-
allel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 9-3).
FIGURE 9-2: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
FIGURE 9-3: EXTER NAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
TABLE 9-1: CERAMIC RESONATORS
T ABLE 9-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Note 1: See Ta bl e 9 - 1 and Table 9-2 for
recommended values of C1 and C2.
2: A series re sisto r (RS) m ay b e re qui red for
AT strip cut crys tals.
3: RF varies with the crystal chosen.
C1(1)
C2(1)
XTALOSC2
OSC1
RF(3)
Sleep
To
logic
PIC16C7XX
RS(2)
internal
OSC1
OSC2
Open
Clock from
ext. system PIC16C7XX
Ranges Tested:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
68-100 pF
15-68 pF
15-68 pF
68-100 pF
15-68 pF
15-68 pF
HS 8.0 M Hz
16.0 MHz 10-68 pF
10-22 pF 10-68 pF
10-22 pF
These values are for design guidance only. See
notes at bottom of page.
Osc Type Crystal
Freq Cap. Range
C1 Cap . Ran ge
C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1 MHz 15 pF 15 pF
4 MHz 15 pF 15 pF
HS 4 MHz 15 pF 15 pF
8 MHz 15-33 pF 15-33 pF
20 MHz 15-33 pF 15-33 pF
These values are for design guidance only. See
notes at bottom of page.
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 9-1).
2: Higher ca pacitance increases th e s t a bil ity
of the oscillator, but also increases the
start-up time.
3: Since each resonator/c rystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents.
4: Rs may be required in HS mode, as well
as XT mode to avoid overdriving crystals
with low drive level specific ation.
PIC16C712/716
DS41106C-page 54 1999-2013 Microchip Technology Inc.
9.2.3 RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers addition al co st sa vin gs . The RC oscil lator
frequenc y is a function of the su ppl y v olt age, the resis-
tor (REXT) and c apacitor (CEXT) val ues and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit-to-unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C
components used. Figure 9-4 shows how the R/C
combination is connected to the PIC16CXXX.
FIGURE 9-4: RC OSCILLATOR MODE
9.3 Reset
The PIC16CXXX differentiates between various kinds
of Reset:
• Power-on Reset (POR)
•MCLR
Reset during normal operation
•MCLR
Reset during Sleep
• WDT Reset (during normal operation)
• WDT Wake-up (during Sleep)
• Brown-out Reset (BOR)
Some regi sters a re not af fected in any Rese t condit ion;
their st atus is unknown on POR and unchanged i n an y
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCL R R ese t du ring Sle ep a nd Bro w n-
out Reset (BOR). They are not affected by a WDT
Wake-up, w hich is viewed as the res ump tio n o f normal
operation. The TO and PD bits are set or cleared
differently in different Reset situations as indicated in
Table 9-4. These bit s are used in softw are to determine
the nature of the Reset. See Table 9-6 for a full
description of Reset states of all registers.
A simp lified block di agram o f the on- chip Re set cir cuit
is sh own in Figure 9 -6.
The PIC microcontrollers have a MCLR noise filter in
the MCLR Reset path. The filter will detect and ignore
small pul ses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
OSC2/CLKOUT
CEXT
REXT
PIC16C7XX
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 k REXT 100 k
CEXT > 20pF
1999-2013 Microchip Technology Inc. DS41106C-page 55
PIC16C712/716
9.4 Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (to a level of 1.5V-2.1V). To take
advant age of the POR, j ust tie the MCLR pin directly (or
through a resistor) to VDD. This will eliminate external
RC components usually needed to create a Power-on
Reset. A maximum rise time for VDD is specified
(param eter D004) . For a slow rise t ime, see Figure 9-5.
When the device starts normal operation (exits the
Reset condition), device operating parameters (volt-
age, fre quency, tempera ture,...) must be m et to ensure
operation. If these conditions are not met, the device
must be held in Reset until the operating conditions are
met. Brown-out Reset may be used to meet the start-
up conditions.
FIGURE 9-5: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
9.5 Power-up T imer (PWRT)
The P ower-up Timer pr ovides a fixe d nominal time- out
(param eter # 33), on powe r-up onl y, from the POR. Th e
Power-up Timer operates on an internal RC oscillator.
The chip is kept in Rese t as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an
acceptable level. A Configuration bit is provided to
enable/disable the PWRT.
The pow er-up time de lay will v ary from chi p to chip due
to VDD, temperature, and process variation. See DC
param ete rs for deta ils .
9.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWR T delay is over (para meter #32). Th is ensures th at
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep.
9.7 Brown-Out Reset (BOR)
The PIC16C712/716 members have on-chip Brown-
out Reset circuitry. A Configuration bit, BODEN, can
disable (if clear/programmed) or enable (if set) the
Brown-ou t Reset ci rcu itry. If VDD falls be low 4 .0V, refer
to VBOR pa ramete r D005(VBOR) for a t ime grea ter than
parameter (TBOR) in Table 12-6. The brown-out situa-
tion will reset the chip. A Reset is not guaranteed to
occur if VDD falls below 4.0V for less than parameter
(TBOR).
On any Reset (Power-on, Brown-out, Watchdog, etc.)
the chip will remain in Reset until VDD rises above
VBOR. The Power-u p Tim er will now be inv oked and will
keep the chip in Reset an additional 72 ms.
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-u p Timer will be re-initialized. Onc e VDD
rises above VBOR, the Power-Up Timer will execute a
72 ms Reset. The Power-up Timer should always be
enabled when Brown-out Reset is enabled. Figure 9-7
shows typical Brown-out situations.
For operations where the desired brown-out voltage is
other than 4V, an external brown-out circuit must be
used. Figure 9-8, 9-9 and 9-10 show examples of
external brown-out protection circuits.
Note 1: External Power-on Reset circuit is
required only if VDD power-up slope is too
slow. The diode D helps dischar ge the
capacitor quic kly when VDD powers down.
2: R < 40 k is recommended to make sure
that voltage drop across R does not vi olate
the device’s electrical specificati on.
3: R1 = 100 to 1 k will limit any current
flowi ng in to MCLR from external capacitor
C in the event of MCLR/VPP pin b reak-
down due to Electrost a tic Disch arge
(ESD) or Electrical Overstress (EOS).
C
R1
R
VDD
MCLR
PIC16C7XX
VDD
PIC16C712/716
DS41106C-page 56 1999-2013 Microchip Technology Inc.
FIGURE 9-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
FIGURE 9-7: BROWN-OUT SITUATIONS
S
RQ
External
Reset
MCLR
VDD
OSC1
WDT
Module
VDD rise
detect
OST/PWRT
On-chip
RC OSC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple counter
PWRT
Chip_Reset
10-bit Ripple counter
Reset
Enable OST
Enable PWRT
SLEEP
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
Brown-out
Reset BODEN
(1)
PWRT
BODEN See Table 9-3 for time-out
situations.
72 ms
VBOR
VDD
Internal
Reset
VBOR
VDD
Internal
Reset 72 ms
<72 ms
72 ms
VBOR
VDD
Internal
Reset
1999-2013 Microchip Technology Inc. DS41106C-page 57
PIC16C712/716
FIGURE 9-8: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
FIGURE 9-9: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
FIGURE 9-10: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 3
9.8 Time-out Sequence
On power-u p th e tim e-o ut s eq uen ce is as f oll ows : Firs t
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary base d on oscil lator con figurat ion and the st atus of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 9-11,
Figure 9-12, and Figure 9-13 depict time-out
sequences on power-up.
Since the time-outs occur from the PO R pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-13). This is useful for testing purposes or to
synchronize more than one PIC16CXXX device
operating in parallel.
Table 9-5 shows the R eset condi tions for some S pecia l
Function Registers, while Table 9-6 shows the Reset
conditions for all the registers.
Note 1: This circuit will activate Reset when
VDD goes below (Vz + 0.7V) where
Vz = Zener voltage.
2: Internal Brown-out Reset circuitry
should be disabled when using this
circuit.
VDD
33k
10k
40k
VDD
MCLR
PIC16C7XX
Q1
Note 1: This brown-out ci rcuit is less ex pensiv e,
albeit les s accurate. Trans istor Q1 turns
off when VDD is below a certain level
such that:
2: Internal Brown-out Reset should be
dis abled wh en using this circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
VDD x R1
R1 + R2 = 0.7V
VDD
R2 40k
VDD
MCLR
PIC16C7XX
R1
Q1
This brown-out protection circuit employs
Microchip Technology’s MCP809 microcontroller
supervisor. The MCP8XX and MCP1XX families
of supervisors provide push-pull and open
collector outputs with both high and low active
Reset pins. There are 7 different trip point
selections to accommodate 5V and 3V sy stems
MCLR
PIC16C7XX
VDD
VDD
Vss
RST
MCP809
VDD
bypass
capacitor
PIC16C712/716
DS41106C-page 58 1999-2013 Microchip Technology Inc.
9.9 Power Control /Status Register
(PCON)
The Power Control/Status Register, PCON has two
bits.
Bit 0 is Brown-out Reset S t atus b it, BOR. If the BODEN
Configuration bit is set, BOR is ‘1’ on Power-on Rese t.
If the BODEN Configuration bit is clear, BOR is
unknow n on Power-o n Re set .
The BOR Status bit is a “don’t care” and is not neces-
sarily predict able if the brown-out circuit is disabled (the
BODEN Configuration bit is clear). BOR must then be
set by the user and checked on subsequent Resets to
see if it is clear, indicating a brown-out has occurred.
Bit 1 is POR (Power-on Reset Status bi t). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS
TABLE 9-4: STATUS BITS AND THEIR SIGNIFICANCE
TABLE 9-5: RESET CONDITION FOR SPECIAL REGISTERS
Oscillator Co nfigu ration Power-up Brown-out Wake-up from
Sleep
PWRTE = 0PWRTE = 1
XT, HS, LP 72 ms + 1024T
OSC 1024TOSC 72 ms + 1024TOSC 1024TOSC
RC 72 ms — 72 ms —
POR BOR TO PD
0x11Power-on Reset
0x0xIllegal, TO is set on POR
0xx0Illegal, PD is set on POR
1011Brown-o ut Reset
1101WDT Reset
1100WDT Wake-up
11uuMCLR Reset during normal operat ion
1110MCLR Reset during Sleep or interrupt wake-up from Sleep
Condition Program
Counter STATUS
Register PCON
Register
Power-on Reset 000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --uu
MCLR Reset during Sleep 000h 0001 0uuu ---- --uu
WDT Reset 000h 0000 1uuu ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --uu
Brown-out Reset 000h 0001 1uuu ---- --u0
Interrupt wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, – = unimplemented bit read as ‘0’.
Note1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
1999-2013 Microchip Technology Inc. DS41106C-page 59
PIC16C712/716
TABLE 9-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS OF THE PIC16C712/716
Register Power-on Reset,
Brown-out Reset MCLR Resets
WDT Reset Wake-up via WDT or
Interrupt
Wxxxx xxxx uuuu uuuu uuuu uuuu
INDF N/A N/A N/A
TMR0 xxxx xxxx uuuu uuuu uuuu uuuu
PCL 0000h 0000h PC + 1(2)
STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR xxxx xxxx uuuu uuuu uuuu uuuu
PORTA(4) --0x 0000 --xx xxxx --xu uuuu
PORTB(5) xxxx xxxx uuuu uuuu uuuu uuuu
DATACCP ---- -x-x ---- -u-u ---- -u-u
PCLATH ---0 0000 ---0 0000 ---u uuuu
INTCON 0000 -00x 0000 -00u uuuu -uuu(1)
PIR1 ---- 0000 ---- 0000 ---- uuuu(1)
-0-- 0000 -0-- 0000 -u-- uuuu(1)
TMR1L xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H xxxx xxxx uuuu uuuu uuuu uuuu
T1CON --00 0000 --uu uuuu --uu uuuu
TMR2 0000 0000 0000 0000 uuuu uuuu
T2CON -000 0000 -000 0000 -uuu uuuu
CCPR1L xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON --00 0000 --00 0000 --uu uuuu
ADRES xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 0000 00-0 0000 00-0 uuuu uu-u
OPTION_REG 1111 1111 1111 1111 uuuu uuuu
TRISA --11 1111 --11 1111 --uu uuuu
TRISB 1111 1111 1111 1111 uuuu uuuu
TRISCCP xxxx x1x1 xxxx x1x1 xxxx xuxu
PIE1 ---- 0000 ---- 0000 ---- uuuu
-0-- 0000 -0-- 0000 -u-- uuuu
PCON ---- --0q ---- --uq ---- --uq
PR2 1111 1111 1111 1111 1111 1111
ADCON1 ---- -000 ---- -000 ---- -uuu
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition
Note 1: One or more bits in INTCON and/or PIR1 will be affe cted (to cause wake-up) .
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Ta bl e 9-5 for Reset value for specific condition.
4: On any device Reset, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
PIC16C712/716
DS41106C-page 60 1999-2013 Microchip Technology Inc.
FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
FIGURE 9-12: TIME-O UT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 9-13: TIME-O UT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
1999-2013 Microchip Technology Inc. DS41106C-page 61
PIC16C712/716
9.10 Interrupts
The PIC16C712/716 devices have up to 7 sources of
interrupt. The Interrupt Control Register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts or disables (if
cleared ) all i nterrupt s. W hen bit GIE i s enab led, a nd an
inter rupt’s flag bit and mask bit are s et, the int errupt will
vector immediately. Individual interrupts can be
disabled through their corresponding enable bits in
various registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on Reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enable s inte rrup t s.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR 0 over flo w interru pt f lag s are co nt a ine d in
the INTCON register.
The peripheral interrupt flags are contained in the
S pec ial Function R egisters, PIR1 and PIR2. The corre-
sponding interrupt enable bits are contained in Special
Functio n Regis te r s, PIE1 an d PIE2, an d the perip hera l
interrupt enable bit is contained in Special Function
Register, INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pu sh ed onto the st ack and the PC is lo ade d
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the i nterr upt flag bits. T he inte rrupt flag bi t(s) mu st be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one o r two cy c le ins tructions. Indi vi dua l
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
FIGURE 9-14: INTERRUPT LOGIC
Note: Indiv idual in terrupt flag bit s are set regard-
les s of the stat us of their corresponding
mask bit or the GIE bit.
ADIF
ADIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in Slee p mod e)
Interrupt to CPU
PIC16C712/716
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9.10.1 INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered,
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routin e before re-enablin g this interrupt. The INT in ter-
rupt can wake-up the processor from Sleep, if bit INTE
was set prior to going into Sleep. The status of global
interrupt enable bit GIE decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 9.13 “Power-down Mode
(Sleep)” for details on Sleep mode.
9.10.2 TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 4.0 “Timer0 Module”)
9.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2 “PORTB and the TRISB Register”)
9.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. T y pically, users m ay wish to s ave key reg-
isters d uri ng a n i nte rrupt , (i.e ., W reg ist er a nd STATUS
register). This w il l hav e to be i mp lemented in softwar e.
Example 9-1 stores and restores the W and STATUS
registers. The register, W_TEMP, must be defined in
each ba nk and m ust be de fined at th e same offset from
the bank base address (i.e., if W_TEMP is defined at
0x20 i n b ank 0 , i t m us t als o be defined at 0xA0 i n b an k
1).
The exam ple:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register.
d) Executes the Interrupt Service Routine code
(User-generated).
e) Restores the STATUS register (and bank select
bit).
f) Restores the W and PCLATH registers.
EXAMPLE 9-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero
SWAPF STATUS,W ;Swap status to be saved into W
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3
MOVWF PCLATH_TEMP ;Save PCLATH into W
CLRF PCLATH ;Page zero, regardless of current page
BCF STATUS, IRP ;Return to Bank 0
MOVF FSR, W ;Copy FSR to W
MOVWF FSR_TEMP ;Copy FSR from W to FSR_TEMP
:
:(ISR)
:
MOVF PCLATH_TEMP, W ;Restore PCLATH
MOVWF PCLATH ;Move W into PCLATH
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
1999-2013 Microchip Technology Inc. DS41106C-page 63
PIC16C712/716
9.12 Watchdog Timer (WDT)
The Watchdog Timer is as a free running, on-chip, RC
oscillator which does not require any external compo-
nent s. T his RC oscilla tor is s ep arate from the R C osci l-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CL KOUT pins of th e devic e have been sto pped,
for example, by execution of a SLEEP instruction.
During no rma l o pera tion, a WDT Time-out gen erat es a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT Time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-u p) . T he TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer Time-out.
The WDT can be permanently disabled by clearing
Configuration bit WDTE (Section 9.1 “Configuration
Bits”).
WDT time-out period values may be found in the
Electrical Specifications section under TWDT (parame-
ter #31). Values for the WDT prescaler (actually a
pos tscaler, but sha red w ith th e Timer 0 pre scale r) may
be assigned using the OPTION_REG register.
.
FIGURE 9-15: WATC HDOG TIMER BLOCK DIAGRAM
FIGURE 9-16: SUMMARY OF WATCHDOG TIMER REGISTERS
Note: The CLRWDT and SLEEP instructions clear
the WDT and the p ostsc aler, if as signed to
the WDT, and prevent it from timing out
and generating a device Reset condition.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
presc al er ass ig nme nt is not changed.
Address Name Bits 13:8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits (1) —BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0
81h OPTION_REG N/A RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend:Shade d cell s are not us ed by the Watchdog Timer.
Note 1: See Figure 9-1 for operation of these bits.
From TMR0 Clock Source
(Figure 4-2)
To TMR0 (Figure 4-2)
Postscaler
WDT Timer
WDT
Enable Bit
0
1M
U
X
PSA
8-to-1 MUX PS2:PS0
01
MUX PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
8
PIC16C712/716
DS41106C-page 64 1999-2013 Microchip Technology Inc.
9.13 Power-down Mode (Sleep)
Power-Down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keep s runni ng, the PD bi t (STATUS<3>) is c lea red , th e
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or high-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external
circuitry is drawing current from the I/O pin, power-
down the A/ D and the dis able e xternal c locks. Pu ll all I/
O pins, that are high-impedance inputs, high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at VDD or
VSS for lowest current consumption. The contribution
from on-chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
9.13.1 WAKE- UP FROM SLEE P
The dev ice ca n wa ke up f rom Sle ep t hrough o ne of th e
following events:
1. External Reset input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT p in , RB port change, or s ome
peripheral interrupts.
External MCLR Reset will cause a device Reset. All
other events are considered a continuation of program
execut ion and c aus e a “wak e-u p”. The TO and PD bits
in the STATUS register can be used to determine the
cause of device Reset. The PD bit, which is set on
powe r-up, is cleared w hen SLEEP is invoked. The TO
bit is cleared if a WDT Time-out oc curred (and caused
wake-up).
The follo wing periph eral interrupt s can wake the device
from Sleep:
1. TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
2. CCP Capture mode interrupt.
3. Special Event Trigger (Timer1 in Asynchronous
mode using an external clock).
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
1999-2013 Microchip Technology Inc. DS41106C-page 65
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When the SLEEP instruction is being e xecuted, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-u p thro ugh an int errup t ev ent, the co rres pon ding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instr uction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
9.13.2 WAKE -UP USIN G INTERR UPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt fla g bit s et, one of the fo llowin g wil l occur:
• If the interrupt occurs before the ex ecution of a
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefo re, the WDT an d WDT
pos tsc aler will not be cl eared, the TO bit will not
be set and PD bits will not be cle are d.
• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction, the de vice will im me-
diately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postsc aler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instr uction ex ecuted , test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instru c-
tion should be executed before a SLEEP instruction.
FIGURE 9-17: WAKE-UP FROM SLEEP THROUGH INTERRUPT
9.14 Program Verification/Code
Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verificati on purp os es .
9.15 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during Program/Verify. It is
recommended that only the 4 Least Significant bits of
the ID location are used.
For ROM devices, these values are submitted along
with the ROM code.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC PC + 1 PC + 2
Inst(PC) = Sleep
Inst(PC - 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
TOST(2)
PC + 2
Note 1: XT, HS or LP Oscillator mode assumed.
2: T
OST = 1024TOSC (drawing not to scale) This delay will not be there for RC Osc mode.
3: GIE = 1 assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
Note: Microchip does not recommend code
prote cting wi nd ow ed devices .
PIC16C712/716
DS41106C-page 66 1999-2013 Microchip Technology Inc.
9.16 In-Circuit Serial Programming™
PIC16CXXX microcontrollers can be serially
progra mmed w hile in t he en d app licati on c ircuit. This is
simply don e with two lines fo r clock and da ta, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
For complete details on serial programming, please
refer to the In-Circuit Serial Programming™ (ICSP™)
Guide, (DS30277).
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10.0 INSTRUCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXXX instruc-
tion set sum mary in Table 10-2 list s byte-oriented, bit-
oriented, and literal and control operations.
Table 10-1 shows the opcode field descriptions.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W regis ter . If ‘d’ is one, the res ult is place d
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator which sel ec t s the number of th e bi t a ffected
by the op erat ion, while ‘f’ represent s the num be r of the
file in which the bit is located.
For literal and control operations, ‘k’ represents an
eight or eleven bit constant or literal value.
TABLE 10-1: OPCODE FIELD
DESCRIPTIONS
The instruction set is highly orthogonal and is grouped
into three basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal and cont rol operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In thi s cas e, t he ex ec u ti o n tak es tw o in s tru ct i o n cy cles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an osc illator frequency of 4 M Hz, th e normal i nstructio n
executi on tim e is 1 s. If a con dition al tes t is tr ue or th e
program counter is changed as a result of an
instruction, the instruction execution time is 2 s.
Table 10-2 lists the instructions recognized by the
MPASM assembler.
Figure 10-1 shows the general formats that the
instructions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 10-1: GENERAL FORMAT FOR
INSTRUCTIONS
A description of each instruction is available in the PIC®
Mid-Range Reference Manual, (DS33023).
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file r egister
kLiteral field, constant data or label
xDon’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
PC Program Counter
TO Time-out bit
PD Power-down bit
ZZero bit
DC Digit Carry bit
CCarry bit
Note: To maintain upward compatibility with
future PIC16CXXX products, do not use
the OPTION and TRIS instructi ons.
Byte-oriented file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (litera l )
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit imm ediate value
General
CALL and GOTO instructions only
PIC16C712/716
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TABLE 10-2: PIC16CXXX INSTRUCTION
SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Compleme nt f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
0011
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Ski p if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR liter a l with W
Move literal to W
Re tu r n from inter rup t
Return with literal in W
Return from Subrou tine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if as signed
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
1999-2013 Microchip Technology Inc. DS41106C-page 69
PIC16C712/716
11.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C18 and MPLAB C30 C Compilers
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD 2
• Device Progra mm ers
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
11.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- Emulator (sold separa tel y)
- In-Circu it Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Visual device initializer for easy register
initialization
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Exten si ve on-l in e help
• Integration of se lect third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
The MPLAB IDE allows you to:
• Edit your source files ( eithe r asse mbly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug us ing :
- Sourc e files (assembl y or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
PIC16C712/716
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11.2 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
The MPASM Assembler generates relocatable object
files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST file s that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
sour ce fil es
• Directi ves that allow complete control over the
assembly process
11.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC18 family of microcontrollers and
dsPIC30F family of digital signal controllers. These
compilers provide powerful integration capabilities,
superior code optimization and ease of use not found
with other compilers.
For easy source level debugging, the comp ilers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
11.4 MPLINK Object Linker /
MPLIB Object Librari an
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler . It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB O bject Li brarian manag es the cre ation an d
modification of library files of precompiled code. When
a routine from a library is called from a source file , only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many di fferent applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, rep lacement, delet ion and extraction
11.5 MPLAB ASM30 Assembler, Linker
and Librarian
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or lin ked with other relocatable ob ject files and
arch ives to c rea te an e xecu tabl e fil e. N otab le fe atu res
of the assembler include:
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich dire cti ve set
• Flexible macro language
• MPLAB IDE compatibility
11.6 MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, as well as internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the laboratory environment, making it an excellent,
economical software development tool.
1999-2013 Microchip Technology Inc. DS41106C-page 71
PIC16C712/716
11.7 MPLAB ICE 2000
High-Performance
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microc ontroller design tool set for PIC micro-
controllers. Software control of the MPLAB ICE 2000
In-Circuit Emulator is advanced by the MPLAB Inte-
grated Development Environment, which allows edit-
ing, building, downloading and source debugging from
a sin gle envir onment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing feat ures. Interc hangeabl e proces sor modul es allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
11.8 MPLAB ICE 4000
High-Performance
In-Circuit Emulator
The MPLAB ICE 4000 In-Circuit Emu lator is intende d to
provide the product development engineer with a
complete microcontroller design tool set for high-end
PIC MCUs and dsPIC DSCs. Software control of the
MPLAB ICE 4000 In-Circuit Emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environm ent.
The MPLAB ICE 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanc ed emulator fe atures inc lude complex t riggering
and timing, and up to 2 Mb of emulation memory.
The MPLAB ICE 4000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
11.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug sou rce code by s etting bre akpoi nts , singl e step -
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
11.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64 ) for men us an d error m essages and a m odu-
lar, detachable socket assembly to support various
pack age types. The ICSP™ cable assembly is in cluded
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Devic e Programmer ca n read, verif y and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 h as high-spe ed co mmunicat ions an d
optimized algorithms for quick programming of large
memory devices and in corporates an SD/MMC card for
file storage and secure data applications.
PIC16C712/716
DS41106C-page 72 1999-2013 Microchip Technology Inc.
11.11 PICSTART Plus Development
Programmer
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a CO M (RS-232) port. MPLAB
Inte grated D evelopm ent Envir onment software m akes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76 X, may be sup ported with an a dapter socket.
The PICSTART Plus Deve lopment Programme r is CE
compliant.
11.12 Demonstration, Development and
Evaluation Boards
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards inclu de prototyping a reas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The board s suppo rt a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces , LCD displays, potentiometers and additional
EEPROM memory .
The demonstration and development boards can be
used in teac hing environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart® battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
and the latest “Product Selector Guide” (DS00148) for
the complete list of demonstration, development and
evaluation kits.
1999-2013 Microchip Technology Inc. DS41106C-page 73
PIC16C712/716
12.0 ELECTRIC AL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature.............................................................................................................................. -65°C to +150 °C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) .........................................-0.3V to (VDD + 0.3V)
Volta ge on VDD with res p ect to VSS ......................................................................................................... -0.3V to +7.5V
Volta ge on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V
Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V
Total powe r dissipation (Note 1) (PDIP and SOIC)...................................................................................................1.0W
Total powe r dissipation (Note 1) (SSOP)................................................................................................................0.65W
Maximum curr ent o ut of VSS pin ...........................................................................................................................300 mA
Maximum curr ent into VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA
Output cl amp current, IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum curr ent su nk byPORTA and PORTB (combined).................................................................................200 mA
Maximum current sourced by PORTA and PORTB (combined)...........................................................................200 mA
Note 1: Power dissipation is calcula ted as follow s: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL)
2: V o ltage sp ikes below VSS at the MCLR/VPP pin, inducin g curr ent s g reater than 8 0 mA, ma y ca use l atch-u p.
Thus, a series resistor of 50 -100 should be used when applying a “low” level to the MCLR/VPP pin rat her
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maxi mum rating conditions for
extended periods may affect device reliability.
PIC16C712/716
DS41106C-page 74 1999-2013 Microchip Technology Inc.
FIGURE 12-1: PIC16C712/716 VOLTAGE-FREQUENCY GRAPH, -40°C < TA < +125°C
FIGURE 12-2: PIC16LC712/716 VOLTAGE-FREQUENCY GRAPH, 0°C < TA < +70°C
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(Volts)
30
2.0
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
40
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
4 10
Frequency (MHz)
VDD
20
(Volts)
25
2.0
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
1999-2013 Microchip Technology Inc. DS41106C-page 75
PIC16C712/716
12.1 DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Ex tended)
PIC16C712/716-20 (Commercial, Industrial, Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
D001
D001A VDD Supply Vo ltage 4.0
4.5
VBOR*
—
—
—
5.5
5.5
5.5
V
V
V
XT, RC and LP osc mode
HS osc mode
BOR enabled(7)
D002* VDR RAM Data Retention Voltage(1) —1.5—V
D003 VPOR VDD Start Voltag e to ensure inter-
nal Power-on Reset signal —VSS — V See section on Power-on Reset for details
D004*
D004A* SVDD VDD Rise Rate to ensure internal
Power-on Reset signal 0.05
TBD —
——
—V/ms PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
D005 VBOR Brown-out Reset
voltage trip point 3.65 — 4.35 V BODEN bit set
D010
D013 IDD Supply Current(2,5) —
—0.8
4.0 2.5
8.0 mA
mA FOSC = 4 MHz, VDD = 4.0V
FOSC = 20 MHz, VDD = 4.0V
D020
D021
D021B
IPD Power-down Current(3,5) —
—
—
—
10.5
1.5
1.5
2.5
42
16
19
19
A
A
A
A
VDD = 4.0V, WD T enabled,-40C to +85C
VDD = 4.0V, WD T disabled, 0C to +70C
VDD = 4.0V, WD T disabled,-40C to +85C
VDD = 4.0V, WDT disabled,-40C to +125C
D022*
D022A* IWDT
IBOR
Module Diffe re ntial Curr e nt(6)
Watchdog Timer
Brown-out Reset —
—6.0
TBD 20
200 A
AWDTE bit set, VDD = 4. 0V
BODEN bit set, VDD = 5.0V
1A FOSC LP Oscillator Operating Frequency
RC Oscillator Operating Frequency
XT Oscillator Operating Frequency
HS Oscillator Operating Frequency
0
0
0
0
—
—
—
—
200
4
4
20
KHz
MHz
MHz
MHz
All temperatures
All temperatures
All temperatures
All temperatures
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note1: T his is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current
consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the
part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS.
4: For RC Osc mode, current through REXT is not i ncluded . The current th rough the resistor can be estimated by the formula
Ir = VDD/2REXT (mA) with REXT in kOhm.
5: T imer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for
design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base
IDD or IPD measurement.
7: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will operate correctly to
this trip point.
PIC16C712/716
DS41106C-page 76 1999-2013 Microchip Technology Inc.
12.2 DC Characteristics: PIC16LC712/716-04 (Commercial, Industrial)
DC CHARACTERISTICS Standard Operating Condition s (unless otherwise stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C for industrial
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
D001 VDD Supply Voltage 2.5
VBOR*—
—5.5
5.5 V
V BOR enabled (Note 7)
D002* VDR RAM Data Retention Voltage(1) —1.5—V
D003 VPOR VDD St art Voltage to ensure inter-
nal Power-on Reset signal —VSS — V See section on Power-on Reset for details
D004*
D004A* SVDD VDD Rise Rate to ensure internal
Power-on Reset signal 0.05
TBD —
——
—V/ms PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
D005 VBOR Brown-out Reset
voltage trip point 3.65 — 4.35 V BODEN bit set
D010
D010A
IDD Supply Current(2,5) —
—
2.0
22.5
3.8
48
mA
A
XT, RC osc modes
FOSC = 4 MHz, VDD = 3.0V (Note 4)
LP osc mode
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D020
D021
D021A
IPD Power-down Current(3,5) —
—
—
7.5
0.9
0.9
30
5
5
A
A
A
VDD = 3.0V, WDT enabled, -40C to +85C
VDD = 3.0V, WDT disabled, 0C to +70C
VDD = 3.0V, WDT disabled, -40C to +85C
D022*
D022A* IWDT
IBOR
Module Differential Current(6)
Watchdog Timer
Brown-out Reset —
—6.0
TBD 20
200 A
AWDTE bit set , VDD = 4.0V
BODEN bit set, VDD = 5.0V
1A FOSC LP Oscillator Operating Frequency
RC Oscillator Operating Frequency
XT Oscillator Operating Frequency
HS Oscillator Operating Frequency
0
0
0
0
—
—
—
—
200
4
4
20
KHz
MHz
MHz
MHz
All temperatures
All temperatures
All temperatures
All temperatures
* T hese parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note1: Th is is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current
consumption.
The test conditions for all IDD measurem ents in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the
part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS.
4: For RC O sc mode, current through REXT is not include d. The current throug h the resist or can be estimated by the formula
Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is
for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base
IDD or IPD measurement.
7: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will operate correctly to
this trip point.
1999-2013 Microchip Technology Inc. DS41106C-page 77
PIC16C712/716
12.3 DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended)
PIC16C712716-20 (Commercial, Industr ial, Extended)
PIC16LC712/716-04 (Commercial, Industri a l)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operati ng tem per ature 0°C T
A +70°C for commer cial
-40°C T
A +85°C for industrial
-40°C T
A +125°C for extended
Operating voltage VDD range as described in DC spec Section 12.1
“DC Characteristics: PIC16C712/716-04 (Commercial, Industrial,
Extended) PIC16C712/716-20 (Commercial, Industrial,
Extended)” and Section 12.2 “DC Characteristics: PIC16LC712/
716-04 (Commercial, Industrial)”
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
Input Low Voltage
VIL I/O ports
D030
D030A with TTL buffer VSS
VSS
—
—0.8V
0.15VDD
V
V4.5V VDD 5.5V
otherwise
D031 with Schmitt Trigger buffer VSS —0.2VDD V
D032 MCLR, OSC1 (in RC mode) Vss —0.2VDD V
D033 OSC1 (in XT, HS and LP
modes) Vss —0.3VDD V(Note 1)
Input High Voltage
VIH I/O ports —
D040 with TTL buffer 2 .0 —VDD V4.5V VDD 5.5V
D040A 0.25VDD
+ 0.8V
—VDD Votherwise
D041 with Schmitt Trigger buffer 0.8VDD —VDD V For entire VDD range
D042 MCLR 0.8VDD —VDD V
D042A OSC1 (XT, HS and LP modes) 0.7VDD —VDD V(Note 1)
D043 O S C1 (in RC mode) 0.9VDD —VDD V
Input Leakage Current
(Notes 2, 3)
D060 IIL I/O ports ——1AVss VPIN VDD,
Pin at high-impedance
D061 MCLR, RA4/T0CKI ——5AVss VPIN VDD
D063 OSC1 ——5AVss VPIN VDD,
XT, HS and LP osc modes
D070 IPURB PORTB weak pull-up current 50 250 400 AVDD = 5V, VPIN = VSS
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Not e 1 : In RC Oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC
MCU be driven with external cl ock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
PIC16C712/716
DS41106C-page 78 1999-2013 Microchip Technology Inc.
Output Low Voltage
D080 VOL I/O ports ——0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40C to +85C
——0.6 V IOL = 7.0 mA, VDD = 4.5V,
-40C to +125C
D083 OSC2/CLKOUT
(RC Osc mode) ——0.6 V IOL = 1.6 mA, VDD = 4.5V,
-40C to +85C
——0.6 V IOL = 1.2 mA, VDD = 4.5V,
-40C to +125C
Output High Voltage
D090 VOH I/O ports (Note 3) VDD-0.7 ——VIOH = -3.0 mA, VDD = 4.5V,
-40C to +85C
VDD-0.7 ——VIOH = -2.5 mA, VDD = 4.5V,
-40C to +125C
D092 O S C2/CLKOUT (RC Osc
mode) VDD-0.7 ——VIOH = -1.3 mA, VDD = 4.5V,
-40C to +85C
VDD-0.7 ——VIOH = -1.0 mA, VDD = 4.5V,
-40C to +125C
D150* VOD Open-Drain High Voltage ——8. 5 V RA4 pin
Capacitive Loading Specs on
Output Pins
D100 COSC2 OSC2 pin ——15 pF In XT, HS and LP modes when
external clock is used to drive
OSC1.
D101 CIO All I/O pins and OSC2 (in RC
mode) ——50 pF
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operati ng tem per ature 0°C T
A +70°C for commer cial
-40°C T
A +85°C for industrial
-40°C T
A +125°C for extended
Operating voltage VDD range as described in DC spec Section 12.1
“DC Characteristics: PIC16C712/716-04 (Commercial, Industrial,
Extended) PIC16C712/716-20 (Commercial, Industrial,
Extended)” and Section 12.2 “DC Characteristics: PIC16LC712/
716-04 (Commercial, Industrial)”
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Not e 1 : In RC Oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC
MCU be driven with external cl ock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
1999-2013 Microchip Technology Inc. DS41106C-page 79
PIC16C712/716
12.4 AC (Timing) Charact eristics
12.4.1 TIMING PARAME TER SYMBOLOGY
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
2. TppS
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercas e letters and their meanings:
SFFall PPeriod
HHigh RRise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
PIC16C712/716
DS41106C-page 80 1999-2013 Microchip Technology Inc.
12.4.2 TIMING CONDITIONS
The temperature and voltages specified in Table 12-1
apply to all timing specifications, unless otherwise
noted. Figure 12-3 specifies the load conditions for the
timing specification s.
TABLE 12-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
FIGURE 12-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Condition s (unless otherwise stated)
Operating temperature 0°C TA +70°C for commercial
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Operating voltage VDD range as described in DC spec Section 12.1 “DC Characteristics:
PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712/716-20 (Commercial,
Industrial, Extended)” and Section 12.2 “DC Characteristics: PIC16LC712/716-04 (Com-
mercial, Industrial)”.
LC parts operate for commercial/industrial temp’s only.
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL=464
CL= 50 pF for al l pins except OSC2/CLKO UT
15 pF for OSC2 output
Load condition 1 Load condition 2
Legend:
1999-2013 Microchip Technology Inc. DS41106C-page 81
PIC16C712/716
12.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 12-4: EXTERNAL CLOCK TIMING
TABLE 12-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
1A FOSC External CLKIN Frequency
(Note 1) DC — 4 MHz RC and XT osc modes
DC — 4 MHz HS osc mode (-04)
DC — 20 MHz HS osc mode (-20)
DC — 200 kHz LP osc mode
Oscillator Frequency
(Note 1) DC — 4 MHz RC osc mode
0.1 — 4 MHz XT osc mode
4 — 20 MHz HS osc mode
5 — 200 kHz LP osc mode
1T
OSC External CLKIN Period
(Note 1) 250 — — ns RC and XT osc modes
250 — — ns HS osc mode (-04)
50 — — ns HS osc mode (-20)
5— —s LP osc mode
Oscillator Period
(Note 1) 250 — — ns RC osc mode
250 — 10,000 ns XT osc mode
250 — 250 ns HS osc mode (-04)
50 — 250 ns HS osc mode (-20)
5— —s LP osc mode
2TCY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC
3* TosL,
TosH Extern al Clock in (OSC1) High or
Low Time 100 — — ns XT oscillator
2.5 — — s LP oscillator
15 — — ns HS oscillator
4* TosR,
TosF Extern al Clock in (OSC1) Rise or
Fall Time — — 25 ns XT oscillator
— — 50 ns LP osc illator
— — 15 ns HS osc illator
* These parameters are characterized bu t not tested.
† Dat a in “Typ” column is a t 5V, 25°C un les s oth erwis e stated. Th es e parameters are fo r de si gn guidance on ly
and are not tested.
Note1: Instruction cycle period (TCY) equals four times the input oscillator time bas e pe riod . All spec if ied val ues are
based on charac terizat ion dat a for tha t p articular o scill ator type under st and ard operat ing condit ions with the
device exe cutin g code. Ex ceedi ng thes e spec ified li mit s may result i n an unst abl e osci llator o pera tion and /or
higher th an ex pected curren t cons umpti on. All devices are te sted to operat e at “min.” value s with a n exte rnal
clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.
3
344
1
2
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
CLKOUT
PIC16C712/716
DS41106C-page 82 1999-2013 Microchip Technology Inc.
FIGURE 12-5: CLKOUT AND I/O TIMING
TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
10* TosH2ckL OSC1 to CLKOUT — 75 200 ns Note 1
11* TosH2ckH OSC1¦ to CLKOUT¦ — 75 200 ns Note 1
12* Tck R CLKO UT rise time — 35 100 ns Note 1
13* TckF CLKOUT fall time — 35 100 ns Note 1
14* TckL2io V CLKOUT Ø to Port out valid — — 0.5TCY + 20 ns Note 1
15* TioV2ckH Port in valid before CLKOUT ¦ Tosc + 200 — — ns Note 1
16* TckH2ioI Port in hold after CLKOUT ¦ 0 — — ns Note 1
17* TosH2ioV OSC1¦ (Q1 cycle) to Port out valid — 50 150 ns
18* TosH2ioI OSC1¦ (Q2 cycle) to Port input
invalid (I/O in hold time) Standard 100 — — ns
18A* Extended (LC) 200 — — ns
19* TioV2osH Port input valid to OSC1¦ (I/O in setup time) 0 — — ns
20* TioR Port output rise time Standard — 10 40 ns
20A* Extended (LC) — — 80 ns
21* TioF Port output fall time Standard — 10 40 ns
21A* Extended (LC) — — 80 ns
22††* TINP INT pin high or low time TCY ——ns
23††* TRBP RB7:RB4 change INT high or low time TCY ——ns
* These parameters are characterized but not tested.
† Dat a in “Typ” column is a t 5V, 25°C unl ess ot herwise sta ted. The se p arame ters are fo r desig n guida nce on ly
and are not tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
Note: Refer to Figure 12-3 for load conditions.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12
16
old value new value
1999-2013 Microchip Technology Inc. DS41106C-page 83
PIC16C712/716
FIGURE 12-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
FIGURE 12-7: BROWN-OUT RESET TIMING
TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No. Sym. Characteristic Min. Typ† Max. Units Conditions
30 TmcL MCLR Pulse Width (low) 2 — — sVDD = 5V, -40°C to +125°C
31* TWDT Watchdog T imer Time-out Period
(No Prescaler) 71833ms
VDD = 5V, -40°C to +125°C
32 TOST Oscillation S tart-up Timer Period — 1024 TOSC ——
TOSC = OSC1 period
33* TPWRT Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C
34 TIOZ I/O High-impedance from MCLR
Low or WDT Reset ——2.1
s
35 TBOR Brown-out Reset Pulse Width 100 — — sVDD BVDD (D005)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 12-3 for load conditions.
VDD BVDD
35
PIC16C712/716
DS41106C-page 84 1999-2013 Microchip Technology Inc.
FIGURE 12-8: TIMER0 AND TIMER1 EXTERNAL CLOC K TIMINGS
TABLE 12-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
41* Tt0L T 0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns
With Prescaler Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4,.. ., 25 6 )
45* Tt1H T1CKI High Time Synchronous, Prescaler = 10.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
Standard 15 — — ns
Extended (LC) 25 — — ns
Asynchronous Standard 30 — — ns
Extended (LC) 50 — — ns
46* Tt1L T1CKI Low Time Synchronous, Prescaler = 10.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
Standard 15 — — ns
Extended (LC) 25 — — ns
Asynchronous Standard 30 — — ns
Extended (LC) 50 — — ns
47* Tt1P T1CKI input period Synchronous Standard Greater of:
30 OR TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
Extended (LC) Greater of:
50 OR TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Asynchronous Standard 60 — — ns
Extended (LC) 100 — — ns
Ft1 Timer1 oscillato r input frequency range
(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz
48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc — 7Tosc —
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 12-3 for load conditions.
46
47
45
48
41
42
40
T0CKI
T1OSO/T1CKI
TMR0 or
TMR1
1999-2013 Microchip Technology Inc. DS41106C-page 85
PIC16C712/716
FIGURE 12-9: CAPTURE/COMPARE/PWM TIMINGS
TABLE 12-6: CAPTURE/COMPARE/PWM REQUIREMENTS
Param
No. Sym. Characteristic Min Typ† Max Units Conditions
50* TccL CCP1 input low
time No Prescaler 0.5TCY + 20 — — ns
With Prescaler Standard 10 — — ns
Extended (LC) 20 — — ns
51* TccH CCP1 input high
time No Prescaler 0.5TCY + 20 — — ns
With Prescaler Standard 10 — — ns
Extended (LC) 20 — — ns
52* TccP CCP1 input period 3TCY + 40
N— — ns N = prescale value
(1,4, or 16)
53* Tc cR CCP1 output rise time Standard — 10 25 ns
Extended (LC) — 25 45 ns
54* TccF CCP1 output fall time Standard — 10 25 ns
Extended (LC) — 25 45 ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 12-3 for load conditions.
CCP1
(Capture Mode)
50 51
52
CCP1
53 54
(Compare or PWM Mode)
PIC16C712/716
DS41106C-page 86 1999-2013 Microchip Technology Inc.
TABLE 12-7: A/D CONVERTER CHARACTERISTICS:
PIC16C712/716-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16C712/716-20 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16LC712/716-04 (COMMERCIAL, INDUSTRIAL)
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
A01 NRResolution — — 8-bits bit VREF = VDD = 5.12V,
VSS £ VAIN £ VREF
A02 EABS Total Absolu te e r ro r ——< ± 1 LSb VREF = VDD = 5.12V,
VSS £ VAIN £ VREF
A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS £ VAIN £ VREF
A04 EDL Diff erential linearity error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS £ VAIN £ VREF
A05 EFS Full scale error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS £ VAIN £ VREF
A06 EOFF Offset error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS £ VAIN £ VREF
A10 — Monotonicity — guaranteed
(Note 3) ——VSS £ VAIN £ VREF
A20 VREF Reference voltage 2.5V — VDD + 0.3 V
A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V
A30 ZAIN Recommended impedance of
analog voltage source — — 10.0 k
A40 IAD A/D conversion cur-
rent (VDD)Standard — 180 — A A verage current consump-
tion when A/D is on.
(Note 1)
Extended (LC) — 90 — A
A50 IREF VREF in put current (Note 2) 10
—
—
—
1000
10
A
A
During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 9.1
“Configuration Bits”.
During A/D Conversion
cycle
2: * These parameters are characterized but not tested.
3: † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: When A/D is off, it will not consum e any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.
1999-2013 Microchip Technology Inc. DS41106C-page 87
PIC16C712/716
FIGURE 12-10: A/D CONVERSION TIMING
TABLE 12-8: A/D CONVERSION REQUIREMENTS
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
130 TAD A/D clock period Standard 1.6 — — sTOSC based, VREF 3.0 V
Extended (LC) 2.0 — — sT
OSC based, VREF full range
Standard 2.0 4.0 6.0 s A/D RC Mode
Extended (LC) 3.0 6. 0 9. 0 s A/D RC Mode
131 TCNV Conversion time (not including S/H time)
(Note 1) 11 — 11 TAD
132 TACQ Acquisition time (Note 2)
5*
20
—
—
—
s
s The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP in stru ction to be
executed.
135 TSWC Switching from convert Æ sample time 1.5 § — — TAD
:* These parameters are characterized but not tested.
:† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
:§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 9.1 “Configuration Bits” for min. conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(TOSC/2) (1)
7 6543210
Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This
allows the SLEEP instruction to be executed.
1 Tcy
134
PIC16C712/716
DS41106C-page 88 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41106C-page 89
PIC16C712/716
13.0 PACKAGING INFORMATION
13.1 Package Marking Information
18-Lead PDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16C716-04/P
0510017
XXXXXXXX
18-Lead CERDIP Windowed
XXXXXXXX
YYWWNNN
PIC16C
Example
716/JW
0510017
18-Lead SOIC (.300”)
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
PIC16C712-20
/SO 0510017
20-Lead SSOP
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Example
PIC16C712
-20I/SS
0510017
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the ful l Micro chip p art nu mber ca nnot be m arked on one line , it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
PIC16C712/716
DS41106C-page 90 1999-2013 Microchip Technology Inc.
13.2 Package Detail s
The follow ing sections give the technical details of the
packages.
18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
1510515105
Mold Draft Angle Bottom 1510515105
Mold Draft Angle Top 10.929.407.87.430.370.310
eB
Overall Row Spacing § 0.560.460.36.022.018.014BLower Lead Width 1.781.461.14.070.058.045
B1
Upper Lead Width 0.380.290.20.015.012.008
c
Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 22.9922.8022.61.905.898.890DOverall Len gth 6.606.356.10.260.250.240E1Molded Package Width 8.267.947.62.325.313.300EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.683.302.92.145.130.115A2Molded Package Thickness 4.323.943.56.170.155.140ATop to Seating Plane 2.54
.100
p
Pitch 1818
n
Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units
1
2
D
n
E1
c
eB
E
p
A2
L
B1
B
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
1999-2013 Microchip Technology Inc. DS41106C-page 91
PIC16C712/716
18-Lead Plasti c Small Outline (SO) – Wide, 300 mil (SOIC)
Foot A ngle 048048
1512015120
Mold Draft Angle Bottom 1512015120
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.300.270.23.012.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 11.7311.5311.33.462.454.446DOverall Length 7.597.497.39.299.295.291E1Molded Package Widt h 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff § 2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050
p
Pitch 1818
n
Numb er of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
L
c
h
45
1
2
D
p
n
B
E1
E
A2
A1
A
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
PIC16C712/716
DS41106C-page 92 1999-2013 Microchip Technology Inc.
18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
3.30 3.56 3.81
5.335.084.83.210.200.190W2Window Length .150.140.130W1Wi ndow Width 10.809.788.76.425.385.345eBOverall Row Spacing § 0.530.470.41.021.019.016BLower Lead Width 1.521.401.27.060.055.050B1Upper Lead Width 0.300.250.20.012.010.008
c
Lead Thickness 3.813.493.18.150.138.125LTip to Seating Plane 23.3722.8622.35.920.900.880DOverall Length 7.497.377.24.295.290.285
E1
Ceramic Pkg . Width 8.267.947.62.325.313.300EShoulder to Shoulder Width 0.760.570.38.030.023.015A1Standoff 4.194.063.94.165.160.155A2Ceramic Pa ckag e Height 4.954.644.32.195.183.170A
Top to Seating Plane 2.54.100
p
Pitch 1818
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
1
2
D
n
W2
E1
W1
c
eB
E
p
L
A2
B
B1
A
A1
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-036
Drawing No. C04-010
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
1999-2013 Microchip Technology Inc. DS41106C-page 93
PIC16C712/716
20-Lead Plasti c Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
10501050
Mold Draft Angle Bottom 10501050
Mold Draft Angle Top 0.380.320.25.015.013.010BLead Width 203.20101.600.00840
Foot A ngle 0.250.180.10.010.007.004
c
Lead Thickness 0.940.750.56.037.030.022LFoot Length 7.347.207.06.289.284.278DOverall Length 5.385.255.11.212.207.201E1Molded Package Width 8.187.857.59.322.309.299EOverall Width 0.250.150.05.010.006.002A1Standoff § 1.831.731.63.072.068.064A2Molded Package Thickness 1.981.851.73.078.073.068AOverall Height 0.65.026
p
Pitch 20
20
n
Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
L
c
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
PIC16C712/716
DS41106C-page 94 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41106C-page 95
PIC16C712/716
APPENDIX A: REVISION HISTORY
APPENDIX B: CONVERSION
CONSIDERATIONS
There are no previous versions of this device.
APPENDIX C: MIGRATION FROM
BASE-LINE TO
MID-RANGE DEVICES
This section discusses how to migrate from a baseline
device (i.e., PIC16C5X) to a mid-range device (i.e.,
PIC16CXXX).
The following are the list of modifications over the
PIC16C5X mi cro con trol ler family:
1. Instruction word length is increased to 14-bits.
This allows larger page sizes both in program
memory (2K now as oppose d to 512 befor e) and
register file (128 bytes now versus 32 bytes
before).
2. A PC high latch register (PCLATH) is added to
handle program memory paging. Bits PA2, PA1,
PA0 are removed from STATUS register.
3. Data memory paging is redefined slightly.
STATUS register is modified.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out although they are kept for compati-
bility with PIC16C5 X.
5. OPTION_REG and TRIS registers are made
addressable.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8 deep.
8. Reset vector is changed to 0000h.
9. Reset of all registers is revisited. Five different
Reset (and wake-up) types are recognized.
Registers are reset differently.
10. Wake-up from Slee p through interrupt is added.
11. Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These
timers are invok ed s electi vely to a void unne ces-
sary delays on power-up an d wake-up.
12. PORTB has weak pull-ups and interrupt on
change fea ture.
13. T0CKI pin is also a port pin (RA4) now.
14. FSR is made a full eight-bit register.
15. “In- circuit serial p rogramming” is made possibl e.
The use r can pro gram PIC16CXX devices using
only five pins: VDD, VSS, MCLR/VPP, RB6 (clock)
and RB7 (data in/out).
16. PCON STATUS register is added with a Power-
on Reset Status bit (POR).
17. Code protection scheme is enhanced such that
portions of the program memory can be
protected, while the remainder is unprotected.
18. Brown-out protection circuitry has been added.
Controlled by Configuration Word bit BODEN.
Brown-ou t Reset ensures th e device is placed in
a Reset condition if VDD dips below a fixed
setpoint.
To c onvert code written for PIC16C5X to PIC16CXXX,
the user should take the following steps:
1. Remove any program memory page select
operations (P A2, P A1, P A0 bits) for CALL, GOTO.
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
3. Eliminate any data memory page switching.
Redefine data variables to reallocate them.
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
5. Change Reset vector to 0000h.
Version Date Revision Description
A 2/99 This is a new data sheet. How-
ever , the devices desc ribed in this
dat a sh eet are the upg rad es to
the devices found in the
PIC16C6X Dat a Shee t,
DS30234, and the PIC16C7X
Data Sheet, DS30390.
B 9/05 Removed Preliminary Status.
C 1/13 Added a note to each package
outline dra wing.
PIC16C712/716
DS41106C-page 96 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41106C-page 97
PIC16C712/716
INDEX
A
A/D..................................................................................... 45
A/D Converter Enable (ADIE Bit)............................... 16
A/D Converter Flag (ADIF Bit) ......... .................... 17, 47
A/D Converter Interr u p t, Configurin g ........ .................47
ADCON0 Register................................................ 11, 45
ADCON1 Register.......................................... 12, 45, 46
ADRES Register ............................................11, 45, 47
Analog Port Pins, Config u ring........ ............................ 49
Block Diag ram......... .......... ........... ..................... ......... 47
Block Diagram, Analog Input Model ........................... 48
Channel Select (CHS2:CHS0 Bits)............................ 45
Clock Select (ADCS1:ADCS0 Bits)............................ 45
Configuring the Module.............................................. 47
Conversi o n Clo ck (Tad)............. ..................... ........... 49
Conversion Status (GO/DONE Bit)...................... 45, 47
Conversions............................................................... 50
Converter Characteristics .......................................... 86
Module On/Off (ADON Bit). ........................................ 45
Port Configuration Control (PCFG2:PCFG0 Bits)...... 46
Sampling Requirements............................. ......... .. .... . 48
Special Event Trigger (CCP)................................ 41, 50
Timing Dia g ram......... .......... ........... ..................... ....... 87
Absolute Maximum Ratings ............................................... 73
ADCON0 Register........................................................ 11, 45
ADCS1:ADCS0 Bits............ ........... .......... ........... ....... 45
ADON Bit ................................................................... 45
CHS2:CHS0 Bits............... ..................... .................... 45
GO/DONE Bit ....................................................... 45, 47
ADCON1 Register ..................................................1 2, 45, 46
PCFG2: PCFG0 Bits................... .......... ........... .......... . 46
ADRES Register ....................................................1 1, 45, 47
Analog-to-Digital Converter. See A/D Architecture
PIC16C712/716 Block Diagram................................... 5
Assembler
MPASM Assembler.................................................... 70
B
Banking, Data Memory ................................................ 10, 13
BOR. See Brown-out Reset
Brown-Out Reset (BOR).................................................... 55
Brown-out Reset (BOR)................................... 51, 54, 58, 59
BOR Enable (BODEN Bit).......................................... 52
BOR Status (BO R Bit)....... . .......... .......... ........... ......... 18
Timing Dia g ram......... .......... ........... ..................... ....... 83
C
C Compilers
MPLAB C18..... ..................... ........... .......... ........... ..... 70
MPLAB C30..... ..................... ........... .......... ........... ..... 70
Capture (CCP Module) ...................................................... 40
Block Diag ram......... .......... ........... ..................... ......... 40
CCP Pin Configuration............................................... 40
CCPR1H:CCPR1L Registers..................................... 40
Changing Between Capture Prescalers..................... 40
Softwa re In terrupt ..... .......... ..................... ........... ....... 40
Timer1 Mode Selection ..............................................40
Capture/Compare/PWM (CCP)................ .......................... 39
Capture Mode. See Capture
CCP1CON Register............................................. 11, 39
CCPR1H Register...... .......................................... 11, 39
CCPR1L Register .... ............................................ 11, 39
Compare Mode. See Compare
Enable (CCP1IE Bit).................................................. 16
Flag ( C C P1IF Bi t) ............. ...... ...... ...... ..... .......... ...... .. 17
PWM Mode. See PW M
Time r R e so u r ces ..... ......... .......... ...... ......... .......... ...... 39
Timing Dia g ram.... .......... ........... ..................... ........... 85
CCP1CON Regis te r............ ........... ............................... ..... 39
CCP1M3:CCP1M0 Bits ............................................. 39
CCP1X:CCP1Y Bits...... ................................ .......... ... 39
Code Protection........................................................... 51, 65
CP1:CP0 Bits................ ..................... ........... .......... ... 52
Compare (CCP Module)......... ......... .. .... .... ......... .. .... .... .... . 41
Block Diagram ........................................................... 41
CCP Pin Configuration .............................................. 41
CCP R 1 H :C CPR1 L R e g i st e r s ... ...... ...... ..... ...... ...... .... 41
Software Interrupt...................................................... 41
Special Event Trigger.................................... 34, 41, 50
Timer1 Mode Selection .............................................. 41
Configurati o n Bi ts .......... ...... ......... .......... ...... ......... ...... ...... 51
Conversi o n Consid e rations ............................................ .... 95
Customer Change Notification Service ............................ 101
Custome r Notification Service....... ............................... ... 101
Customer Support...................................... ............. ...... ... 101
D
Data Memor y........ .......... ........... ............................... ......... 10
Bank Select (RP1:RP0 Bits) ................................ 10, 13
General Pu rpose Registers............................ ........... 10
Register File Map ...................................................... 10
Spec i a l Fun ction R e g i sters........... ......... .......... . . ...... .. 11
DC Ch a r a cteri s t i c s. .. ...... .......... ......... .......... ......... ...... .. 75, 77
Development Support ........................................................ 69
Direct Add ressing ......................... ..................... ................ 20
E
Elect r i ca l C h a ra c t e r i stics . .. ...... ..... ...... ...... ..... .......... ...... .... 7 3
Errata ................................................................................... 3
Exter n al Po w e r-on R e se t C i r cu i t ..... ...... .. ...... ..... ...... ...... .... 55
F
Family of Devices
PIC1 6 C 7 XX....... .......... ..... .......... ...... ..... .......... ...... ...... 2
Firm w a r e Instructi o n s .............. ......... .......... ......... .......... .... 6 7
I
I/O Ports ........ ........... .......... ........... . ......... ........... .......... ..... 21
ID Locations................................................................. 51, 65
In-C i rc ui t Se rial Pro g r a m ming ™ (ICSP™ ).... ..... .. ...... .. 51, 65
Indir ect Add res si n g.... .. .......... ..... .......... ...... ......... .......... .... 2 0
FSR Register................................................. 10, 11, 20
IND F R e g i ster.... ...... ......... .......... ...... ......... .......... ...... 11
Instruction Format.............................................................. 67
Instruction Set.................................................................... 67
Summary Table ......................................................... 68
INT Interru p t ( RB0 /INT) . See Interrupt Sources
INTCON Register......................................................... 11, 15
GIE Bi t..... ........... .......... ............... . .......... .......... ......... 15
INTE Bi t................ .......... ............... ............... .......... ... 15
INTF Bit ........ .......... ........... ..................... .......... ......... 15
PEIE Bit... ........... .......... ........... ............... .......... ......... 15
RBIE Bit..................................................................... 15
RBIF Bit................ .......... ........... .......... ................ 15, 24
T0IE Bi t...... ........... .......... ........... . ......... ........... .......... . 15
T0IF Bit................... ........... ..................... .......... ......... 15
Inter net Address ............................ .......... ........... .......... .... 101
PIC16C712/716
DS41106C-page 98 1999-2013 Microchip Technology Inc.
Interrupt Sources.......................................................... 51, 61
A/D Conversion Complete ......................................... 47
Block Diag ram............... .......... ..................... ........... ....61
Capture Co mplete (CCP)............................................40
Compare Complete (CCP)......................................... 41
Interrupt-on-Change (RB7: RB4 ) ............................... 24
RB0/INT Pin, External................................................ 62
TMR0 Overflow.................................................... 30, 62
TMR1 Overflow.................................................... 31, 34
TMR2 to PR2 Match ..................................................37
TMR2 to PR2 Match (PWM ) ................................ 36, 42
Inter rupts, Context Savi n g Duri n g .... ........... ..................... ..62
Interrupts, Enable Bits
A/D Converter Enable (ADIE Bit)............................... 16
CCP1 Enable (CCP1IE Bit).................................. 16, 40
Global Interrupt Enable (GIE Bit) ......................... 15, 61
Interrupt-on-Change (RB7:RB4) Enable
(RBIE Bit)..................................................... 15, 62
Peripheral Interrupt Enable (PEIE Bit) ....................... 15
RB0/INT Enable (INTE Bit) ........................................ 15
TMR0 Overflow Enable (T0IE Bit).............................. 15
TMR1 Overflow Enable (TMR1IE Bit) ........................16
TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 16
Interrupts, Flag Bits
A/D Converte r Fla g (A DIF Bit) ................. ............ 17, 47
CCP1 F l a g (CCP1 I F Bi t ).... .. ...... ......... ...... ..... 1 7, 4 0 , 4 1
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ................ .......... ........... .......... 15, 24, 62
RB0/INT Flag (INTF Bit) ............................................. 15
TMR0 Overflow Flag (T0IF Bit)............................ 15, 62
TMR1 Overflow Flag (TMR1IF Bit) ............................ 17
TMR2 to PR 2 M a t ch Flag (TMR2IF Bi t).............. ..... .. 1 7
M
Master Clear (MCLR)
MCLR Reset, Normal Operat io n........ ............ 54, 58, 59
MCLR Reset, Slee p... ........... .......... ........... .......... ...... 59
MCLR Reset, Slee p... ........... .......... ........... .......... 54, 58
Memory Organization
Data Memor y ..... ........... ..................... .......... .............. 10
Program Memory ......................................................... 9
Microc h i p In ternet Web Site...... .......... ........... .......... ........ 101
MPLAB ASM30 Assembler, Linker, Librarian .................... 70
MPLAB ICD 2 In-Circuit Debugger..................................... 71
MPLAB ICE 2000 High-Performance Universal
In-Circuit Em ulator..................................................... 71
MPLAB ICE 4000 High-Performance Universal
In-Circuit Em ulator..................................................... 71
MPLAB Integrated Development Environment Software ... 69
MPLAB PM3 Device Programmer...................................... 71
MPLINK Object Linker/MPLIB Object Librarian ................. 70
O
OPCODE Field Descriptions.............................................. 67
OPTION_REG Register............................................... 12, 14
INTEDG Bi t................... .......... ........... ..................... ... 14
PS2:PS0 Bits ....................................................... 14, 29
PSA Bit................................................................. 14, 29
RBPU Bit........ .......... ........... .......... ..................... ........ 14
T0CS Bit............................................................... 14, 29
T0SE Bit................................................................14, 29
Oscillator Configuration................................................ 51, 53
HS........................................................................ 53, 58
LP......................................................................... 53, 58
RC.................................................................. 53, 54, 58
Selection (FOSC1:FOSC0 Bits)................................. 52
XT........................................................................ 53, 58
Oscillator, Timer1........................................ ................. 31, 34
Oscillator, WDT.................................................................. 63
P
Packaging.......................................................................... 89
Det a il s. ...... .......... ................. ......... .............. ............. .. 90
Paging, Program Memory.............................................. 9, 19
PCON Regist er............................................................ 18, 58
BOR Bit........... ..... ...... ...... ......... ...... ...... ......... ...... ...... 18
POR Bit........... ..... ...... ...... ......... ...... ...... ......... ...... ...... 18
PICSTART Plus Deve lopment Program mer...................... 72
PIE1 R e g is t e r...... ...... ..... ...... ...... ...... ..... ...... ...... ..... ...... 12, 1 6
ADIE Bit..................................................................... 16
CCP1IE Bit ............. .............. ................................ ..... 16
TMR1IE Bit................................................................ 16
TMR2IE Bit................................................................ 16
Pin Functions
MCLR/VPP ................................................................... 6
RA0/ AN0... .. ...... ......... ...... ...... ..... .......... ...... ..... ...... ...... 6
RA1/ AN1... .. ...... ......... ...... ...... ..... .......... ...... ..... ...... ...... 6
RA2/ AN2... .. ...... ......... ...... ...... ..... .......... ...... ..... ...... ...... 6
RA3/AN3/VREF............................................................. 6
RA4/T0CKI ....... ........................................................... 6
RB0/INT....................................................................... 7
RB1........... .......... ......... ...... ......... .......... ......... .......... .... 7
RB2........... .......... ......... ...... ......... .......... ......... .......... .... 7
RB3........... .......... ......... ...... ......... .......... ......... .......... .... 7
RB4........... .......... ......... ...... ......... .......... ......... .......... .... 7
RB5........... .......... ......... ...... ......... .......... ......... .......... .... 7
RB6........... .......... ......... ...... ......... .......... ......... .......... .... 7
RB7........... .......... ......... ...... ......... .......... ......... .......... .... 7
VDD.............................................................................. 7
VSS .............................................................................. 7
Pinout Descriptions
PIC16C712/716 Pinout Description............................. 6
PIR1 Register .............................................................. 11, 17
ADIF Bi t............. ........... .......... ............... ............... ..... 17
CCP1IF Bit....... ........... .......... ..................... ........... ..... 17
TMR1IF Bit................................................................. 17
TMR2IF Bit ................................................................. 17
Pointer, FSR...................................................................... 20
POR. See Power-on Reset
PORTA
Initialization................................................................ 21
PORTA Register.................................................. 11, 21
RA3:RA0 Port Pins.................................................... 21
RA4/T0CKI Pin..... ..................... ................................ 22
TRISA Register .................................................... 12, 21
PORTB
Block Diagr am of R B1 /T1 OSO/T 1 C KI Pin.. .. . ...... ...... 24
Block Diagram of RB2/T10SI Pin ............................... 25
Block Diagram of RB3/CCP1 Pin ............................... 25
Initialization................................................................ 23
PORTB Register.................................................. 11, 23
Pull-up Enable (RBPU Bit). .. ..... .......... ...... ..... ...... ...... 14
RB0/INT Edge Select (INTEDG Bit) .......................... 14
RB0/ INT Pin , Externa l .. ...... ......... ...... ...... ...... ......... .... 6 2
RB3:RB0 Port Pins.................................................... 23
RB7:RB4 Interrupt-on-Change ........................... .... ... 62
RB7:RB4 Interrupt-on-Change Enable (RBIE Bit ) 15, 62
RB7:RB4 Interrupt-on-Change Flag
(RB IF B i t)....... ...... .......... ......... .......... ..... 15, 2 4 , 6 2
RB7:RB4 Port Pins.................................................... 26
TRISB Register .................................................... 12, 23
1999-2013 Microchip Technology Inc. DS41106C-page 99
PIC16C712/716
PORTC
TRISC Register............... ..................... ........... ........... 12
Postscaler, Timer2
Select (TOUTPS3:TOUTPS0 Bits) .............. .............. 36
Postscaler, WDT................................................................ 29
Assignment (PSA Bit) ............. ........... .................. 14, 29
Block Diag ram......... .......... ........... ..................... ......... 30
Rate Select (PS2:PS0 Bits) ................................. 14, 29
Switching Between Timer0 and WDT........................ 30
Power-down Mode. See Sleep
Power-on Res e t (POR)......... .......... ........... 51, 54, 55, 58, 59
Oscillator Start-up Timer (OST)........................... 51, 55
POR Status (PO R Bit)........... ............... ........... ........... 18
Power Contro l (PCON) Register................................ 58
Power-down (PD Bit) ........................................... 13, 54
Power-on R e se t C i r cu i t , Extern a l........ .......... ..... .. ...... 55
Power-up Timer (PWRT) ........ ............................. 51, 55
PWRT Enable (PWRTE Bit)....................................... 52
Time-out (TO Bit)................................................. 13, 54
Time-out Sequence............................................. .... ... 57
Time-out Sequence on Power-up .............................. 60
Timing Dia g ram......... .......... ........... ..................... ....... 83
Presca le r, Captur e........ .......... ........... ..................... .......... . 40
Presca le r, Timer0....... ........... ..................... .......... .............. 29
Assignment (PSA Bit) ............. ........... .................. 14, 29
Block Diag ram......... .......... ........... ..................... ......... 30
Rate Select (PS2:PS0 Bits) ................................. 14, 29
Switching Between Timer0 and WDT........................ 30
Presca le r, Timer1....... ........... ..................... .......... .............. 32
Select (T1CKPS1:T1CKPS0 Bits).............................. 31
Presca le r, Timer2....... ........... ..................... .......... .............. 42
Select (T2CKPS1:T2CKPS0 Bits).............................. 36
Product Identification System .......................................... 103
Program Counter
PCL Register........................................................ 11, 19
PCLATH Register .......................................... 11, 19, 62
Reset Conditions.................................... .................... 58
Program Memory ................................................................. 9
Inter rupt Vector ............ .......... ........... .......... ........... ......9
Paging.................................................................... 9, 19
Program Memory Map................................................. 9
Reset Vec tor................. .......... ........... ..................... ..... 9
Program Verification .......................................................... 65
Programming, Device Instructions..................................... 67
PWM (CCP Module) . ......................................................... 42
Block Diag ram......... .......... ........... ..................... ......... 42
CCPR1H:CCPR1L Registers..................................... 42
Duty Cycle....................... ..................... ..................... . 42
Example Frequencies/Resolutions . ........................... 43
Output Dia g ram............. .......... ..................... ........... ... 42
Period......................................................................... 42
Set-Up for PWM Operation........................................ 43
TMR2 to PR2 Match ............................................36, 42
TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 16
TMR2 to PR2 Match Flag (TMR2IF Bit) .....................17
Q
Q-Clock.............................................................................. 42
R
RAM. See Data Memory
Reader Response............................................................ 104
Register File....... ..................... ..................... ..................... . 10
Register File Map................ .......... ..................... ................ 10
Reset ............................................................................51, 54
Block Diag ram......... .......... ........... ..................... ......... 56
Brown-out Reset (BOR). See Brown-out Reset (BOR)
MCLR Reset. See MCLR
Power-on Reset (POR). See Power-on Reset (POR)
Reset Conditions for All Registers............................. 59
Reset Conditions for PCON Register . ....................... 58
Reset Conditions for Program Counter ..................... 58
Reset Conditions for STATUS Register . ................... 58
Timing Diagram ......................................................... 83
WDT Reset. See Watchdog Timer (WDT)
Revision History ................................................................. 95
S
Sleep .... ...... ...... ......... ...... ...... ......... ...... ......... ...... ...... ........ 64
Sleep .... ...... ...... ......... ...... ...... ......... ...... ......... ...... ...... .. 51, 54
Software Simulator (MPLAB SIM) ..................................... 70
Special Event Trigger. See Com pare
Special Feature s of th e CPU.......................... ................... 51
Special Function Registers................................................ 11
Speed, Operating ................................................................ 1
Stack. ...... .......... ..... .......... ...... ..... .......... ...... ......... ...... ...... .. 19
STATU S Regi ster........ ...... ...... ..... ...... ...... ..... ...... .. 11, 13 , 6 2
C Bit ........................................................................... 13
DC Bit........................................................................ 13
IRP Bit .................. .......... ........... ..................... .......... . 13
PD Bit .................................................................. 13, 54
RP1:RP0 Bits................ ..................... ........... .......... ... 13
TO Bit.................................................................. 13, 54
Z Bit....... ........... .......... ............... ............... .......... ....... 13
T
T1CON Registe r......... .......... ....................................... 11, 31
T1CKPS1:T1CKPS0 Bits........................................... 31
T1OSCEN Bi t ................. ........... .......... ........... ........... 31
T1SYNC Bit............................................................... 31
TMR1CS Bit............................................................... 31
TMR1ON Bit.............................................................. 31
T2CON Registe r......... .......... ....................................... 11, 36
T2CKPS1:T2CKPS0 Bits........................................... 36
TMR2ON Bit .............................................................. 36
TOU TPS3:TOU T PS0 Bi ts ...... .. ...... ...... ......... ...... ...... 36
Timer0 ............................................................................... 29
Block Diagram ........................................................... 29
Clock Source Edge Select (T0SE Bit) ... .............. 14, 29
Clock So urce Sel e c t (T 0C S Bit) ....... .. ..... ...... ...... 14, 29
Overflow Enable (T0IE Bit)........................................ 15
Overflow Fla g (T0IF Bit) ...... .......... ..................... . 15, 62
Overflow In terrupt ................... ..................... ........ 30, 62
Prescaler. See Prescaler, Timer0
Timing Dia g ram.... .......... ........... ..................... ........... 84
TMR0 R e g i s t e r .. .. ...... ......... ...... .......... ......... .......... .... 1 1
Timer1 ............................................................................... 31
Block Diag ram........ ........... ..................... ................... 32
Capacitor Selection ................................................... 34
Clock Source Select (TMR1CS Bit)........................... 31
Extern a l C l o ck In put Syn c (T1 SYNC Bit ) ...... ...... ...... . 31
Module On/Off (TMR1ON Bit) ................................... 31
Oscillator .............................................................. 31, 34
Oscillato r Enabl e (T1OSCEN Bit) ....... ............. .......... 31
Overflow Enable (TMR1IE Bit) ......................... .... .... . 16
Overflow Flag (TMR1IF Bit)....................................... 17
Overflow Interrupt................................................ 31, 34
Prescaler. See Prescaler, Timer1
Special Event Tr igger (CCP)............................... 34, 41
T1CON Register.................................................. 11, 31
Timing Dia g ram.... .......... ........... ..................... ........... 84
TMR1 H R e g i s t e r............ ......... .......... ..... .......... .... 1 1 , 3 1
PIC16C712/716
DS41106C-page 100 1999-2013 Microchip Technology Inc.
TMR1L Register................................................... 11, 31
Timer2
Block Diag ram............... .......... ..................... ........... ... 36
Postscaler. See Postscaler, Timer2
PR2 Register ..................................................12, 36, 42
Prescaler. See Prescaler, Time r2
T2CON Register .................................................. 11, 36
TMR2 Register..................................................... 11, 36
TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 16
TMR2 to PR2 Match Flag (TMR2IF Bit) .....................17
TMR2 to PR2 Match Interrupt........................ 36, 37, 42
Timing Diagrams
Time-out Sequence on Power-up ..............................60
Wake-up from Sleep via Interrupt ...............................65
Timing Diagrams and Specifications.................................. 81
A/D Conversion................. ..................... .................... 87
Brown-out Reset (BOR)............................................. 83
Capture/Compare/PWM (CCP).................................. 85
CLKOUT and I/O ........................................................82
External Clock ............................................................81
Oscillator Start-up Timer (OST)......................... ........ 83
Power-up Timer (PWRT) ................ ..................... ...... 83
Reset.......................................................................... 83
Timer0 and Timer1..................................................... 84
Watchdog Timer (WDT)............................................. 83
W
W Register......................................................................... 62
Wake-up from Sleep.......................................................... 51
Wake-up from Sleep.......................................................... 64
Interrupts ............................................................. 58, 59
MCLR Reset........................... ................................ ... 59
Timing Dia g ram ........ .......... ........... ..................... ....... 65
WDT Reset ..... ..................... ................................ ...... 59
Watchdog Timer (WDT)............................................... 51, 63
Block Diag ram ........ .......... ................................ ......... 63
Enable (WDTE Bit) .............................................. 52, 63
Postscaler. See Postscaler, WDT
Program ming Co n side r a tions.... .......... ...................... 63
RC Oscillator.............................................................. 63
Time-out Peri o d................ ............... . ......... ........... ..... 63
Timing Dia g ram ........ .......... ........... ..................... ....... 83
WDT Reset, Normal Operation ...................... 54, 58, 59
WDT Re set, S leep. ...... .......... ......... .......... ..... 54, 5 8 , 5 9
WWW Address ................... .......... ................... ............... . 101
WWW, On-Line S upport ...................................................... 3
1999-2013 Microchip Technology Inc. DS41106C-page 101
PIC16C712/716
THE MICROCHIP WEB SITE
Microc hip pro vides onl ine s upport v ia our W WW site at
www.microchip.com. This web si te i s us ed as a m ean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
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Microchip sales offices, distributors and factory
representatives
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To register, access the Microchip web site at
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registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
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• Distributor or Representative
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Customers should contact their distributor,
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customers. A listing of sales offices and locations is
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Technical s upport is avail able throug h the web si te
at: http://microchip.com/support
PIC16C712/716
DS41106C-page 102 1999-2013 Microchip Technology Inc.
READER RESP ONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
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DS41106CPIC16C712/716
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
1999-2013 Microchip Technology Inc. DS41106C-page 103
PIC16C712/716
PIC16C712/716 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
* JW Devices are UV er asable and can be programm ed to any device configurat ion. JW Devices meet the electr ical requirement of
each oscillator type (including LC devices).
Sales and Support
PART NO. -XX X/XX XXX
PatternPackageTemperature
Range
Frequency
Range
Device
Device: PIC16C712(1), PIC16C712T(2);VDD range 4.0V to 5.5V
PIC16LC712(1), PIC16LC712T(2);VDD range 2.5 V to 5.5V
PIC16C716(1), PIC16C716T(2);VDD range 4.0V to 5.5V
PIC16LC716(1), PIC16LC716T(2);VDD range 2.5 V to 5.5V
Frequency Range: 04 = 4 MHz
20 = 20 MHz
Temperature
Range: blank = 0C to 70C (Commercial)
I= -40C to +85C (Industrial)
E= -40C to +125C (Extended)
Package: JW = Win dowed CERDIP
SO = SOIC
P=PDIP
SS = SSOP
Pattern: QTP, SQTP, Code or Special Requirements
(blank otherwise)
Examples:
a) PIC16C716 – 04/P 301 = Commercial temp.,
PDIP package, 4 MHz, normal VDD limits, QTP
pattern #301.
b) PIC16LC712 – 04I/SO = Industrial temp., SOIC
package, 200 kHz, Extend ed VDD limits.
c) PIC16C712 – 20I/P = Industrial temp., PDIP
package, 20MHz, nor mal VDD limits.
Note 1: C = CMOS
LC = Low Power CMOS
2: T = in tape and reel – SOIC, SSOP
packages only.
3: LC extended temperature device is not
offered.
4: LC is not offered at 20 MHz
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Wor ldwide Site (www.microchip.com)
1999-2013 Microchip Technology Inc. DS41106C-page 104
PIC16C712/716
NOTES:
1999-2013 Microchip Technology Inc. DS41106C-page 105
Information contained in this publication regarding device
applications and the like is p ro vided on ly for your c on ve nience
and may be supers eded by updat es . I t is y o u r r es ponsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
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PICSTART, PIC 32 logo, rfPIC, SST, SS T Logo, SuperFlash
and UNI/O are registered trademarks of Microchip T echnology
Incorporated in the U.S.A. and other countries.
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MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE, In-Circ u it Serial
Programm ing, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germ any II GmbH & C o. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 1999-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769751
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and d sPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS41106C-page 106 1999-2013 Microchip Technology Inc.
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11/29/12
