Publication Date : December 2013
1
< Dual-In-Line Package Intelligent Power Module >
PSS30S92F6-AG
PSS30S92E6-AG
TRA NSFER MOLDING TYPE
INSULATED TYPE
OUTLINE
MAIN FUNCTION AND RATI NGS
3 phase DC/AC inverter
600V / 30A (CSTBT)
N-side IGBT open emitter
Built-in boot s t rap dio des with current limiting resistor
APPLICATION
AC 100~240Vrms(DC voltage:400V or below) class
low power motor control
TYPE NAME
PSS30S92F6-AG
With temperature output function
PSS30S92E6-AG
With OT protection function
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
● For P-side : Drive circuit, High voltage high-speed lev el shifting, Cont r ol supp ly under-voltage (UV) protection
● For N-side : Drive circuit, Control supply under-volt age protection (UV), Short circuit protection (SC),
Over temperature protection (OT, PSS30S92E6-AG only)
● Fault signal ing : Corresponding to SC fault (N-side IGBT), UV fault (N-side supply) and OT fault
● Temperature output : Outputting LVIC temperature by analog signal (PSS30S92F6-AG only)
● Input interf ac e : 3, 5V line, Schmitt trigger receiver circuit (High Active)
● UL Recognized : UL1557 File E323585
INTERNAL CIRCUIT
V
UFB
(2)
V
VFB
(3)
V
WFB
(4)
W(21)
P
W
P
(7)
U
P
(5)
V
P1
(8)
IGBT1
IGBT2
IGBT3
Di1
Di2
Di3
V
NC
(9)
U
N
(10)
V
N
(11)
W
N
(12)
F
O
(14)
V
N1
(13)
V
NC
(16)
NW(18)
CIN(15)
IGBT4
IGBT5
IGBT6
Di4
Di5
Di6
NU(20)
NV(19)
LVIC
HVIC
V(22)
U(23)
P(24)
V
OT
(17)
·Built-in temperature output type: V
OT
(PSS**S92F6-AG)
·
Built-in OT type: NC (No Connectio n)
(PSS**S92
E
6-AG)
< Dual-In-Line Package Intelligent Power Module >
PSS30S92F6-AG, PSS30S92E6-AG
TRA NSFER MOLDING TYPE
INSULATED TYPE
Publication Date : December 2013
2
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
Parameter
Condition
Ratings
Unit
VCC
Supply voltage
Applied between P-NU,NV,NW
450
V
VCC(surge) Supply voltage (surge) Appli ed between P-NU,NV,NW 500 V
VCES Collector-emitter voltage 600 V
±IC Each IGBT collector current TC= 25°C 30 A
±ICP
Each IGBT collector current (peak)
TC= 25°C, less than 1ms
60
A
PC
Collector dissipation
TC= 25°C, per 1 chip
47.6
W
Tj
Junction temperature
(Note 1)
-30~+150
°C
Note1: T he maximum junction tem perature r ating of built-in power chips is 150°C(@Tc≤100°C).However, to ensure safe operation of DIPIPM, the average
junction temperature should be limited to Tj(Ave)≤125°C (@Tc≤100°C).
CONTROL (PROTECTION) PART
Symbol
Parameter
Condition
Ratings
Unit
V
D
Control supply voltage
Applied between
V
P1
-V
NC
, V
N1
-V
NC
20
V
VDB Control supply voltage Applied between
V
UFB-U, VVFB-V, VWFB-W 20 V
VIN Input voltage Applied between
U
P, VP, WP-VPC, UN, VN, WN-VNC -0.5~VD+0.5 V
VFO
Fault output supply voltage
Applied between
FO-VNC
-0.5~VD+0.5
V
IFO
Fault output current
Sink current at FO terminal
1
mA
VSC
Current sensing input voltage
Applied between CIN-VNC
-0.5~VD+0.5
V
TOTAL SYSTEM
Symbol
Parameter
Condition
Ratings
Unit
VCC(PROT)
Self protection supply voltage limit
(Short circuit protection capability)
V
D
= 13.5~16.5V, Inverter Part
Tj = 125°C, non-repetitive, less than 2μs
400 V
TC Module case operation temperature Measurem ent point of Tc is provided in Fig.1 -30~+100 °C
Tstg Storage temperature -40~+125 °C
Viso Isolation voltage
60Hz, Sinusoidal, AC 1min, between connected all pins
and heat sink plate
1500 Vrms
Fig. 1: TC ME ASU R EMENT POIN T
THERMAL RESISTANCE
Symbol Parameter Condition
Limits
Unit
Min.
Typ.
Max.
Rth(j-c)Q
Junction to case thermal
resistance (Note 2)
Inverter IGBT part (per 1/6 m odul e)
-
-
2.1
K/W
Rth(j-c)F
Inverter FWDi part (per 1/6 module)
-
-
3.0
K/W
Note 2: Grease with good t hermal c onductivit y and long -term endur ance sho uld be applied evenly with about +100μm~+200μm on the contacting surface of
DIPIPM a nd he at sink . The c ontact ing t hermal resis tance betwee n D IPIPM ca se and h eat s ink R th(c-f) i s dete rmine d b y the thick n ess and t he the rmal
conductivity of the applied grease. For referen ce, Rt h (c-f) is about 0.3K/W (per 1/6 module, grease thickness: 20μm, thermal conductivity: 1.0W/m•k).
Control terminals
DIPIPM
Tc point
IGBT chip position
Heat sink side
11.6mm
3mm
Power terminals
< Dual-In-Line Package Intelligent Power Module >
PSS30S92F6-AG, PSS30S92E6-AG
TRA NSFER MOLDING TYPE
INSULATED TYPE
Publication Date : December 2013
3
ELECTRICAL CHARACTERISTICS
(Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol Parameter Condition Limits Unit
Min.
Typ.
Max.
VCE(sat) Collector-emitter saturation
voltage VD=VDB = 15V, VIN= 5V
IC= 30A, Tj= 25°C
-
1.65
2.00
V
IC= 30A, Tj= 125°C
-
1.85
2.20
IC=3.0A, Tj= 25°C
-
0.90
1.10
VEC
FWDi forward voltage
VIN= 0V, -IC= 30A
-
2.30
2.80
V
ton
Switching times VCC= 300V, VD= VDB= 15V
IC= 30A, Tj= 125°C, VIN= 0↔5V
Inductive Load (upper-lower arm)
0.90 1.55 2.30 μs
tC(on) - 0.40 0.65 μs
toff
-
1.65
2.40
μs
tC(off)
-
0.15
0.30
μs
trr
-
0.30
-
μs
ICES Collector-emitter cut-off
current VCE=VCES
Tj= 25°C
-
-
1
mA
T
j
= 125°C
-
-
10
CONTROL (PROTECTION) PART
Symbol Parameter Condition
Limits
Unit
Min.
Typ.
Max.
ID Circuit current Total of VP1-VNC, VN1-VNC
VD=15V, VIN=0V
-
-
3.40
mA
VD=15V, VIN=5V - - 3.40
IDB Each part of VUFB-U,
VVFB-V, VWFB-W VD=VDB=15V, VIN=0V - - 0.30
VD=VDB=15V, VIN=5V
-
-
0.30
VSC(ref)
Short circuit trip level
VD = 15V
(Note 3)
0.455
0.480
0.505
V
UVDBt
P-side Control supply
under-voltage protection(UV ) Tj ≤125°C
Trip level
10.0
-
12.0
V
UVDBr
Reset level
10.5
-
12.5
V
UV
Dt
N-side Control supply
under-voltage protection(UV )
Trip level
10.3
-
12.5
V
UVDr Reset l evel 10.8 - 13.0 V
VOT Temperat ure Output
(PSS**S92F6-AG) (Note 4) Pull down R=5kΩ
LVIC Temperature=90
°
C
2.63 2.77 2.91 V
LVIC Temperature=25°C
0.88
1.13
1.39
V
OTt
Over temperature protect i on
(OT, PSS**S92E6-AG) (Note5)
VD = 15V
Trip level
100
120
140
°C
OTrh
Detect LVIC t emperature
Hysteresis of trip-reset
-
10
-
°C
VFOH
Fault output voltage
VSC = 0V, FO terminal pulled up to 5V by 10kΩ
4.9
-
-
V
VFOL VSC = 1V, IFO = 1mA - - 0.95 V
tFO Fault output pulse width (Note 6) 20 - - μs
IIN
Input current
VIN = 5V
0.70
1.00
1.50
mA
Vth(on)
ON threshold voltage
Applied between UP, VP, WP, UN, VN, WN-VNC
-
2.10
2.60
V
Vth(off)
OFF threshold voltage
0.80
1.30
-
Vth(hys)
ON/OFF threshol d
hysteresis voltage
0.35 0.65 -
VF Bootstrap Di forward voltage IF=10mA including voltage drop by limiting resistor (Note 7) 0.9 1.3 1.7 V
R
Built-in limiting resistance
Included in bootstrap Di
48
60
72
Ω
Note 3 : SC protection works only for N-si d e IGB T. Please select the external shunt resistance such that the SC trip-level is less than 1.7 times of the current rating.
Note 4 : DIPIPM don't shutdown IGBTs and output fault signal automatically when temperature rises excessively. When temperature exceeds the protective level that
user defined, controller (MCU) should stop the DIPIPM. Temperature of LVIC vs. VOT output characteristics is described in Fig. 3.
5 : When the LV IC t emperatur e exceeds OT trip tem perature le vel(OTt), OT protection wo rks and Fo outp uts. In that case if the h eat sink dropped off or fixed
loosely, don't reuse that DIPIPM. (There is a possibility that junction temperature of power chips exceeded maximum Tj(150°C).
6 : Fault sig nal Fo outputs when SC, UV or OT protect ion work s. Fo p ulse width i s different for each protecti on modes. At SC failure, Fo pul se width is a fixed
width (=minimum 20μs), but at UV or OT failure, Fo out pu ts continuously until recovering from UV or OT state. (But minimum Fo pulse width is 20μs.)
7 : The characteristics of bootstrap Di is described i n Fig. 2.
Fig. 2 Characteristics of bootstrap Di VF-IF curve (@Ta=25°C) including voltage drop by limiting resistor (Right chart is enlarged chart.)
0
40
80
120
160
200
240
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I
F
[mA]
V
F
[V]
0
10
20
30
40
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
I
F
[mA]
V
F
[V]
< Dual-In-Line Package Intelligent Power Module >
PSS30S92F6-AG, PSS30S92E6-AG
TRA NSFER MOLDING TYPE
INSULATED TYPE
Publication Date : December 2013
4
Fig. 3 Temperature of LVIC vs. VOT output charact eri sti cs
2.77
2.63
2.91
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
60 70 80 90 100 110 120
LVIC temperature (°C)
V
OT
output (V)_
Typ.
Max.
Min.
Fig. 4 VOT output circuit
(1) It is recommended to insert 5kΩ (5.1kΩ is recommended) pull down resis tor for getti ng linear output characteristics at low temperature
below room temperature. When the pull down resistor is inserted between VOT and VNC(control GND), the extra circuit current, which is
calculated approximately by VOT output voltage divided by pull down resistance, flows as LVIC circuit current continuously. In the case of
using VOT for detecting high temperature over room temperature on ly, it is unnecessary to insert the pull down resistor.
(2) In the case of using VOT with low voltage controller like 3.3V MCU, VOT output might exceed control supply voltage 3.3V when
temperature rises excessively. If system uses l ow voltage controller, it is recommended to insert a clamp Di between control supply of
the controller and VOT output for preventing over voltage destruction.
(3) In the case of not using VOT, leave VOT output NC (No Connection).
Refer the application not e for this series about the usage of VOT.
Ref
V
OT
Temperature
Signal
V
NC
Inside LVI C
of DIP IPM
MCU
5kΩ
< Dual-In-Line Package Intelligent Power Module >
PSS30S92F6-AG, PSS30S92E6-AG
TRA NSFER MOLDING TYPE
INSULATED TYPE
Publication Date : December 2013
5
MECHANICAL CHARACTERI S TICS AND RATINGS
Parameter Condition
Limits
Unit
Min.
Typ.
Max.
Mounting torque Mounting sc rew : M3 (Note 8) Recommended 0.69N·m 0.59 0.69 0.78 N·m
Terminal pulling strength
Control termi nal: Load 4.9N
Power terminal: Load 9.8N
EIAJ-ED-4701 10 - - s
Terminal bending strength
Control termi nal: Load 2.45N
Power terminal: Load 4.9N
90deg. bend
EIAJ-ED-4701 2 - - times
Weight - 8.5 - g
Heat-sink flatness
(Note 9)
-50
-
100
μm
Note 8: Plain washers (ISO 7089~7094) are recommended.
Note 9: Measurement point of heat sink flatness
RECOMMENDED OPERATION CONDITIONS
Symbol Parameter Condition
Limits
Unit
Min.
Typ.
Max.
VCC
Supply voltage
Applied between P-NU, NV, NW
0
300
400
V
VD
Control supply voltage
Applied between VP1-VNC, VN1-VNC
13.5
15.0
16.5
V
VDB Control supply voltage Applied bet ween VUFB-U, VVFB-V, VWFB-W 13.0 15.0 18.5 V
ΔVD, ΔVDB Control supply variation -1 - +1 V/μs
t
dead
Arm shoot-through blocking time
For each input signal
2.0
-
-
μs
fPWM
PWM input frequency
TC ≤ 100°C, Tj ≤ 125°C
-
-
20
kHz
IO Allowable r.m .s . c urrent VCC = 300V, VD = 15V, P.F = 0.8,
Sinusoidal PWM
TC ≤ 100°C, Tj ≤ 125°C
(Note10)
fPWM= 5k Hz - - 15.0 Arms
fPWM= 15kHz - - 10.0
PWIN(on)
Minimum input pulse width
(Note 11)
0.7
-
-
μs
PWIN(off)
200V≤V
CC
≤350V,
13.5V≤VD≤16.5V,
13.0V≤VDB≤18.5V,
-20°C≤Tc≤100°C,
N-line wiring inductance
less than 10nH (Note 12)
Below rated current 0.7 - -
Between rated current
and 1.7 times of rated
current 1.5 - -
VNC
VNC variation
Between VNC-NU, NV, NW (including surge)
-5.0
-
+5.0
V
Tj
Junction temperature
-20
-
+125
°C
Note 10: Allowable r.m.s. current depends on the actual application conditions.
11: DIPIPM might not make response if the input signal pulse width is less than PWIN(on).
12: IPM might make delayed response or no response for the input signal with off pulse width less than PWIN(off). Please refer below about delayed response.
Delayed Response against Shorter Input Off Signal than PWIN(off) (P-side only)
4.6mm
-
+
Heat sink side
Heat sink side
Measurement position
17.5mm
+
-
P Side Control Input
Internal IGBT Gate
Output Current Ic
t1
t2
Real line: off pulse width > PW IN(off); turn on time t1
Broken line: off pulse width
< PWIN(off); turn on time t2
(t1:Normal switching t
ime)
< Dual-In-Line Package Intelligent Power Module >
PSS30S92F6-AG, PSS30S92E6-AG
TRA NSFER MOLDING TYPE
INSULATED TYPE
Publication Date : December 2013
6
Fig. 5 Timing Charts of T he DIPIPM Protective Functions
[A] Short-Circuit Protection (N-side only with the external shunt resistor and RC filter)
a1. Normal operation: IGBT ON and outputs current.
a2. Short circuit current detecti on (SC tri gger)
(It is recommended to set RC time constant 1.5~2.0μs so that IGBT shut down within 2.0μs when SC.)
a3. Al l N -side IGBT's gates are hard interrupted.
a4. Al l N -side IGBTs turn OFF.
a5. FO outputs for tFo=mi nimum 20μs.
a6. Input = “L”: IG B T OFF
a7. Fo finishes output, but IGB Ts don't turn on until inputting next ON si gnal (LH).
(IGBT of each phase can return to normal state by inputting ON signal to each phase.)
a8. Normal operation: IGBT ON and outputs current.
[B] Under-Voltage Protection (N-side, UVD)
b1. Control supply voltage V D exceeds under voltage reset level (UVDr), but IGBT turns ON by next ON signal (LH).
(IGBT of e ach phase can return to normal state by inputting ON signal to each phase.)
b2. Normal operation: IGBT ON and outputs current.
b3. VD level drops to under voltage trip level. (UVDt).
b4. Al l N -side IGBTs t urn OFF in spite of control input condition.
b5. Fo outputs for tFo=minimum 20μs, but output is extended during VD keeps below UVDr.
b6. VD level reaches UVDr.
b7. Normal operation: IGBT ON and outputs current.
Lower-side cont rol
input
Protection circuit state
Internal IGBT gate
Output current Ic
Sense voltage of
the
shunt resistor
Error output Fo
SC
trip current level
a2
SET
RESET
SC
reference voltage
a1
a3
a6
a7
a4
a8
a5
D
elay by RC filtering
UVDr
RESET
SET
RESET
UV
Dt
b1
b2
b3
b4
b6
b7
b5
Control input
Protection circuit state
Control supply voltage V
D
Output current Ic
Error output Fo
< Dual-In-Line Package Intelligent Power Module >
PSS30S92F6-AG, PSS30S92E6-AG
TRA NSFER MOLDING TYPE
INSULATED TYPE
Publication Date : December 2013
7
[C] Under-Voltage Protection (P-s ide, UVDB)
c1. Control supply voltage VDB rises. After the voltage reaches under voltage reset level UVDBr, IGBT turns on by next ON signal (LH).
c2. Normal operation: IGBT ON and outputs current.
c3. VDB level drops to under voltage trip level (UVDBt).
c 4. IG BT of the correspond phase only turns OFF in spite of control input signal level, but there is no FO signal output.
c5. VDB level reaches UVDBr.
c6. Normal operation: IGBT ON and outputs current.
[D] Over Temperatur e Protection (N-side, Detecting LVIC temperature)
d1. Normal operation: IGBT ON and outputs current.
d2. LVIC temperature exceeds over temperat ure trip l evel(OTt).
d3. All N-side IGBTs turn OFF in spite of control input condition.
d4. Fo outputs for tFo=minimum 20μs, but output is extended during LVIC temperature keeps over OTt.
d5. LVIC temperature drops to over temperature reset level.
d6. Normal operation: IGBT turns on by next ON signal (LH).
(IGBT o f each phase can return to normal state by inputting ON signal to each phase.)
SET
RESET
OT
t
d1
d2
d3
d5
d6
d4
OT
t
- OT
rh
Control input
Protection circuit state
Temperat ure of LVIC
Output current Ic
Error output Fo
Control input
Protection circuit state
Control supply voltage V
DB
Output current Ic
Error output Fo
UV
DBr
RESET
SET
RESET
UV
DBt
Keep High-level (no fault output)
c1
c2
c3
c4
c5
c6
< Dual-In-Line Package Intelligent Power Module >
PSS30S92F6-AG, PSS30S92E6-AG
TRA NSFER MOLDING TYPE
INSULATED TYPE
Publication Date : December 2013
8
Fig. 6 Example of Applic ation Circuit
(1) If contr ol GND is c onnected with power GND by common broad pattern, it may cause malfunction by power GND f luctuation.
It is recommended to connect control GND and pow er GND at only a point N1 (near the terminal of s hunt resistor).
(2) It is rec om mended to insert a Zener diode D1(24V/1W) between each pair of contr ol supply t erminals to prevent surge dest ruction.
(3) To pr event surge destructi on, the wiri ng between the smoothing capacitor and the P, N1 terminals should be as short as possi ble.
Generally a 0.1-0.22μF snubber capacitor C3 between the P-N 1 term inals i s recommended.
(4) R1, C4 of RC filter for preventing protection circuit malfunction is recommended to select tight tolerance, temp-compensated type.
The time constant R1C4 should be set so that SC current is shut down within 2μs. (1.5μs~2μs is general value.) SC interrupting time
might vary with t he w iring pattern, so the enough evaluation on the real system is necessary.
(5) To pr event malfuncti on, the wiring of A, B, C should be as short as possible.
(6) The point D at whi c h the wi r ing to CI N fi l ter i s divi ded s hould be near t he terminal of shunt res i stor. NU, NV, NW ter minal s should be
connected at near NU, NV, NW terminals.
(7) All capaci tors shoul d be mounte d as clos e to the termi nals as possible. (C1: good temper ature, frequenc y characteristic electrolytic
type and C2:0.22μ-2μF, good tem perature, frequenc y and DC bi as characteristic cer am ic type are recommended.)
(8) Input drive is High-active type. There is a minimum 3.3kΩ pull-down resistor in the input circuit of IC. To prevent malfunction, the
wiring of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on
and turn-off threshold voltage.
(9) Fo output is open drain type. It should be pul led up to MC U or control power supply ( e.g. 5V,15V) by a resist or that makes IFo up to
1mA. (IFO is estimated roughly by the formula of control power supply voltage divided by pull-up resistance. In the case of pulled up to
5V, 10kΩ (5kΩ or more) is recommended.)
(10) Thanks to built-in H V IC, direct coupling to MC U w ithout any opto-coupler or transformer isolation is possibl e.
(11) Two V NC t erminals (9 & 16 pin) are c onnected ins ide DIPIPM , please connec t either one to the 15V power s upply GND outs ide and
leave another one open.
(12) If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous operation.
To avoid such probl em , line r ipple voltag e should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p.
(13) For D IPIPM, it isn't recommended to drive sam e load by parallel connection wit h other phase IGBT or other DIPIPM.
D1
+
+
MCU
C2
15V VD
M
C4
R1
Shunt
resistor
N1
B
C
5V
A
C2
V
UFB
(2)
V
VFB
(3)
V
WFB
(4)
+
U
N
(10)
V
N
(11)
W
N
(12)
Fo(14)
V
N1
(13)
V
NC
(16)
P(24)
U(23)
W(21)
LVIC
V(22)
V
P
(6)
W
P
(7)
U
P
(5)
V
P1
(8)
CIN(15)
IGBT1
IGBT2
IGBT3
Di1
Di2
Di3
C1
C1
C2
+
D
D1
V
NC
(9)
C3
HVIC
NW(18)
IGBT4
IGBT5
IGBT6
Di4
Di5
Di6
NU(20)
NV(19)
Power GND wiring
Control GND wiring
V
OT
(17)
5kΩ
Long GND wiring here might
generate noise to input signal and
cause IGBT malfunction.
Long wiring here might cause SC
level fluctuation and malfunction.
Long wiring here might
cause short circuit fail ure
Bootstrap negat i ve electrodes
should be connected to U,V,W
terminals direct l y and separated
from the main output wires
Built-in temperature
output type only
(PSS**S92F6-AG)
+
< Dual-In-Line Package Intelligent Power Module >
PSS30S92F6-AG, PSS30S92E6-AG
TRA NSFER MOLDING TYPE
INSULATED TYPE
Publication Date : December 2013
9
Fig. 7 MCU I/O Interface Circuit
Fig. 8 Pattern Wiring Around the Shunt Resistor
Fig. 9 Pattern Wiring Around the Shunt Resistor (for the case of open emitter)
When DIPIPM is operated with three shunt resistors, voltage of each shunt resistor cannot be input to CIN terminal directly. In that case, it is necessary to use
the exter nal pr otection circ ui t as below.
(1) It is necessary to set the time constant RfCf of external comparator input so that IGBT stops within 2μs when short circuit occurs.
SC interrupting time might vary with the wiring pattern, comparator speed and so on.
(2) It is recommended for the threshold voltage Vref to set to the same rating of short circuit trip level (Vsc(ref): typ. 0.48V).
(3) Select t he exter nal shu nt resi s tance so that SC trip-level is less than sp eci fie d v alue (=1.7 times of rating current).
(4) To avoid malfunction, the wiring A, B, C should be as short as possible.
(5) The point D at which the wiring to comparator is divided should be close to the terminal of shunt resistor.
(6) OR output high level when prote c tio n w ork s should be over 0.505V (= maximum Vsc(ref) rating).
UP,VP,WP,UN,VN,WN
Fo
VNC(Logic)
DIPIPM
MCU
10kΩ
5V line
3.3kΩ(min)
Note)
Design fo r input RC filter depe nds on PWM control sch eme used
in the applicati on and wiring impedance of the printed circuit board.
DIPIPM input signal interface integrates a minimum 3.3kΩ
pull-down resistor. Therefore, when inserting RC filter, it is
necessary to satisfy turn-on threshold voltage requir em en t.
Fo output is open drain type. It should be pulled up to control
power supply (e.g. 5V, 15V) with a resistor that makes Fo sink
current IFo 1mA or less. In the case of pulled up to 5V supply, 10kΩ
（5kΩ or more） is recommended.
Wiring Inductance should be less than 10nH.
Inductance of a copper pattern with
length=17mm, width=3mm is about 10nH.
NU, NV, NW should be connected
each other at near terminals.
N1
V
NC
NU
NV
NW
DIPIPM
V
NC
GND wiring fro m V
NC
should
be
connected close to the
terminal of shunt res istor.
Shunt
resistor
DIPIPM
NU
NV
NW
N1
Low inductance shunt resistor like surface mounted (SMD) type is recommended.
GND wiring fro m V
NC
should
be
connected close to the
terminal of shunt res istor.
Shunt
resistors
Each wiring Inductance should be less than 10nH.
Inductance of a copper pattern with
length=17mm, width=3mm is about 10nH.
P
V
U
W
N-side IGBT
P-side IGBT
Drive circuit
DIPIPM
VNC
NW
Drive circuit
CIN
NV
NU
-
Vref
+
Vref
Vref
Comparators
(Op
en collector output type)
External protection circuit
Protection circuit
Shunt
resistors
Rf
Cf
5V
B
A
C
OR output
D
N1
-
+
-
+
< Dual-In-Line Package Intelligent Power Module >
PSS30S92F6-AG, PSS30S92E6-AG
TRA NSFER MOLDING TYPE
INSULATED TYPE
Publication Date : December 2013
10
Fig. 10 Package Outlines
PSS**S92F6-AG, PSS**S9 2E6-AG Dimensions in mm
1) 9 & 16 pins (VNC) are connected inside DIPIPM, please connect either one to the control power supply GND outside and leave another one open.
2) No.17 is VOT for built-in temperat ure out put fu nc tio n type (PSS**S92F6-AG) and NC (No Connection) for built-in OT protection function type (PSS**S92E6-AG).
QR Code is registered trademark of DENSO WAVE INCORPORATED in JAPAN and other countries.
TERMINAL CODE
1-A
NC(VNC)
1-B
NC(VP1)
2
VUFB
3
VVFB
4
VWFB
5
UP
6
VP
7
WP
8
VP1
9
VNC *1
10
UN
11
VN
12
WN
13
VN1
14
Fo
15
CIN
16
VNC *1
17
NC / VOT *2
18
NW
19
NV
20
NU
21
W
22
V
23
U
24
P
25
NC
< Dual-In-Line Package Intelligent Power Module >
PSS30S92F6-AG, PSS30S92E6-AG
TRA NSFER MOLDING TYPE
INSULATED TYPE
Publication Date : December 2013
11
Revision Record
Rev. Date Page Revised contents
1
12/25/2013
-
New
< Dual-In-Line Package Intelligent Power Module >
PSS30S92F6-AG, PSS30S92E6-AG
TRA NSFER MOLDING TYPE
INSULATED TYPE
Publication Date : December 2013
12
© 2013 MITSUBISHI ELECTRIC CORPORATION. ALL RIGHTS RESERVED.
DIPIPM and CSTBT are registered trademarks of MITSUBISHI ELECTRIC CORPORAT ION.
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