CML Semiconductor Products 4-Level FSK Modem Data Pump FX91 9A D/919A/2 January 1996 1.0 Features Advance Information e 4-Level FSK Modulation Flexible Operating Modes Half Duplex, 4800 to 19.2k bits/sec Host Processor Interface * Full Data Packet Framing Low Power 3.3V/5V Operation 24-Pin Small Form Package Option RADIO FX91 9A HOST pC ANALOGUE Tx DATA AND MODULATOR #4 CONTROL ; ~~ BUS SYSTEM E + ___ > ANALOGUE Rx PROCESSING BISCRIMINATOR PUMP 11 Brief Description The FX919A is a CMOS integrated circuit that contains all of the baseband signal processing and Medium Access Control (MAC) protocol functions required for a high performance 4-level FSK Wireless Packet Data Modem. It interfaces with the modem host processor and the radio modulation/demodulation circuits to deliver reliable two-way transfer of the application data over the wireless link. The FX919A assembles application data received from the processor, adds forward error correction (FEC) and error detection (CRC) information and interleaves the result for burst-error protection. After adding symbol and frame sync codewords, it converts the packet into filtered 4-level analogue signals for modulating the radio transmitter. In receive made, the FX919A performs the reverse function using the analogue signals from the receiver discriminator. After error correction and removal of the packet overhead, the recovered application data is supplied to the processor. Any residual uncorrected errors in the data will be flagged. A readout of the SNR value during receipt of a packet is also provided. The FX919A uses data block sizes and FEC/CRC suitable for applications which require the high-speed transfer of data over narrow-band wireless links. The device is programmable to operate at most standard bit-rates from a wide choice of Xtal/clock frequencies. 8.87 M@ 2374376 OOf810b5 OTs4-Level FSK Modem Data Pump FX919A CONTENTS Section Page 1.0 Features oo... ceeeeeeeeeseeneeesesessetereseeenseeststieressesecsasesssessaeseaseneeeesseooes 8.87 1.1 Brief DeSCrption ee esses etecseeneeeeeneennessertessseeenneseessenneneassees 8.87 1.2 Block Diagram... 1.3 Signal List... eeeeeeseeceeeeeeeeeceteeeeeesaneaceeseaasoesaeseesaeeenmaneaseesenenagee 8.90 1.4 External Component... ce ecsesreressececcenersrsesscesceseeensenesssasseseeeseseeenenes 8.92 1.5 General Description oo... ccesceeceesesesesrecceeceeseneeeeeeeesanecaerssaceaseenseeceneenes 8.93 1.5.1 Description of Blocks....... -- 8.93 1.5.2 Modem - uC Interaction... . 8.96 1.5.3 Binary to Symbol Translation . .. 8.97 1.5.4 Frame Structure ....cccccccsssessecsecsssscssesesseesesessserssenessessenessees 8.98 1.5.5 The Programme's ViCW....cccccccsseccsssstssesereseereenrsiseseserstees 8.99 1.5.5.1 Data Block Buffer....... 1.5.5.2 Command Register .... 1.5.5.3 Control Register......... 1.5.5.4 Mode Register... eee 1.5.5.5 Status Register... ee 1.5.5.6 Data Quality Register... 1.5.6 CRC, FEC, and interleaving... cccsscssssssseccssnsreseresssaeaee 8.113 1.6 Application Notes -....00.....ccccccccssseeesseeeeeeceetaecessesesereeessssseesnessesenreeisenes 8.115 1.6.1 Transmit Frame Example... 1.6.2 Receive Frame Example... cc cecescscecserseeeseessesseeeeneesees . 1.6.3 Clock Extraction and Level Measurement Systems 8.116 1.6.4 AC Coupling............. 8.118 1.6.5 Radio Performance... eeesesesessessesesescesessesscsseseesseneeseeeees 8.119 1.7 Performance Specification 0.00.0... eee eee reeeeceeseeenesseenesseneeenensenees 8.1214 1.7.1 Electrical Performance 1.7.2 Packaging.............0.. Note: As this product is still in development, it is likely that a number of changes and additions will be made to this specification. Items marked TBD or left blank will be included in later issues. 8.88 ME 237437b 00010bb T30 mmFX919A 4-Level FSK Modem Data Pump Block Diagram 1.2 SS SSa Jayng Ndyno x1, x, dOXt L o Svia xy A SYadINg ONY yOLVYTTIOSO aka H90T19 XL zood No ocatie,, << NOILOWYLXS |] uy xe A MOO TOISAS Xe OY duny ynduy xy 10a [" sraquidAg xe , S|OQWAS XL LO3.LIq SNAS SAVATYS.LNI-AG awveg faa Tas LNI | aaooaa any {$< REGOONS $9auday}e YaNOSHO PYOLWHSNS9 ;_$-- 4 I Oud , > wagging , wood viva 4 <____--> suadane yy, yaisigay waisiogy walsiogy viva [oo JOXLNOD 3qoN CNYWWOD > $$ > fe ie Ur gi HaLSIOgy wALSIOZY ALMWnO yING SNLV1S MOOTDNVLK "| ! | S39OVAYSLNI YaTIONLNOOW Figure 1 Block Diagram 8.89 MB 2374376 OOO10b7 1774-Level FSK Modem Data Pump FX919A 1.3 Signal! List Package . wae D2/D5 Signal Description Pin No. Name Type 1 IRON O/P A 'wire-ORable output for connection to the host LLC's Interrupt Request input. This output has a low impedance pull down to Vgs when active and is high impedance when inactive. 2 D7 BI ) 3 D6 BI ) 4 DS Bl ) 5 D4 Bl ) 8-bit bidirectional 3-state uC interface data 6 D3 BI ) lines. 7 D2 BI ) 8 D1 Bi ) 9 DO Bi ) 10 RDN VP Read. An active low logic level input used to , control the reading of data from the modem into ! the host pc. WW WRN VP Write. An active low logic level input used to control the writing of data into the modem from the host pC. 12 Vss Power The negative supply rail (ground). 13 CSN VP Chip Select. An active low logic level input to the modem, used to enable a data read or write operation. 14 AO VP ) Two logic level modem register select 15 Al UP ) inputs. 16 XTALN O/P The output of the on-chip oscillator. 17 XTAL/CLOCK VP The input to the on-chip oscillator, for externa! Xtal circuit or clock. 18 DOC 2 O/P ) Connections to the Rx level measurement 19 DOC 1 O/P ) circuitry. A capacitor should be connected ) from each pin to Vss. 8.90 Mf 23743576 GOOl0bS 6034-Level FSK Modem Data Pump FX919A Package : aa D2/D5 Signal Description Pin No. Name Type 20 TXOP O/P The Tx signal output from the modem. 21 VBIAS O/P A bias line for the internal circuitry, held at 2 Vpp. This pin must be decoupled to Vgs by a capacitor mounted close to the device pins. 22 RXIN VP The input to the Rx input amplifier. 23 RXFB O/P The output of the Rx input amplifier and the input to the Rx RRC filter. 24 Vop Power The positive supply rail. Levels and voltages are dependent upon this supply. This pin should be decoupled to Vgs by a capacitor. Notes: I/P = Input O/P = Output BI =~ Bidirectional 8.91 Me 2374376 OOOL0b9 7474-Level FSK Modem Data Pump FX919A 1.4 . Ri R2 R3 R4 Note 1: Note 2: Note 3: External Components Voo == TT C1 cs - ~~ Yoo FROM Rx FM [ my 24 DISCRIMINATOR py <____}72 23] Ww pe <> 3 22}eB ig D5 <>] 4 aq} Vaws & D4 <____ 5 20 L-TXOP. > E ps slp FX919A | Doct Tom - D2/D poc2 FREQUENCY D2 <____~-_>]17 18 eaglooK 7 i D1 <_____>8 17 be XTAUCL | XTAUICLOCK | MODULATOR a 2 op if REAM Tox Jos os [os & RON 10 15k S WRN 11 44}e A pret Vsg g yi 'p7|_ XTALICLOCK i = CSN 12 13 ' : | AO Ves[ | xi cal At T ' 1 | We R3 | C4 | v~| XTALN ' ' Ves_! Figure 2 Recommended External Components See Section 1.5.1 C1 0.1 pF + 20% C5 + 5%, see Note 3 100k ohm + 5% C2 0.1 pF + 20% C6 + 20%, see Note 2 1M ohm + 20% C3 + 20%, see Note 1 C7 + 20%, see Note 2 100k ohm + 5% C4 + 20%, see Note 1 c8 + 5%, see Note 3 See Section 1.5.5.3 The values used for C3 and C4 should be suitable for the frequency of the crystal X1. Asa guide, values (including stray capacitances) of 33pF at 1MHz falling to 18pF at 10MHz will generally prove suitable. C6 and C7 values (in nano Farads) should be equal to 50000 + symbol_rate, e.g. Rate C/C7 4800 10.0 9600 4.7 C5 and C8 values (in pico Farads) should be equal to 750000 + symbol rate, e.g. Rate C5/C8 2400 330 4800 1 9600 8.92 Mm 237437b 0001070 4b)4-Level FSK Modem Data Pump FX919A 1.5 General Description 1.5.1 Description of Blocks Data Bus Buffers Eight bidirectional 3-state logic level buffers between the modem's internal registers and the host yC's data bus lines. Address and R/W Decode This block controls the transfer of data bytes between the wC and the modem's internal registers, according to the state of the Write and Read Enable inputs (WRN and RDN), the Chip Select input (CSN) and the Register Address inputs AO and A1. The Data Bus Buffers, Address and R/W Decode blocks provide a byte-wide parallel pC interface, which can be memory-mapped, as shown in Figure 3. uC Data Bus bo bo D1 D1 D2 D2 D3 D3 D4 D4 DS D5 D D6 D7 D7 WRN WRN HCONTROLLER RDN 7 RDN MODEM bp IRQN puil up IRON resistor < other IRON inputa| IRQN + fo wController AO AO Al Al Madem An : | Address CSN yC Address Bus Decode Figure 3 Typical Modem pC Connections Status and Data Quality Registers Eight-bit registers which the uC can read to determine the status of the modem and the received data quality. Command, Mode and Control Registers The values written by the LC to these 8-bit registers control the operation of the modem. Data Buffer A 12-byte buffer used to hold receive or transmit data to or from the pC. CRC Generator/Checker A circuit which generates (in transmit mode) or checks (in receive mode) the Cyclic Redundancy Checksum bits, which may be included in transmitted data blocks so that the receive modem can detect transmission errors. 8.93 Me 237437b 0001071 3T44-Level FSK Modem Data Pump FX919A FEC Generator/Checker In transmit mode, this circuit adds Forward Error Correction bits to the transmitted data, then converts the resulting binary data to 4-level symbols. In receive mode, it translates received 4-level symbols to binary data, using the FEC information to correct a large proportion of transmission errors. Interleave/De-interieave Buffer This circuit interleaves data symbols within a block before transmission and de-interleaves the received data so that the FEC system is best able to handle short noise bursts or fades. Frame Sync Detect This circuit, which is only active in receive mode, is used to look for the 24-symbol Frame Synchronisation pattern which is transmitted to mark the start of every frame. Rx VP Amp This amplifier allows the received signal input to the modem to be set to the optimum level by suitable selection of the external components R1 and R2. The value of R1 should be calculated to give 0.2 x Von pk-pk at the RXFB pin for a received '...43 +3 -3 -3 ... sequence. A capacitor may be fitted in series with R1 if ac coupling of the received signal is desired (see Section 1.6.4), otherwise the dc level of the received signal should be adjusted so that the signal at the modem's RXFB pin is centred around Vpias (% Vpp). RRC Low Pass Filter This filter, which is used in both transmit and receive modes, is a linear-phase lowpass filter with a Root Raised Cosine frequency response defined by: I Hf) =1 for 0 <= f < (1-bV(2T) , | = square root of {0.5 [1 - sin(n T (f - 0.5/T)/b)}} for (1-b)(2T) <= f <= (1+b)/(2T) =0 for (1+b)(2T) < f where b = 0.2, T = 1/symbol rate This frequency response is illustrated in Figure 5. In transmit mode, the 4-level symbols are passed through this filter to eliminate the high frequency components which would otherwise cause interference into adjacent radio channels. +3 +1 S\/ Bit 1 3 pairs ; pats 1 ' Data ) binary - Symbols Transmit ' |_| Frequency it encoding | symbol _ filter t | modulator Pee enw ewes ' boc eee eee eee eee Modem .____________-____- } Figure 4 Translation of Binary Data to Filtered 4-Level Symbols in Tx Mode 8.94 Me 2374376 0001072 2344-Level FSK Modem Data Pump FX9194 In receive mode, the filter is used to reject HF noise and to equalise the received signal to a form suitable for extracting the 4-level symbols. Tx Output Buffer This is a unity gain amplifier used in transmit mode to buffer the output of the Tx low pass filter. In receive mode, the input of this buffer is connected to Vaiag unless the RXEYE bit of the Control Register is '1', when it is connected to the received signal. When changing from Rx to Tx mode the input to this buffer will be connected to Vajas for 8 symbol times while the RRC filter settles. Note: The RC low pass filter formed by the external components R4 and C5 between the TXOP pin and the input to the radio's frequency modulator forms an important part of the transmit signal filtering. These components may form part of any de level-shifting and gain adjustment circuitry. The value used for C5 should take into account stray circuit capacitances, and its ground connection should be positioned to give maximum attenuation of high frequency noise into the modulator. The signal at the TXOP pin is centred around Vgjag and is approx 0.2 x Vopp pk-pk for a continuous '+3 +3 -3 -3...' pattern. A capacitor may be fitted in series with the input to the frequency modulator if ac coupling is desired, see Section 1.6.4. -30 + + + 0 0.2 0.4 0.6 0.8 1 Frequency / Symbol rate Figure 5 RRC Filter Frequency Response (including the external RC filter R4/C5) 8.95 MH 2374376 0001073 1704-Level FSK Modem Data Pump FX919A Figure 6 Transmitted Signal Eye Diagram Rx Level/Clock Extraction These circuits, which operate only in receive mode, derive a symbol rate clock from the received signal and measure the received signal amplitude and dc offset. This information is then used to extract the received 4-level symbols and also to provide an input to the received Data Quality measuring circuit. The external capacitors C6 and C7 form part of the received signal level measuring circuit. Clock Oscillator and Dividers These circuits derive the transmit symbol rate (and the nominal receive symbol rate) by frequency division of a reference frequency which may be generated by the on-chip Xtal oscillator or applied from an external source. Note: If the on-chip xtal oscillator is to be used, then the external components X1, C3, C4 and R3 are required. If an external clock source is to be used, then it should be connected to the XTAL/CLOCK input pin, the XTALN pin should be left unconnected, and X1, C3, C4 and R3 not fitted. 1.5.2 Modem - pC Interaction In general, data is transmitted over-air in the form of messages, or Frames, consisting of a Frame Preamble followed by one or more formatted data blocks. The Frame Preamble includes a Frame Synchronisation pattern designed to allow the receiving modem to identify the start of a frame. The following data blocks are constructed from the 'raw data using a combination of CRC (cyclic redundancy checksum) generation, Forward Error Correction coding and Interleaving. Details of the message formats handled by the modem are given in Section 1.5.3 and Figures 7 and 7a. To reduce the processing load on the associated pC, the FX919A modem has been designed to perform as much as possible of the computationally intensive work involved in Frame formatting and de-formatting and - when in receive mode - in searching for and synchronising onto the Frame Preamble. In normal operation the modem will only require servicing by the pC once per received or transmitted block. Thus, to transmit a biock, the controlling LC has only to load the - unformatted - raw binary data into the modem's Data Block Buffer then instruct the modem to format and transmit that data. The modem will then calculate and add the CRC bits as required, encode the result as 4-level symbols (with Forward Error Correction coding) and interleave the symbols before transmission. 8.96 mH 2374376 0001074 O074-Level FSK Modem Data Pump FX919A In receive mode, the modem can be instructed to assemble a block's worth of received symbols, de- interleave the symbols, translate them to binary - using the FEC coding to correct as many errors as possible - and check the resulting CRC before placing the received binary data into the Data Block Buffer for the pC to read. The modem can also handle the transmission and reception of un-formatted data - to allow for example the transmission of Symbol and Frame Synchronisation sequences or special test patterns. 1.5.3 Binary to Symbol Translation Although the over-air signal, and hence the signals at the modem TXOP and RXIN pins, consists of 4- level symbols, the raw data passing between the modem and the uC is in binary form. Translation between binary data and the 4-level symbols is done in one of two ways, depending on the task being performed. Direct: the simplest form, which converts between 2 binary bits and a single symbol. ms bit Is bit 3 1 1 +1 1 0 -1 0 3 1 This is expanded so that an 8-bit byte translates to four symbols for the T4S, T24S and R4S tasks described in Section 1.5.5.2. msb Isb Bits: 7 | 6 5 | 4 3 | 2 1 | 0 Symbols: a b Cc d sent first sent last With FEC: This is more complicated, but essentially translates groups of 3 binary bits to pairs of 4-level symbols using a Forward Error Correcting coding scheme for the block oriented tasks THB, TIB, TLB, RHB and RILB described in Section 1.5.5.2. 8.97 MB 2374376 O601075 Tus4-Level FSK Modem Data Pump FX919A 1.5.4 Frame Structure Figure 7 below shows how an over-air message frame may be constructed from Frame and Symbol Sync pattems, followed by one or more Header, Intermediate or Last blocks. Header Block Intermediate Blocks Last Block 2 dab a als ale ab % Ja) ba lade lad lab ae tl dad? J eels ea Sah Sh Sas) bat 2 Byte 0 mei $f ore? 4 + 4 + 4 Bred gg = + 4 - 4 Bred gg Data Bytes $ Data Bytes 4 - Data Bytes 4 wes gf Yt + @ 4 Byte 7 , 1 , ft Byte 8 q Bred q , 7 [ CRC2 a Byte 10 7 (4 bytes) | Byte t1 q FEC TRELLIS CODING / DECODING ( ERROR CORRECTION ) ded CQ abot Oo} 2 gaan INTERLEAVING / DE-INTERLEAVING Over-air SYMBOL | FRAME a eee signal . [re ye | BLOCK / INTERMEDIATE BLOCKS (symbols) oeeees 4 66 66 - 2 66 FRAME > PREAMBLE FRAME Frame Sync: af fale [4 [a [3 ls [3 [fs [3 fs fe Cr fe [a7 fe Te [1 73 Js J sent first last Symbol Syne : at least 24 symbols of '..+3 +3 -3 -3...." sequence Figure 7 Over Air Signal Format The 'Header' block is self-contained in that it includes its own checksum (CRC1), and would normally carry information such as the addresses of the called and calling parties, the number of following blocks in the frame (if any) and miscellaneous control information. The Intermediate block(s) contain only data, the checksum for all of the data in the Intermediate and Last blocks (CRC2) being contained at the end of the Last block. 8.98 ME 2374376 OOOL07L 1874-Level FSK Modem Data Pump FX919A This arrangement, whilst efficient in terms of data capacity, may not be optimum for poor signal-to-noise conditions, since a reception error in any one of the Intermediate or Last blocks would invalidate the whole frame. in these conditions, increased throughput may be obtained by using the 'Header block format for all blocks of the frame, so that blocks which are received correctly can be identified as such, and need not be re-transmitted. This, and some other possible frame structures, are shown in Figure 7a below. A A. [SYMBOL] FRAME - | SYNC | SYNC HEADER BLOCKS | B /symMBoL] FRAME eT [ SYNG SYNC INTERMEDIATE BLOCKS Ast | .. c [syMBoL] FRAME - C | SYNC SYNC | INTERMEDIATE BLOCKS i Figure 7a Some Alternative Frame Structures The FX919A performs all of the black formatting and de-formatting, the binary data transferred between the modem and its nC being that enclosed by the thick dashed rectangles near the top of Figure 7. 1.5.5 The Programmer's View The modem appears to the programmer as 4 write only 8-bit registers shadowed by 3 read only registers, individual registers being selected by the AO and A1 chip inputs: Ai | AO Write to Modem Read from Modem 0 0 Data Buffer Data Buffer 0 1 Command Register Status Register 1 0 Control Register Data Quality Register 1 1 Mode Register not used Note that there is a minimum allowable time between accesses of the modem's registers, see Section 1.7.1 for details. 1.5.5.1. Data Block Buffer This is a 12-byte read/write buffer which is used to transfer data (as opposed to command, status, mode, data quality or control information) between the modem and the host uC. It appears to the UC as a single 8-bit register; the modem ensuring that sequential pC reads or writes to the buffer are routed to the correct locations within the buffer. The pC should only access this buffer when the Status Register BFREE (Buffer Free) bit is 1. The buffer should only be written to while in Tx mode and read from while in Rx mode. Note that in receive mode the modem will function correctly even if the received data is not read from the Data Buffer by the pc. 8.99 MB 2374376 0001077 Babb =4-Level FSK Modem Data Pump FX919A 1.5.5.2 Command Register Writing to this register tells the modem to perform a specific action or actions, depending on the setting of the TASK, AQLEV and AQSC bits. Command Register f7Te[Ts[4[3]{2]1] 0 | ' \ : Yn ; / AQSC | reserved, TASK AQLEV set to 00 0' When it has no action to perform, the modem will be in an idle' state. If the modem is in transmit mode the input to the Tx RRC filter will be connected to Vaias. In receive mode the madem will continue to measure the received data quality and extract symbols from the received signal, supplying them to the de-interleave buffer, but will otherwise ignore the received data. Command Register B7: AQSC - Acquire Symbol Clock This bit has no effect in transmit mode. In receive mode, whenever a byte with the AQSC bit set to '1' is written to the Command Register, and TASK is not set to RESET, it initiates an automatic sequence designed to achieve symbol timing synchronisation with the received signal as quickly as possible. This involves setting the Phase Locked Loop of the received bit timing extraction circuits to its widest bandwidth, then gradually reducing the bandwidth as timing synchronisation is achieved, until it reaches the normal! value set by the PLLBW bits of the Control Register. Setting this bit to '0' (or changing it from 1' to '0') has no effect, however note that the acquisition sequence will be re-started every time that a byte written to the Command Register has the AQSC bit set to'1'. The AQSC bit will normally be set at the same time as a SFS (Search for Frame Sync) or SFSH (Search for Frame Sync plus Header block) task is written to the FX919A, however it may also be used independently to re-establish clock synchronisation quickly after a long fade. Alternatively, a SFS or SFSH task may be written to the Command Register with the AQSC bit at 'O' if it is known that clock synchronisation does not need to be re-established. Command Register B6: AQLEV - Acquire Receive Signal Levels This bit has no effect in transmit mode. In receive mode, whenever a byte with the AQLEV bit set to 1 is written to the Command Register and TASK is not set to RESET, it initiates an automatic sequence designed to measure the amplitude and de offset of the received signal as rapidly as possible. This sequence involves setting the measurement circuits to respond quickly at first, then gradually increasing their response time, hence improving the measurement accuracy, until the normal value set by the LEVRES bits of the Control Register is reached. Setting this bit to 0' (or changing it from 1 to '0') has no effect, however note that the acquisition sequence will be re-started every time that a byte written to the Command Register has the AQLEV bit set tol. 8.100 MB 2374376 0001078 754-Level FSK Modem Data Pump FX919A The AQLEV bit will normally be set at the same time as a SFS (Search for Frame Sync) or SFSH (Search for Frame Sync plus Header Block) task is initiated, however it may also be used independently to re- establish signal levels quickly after a long fade. Alternatively, a SFS or SFSH task may be written to the Command Register with the AQLEV bit at '0' if it is known that there is no need to re-establish the received signal levels. Command Register B5, B4, B3 These bits should be set to '0'. Command Register B2, B1, BO: TASK Operations such as transmitting or receiving a data block are treated by the modem as tasks and are initiated when the UC writes a byte to the Command Register with the TASK bits set to anything other than the 'NULL' code. The pC should not write a task (other than NULL or RESET) to the Command Register or write to or read from the Data Buffer when the BFREE (Buffer Free) bit of the Status Register is 0. Different tasks apply in receive and transmit modes. When the modem is in transmit mode, all tasks other than NULL or RESET instruct the modem to transmit data from the Data Buffer, formatting it as required. The pC should therefore wait until the BEREE (Buffer Free) bit of the Status Register is '1', before writing the data to the Data Block Buffer, then it should write the desired task to the Command Register. If more than 1 byte needs to be written to the Data Block Buffer, byte number 0 of the block should be written first. Once the byte containing the desired task has been written to the Command Register, the modem will: Set the BFREE (Buffer Free) bit of the Status Register to '0'. Take the data from the Data Block Buffer as quickly as it can - transferring it to the Interleave Buffer for eventual transmission. This operation will start immediately if the modem is idle (i.e. not transmitting data from a previous task), otherwise it will be delayed until there is sufficient room in the Interleave Buffer. Once all of the data has been transferred from the Data Block Buffer the modem will set the BFREE and IRQ bits of the Status Register to '1', (causing the chip IRQN output to go low if the IRQNEN bit of the Mode Register has been set to '1') to tell the uC that it may write new data and the next task to the modem. This lets the pC write a task and the associated data to the modem while the modem is still transmitting the data from the previous task. Task | Task 2 Data from uC to Block Buffer = = Task from yC to Command Register 7 5 Vv Vv BFREE bit of Status Register t J l J v v IRQ bit of Status Register J J IRQN ofp (IRQNEN ='1') 1 l Sse@eaeue & a TXOP signal | from task | | from task 2 Benue wm ese a a Figure 8 Transmit Task Overlapping 8.101 MH 2374376 0001079 994-Level FSK Modem Data Pump FX919A When the modem is in receive mode, the pC should wait until the BFREE bit of the Status Register is 1, then write the desired task to the Command Register. Once the byte containing the desired task has been written to the Command Register, the modem will: Set the BFREE bit of the Status Register to 0. Wait until enough received symbols are in the De-interleave Buffer. Decode them as needed, and transfer the resulting binary data to the Data Block Buffer Then the modem will set the BFREE and !RQ bits of the Status Register to 1', (causing the IRQN output to go low if the IRQNEN bit of the Mode Register has been set to '1') to tell the pC that it may read from the Data Block Buffer and write the next task to the modem. If more than 1 byte is contained in the buffer, byte number 0 of the data will be read out first. in this way the uC can read data and write a new task to the modem while the received symbols needed for this new task are being received and stored in the De-interleave Buffer. aw RXIN signal for task | | for task 2 am IRON ofp (IRQNEN = '1') ~L l IRQ bit of Status Register J J A rN BFREE bit of Status Register JS L__J A A Task from pC to Command Register 7 Task 1 Task 2 Data from Block Buffer to pC MME Trask | data Figure 9 Receive Task Overlapping Detailed timings for the various tasks are given in Figures 10 and 11. FX919A Modem Tasks: B2 Bi BO Receive Mode Transmit Mode 0 0 Oo | NULL NULL 0 0 1 SFSH Search for FS + Header T24S Transmit 24 symbois 0 1 oO | RHB Read Header Biock THB Transmit Header Block 0 1 1 RILB Read Intermediate or Last TIB Transmit Intermediate Block Block 1 0 0 | SFS Search for Frame Sync TLB Transmit Last Block 1 0 1 R4S Read 4 symbols T4S Transmit 4 symbols 1 1 0 | NULL NULL 1 1 1 RESET Cancel any current action RESET Cancel any current action NULL: No effect This task is provided so that a AQSC or AQLEV command can be initiated without loading a new task. 8.102 MB 2374376 0001080 3004-Level FSK Modem Data Pump FX919A SFSH: Search for Frame Sync plus Header Block This task causes the modem to search the received signal for a valid 24-symbol Frame Sync sequence followed by Header Block which has a correct CRC1 checksum. The task continues until a valid Frame Sync plus Header Block has been found. The search consists of two stages: First of all the modem will attempt to match the incoming symbols against the 24-symbol Frame Synchronisation pattern to within the tolerance defined by the FSTOL bits of the Control Register. Once a match has been found, the modem will read in the next 66 symbols as if they were a Header block, decoding the symbols and checking the CRC1 checksum. if this is incorrect, the modem will resume the search, looking for a fresh Frame Sync pattern. if the received CRC1 is correct, the 10 decoded data bytes will be placed into the Data Block Buffer, the BFREE and IRQ bits of the Status Register will be set to '1' and the CRCERR bit cleared to 'O. On detecting that the BFREE bit of the Status Register has gone to 1, the pC should read the 10 bytes from the Data Block Buffer then write the next task to the modem's Command Register. RHB: Read Header Block This task causes the modem to read the next 66 symbols as a Header Block, decoding them, placing the resulting 10 data bytes and the 2 received CRC1 bytes into the Data Block Buffer, and setting the BFREE and IRQ bits of the Status Register to '1' when the task is complete to indicate that the uC may read the data from the Data Block Buffer and write the next task to the modem's Command Register. The CRCERR bit of the Status Register will be set to '1' or '0' depending on the validity of the received CRC1 checksum bytes. RILB: Read Intermediate or 'Last' Block This task causes the modem to read the next 66 symbols as an Intermediate or Last block (the uC should be able to teil from the 'Header block how many blocks are in the frame, and hence when to expect the 'Last' block). In each case, it will decode the 66 symbols and place the resulting 12 bytes into the Data Block Buffer, setting the BFREE and IRQ bits of the Status Register to '1' when the task is complete. If an Intermediate block is received then the pC should read out all 12 bytes from the Data Block Buffer and ignore the CRCERR bit of the Status Register, for a Last block the uC need only read the first 8 bytes from the Data Block Buffer, and the CRCERR bit in the Status Register will reflect the validity of the received CRC2 checksum. SFS: Search for Frame Sync This task causes the modem to search the received signal for a 24-symbol sequence which matches the Frame Synchronisation pattern to within the tolerance defined by the FSTOL bits of the Mode Register. When a match is found the modem will set the BFREE and IRQ bits of the Status Register to '1' to indicate to the pC that it should write the next task to the Command Register. 8.103 MM 2374376 0001081 247 mm4-Level FSK Modem Data Pump FX919A R4S: Read 4 Symbols This task causes the modem to read the next 4 symbols and translate them directly (without de- interleaving or FEC) to an 8-bit byte which is placed into the Data Block Buffer. The BFREE and IRQ bits of the Status Register will then be set to '1' to indicate that the uC may read the data byte from the Data Block Buffer and write the next task to the Command Register. This task is intended for special tests and channel monitoring - perhaps preceded by SFS task. T24S: Transmit 24 Symbols This task, which is intended to facilitate the transmission of Symbol and Frame Sync patterns as well as special test sequences, takes 6 bytes of data from the Data Block Buffer and transmits them as 24 4-level symbols without any CRC or FEC. Byte 0 of the Data Block Buffer is sent first, byte 5 last. Once the modem has read the data bytes from the Data Black Buffer, the BFREE and IRQ bits of the Status Register will be set to '1, indicating to the C that it may write the data and command byte for the next task to the modem. The tables below show what data has to be written to the Data Block Buffer to transmit the FX919A Symbol and Frame Sync sequences: Symbol Sync Block Buffer Hex + 3 111101 F5 E : 11110101 +3 | -3 : 14 F5 + 3 : 1111 F5 - : 11110101 +3 | -3 : 11110101 F5 Frame Sync to Data Block +1 71 : 001 : 00110111 1 (| +1 : 1 +3 71 : 11110010 +1 : 01011 : 00011011 THB: Transmit Header Block This task takes 10 bytes of data (Address and Control) from the Data Block Buffer, calculates and appends the 2-byte CRC1 checksum, translates the result to 4-level symbols (with FEC), interleaves the symbols and transmits the result as a formatted 'Header Block. Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status Register will be set to '1'. 8.104 MH 237437b GOO1l08e 1434-Level FSK Modem Data Pump FX919A TIB: Transmit Intermediate Block This task takes 12 bytes of data from the Data Block Buffer, updates the 4-byte CRC2 checksum for inclusion in the Last' block, translates the 12 data bytes to 4-level symbols (with FEC), interleaves the symbols and transmits the result as a formatted Intermediate Block. Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status Register will be set to '1'. TLB: Transmit Last Block This task takes 8 bytes of data from the Data Block Buffer, updates and appends the 4-byte CRC2 checksum, translates the resulting 12 bytes to 4-level symbols (with FEC), interleaves the symbols and transmits the result as a formatted Last' Block. Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status Register will be set to '1'. T4S: Transmit 4 Symbols This command is similar to T24S but takes only one byte from the Data Block Buffer, transmitting it as four 4-level symbols. RESET: Stop any current action This task takes effect immediately, and terminates any current action (task, AQSC or AQLEV) the modem may be performing and sets the BFREE bit of the Status Register to '1', without setting the IRQ bit. It should be used when Vpp is applied, to set the modem into a known state. Note that due to delays in the transmit filter, it will take several symbol times for any change to appear at. the TXOP pin. 8.105 Mm 2374376 0001083 O174-Level FSK Madem Data Pump FX919A Task Timings Data to Data Block Buffer fq Task to Command Register | i | B3 -t4 < 4s < is > IBEMPTY bit l j , t 7 . r BFREE bit t + t t Q [7d 2 fi Le 73 3 Bb e_ as ats 7 Symbols to ff T T RRC filter from task #1 from task #2 from task #3 Modem Tx output Figure 10 Transmit Task Timing Diagram Time Task (symbol times) u Modem in idle state. Time from writing first { task to application of first transmit bit to Tx Any 1to2 | RRC filter t2 | Time from application of first symbol of the T2485 5 task to the Tx RRC filter until BFREE goes THB/TIB/TLB 16 to a logic '1' (high). T4S 0 t3 | Time to transmit all symbols of the task T24S 24 THB/TIB/TLB 66 T4S 4 t4 | Max time allowed from BFREE going toa T24S 18 logic '1' (high) for next task (and data) to THB/TIB/TLB 49 be written to modem T4S 3 8.106 MB 2374376 0001084 T5b4-Level FSK Modem Data Pump FX919A Modem Rx input for task #1 for task #2 for task #3 Symbolsto 8 + i ft rr De-interleave circuit B B B | Data from Data Block Buffer ica Task to Command Register ai 6 I 2 6 i 3 5 t6 je 16 | ke | <>] | | BEREE bit l "1 ay l J Figure 11 Receive Task Timing Diagram Time Task (symbol times) t3 | Time to receive all symbols of task SFS 24 (minimum) SFSH 90 (minimum) RHB/RILB 66 R4S 4 t6 | Maximum time between first symbol of task SFS 21 entering the de-interleave circuit and the SFSH 21 task being written to modem. RHB/RILB 49 R4S 3 t7 |Maximum time from the last bit of the task Any 1 entering the de-interteave circuit to BFREE going to a logic 1 (high) 8.107 MM 237437b 0001085 99 oo4-Level FSK Modem Data Pump FX919A RRC Filter Delay The previous task timing figures are based on the signal at the input to the RRC filter (in transmit mode) or the input to the de-interleave buffer (in receive mode). There is an additional delay of about 8 symbol times through to the RRC filter in both transmit and receive modes, as illustrated below: j | Tx Symbo! to RAC Filter Tx Symbol at Txop pin / Rx Symbol from FM discriminator Rx Symbol to De-interleave Buffer | | +- Symbol-times Figure 12 RRC Low Pass Fiiter Delay 1.5.5.3 Control Register This 8-bit write-only register controls the modem's symbol rate, the response times of the receive clock extraction and signal level measurement circuits and the Frame Sync pattem recognition tolerance. Control Register { | | L7;,e{[Ts[4]3f2}iifo} \ 1 SN : JN : XN CKDIV. FSTOL LEVRES PLLBW Control Register B7, B6: CKDIV - Clock Division Ratio These bits control a frequency divider driven from the clock signal present at the XTALN pin, and hence determine the nominal symbol rate. The table below shows how symbol rates of 2400/4800/9600 symbols/sec may be obtained from common Xtal frequencies: Xtal 2.4576 4.9152 Division Ratio: B7 | B6 | Xtal Rate Rate 0 0 12 9600 1 1 4800 9600 1 1 1 4096 2400 Note: Device operation is not guaranteed below 2400 or above 9600 symbols/sec. 8.108 MB 2374376 0001086 4294-Level FSK Modem Data Pump FX919A Control Register B5, B4: FSTOL - Frame Sync Tolerance These two bits have no effect in transmit mode. In receive mode, they define the maximum number of mismatches which will be allowed during a search for the Frame Sync pattern: B5 | B4 Mismatches allowed Q 2 4 Note: A single 'mismatch' is defined as the difference between two adjacent symbol levels, thus if the symbol '+1' were expected, then received symbol values of '+3' and '-1' would count as 1 mismatch, a received symbol value of '-3' would count as 2 mismatches. Control Register B3, B82: LEVRES - Level Measurement Modes These two bits have no effect in transmit mode. In receive mode they set the 'normal' operating mode of the Rx signal amplitude and dc offset measuring circuits. This setting will be temporarily overridden by the automatic sequencing of an AQLEV command. B3 | B2 Mode 0 0 Hoid 0 1 Slow Peak Detect 1 0 Lossy Peak Detect 1 1 Clamp For most applications these two bits should be set to 'Slow Peak Detect mode, in which the peak positive and peak negative excursions of the received signal (after filtering) are measured to establish the amplitude and de offset of the signal. The decay time-constant of the peak rectifier circuits used in this mode is approximately 750 symbol times. The Hold setting freezes the stored values of the current amplitude and offset measurements and may therefore be used to improve performance during short fades or while the radio is switched from receive mode for the transmission of a short acknowledgement. It should be noted, however, that the measured amplitude and offset values are stored on the external capacitors C7 and C8 and will decay gradually when the Hold setting is chosen, the discharge time-constant being approximately 750 symbol times. The Lossy Peak Detect' setting is similar to Slow Peak Detect except that the decay time-constant of the peak detectors are reduced to approximately 25 symbol times to give a faster response to signal changes at the expense of a reduction in BER performance. This mode is used by the automatic Level Measurement acquisition sequence but may also be useful in non-standard systems. The 'Clamp' setting is primarily intended for use by the automatic Level Measurement acquisition sequence as described in Section 1.6.3, but may also be useful in non-standard systems. In this mode the DOC1 and DOC2 pins are connected directly to the output of the circuit that normally drives the peak detectors. Control Register 81, BO: PLLBW - Phase-Locked Loop Modes These two bits have no effect in transmit mode. In receive mode, they set the normal bandwidth of the Rx clock extraction Phase Lacked Loop circuit. This setting will be temporarily overridden by the automatic sequencing of an AQSC command. 8.109 Me 2374376 0001087 76454-Level FSK Modem Data Pump FX919A B1 | BO | PLL Mode Working Bandwidth (_ + ppm) 0 0 Hold > 0 1 Narrow Bandwidth 20 1 Oo Medium Bandwidth 100 1 1 Wide Bandwidth 650 Note: 'Working Bandwidths' are the maximum difference between the actual received symbol rate and the nominal rate determined by the tolerance of the modem's Xtal frequency, to give minimal degradation of a reasonably random received signal. The minimum bandwidth consistent with the transmit and receive modem symbol rate tolerances should be chosen, ie. if the Xtals used with both modems have accuracies of within + 50ppm, then the PLLBW bits should be set to '10' (Medium Bandwidth). However, to allow the PLL to settle quickly it is recommended that when very close tolerance Xtals are used, then the PLLBW bits should be set to Medium whenever an AQSC is triggered, and only changed to Narrow about 200 symbol times later. The Wide Bandwidth setting is intended for message acquisition in systems where the uC cannot detect the start of a received message, as it allows the modem to respond rapidly to fresh messages and recover rapidly after a fade without pC intervention - although at the cost of reduced Bit Error Rate vs Signal to Noise performance. The 'Hold' setting disables the PLL feedback loop, and may be used during signal fades. 1.5.5.4 Mode Register The contents of this 8-bit write only register control the basic operating modes of the modem: Mode Register f7Te{[s[4]3 [2]i1] 0} | | | INVSYM | RXEYE Set to '0000 IRQNEN TXRXN Mode Register B7: IRQNEN - IRQN Output Enable When this bit is set to 1', the [RON chip output pin is pulled low (to Vgs) whenever the IRQ bit of the Status Register is a 1. Mode Register B6: INVSYM - Invert Symbols This bit controls the polarity of the transmitted and received symbol voltages. B6 Symbol! Signal at TXOP Signal at RXFB 0 '+3' Above Veias Below Vaiss '-3' Below Vaiss Above Vajas 1 +3! Below Vas Above Vaiss '-3' Above Veias Below Vers 8.110 mm 2374376 0001088 bTh =4-Level FSK Modem Data Pump FX919A Mode Register B5: TXRXN - Tx/Rx Mode Setting this bit to '1' puts the modem into Transmit mode, clearing it to '0' puts the modem into Receive mode. Note that changing between receive and transmit modes will cancel any current task. Mode Register B4: RXEYE - Show Rx Eye This bit should normally be set to 0. Setting it to 1 when the modem is in receive mode configures the modem into a special test mode, in which the input of the Tx o/p buffer is connected to the Rx Symbol/Clock extraction circuit at a point which carries the equalised receive signal. This may be monitored with an oscilloscope (at the TXOP pin itself), to assess the quality of the complete radio channel including the Tx and Rx modem filters, the Tx modulator and the Rx IF filters and FM demodulator. The resulting eye diagram (for reasonably random data) should ideally be as shown in the following Figure 13, with 4 crisp and equally spaced crossing points. Figure 13 Ideal 'RXEYE' Signal Mode Register B3, B2, B1, BO This bits should be set to '0000'. 1.5.5.5 Status Register This register may be read by the pC to determine the current state of the modem. Status Register L7/;e{;s5}4]}3}2i1]o} t | | BFREE | DIBOVF | Reserved IRQ IBEMPTY CRCERR 8.111 Mm 23743976 0001089 5354-Level FSK Modem Data Pump FX919A Status Register B7: IRQ - Interrupt Request This bit is set to '1' by: The Status Register BFREE bit going from 0' to '1, unless this is caused by a RESET task or by a change to the Mode Register TXRXN bit. or The Status Register IBEMPTY bit going from '0' to '1, unless this is caused by a RESET task or by changing the Mode Register TXRXN bit. or The Status Register DIBOVF bit going from '0' to '1'. The IRQ bit is cleared to O' immediately after a read of the Status Register. If the IRQNEN bit of the Mode Register is '1', then the chip IRQN output will be pulled low (to Ves) whenever the IRQ bit is set to '1', and will go high impedance when the Status Register is read. Status Register B6: BFREE - Data Block Buffer Free This bit reflects the availability of the Data Block Buffer and is cleared to 0 whenever a task other than NULL or RESET is written to the Command Register. In transmit mode, the BFREE bit will be set to '1' (also setting the Status Register IRQ bit to 1') by the modem when the modem is ready for the uC to write new data to the Data Block Buffer and the next task to the Command Register. in receive mode, the BFREE bit is set to '1' (also setting the Status Register IRQ bit to 1') by the modem when it has completed a task and any data associated with that task has been placed into the Data Block Buffer. The pC may then read that data and write the next task to the Command Register. The BFREE bit is also set to '1' - but without setting the IRQ bit - by a RESET task or when the Mode Register TXRXN bit is changed. Status Register B5: IBEMPTY - Interleave Buffer Empty In transmit mode, this bit will be set to '1' - also setting the IRQ bit - when less than two symbols remain in the Interleave Buffer. Any transmit task written to the modem after this bit goes to '1' will be too late to avoid a gap in the transmit output signal. The bit is also set to {' by a RESET task or by a change of the Mode Register TXRXN bit, but in these cases the IRQ bit will not be set. The bit is cleared to 0' within one symbol time after a task other than NULL or RESET is written to the Command Register. Note: When the modem is in transmit mode and the Interleave Buffer is empty, a mid level (half-way between +1' and '-1'} signal will be sent to the RRC filter. in receive mode this bit will be 0. Status Register B4: DIBOVF - De-Interleave Buffer Overflow In receive mode this bit will be set to '1' - also setting the RQ bit - when a RHB, RILB or R4S task is written to the Command Register too late to allow continuous reception. The bit is cleared to 0' immediately after reading the Status Register, by writing a RESET task to the Command Register or by changing the TXRXN bit of the Mode Register. In transmit mode this bit will be '0'. 8.112 Me 2374376 0001090 2ST4-Level FSK Modem Data Pump FX919A Status Register B3: CRCERR - CRC Checksum Error In receive mode this bit will be updated at the end of a SFSH, RHB or RILB task to reflect the result of the receive CRC check. '0' indicates that the CRC was received correctly, '1' indicates an error. Note that this bit should be ignored when an Intermediate block (which does not have an integral CRC) is received. The bit is cleared to '0' by a RESET task, or by changing the TXRXN bit of the Mode Register. In transmit mode this bit is '0'. Status Register B2, Bi, BO These bits are reserved for future use. 1.5.5.6 Data Quality Register In receive mode, the FX919A continually measures the quality of the received signal, by comparing the actual received waveform over the previous 64 symbol times against an internally generated ideal. The result is placed into bits 3-7 of the Data Quality Register for the uC to read at any time, bits 0-2 being always set to '0'. Figure 14 shows how the value (0-255) read from the Data Quality Register varies with received signal-to-noise ratio: 250 200 150 ve a 100 LD . 0 5 7 9 11 13 15 S/N dB (noise in 2* symbol-rate bandwidth) Figure 14 Typical Data Quality Reading vs S/N In transmit mode and for 64 symbol times after enabling receive mode or after starting an AQSC or AQLEV sequence the value in the Data Quality Register will be invalid. 1.5.6 CRC, FEC and interleaving Cyclic Redundancy Codes CRC1 This is a sixteen-bit CRC check code contained in bytes 10 and 11 of the Header Block. It is calculated by the modem from the first 80 bits of the block { Bytes 0 to 9 inclusive) using the generator palynomial: x16 491245544 8.113 M@ 2374376 0001091 14564-Level FSK Modem Data Pump FX919A CRC2 This is a thirty-two-bit CRC check code contained in bytes 8 to 11 of the Last Block. It is calculated by the modem from all of the data and pad bytes in the Intermediate Blocks and in the first 8 bytes of the Last Block using the generator polynomial: x32 4 x26 4 x23 4 x22 4 16 4 12 4 11 4 x10 4 x84 x7 4 xD a xt a x2 a xt at Note: In receive mode the CRC2 checksum circuits are initialised on completion of any task other than NULL or RILB. In transmit mode the CRC2 checksum circuits are initialised on completion of any task other than NULL, TIB or TLB. Forward Error Correction in transmit mode, the FX919A uses a Trellis Encoder to translate the 96 bits (12 bytes) of a Header, Intermediate or Last Block into a 66-symbol sequence which includes FEC information. In receive mode, the FX919A decodes the received 66 symbols of a block into 96 bits of binary data using a Soft Decision Viterbi algorithm to perform decoding and error correction. Interleaving The 66 symbols of a Header, Intermediate or Last block are interleaved by the modem before transmission to give protection against the effects of noise bursts and short fades. In receive mode, the FX919A de-interleaves the received symbols prior to decoding. 8.114 Mm 237437b OOOL0%e Cece4-Level FSK Modem Data Pump FX919A 1.6 Application Notes 1.6.1 Transmit Frame Example The operations needed to transmit a single Frame consisting of Symbol and Frame Sync sequences, and one each Header, Intermediate and Last blocks are shown below: 1. Ensure that the Control Register has been loaded with a suitable CKDIV value, that the IRQNEN and TXRXN bits of the Mode Register are 1', the RXEYE bit is '0' and the INVSYM bit is set appropriately. 2. Read the Status Register to ensure that the BFREE bit is '1', then write 6 Symbol Sync bytes to the Data Block Buffer and a T24S task to the Command Register. 3. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be 0'. 4. Write 6 Frame Sync bytes to the Data Block Buffer and a T24S task to the Command Register. 5. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. 6. Write 10 Header Block bytes to the Data Block Buffer and a THB task to the Command Register. 7, Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be 0. 8. Write 12 Intermediate Block bytes to the Data Block Buffer and a TIB task to the Command Register. 9. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be 0'. 10. Write 8 Last Block bytes to the Data Block Buffer and a TLB task to the Command Register. 11. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0. 12. Wait for another interrupt from the modem, read the Status Register; the IRQ, BFREE and IBEMPTY bits should be 1. Note: The final symbol of the frame will start to appear approximately 2 symbol times after the Status Register IBEMPTY bit goes to '1'; a further 16 symbol times should be allowed for the symbol to pass completely through the RRC filter. 8.115 MB 237437b 0001093 Tho4-Level FSK Modem Data Pump FX919A 1.6.2 Receive Frame Example The operations needed to receive a single Frame consisting of Symbol and Frame Sync sequences and one each Header, Intermediate and Last blocks are shown below; 1. Ensure that the Control Register has been loaded with suitable CKDIV, FSTOL, LEVRES and PLLBW values, and that the IRQNEN bit of the Mode Register is '1', the TXRXN and RXEYE bits are '0'", and the INVSYM bit is set appropriately. 2. Wait until the received carrier has been present for at least 8 symbol times (see Section 1.6.3). 3. Read the Status Register to ensure that the BFREE bit is '1'. 4. Write a byte containing a SFSH task and with the AQSC and AQLEV bits set to '1' to the Command Register. 5. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be 't' and the CRCERR and DIBOVF bits should be 0. 6. Check that the CRCERR bit of the Status Register is '0' and read 10 Header Block bytes from the Data Block Buffer. 7. Write a RILB task to the Command Register. 8. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the DIBOVF bit 0. 9. Read 12 Intermediate Block bytes from the Data Block Buffer. 10. Write a RILB task to the Command Register. 11. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the DIBOVF bit '0. 12. Check that the CRCERR bit of the Status Register is '0' and read the 8 Last Block bytes from Data Buffer. 1.6.3 Clock Extraction and Level Measurement Systems The FX919A is intended for use in systems where the Symbol Sync pattern is transmitted immediately on start-up of the transmitter. When the carrier is detected by the receiver or when the receiver is switched to another channel, the controlling uC should wait approximately 8 symbol times for the received signal to propagate through the modem's RRC filter then issue a SFS or SFSH task with the AQSC and AQLEV bits set to 1. The 8- symbol delay can usefully be included in the carrier detect circuitry. Setting the AQSC and AQLEV bits to 1' triggers the modem's automatic Symbol Clock Extraction and Level Measurement acquisition sequences, which are designed to measure the received symbol timing, amplitude and dc offset as quickly as possible during the Symbol Sync period before switching to more accurate - but slower - measurement modes for the remainder of the received message. Note that if the acquisition sequences are triggered after the Symbol Sync period - as can happen when the receiver is switched to another channel - they will still function correctly, but will take much longer to acquire accurate level and timing information. 8.116 MB 2374376 O0601094 45T54-Level FSK Modem Data Pump FX919A noise Symbol Sync Frame Syne rest of frame Received signal fram FM discriminator to Modem: 8-symbol delay Set AQSC and AQLEY bits to start acquisition sequences : Level Measurement and Clock Extraction circuits : Increasing accuracy and lengthening response times Figure 15 Acquisition Sequence Timing The operation of the Level Acquisition Sequence depends on the settings of the Control Register LEVRES bits: LEVRES setting: B3 | B2 Details of Level Acquisition Sequence Hold 0 0 | 1 symbol time of 'Clamp' mode then 15 symbol times of 'Lossy Peak Detect mode before reverting to 'Hoid' mode. Slow Peak Detect' 0 1 1 symbol time of 'Clamp' mode then 15 symbol times of 'Lossy Peak Detect' made before reverting to 'Slow Peak Detect' mode. Lossy Peak Detect 1 Q | 1 symbol time of 'Clamp' mode before reverting to Lossy Peak Detect' mode Clamp' 1 1 Remain in 'Clamp' mode. The 1-symbol Clamp time at the start of these sequences is used to make an initial measurement of the dc offset present on the received signal, after which the Lossy Peak Detect' period is used to estimate the signal amplitude. The operation of the Symbol Clock Acquisition Sequence depends on the settings of the Control Register PLLBW bits: PLLBW setting: Bi | Bo | Details of Symbol Clock Acquisition Sequence Hold 0 0 | 16 symbol times of 'Extra-wide BW' mode followed by 30 symbol times of Wide BW' mode before reverting to 'Hold' mode. Narrow' BW 0 1 | 16 symbol times of 'Extra-wide BW' mode followed by 30 symbol times of Wide BW' mode before reverting to 'Narrow BW' mode. Medium BW' 1 0 | 16 symbol times of 'Extra-wide BW' mode followed by 30 symbol times of Wide BW' before reverting to Medium BW' mode. Wide BW' 1 1 | 16 symbol times of 'Extra-wide BW mode before reverting to Wide BW' mode. 8.117 MH 2374376 OOO1095 43)4-Level FSK Modem Data Pump FX919A Note: The 'Extra-wide BW' PLL made is designed to synchronise rapidly to the '+3 +3 -3 -3 ...' Symbol Sync pattern and is available only as part of an automatic acquisition sequence. Although not recommended, it is possible to use the modem in a non-standard system where there is an indeterminate delay between the transmitter start-up and the Symbol! Sync pattern, or where a receive carrier detect signal is not available to the controlling uC. In these cases the Symbol Sync pattern should be extended to about 100 symbols, and the Control Register LEVRES bits should be set to Lossy Peak Detect' and the PLLBW bits to 'Wide BW' before initating a 'SFS + AQSC + AQLEV' task. Once the Frame Sync pattern has been detected, the Control Register settings may be changed to Slow Peak Detect and Medium or Narrow PLL bandwidth for the remainder of the received message. 1.6.4 AC Coupling For a practical circuit, ac coupling from the modem's transmit output to the frequency modulator and between the receiver's frequency discriminator and the receive input of the modem may be desired. There are, however, two problems: Firstly, ac coupling of the signal degrades the Bit Error Rate performance of the modem. The following graph illustrates the typical bit error rates at 4800 symbols/sec (without FEC) for differing degrees of ac coupling: 1E-1 1E-2 [om ui a ower Tx & Rx DC coupled || - 1E-3 | % Tx 5Hz, Rx DC . t Tx 5Hz, Ax 5H2 Tx 5Hz, Ax 10H2 * ea 4 5 6 7 8 9 10 "1 12 13 14 S/N dB (Noise in 20 10 9600Hz band) Figure 16 Effect of AC Coupling on BER Secondly, any ac coupling at the receive input will transform any step in the voltage at the discriminator output to a slowly decaying pulse which can confuse the modem's level measuring circuits. As illustrated in Figure 17 below, the time for this step to decay to 37% of its original value is 'RC where: RC = 14 2x 2x the 3dB cut-off frequency of the RC network ) which is 32 msec, or 153 symbol times at 4800 symbols/sec, for a 5Hz network. 8.118 MH 237437b OOOLOIb 7754-Level FSK Modem Data Pump FXO19A Step input to RC circuit 100% ~ Output of RC circuit 37% < T=RC 5 Figure 17 Decay Time - AC Coupling In general, it will be best to de couple the receiver discriminator to the modem, and to ensure that any ac coupling to the transmitter's frequency modulator has a -3dB cut-off frequency of no higher than 5Hz (for 4800 symbols/sec). 1.6.5 Radio Performance The maximum data rate that can be transmitted over a radio channel using these modems depends on: - RF channel spacing. - Allowable adjacent channel interference. - Symbol rate. - Peak carrier deviation (modulation index). - Tx and Rx reference oscillator accuracies. - Modulator and demodulator linearity. - Receiver IF filter frequency and phase characteristics. - Use of error correction techniques. - Acceptable error rate. As a guide, 4800 symbols/sec can be achieved - subject to local regulatory requirements - over a system with 12.5kHz channel spacing if the transmitter frequency deviation is set to +2.5kHz peak for a repetitive ' +3 43 -3 -3.... ' pattern and the maximum difference between transmitter and receiver carrier frequencies is less than 2400Hz. The modulation scheme employed by these modems is designed to achieve high data throughput by exploiting as much as possible of the RF channel bandwidth. This does, however, place constraints on the performance of the radio. In particular, attention must be paid to: - Linearity, frequency and phase response of the Tx Frequency Modulator. For a 4800 symbois/sec system, the frequency response should be within +2dB over the range 3Hz to 5kHz, relative to 2400Hz. - The bandwidth and phase response of the receiver's IF filters. - Accuracy of the Tx and Rx reference oscillators, as any difference will shift the received signal towards the skirts of the IF filter response and cause a dc offset at the discriminator output. Viewing the received signal eye - using the Mode Register RXEYE function - gives a good indication of the overall transmitter/receiver performance. 8.119 MM 2374376 0001097 O4 a4-Level FSK Modem Data Pump FX919A Rx FREQUENCY Tx FREQUENCY DISCRIMINATOR MODULATOR SIGNAL LEVEL ADJUSTMENT * DG LEVEL SIGNAL AND ADJUSTMENT RXIN RXEB ADJUSTMENT im Tx TxaP CONTROLLER CIRCUITS CIRCUITS bo-p7 }| 0-07 A0- At >| A0-A1 CSN +] csn RON >| RON RON >| RON FX919A MODEM IRON fe IRON Figure 18 Typical Connections Between Radio and FX919A 8.120 me 2374376 Goo109s S404-Level FSK Modem Data Pump FX919A 1.7 Performance Specification 1.7.1 Electrical Performance Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Min. Max. Units Supply (Vpp - Vg) -0.3 7.0 v Voltage on any pin to Vgs -0.3 Vop + 0.3 Vv Current into or out of Vpp and Vgs pins -30 +30 mA Current into or out of any other pin -20 +20 mA D2 Package Min. Max. Units Total Allowable Power Dissipation at Tamb = 25C 800 mW ... Derating 13 mWw/C Storage Temperature -55 +125 C Operating Temperature -40 +85 C D5 Package Min. Max. Units Total Allowable Power Dissipation at Tamb = 25C 550 mw ... Derating g mw/rc Storage Temperature -55 +125 C Operating Temperature -40 +85 C Operating Limits Correct operation of the device outside these limits is not implied. Notes Min, Max. Units Supply (Vpp - Vss) 3.0 5.5 Vv Operating Temperature -40 +85 C Symbol Rate 2400 9600 Symbols/sec Xtal Frequency 1.0 10.0 MHz 8.124 Me 2374376 OOO1099 4a? om4-Level FSK Modem Data Pump FX919A Operating Characteristics For the following conditions unless otherwise specified: Xtal Frequency = 4.9152MHz, Symbol Rate = 4800 symbols/sec, Noise Bandwidth = 0 to 9600HZz, Vpp = 3.3V to 5.0V, Tamb = - 40C to +85C. Notes Min. Typ. Max. Units DC Parameters Ippo} (Vpp = 5.0V) 1 4.0 10.0 mA Ippo (Vpp = 3.3V) 1 2.5 6.3 mA AC Parameters Tx Output TXOP Impedance 2 1.0 2.5 ko Signal Level 3 0.8 1.0 1.2 V pk-pk Output DC Offset wrt Vop/2 4 -0.25 +0.25 Vv Rx Input RXIN Impedance (at 100Hz) 10.0 MQ RXIN Amp Voltage Gain (I/P = 1mVrms at 100Hz) 300 VN Input Signal Level 5 0.7 1.0 1.3 V pk-pk DC Offset wrt Vpp/2 5 -0.5 +05 Vv Xtal/Clock Input High Pulse Width 6 40 ns Low' Pulse Width 6 40 ns Input Impedance (at 100Hz) 10.0 MQ Gain (I/P = 1mVrms at 100Hz) 20 dB pC Interface Input Logic "1" Level 7,8 70% Vop Input Logic "0" Level 7,8 30% Vop input Leakage Current (Vin = 0 to Vpp) 7,8 -5.0 +5.0 pA Input Capacitance 7,8 10.0 pF Output Logic "1" Level (loy = 120yA) 8 92% Vop Output Logic "0" Level (lo. = 360A) 8,9 8% Vop Off State Leakage Current (Vout = Vpp) 9 10 yA Notes: 1. ap OOND MB 2374376 0001100 Teo At 25C. Not including any current drawn from the modem pins by external circuitry other than the Xtal oscillator. Small signal impedance, at Vpp = 5.0V and Tamb = 25C. Measured after the externa! RC filter (R4/C5) fora "+3 +3 -3 -3...." symbol sequence, at Vpp = 5.0V and Tamb = 25C (output level is proportional to Vpp). Measured at the TXOP pin with the modem in the Tx idle mode. For optimum performance, measured at RXFB pin, for a"...+3 +3 -3 -3..." symbol sequence, at Vpp = 5.0V and Tamb = 25C. Optimum level is proportional to Vpp. Timing for an external input to the CLOCK/XTAL pin. WRN, RDN, CSN, AO and Aj pins. DO - D7 pins. IRQN pin. 8.1224-Level FSK Modem Data Pump FX919A Notes Min. Typ. Max. Units pC Parailel Interface Timings (ref. Figure 19) tacst Address valid to CSN low time 0 ns taH Address hold time 0 ns tcsH CSN hold time 0 ns {csHi CSN high time 10 6 clock cycles tcspwL CSN to WRN or RDN low time 0 ns tour Read data hold time Q ns tpHw Write data hold time 0 ns tosw Write data setup time 90 ns tRHCSL RDN high to CSN low time (write) 0 ns tRaAcL Read access time from CSN low 11 175 ns tRARL Read access time from RDN low 11 145 ns trL RDN low time 200 ns trx RDN high to DO-D7 3-state time 50 ns twHcs. WRN high to CSN low time (read) 0 ns twe WRN low time 200 ns Notes: 10. Xtal/Clock cycles at the XTAL/CLOCK pin. 11. With 30pF max to Vss on DO - D7 pins. WRITE CYCLE (DATA TO MODEM) TAH Webs ADDRESS x ADDRESS VALID AO, A1 CSN <P tacsL READ CYCLE (DATA FROM MODEM) eb t ADDRESS ; << 0, At <I ADDRESS VALID ty <"tacsi ' ro, , CSH >; CSN 1 1 ig ts ' ' (i) 1 tWHCSL> | 1 T T WRN / ' tosRWL <> 1 i t RDN RL > tex t ! <__ tpHR@, | \ * TRARL DATA D0 - D7 ' AGL 1 DATA VALID D> 4___- RAGE _y, Figure 19 C Parallel interface Timings 8.123 WB 237437b 0001101 1b54-Level FSK Modem Data Pump FX919A 4 5 6 7 3 9 10 it 12 13 14 S/N dB (Noise in 2 x Symbol Rate Bandwidth) Figure 20 Typical Bit Error Rate With and Without FEC B.124 Mm 23743976 0001102 6711.7.2 Package Outlines The FX919A is available in the package styles outlined below. Mechanical package diagrams and _ specifications are detailed in Section 10 of this document. Pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. FX919AD2 24-pin plastic S.0.1.C. (DW) NOT TO SCALE 15.57mm 7.59mm Max. Body Length Max. Body Width Handling Precautions The FX919A is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage. FX919AD5 = 24-pin plastic $.S.O.P. NOT TO SCALE Max. Body Length 8.33mm Max. Body Width 5.38mm Ordering Information FX919AD2 24-pin plastic S.O.I.C. (DW) FX919AD5 24-pin plastic S.S.O.P. CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry. M@@ 2374376 0001103 735