MCP6271/2/3/4/5 170 A, 2 MHz Rail-to-Rail Op Amp Features Description * * * * * * * * The Microchip Technology Inc. MCP6271/2/3/4/5 family of operational amplifiers (op amps) provide wide bandwidth for the current. This family has a 2 MHz gain bandwidth product (GBWP) and a 65 phase margin. This family also operates from a single supply voltage as low as 2.0V, while drawing 170 A (typ.) quiescent current. Additionally, the MCP6271/2/3/4/5 supports rail-to-rail input and output swing, with a common mode input voltage range of VDD + 300 mV to VSS - 300 mV. This family of operational amplifiers is designed with Microchip's advanced CMOS process. 2 MHz Gain Bandwidth Product (typ.) Supply Current: IQ = 170 A (typ.) Supply Voltage: 2.0V to 5.5V Rail-to-Rail Input/Output Extended Temperature Range: -40C to +125C Available in Single, Dual and Quad Packages Single with Chip Select (CS) (MCP6273) Dual with Chip Select (CS) (MCP6275) Applications * * * * * * The MCP6275 has a chip select input (CS) for dual op amps in an 8-pin package and is manufactured by cascading two op amps (the output of op amp A connected to the non-inverting input of op amp B). The chip select input puts the device in Low Power mode. Automotive Portable Equipment Photo Diode Pre-amps Analog Filters Notebooks and PDAs Battery-Powered Systems The MCP6271/2/3/4/5 family operates in the Extended Temperature Range of -40C to +125C, with a power supply range of 2.0V to 5.5V. Available Tools Package Types MCP6271 PDIP, SOIC, MSOP * SPICE Macro Model (at www.microchip.com) * FilterLab(R) Software (at www.microchip.com) NC 1 VIN_ Typical Applications R1 R2 R3 1 VOUTA 1 8 NC + VSS 4 7 VDD A VOUT VIN_ 2 VIN+ 3 MCP6275 VSS 4 6 VINB_ 5 VINB+ _ 14 VOUTD 7 VDD VINA 2 - + + - 13 VIND_ 6 VOUT VINA+ 3 VDD 4 12 VIND+ 11 VSS VINB+ 5 VINB_ 6 10 VINC+ -+ +- 9 V _ INC 5 NC VOUTB 7 CS 8 VOUTC MCP6275 PDIP, SOIC, MSOP VOUTA / VINB+ 1 VINA_ 2 VINA+ 3 VSS 4 2004 Microchip Technology Inc. + - VOUTA 1 5 Cascaded Gain with Chip Select 7 VOUTB MCP6274 PDIP, SOIC, TSSOP 8 CS + 8 VDD - + VSS 4 5 NC NC 1 7 VINA_ 2 6 VOUT VINA+ 3 MCP6273 PDIP, SOIC, MSOP 6 B 3 VIN+ 3 R4 2 VIN 2 MCP6272 PDIP, SOIC, MSOP 8 VDD 7 VOUTB - + + - _ 6 VINB 5 CS DS21810C-page 1 MCP6271/2/3/4/5 1.0 ELECTRICAL CHARACTERISTICS PIN FUNCTION TABLE Name Absolute Maximum Ratings Function VIN+, VINA+, VINB+, VINC+, VIND+ Non-inverting Inputs VIN_, VINA_, VINB_, VINC_, VIND_ Inverting Inputs VDD - VSS .........................................................................7.0V VDD Positive Power Supply All Inputs and Outputs ................... VSS - 0.3V to VDD + 0.3V VSS Negative Power Supply Difference Input Voltage ...................................... |VDD - VSS| Outputs Output Short Circuit Current ..................................continuous VOUT, VOUTA, VOUTB, VOUTC, VOUTD Current at Input Pins ....................................................2 mA NC No Internal Connection Current at Output and Supply Pins ............................30 mA CS Chip Select Storage Temperature.....................................-65C to +150C VOUTA/VINB+ Output of op amp A and non-inverting input of op amp B (MCP6275) Junction Temperature (TJ) . .........................................+150C ESD Protection On All Pins (HBM/MM) ................ 4 kV/400V Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, RL = 10 k to VDD/2 and VOUT VDD/2. Parameters Sym Min Typ Max Units Conditions Input Offset Voltage VOS -3.0 -- +3.0 mV VCM = VSS (Note 1) Input Offset Voltage (Extended Temperature) VOS -5.0 -- +5.0 mV TA= -40C to +125C, VCM = VSS (Note 1) VOS/TA -- 1.7 -- PSRR 70 90 -- Input Offset Input Offset Temperature Drift Power Supply Rejection V/C TA= -40C to +125C, VCM = VSS (Note 1) dB VCM = VSS (Note 1) Input Bias Current and Impedance Input Bias Current At Temperature At Temperature IB -- 1.0 -- pA Note 2 IB -- 50 200 pA TA= +85C (Note 2) IB -- 2 5 nA TA= +125C (Note 2) Input Offset Current IOS -- 1.0 -- pA Note 3 Common Mode Input Impedance ZCM -- 1013||6 -- ||pF Note 3 Differential Input Impedance ZDIFF -- 1013||3 -- ||pF Note 3 VCMR VSS - 0.3 -- VDD + 0.3 V Note 4 Common Mode (Note 4) Common Mode Input Range Common Mode Rejection Ratio CMRR 70 85 -- dB VCM = -0.3V to 2.5V, VDD = 5V Common Mode Rejection Ratio CMRR 65 80 -- dB VCM = -0.3V to 5.3V, VDD = 5V Note 1: 2: 3: 4: The MCP6275's VCM for op amp B (pins VOUTA/VINB+ and VINB-) is VSS + 100 mV. The current at the MCP6275's VINB- pin is specified by IB only. This specification does not apply to the MCP6275's VOUTA/VINB+ pin. The MCP6275's VINB- pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD - 100 mV. The MCP6275's VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL. DS21810C-page 2 2004 Microchip Technology Inc. MCP6271/2/3/4/5 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, RL = 10 k to VDD/2 and VOUT VDD/2. Parameters Sym Min Typ Max Units AOL 90 110 -- dB VOL, VOH VSS + 15 -- VDD - 15 mV ISC -- 25 -- mA Conditions Open-Loop Gain DC Open-Loop Gain (large signal) VOUT = 0.2V to VDD - 0.2V, VCM = VSS, Note 1 Output Maximum Output Voltage Swing Output Short-Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: 2: 3: 4: VDD 2.0 -- 5.5 V IQ 100 170 240 A IO = 0 The MCP6275's VCM for op amp B (pins VOUTA/VINB+ and VINB-) is VSS + 100 mV. The current at the MCP6275's VINB- pin is specified by IB only. This specification does not apply to the MCP6275's VOUTA/VINB+ pin. The MCP6275's VINB- pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD - 100 mV. The MCP6275's VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL. AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. Parameters Sym Min Typ Max Units MHz Conditions AC Response Gain Bandwidth Product GBWP -- 2.0 -- Phase Margin at Unity Gain PM -- 65 -- Slew Rate SR -- 0.9 -- V/s Input Noise Voltage Eni -- 3.5 -- Vp-p Input Noise Voltage Density eni -- 20 -- nV/Hz f = 1 kHz Input Noise Current Density ini -- 3 -- fA/Hz f = 1 kHz Noise f = 0.1 Hz to 10 Hz TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +2.0V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Operating Temperature Range TA -40 -- +125 C Storage Temperature Range TA -65 -- +150 C Conditions Temperature Ranges Note Thermal Package Resistances Thermal Resistance, 8L-PDIP JA -- 85 -- C/W Thermal Resistance, 8L-SOIC JA -- 163 -- C/W Thermal Resistance, 8L-MSOP JA -- 206 -- C/W Thermal Resistance, 14L-PDIP JA -- 70 -- C/W Thermal Resistance, 14L-SOIC JA -- 120 -- C/W Thermal Resistance, 14L-TSSOP JA -- 100 -- C/W Note: The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150C. 2004 Microchip Technology Inc. DS21810C-page 3 MCP6271/2/3/4/5 MCP6273/MCP6275 CHIP SELECT (CS) SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. Parameters Sym Min Typ Max Units Conditions CS Logic Threshold, Low VIL VSS -- 0.2 VDD V CS Input Current, Low ICSL -- 0.01 -- A CS Logic Threshold, High VIH 0.8 VDD -- VDD V CS Input Current, High ICSH -- 0.7 2 A CS = VDD GND Current IQ -- -0.7 -- A CS = VDD Amplifier Output Leakage -- -- 0.01 -- A CS = VDD CS Low to Valid Amplifier Output, Turn-on Time tON -- 4 10 s CS Low 0.2 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.9 VDD/2, VDD = 5.0V CS High to Amplifier Output High-Z tOFF -- 0.01 -- s CS High 0.8 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.1 VDD/2 VHYST -- 0.6 -- V VDD = 5V CS Low Specifications CS = VSS CS High Specifications Dynamic Specifications (Note 1) Hysteresis Note 1: The input condition (VIN) specified applies to both op amp A and B of the MCP6275. The dynamic specification is tested at the output of op amp B (VOUTB). DS21810C-page 4 2004 Microchip Technology Inc. MCP6271/2/3/4/5 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 14% 832 Samples VCM = VSS 16% 14% 12% 10% 8% 6% 4% 2% 10% 8% 6% 4% 2% 0% -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 3.0 2.4 1.8 Input Offset Voltage (mV) FIGURE 2-4: 24% 0 10 20 30 40 50 60 70 80 90 0% 100 Input Bias Current (pA) FIGURE 2-2: TA = +85C. Input Bias Current (nA) FIGURE 2-5: TA = +125C. Input Bias Current with 300 VDD = 2.0 V Input Offset Voltage (V) 250 200 150 100 TA = +125C TA = +85C TA = +25C TA = -40C 50 0 -50 -100 Input Bias Current with VDD = 5.5 V 250 200 150 100 50 TA = +125C TA = +85C TA = +25C TA = -40C 0 -50 Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 2.0V. 2004 Microchip Technology Inc. 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -100 -0.5 Input Offset Voltage (V) 300 3.0 0% 4% 2.8 4% 8% 2.6 8% 2.4 12% 12% 2.2 16% 16% 2.0 20% 422 Samples TA = +125 C 1.8 24% 20% 1.6 422 Samples TA = +85 C 0.6 28% Percentage of Occurrences Percentage of Occurrences 32% Input Offset Voltage Drift. 1.0 Input Offset Voltage. 0.8 FIGURE 2-1: Input Offset Voltage Drift (V/C) 1.4 1.2 0.6 0.0 -0.6 -1.2 -1.8 -2.4 -3.0 0% 832 Samples VCM = VSS TA = -40C to +125C 12% 1.2 18% Percentage of Occurrences Percentage of Occurrences 20% Common Mode Input Voltage (V) FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. DS21810C-page 5 MCP6271/2/3/4/5 Note: Unless otherwise indicated, TA = +25C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 10,000 VCM = VSS Representative Part 250 Input Bias, Offset Currents (pA) Input Offset Voltage (V) 300 200 150 100 50 0 VDD = 5.5V VDD = 2.0V -50 -100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCM = VDD VDD = 5.5V 1,000 Input Bias Current 100 Input Offset Current 10 1 5.5 25 35 Output Voltage (V) FIGURE 2-7: Output Voltage. 55 65 75 85 95 105 115 125 Ambient Temperature (C) Input Offset Voltage vs. FIGURE 2-10: Input Bias, Input Offset Currents vs. Ambient Temperature. 120 110 VDD = 5.0V CMRR 90 110 PSRR, CMRR (dB) 100 CMRR, PSRR (dB) 45 PSRR- 80 PSRR+ 70 60 50 40 100 CMRR 90 PSRR VCM = VSS 80 70 30 20 60 1.E+00 1.E+01 1 1.E+02 10 100 1.E+03 1.E+04 1k 1.E+05 10k 1.E+06 100k -50 1M -25 Frequency (Hz) FIGURE 2-8: CMRR, PSRR vs. Frequency with VDD = 5.0V. FIGURE 2-11: Temperature. 25 50 75 100 125 CMRR, PSRR vs. Ambient 2.5 55 45 Input Bias, Offset Currents (nA) Input Bias, Offset Currents (pA) 0 Ambient Temperature (C) Input Bias Current 35 25 15 5 Input Offset Current -5 TA = +85C VDD = 5.5V -15 -25 2.0 1.5 TA = +125 C VDD = 5.5V Input Bias Current 1.0 0.5 0.0 Input Offset Current -0.5 -1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-9: Input Bias, Input Offset Currents vs. Common Mode Input Voltage with TA = +85C. DS21810C-page 6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-12: Input Bias, Input Offset Currents vs. Common Mode Input Voltage with TA = +125C. 2004 Microchip Technology Inc. MCP6271/2/3/4/5 Note: Unless otherwise indicated, TA = +25C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 1000 Ouput Voltage Headroom (mV) 200 150 100 TA = +125C TA = +85C TA = +25C TA = -40C 50 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 100 10 VOL - VSS VDD - VOH 1 0.01 5.5 0.1 Power Supply Voltage (V) 120 0 100 -30 60 -90 Phase 0 -180 VDD = 5.5V 2.5 75 2.0 VDD = 2.0V 70 1.5 VDD = 5.5V 65 Phase Margin 1.0 55 1.E+08 -50 -25 0 25 50 75 100 50 125 Ambient Temperature (C) Open-Loop Gain, Phase vs. FIGURE 2-17: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. 10 1.8 Falling Edge, VDD = 5.5V 1.6 Slew Rate (V/s) VDD = 5.5V VDD = 2.0V 1 1.4 Falling Edge, VDD = 2.0V 1.2 1.0 0.8 Rising Edge, VDD = 5.5V 0.6 0.4 Rising Edge, VDD = 2.0V 0.2 1M 1.E+07 100k 1.E+06 10k 1.E+05 0.0 1k 1.E+04 0.1 1.E+03 Maximum Output Voltage Swing (VP-P) 60 VDD = 2.0V 0.5 Frequency (Hz) FIGURE 2-14: Frequency. 80 Gain Bandwidth Product 0.0 -210 10k 100k 1M 10M 100M 1.E+07 1k 1.E+06 100 1.E+05 10 1.E+04 1 1.E+03 -150 1.E+02 20 1.E+01 -120 1.E+00 40 Gain-Bandwidth Product (MHz) -60 Open-Loop Phase () Gain 0.1 10 FIGURE 2-16: Output Voltage Headroom vs. Output Current Magnitude. 3.0 80 1.E-01 Open-Loop Gain (dB) FIGURE 2-13: Quiescent Current vs. Power Supply Voltage. -20 1 Output Current Magnitude (mA) Phase Margin () Quiescent Current (A/amplifier) 250 10M -50 -25 Frequency (Hz) FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. 2004 Microchip Technology Inc. 0 25 50 75 100 125 Ambient Temperature (C) FIGURE 2-18: Temperature. Slew Rate vs. Ambient DS21810C-page 7 MCP6271/2/3/4/5 Note: Unless otherwise indicated, TA = +25C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 25 Input Noise Voltage Density (nV/Hz) Input Noise Voltage Density (nV/Hz) 1,000 100 10 1.E-01 1.E+00 0.1 1 1.E+01 1.E+02 10 100 1.E+03 1.E+04 1k 10k 1.E+05 f = 1 kHz 20 15 10 5 0 1.E+06 100k 1M 0.0 0.5 Frequency (Hz) FIGURE 2-19: vs. Frequency. Input Noise Voltage Density 30 25 20 TA = +125C TA = +85C TA = +25C TA = -40C 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.5 4.0 4.5 5.0 3.0 3.5 4.0 4.5 5.0 130 120 110 100 5.5 1 10 100 Frequency (kHz) FIGURE 2-20: Output Short-Circuit Current vs. Power Supply Voltage. FIGURE 2-23: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274). 700 VDD = 2.0 V VDD = 5.5V Op-Amp shuts off here 200 Op-Amp turns on here 150 Hysteresis 100 CS swept high to low CS swept low to high 50 600 Hysteresis 500 400 CS swept high to low Quiescent Current (A) Quiescent Current (A) 2.5 140 Power Supply Voltage (V) 250 2.0 FIGURE 2-22: Input Noise Voltage Density vs. Common Mode Input Voltage at 1 kHz. Channel-to-Channel Separation (dB) Ouptut Short Circuit Current (mA) 35 15 1.0 Common Mode Input Voltage (V) 300 200 CS swept low to high 100 Op-Amp toggles On/Off here 0 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Chip Select Voltage (V) FIGURE 2-21: Quiescent Current vs. Chip Select (CS) Voltage with VDD = 2.0V (MCP6273 and MCP6275 only). DS21810C-page 8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip-Select Voltage (V) FIGURE 2-24: Quiescent Current vs. Chip Select (CS) Voltage with VDD = 5.5V (MCP6273 and MCP6275 only). 2004 Microchip Technology Inc. MCP6271/2/3/4/5 Note: Unless otherwise indicated, TA = +25C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 5.0 5.0 G = +1V/V VDD = 5.0V 4.5 4.0 Output Voltage (V) Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 3.5 3.0 2.5 2.0 1.5 1.0 1.0 0.5 0.5 0.0 G = -1V/V VDD = 5.0V 4.5 -5 0 5 10 15 20 25 30 35 40 0.0 45 -5 0 5 10 15 FIGURE 2-25: Pulse Response. Large Signal Non-inverting FIGURE 2-28: Response. 25 30 35 40 45 Large Signal Inverting Pulse G = +1V/V Output Voltage (10 mV/div) Output Voltage (10 mV/div) G = -1V/V Time (2 s/div) FIGURE 2-26: Pulse Response. Time (2 s/div) Small Signal Non-inverting FIGURE 2-29: Response. 2.5 CS Voltage 2.0 1.5 Output On VOUT 1.0 0.5 Output High-Z 0.0 Small Signal Inverting Pulse 6.0 VDD = 2.0V G = +1V/V VIN = VSS Chip-Select, Output Voltages (V) Chip-Select, Output Voltages (V) 20 Time (5 s/div) Time (5 s/div) -5.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 Time (5 s/div) FIGURE 2-27: Chip Select (CS) to Amplifier Output Response Time with VDD = 2.0V (MCP6273 and MCP6275 only). 2004 Microchip Technology Inc. VDD = 5.5V G = +1V/V VIN = VSS 5.5 CS Voltage 5.0 4.5 4.0 3.5 VOUT 3.0 2.5 2.0 1.5 1.0 Output High-Z Output On 0.5 0.0 -5 0 5 10 15 20 25 30 35 40 45 Time (5 s/div) FIGURE 2-30: Chip Select (CS) to Amplifier Output Response Time with VDD = 5.5V (MCP6273 and MCP6275 only). DS21810C-page 9 MCP6271/2/3/4/5 3.0 APPLICATION INFORMATION - The MCP6271/2/3/4/5 family of op amps is manufactured using Microchip's state-of-the-art CMOS process, specifically designed for low-cost, low-power and general-purpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP6271/2/3/4/5 ideal for battery-powered applications. 3.1 RIN VIN ( Maximum expected V IN ) - VDD R IN ---------------------------------------------------------------------------------------2 mA V SS - ( Minimum expected V IN ) R IN -------------------------------------------------------------------------------------2 mA Rail-to-Rail Input The MCP6271/2/3/4/5 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 3-1 shows the input voltage exceeding the supply voltage without any phase reversal. FIGURE 3-2: Resistor (RIN). 3.2 Input, Output Voltage (V) 6 4 VOUT VIN Input Current Limiting Rail-to-Rail Output The output voltage range of the MCP6271/2/3/4/5 op amp is VDD - 15 mV (min.) and VSS + 15 mV (max.) when RL = 10 k is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-16 for more information. VDD = 5.0V G = +2 V/V 5 VOUT MCP6271 + 3 3.3 2 1 0 -1 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 Time (1 ms/div) FIGURE 3-1: The MCP6271/2/3/4/5 Show No Phase Reversal. The input stage of the MCP6271/2/3/4/5 op amp uses two differential input stages in parallel. One operates at low common mode input voltage (VCM) and the other at high VCM. With this topology, the device operates with VCM up to 300 mV above VDD and 300 mV below VSS. The Input Offset Voltage is measured at VCM = VSS - 300 mV and VDD + 300 mV to ensure proper operation. Input voltages that exceed the input voltage range (VSS - 0.3V to VDD + 0.3V at 25C) can cause excessive current to flow into or out of the input pins. Current beyond 2 mA can cause reliability problems. Applications that exceed this rating must be externally limited with a resistor, as shown in Figure 3-2. MCP6273/5 Chip Select (CS) The MCP6273 and MCP6275 are single and dual op amps with chip select (CS), respectively. When CS is pulled high, the supply current drops to 0.7 A (typ) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. If the CS pin is left floating, the amplifier may not operate properly. Figure 3-3 shows the output voltage and supply current response to a CS pulse. CS VIL VIH toff ton VOUT Hi-Z Hi-Z -170 A, typ IVSS ICS -0.7 A, typ 0.7 A, typ -0.7 A, typ 10 nA, typ 0.7 A, typ FIGURE 3-3: Timing Diagram for the Chip Select (CS) pin on the MCP6273 and MCP6275. DS21810C-page 10 2004 Microchip Technology Inc. MCP6271/2/3/4/5 3.4 Cascaded Dual Op Amps (MCP6275) 3.5 The MCP6275 is a dual op amp with chip select (CS). The chip select input is available on what would be the non-inverting input of a standard dual op amp (pin 5). This feature is provided by connecting the output of op amp A to the non-inverting input of op amp B, as shown in Figure 3-4. The chip select input, which can be connected to a microcontroller I/O line, puts the device in Low Power mode. Refer to Section 3.3 "MCP6273/5 Chip Select (CS)". VINB- VOUTA/VINB+ 1 VINA- VINA+ 6 2 B 3 7 VOUTB Capacitive Loads Driving large capacitive loads can cause stability problems for voltage-feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (RISO in Figure 3-5) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. A MCP6275 - CS VIN + VOUT CL Cascaded Gain Amplifier. The key issue to note from this configuration is that the output of op amp A is loaded by the input impedance. The input impedance of the op amp is typically 10136 pF, as specified in the DC specification table (Refer to Section 3.5 "Capacitive Loads" for further details regarding capacitive loads). The common mode input range of these op amps is specified in the data sheet as VSS - 300 mV and VDD + 300 mV. However, since the output of op amp A is limited to VOL and VOH (20 mV from the rails with a 10 k load), the non-inverting input range of op amp B is limited to the common mode input range of VSS + 20 mV and VDD - 20 mV. FIGURE 3-5: Output Resistor, RISO stabilizes large capacitive loads. Figure 3-6 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). 1,000 Recommended R ISO () FIGURE 3-4: RISO MCP6271 5 100 GN = 1 V/V GN = 2 V/V GN 4 V/V 10 10 100 1,000 10,000 Normalized Load Capacitance; CL / GN (pF) FIGURE 3-6: Recommended RISO values for Capacitive Loads. After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6271/2/3/4/5 SPICE macro model are very helpful. 2004 Microchip Technology Inc. DS21810C-page 11 MCP6271/2/3/4/5 3.6 Supply Bypass 3.8 With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good, high-frequency performance. It also needs a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other parts. 3.7 PCB Surface Leakage In applications where low input bias current is critical, printed circuit board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA, if current-to-flow. This is greater than the MCP6271/2/3/4/5 family's bias current at 25C (1 pA, typ.). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is illustrated in Figure 3-7. VIN- VIN+ Application Circuits 3.8.1 ACTIVE FULL-WAVE RECTIFIER The MCP6271/2/3/4/5 family of amplifiers can be used in applications such as an Active Full-Wave Rectifier or an Absolute Value circuit, as shown in Figure 3-8. The amplifier and feedback loops in this active voltage rectifier circuit eliminate the diode drop problem that exists in a passive voltage rectifier. This circuit behaves as a follower (the output follows the input) as long as the input signal is more positive than the reference voltage. If the input signal is more negative than the reference voltage, however, the circuit behaves as an inverting amplifier. Therefore, the output voltage will always be above the reference voltage, regardless of the input signal. R2 R1 VIN - MCP6272 R5 R3 + VSS VREF R4 D2 FIGURE 3-7: for Inverting Gain. 1. 2. DS21810C-page 12 MCP6272 Example Guard Ring Layout For Inverting (Figure 3-7) and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the common mode input voltage. D1 R1 = R 2 = R 3 = R 4 R1 R5 = -----R2 - Guard Ring VOUT B + A VREF Input VREF Output VREF time FIGURE 3-8: time Active Full-wave Rectifier. 2004 Microchip Technology Inc. MCP6271/2/3/4/5 3.8.2 NON-INVERTING INTEGRATOR The non-inverting integrator shown in Figure 3-9 is easy to build. It saves one op amp over the typical Miller Integrator plus inverting amplifier configuration. The phase accuracy of this integrator depends on the matching of the input and feedback resistors, and the capacitor's time constants. Rf is used to provide feedback at frequencies << 1/(2 RC). R1 VIN + C1 MCP6271 _ Rf VOUT 3.8.3 CASCADED OP AMPS APPLICATIONS The MCP6275 provides the flexibility of low power mode for dual op amps in an 8-pin package. The MCP6275 eliminates the added cost and space in a battery-powered application by using two single op amps with chip select lines or a 10-pin device with a chip select line for each op amp. The only inherent limitation to this device is that the two op amps are internally cascaded. Therefore, this device cannot be used in circuits that require active or passive elements between the two op amps. However, there are several applications where this op amp configuration with a chip select line becomes suitable. The circuits below show possible applications for this device. 3.8.3.1 C2 R2 FIGURE 3-9: Load Isolation With the cascaded op amp configuration, op amp B can be used to isolate the load from op amp A. In applications where op amp A is driving capacitive or low resistive loads in the feedback loop (such as an integrator or filter circuit) the op amp may not have sufficient source current to drive the load. In this case, op amp B can be used as a buffer. Non-Inverting Integrator. B VOUTB A MCP6275 CS FIGURE 3-10: Buffer. 3.8.3.2 Isolating the Load of a Cascaded Gain Figure 3-11 shows a cascaded gain circuit configuration with chip select. Op amps A and B are configured in a non-inverting amplifier configuration. In this configuration, it is important to note that the input offset voltage of op amp A is amplified by the gain of op amp A and B, as shown below: V OUT = V IN G A G B + V OSA G A G B + V OSB G B Where: GA = GB = VOSA = VOSB = op amp A gain op amp B gain op amp A offset voltage op amp B offset voltage Therefore, it is recommended that you set most of the gain with op amp A and use op amp B with relatively small gain, or as a unity-gain buffer. 2004 Microchip Technology Inc. DS21810C-page 13 MCP6271/2/3/4/5 R4 R3 R2 C1 R1 R1 B B VOUT A VIN MCP6275 MCP6275 CS CS FIGURE 3-11: Configuration. 3.8.3.3 Cascaded Gain Circuit FIGURE 3-13: Compensation. Difference Amplifier 3.8.3.5 Figure 3-12 shows op amp A configured as a difference amplifier with chip select. In this configuration, it is recommended that well-matched resistors (0.1%) be used to increase the common mode rejection ratio (CMRR). Op amp B can be used to provide additional gain and isolate the load from the difference amplifier. R4 R2 VOUT A VIN Integrator Circuit with Active Second-Order MFB with an extra pole-zero pair Figure 3-14 is a second-order multiple feedback lowpass filter with chip select. Use the Filterlab(R) software from Microchip to determine the R and C values for op amp A's second-order filter. Op amp B can be used to add a pole-zero pair using C3 and R6. R3 R6 R1 R1 VIN2 C3 C1 B R2 VOUT MCP6275 R1 CS FIGURE 3-12: 3.8.3.4 R2 VIN A VIN1 R3 Difference Amplifier Circuit. Integrator with Active Compensation and a Chip Select C2 R5 R4 B A VOUT MCP6275 CS FIGURE 3-14: Second-Order Multiple Feedback Low-Pass Filter with an Extra PoleZero Pair and Chip Select. Figure 3-13 uses an active compensator (op amp B) to compensate for the non-ideal characteristics introduced at higher frequency integration. The alternative is to use a passive element (such as a resistor) for compensation. However, the quality of compensation would not be constant since the AC characteristics of an amplifier vary over temperature and process. This circuit uses op amp B as a unity-gain buffer to isolate the integration capacitor C1 from op amp A and drives the capacitor with a low-impedance source. Since both amplifiers are matched very well, it provides a higher quality of integration. DS21810C-page 14 2004 Microchip Technology Inc. MCP6271/2/3/4/5 3.8.3.6 Second-Order Sallen-Key with an Extra Pole-Zero Pair Figure 3-15 is a second-order Sallen-Key low-pass filter with chip select. Use the Filterlab(R) software from Microchip to determine the R and C values for the op amp A's second-order filter. Op amp B can be used to add a pole-zero pair using C3 and R5. R2 R4 R3 VIN R1 R5 C3 B A C2 Capacitorless Second Order Low-Pass filter with Chip Select The low-pass filter shown in Figure 3-16 does not require external capacitors and uses only three external resistors, while the op amp's GBWP sets the corner frequency. R1 and R2 are used to set the circuit gain. R3 is used to set the Q. To avoid gain-peaking in the frequency response, Q needs to be low (lower values need to be selected for R3). Note that the amplifier bandwidth varies greatly over temperature and process. This configuration, however, provides a lowcost solution for applications with high bandwidth. VOUT MCP6275 C1 3.8.3.7 VIN R1 R2 R3 CS A B FIGURE 3-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and a Chip Select. VREF VOUT MCP6275 CS FIGURE 3-16: Capacitorless Second-Order Low-Pass Filter with Chip Select Circuit. 2004 Microchip Technology Inc. DS21810C-page 15 MCP6271/2/3/4/5 4.0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6271/2/3/4/5 family of op amps. 4.1 SPICE Macro Model The latest version of the SPICE Macro Model for the MCP6271/2/3/4/5 op amp is available on our web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation at room temperature. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 4.2 FilterLab(R) Software The FilterLab software is an innovative tool that simplifies analog active-filter (using op amps) design. Available at no cost from our web site (www.microchip.com), the FilterLab active-filter software design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. DS21810C-page 16 2004 Microchip Technology Inc. MCP6271/2/3/4/5 5.0 PACKAGING INFORMATION 5.1 Package Marking Information Example: 8-Lead MSOP XXXXXX 6271 YWWNNN 406256 8-Lead PDIP (300 mil) Example: XXXXXXXX XXXXXNNN YYWW MCP6271 E/P256 0406 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Legend: Note: * XX...X YY WW NNN Example: MCP6271 E/SN0406 256 Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. 2004 Microchip Technology Inc. DS21810C-page 17 MCP6271/2/3/4/5 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6274) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) (MCP6274) XXXXXXXXXX XXXXXXXXXX YYWWNNN 14-Lead TSSOP (MCP6274) XXXXXX YYWW NNN DS21810C-page 18 Example: MCP6274-E/P 0409057 Example: MCP6274ESL 0409057 Example: 6274ST 0409 057 2004 Microchip Technology Inc. MCP6271/2/3/4/5 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 A2 A c A1 (F) L Units Dimension Limits n p MIN INCHES NOM MAX MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0 0.08 0.22 5 5 - MIN 8 Number of Pins .026 BSC Pitch A .043 Overall Height A2 .030 .033 .037 Molded Package Thickness A1 .000 .006 Standoff E .193 TYP. Overall Width E1 .118 BSC Molded Package Width D .118 BSC Overall Length L .016 .024 .031 Foot Length Footprint (Reference) F .037 REF 0 8 Foot Angle c Lead Thickness .003 .006 .009 Lead Width B .009 .012 .016 55 15 Mold Draft Angle Top 55 -15 Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. MAX 1.10 0.95 0.15 0.80 8 0.23 0.40 15 15 JEDEC Equivalent: MO-187 Drawing No. C04-111 2004 Microchip Technology Inc. DS21810C-page 19 MCP6271/2/3/4/5 8-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c A1 B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B1 B eB MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS21810C-page 20 2004 Microchip Technology Inc. MCP6271/2/3/4/5 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A2 A L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 2004 Microchip Technology Inc. DS21810C-page 21 MCP6271/2/3/4/5 14-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c A1 B1 eB p B Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width .240 .250 .260 E1 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS21810C-page 22 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 2004 Microchip Technology Inc. MCP6271/2/3/4/5 14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A2 A A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 2004 Microchip Technology Inc. DS21810C-page 23 MCP6271/2/3/4/5 14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP) E E1 p D 2 1 n B A c A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B1 MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 A2 MAX .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS21810C-page 24 2004 Microchip Technology Inc. MCP6271/2/3/4/5 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Examples: a) b) c) Device: MCP6271: MCP6271T: MCP6272: MCP6272T: MCP6273: MCP6273T: MCP6274: MCP6274T: MCP6275: MCP6275T: Single Operational Amplifier Single Operational Amplifier (Tape and Reel) (SOIC, MSOP) Dual Operational Amplifiers Dual Operational Amplifiers (Tape and Reel) (SOIC, MSOP) Single Operational Amplifier with Chip Select Single Operational Amplifier with Chip Select (Tape and Reel) (SOIC, MSOP) Quad Operational Amplifiers Quad Operational Amplifiers (Tape and Reel) (SOIC, TSSOP) Dual Operational Amplifier with Chip Select Dual Operational Amplifier with Chip Select (Tape and Reel) (SOIC, MSOP) Temperature Range: E = -40C to +125C Package: MS P SN SL ST = = = = = d) a) b) c) d) a) b) c) d) Plastic MSOP, 8-lead Plastic DIP (300 mil Body), 8-lead, 14-lead Plastic SOIC, (150 mil Body), 8-lead Plastic SOIC (150 mil Body), 14-lead Plastic TSSOP (4.4mm Body), 14-lead MCP6271-E/SN: Extended Temperature, 8LD SOIC package. MCP6271-E/MS: Extended Temperature, 8LD MSOP package. MCP6271-E/P: Extended Temperature, 8LD PDIP package. MCP6271T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. MCP6272-E/SN: Extended Temperature, 8LD SOIC package. MCP6272-E/MS: Extended Temperature, 8LD MSOP package. MCP6272-E/P: Extended Temperature, 8LD PDIP package. MCP6272T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. MCP6273-E/SN: Extended Temperature, 8LD SOIC package. MCP6273-E/MS: Extended Temperature, 8LD MSOP package. MCP6273-E/P: Extended Temperature, 8LD PDIP package. MCP6273T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. a) MCP6274-E/P: b) MCP6274T-E/SL: c) MCP6274-E/SL: d) MCP6274-E/ST: a) MCP6275-E/SN: b) c) d) Extended Temperature, 14LD PDIP package. Tape and Reel, Extended Temperature, 14LD SOIC package. Extended Temperature, 14LD SOIC package. Extended Temperature, 14LD TSSOP package. Extended Temperature, 8LD SOIC package. MCP6275-E/MS: Extended Temperature, 8LD MSOP package. MCP6275-E/P: Extended Temperature, 8LD PDIP package. MCP6275T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2004 Microchip Technology Inc. DS21810C-page 25 MCP6271/2/3/4/5 NOTES: DS21810C-page 26 2004 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2004 Microchip Technology Inc. DS21810C-page 27 WORLDWIDE SALES AND SERVICE AMERICAS China - Beijing Korea Corporate Office Unit 706B Wan Tai Bei Hai Bldg. No. 6 Chaoyangmen Bei Str. Beijing, 100027, China Tel: 86-10-85282100 Fax: 86-10-85282104 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Chengdu 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: www.microchip.com 3780 Mansell Road, Suite 130 Alpharetta, GA 30022 Tel: 770-640-0034 Fax: 770-640-0307 Rm. 2401-2402, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599 Boston China - Fuzhou 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821 Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521 Atlanta Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 Kokomo 2767 S. Albright Road Kokomo, IN 46902 Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 San Jose 1300 Terra Bella Avenue Mountain View, CA 94043 Tel: 650-215-1444 Fax: 650-961-0286 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Australia Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Hong Kong SAR Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Singapore Taiwan Kaohsiung Branch 30F - 1 No. 8 Min Chuan 2nd Road Kaohsiung 806, Taiwan Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE China - Shanghai Austria Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark China - Shenzhen Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45-4420-9895 Fax: 45-4420-9910 Rm. 1812, 18/F, Building A, United Plaza No. 5022 Binhe Road, Futian District Shenzhen 518033, China Tel: 86-755-82901380 Fax: 86-755-8295-1393 China - Shunde Room 401, Hongjian Building, No. 2 Fengxiangnan Road, Ronggui Town, Shunde District, Foshan City, Guangdong 528303, China Tel: 86-757-28395507 Fax: 86-757-28395571 China - Qingdao Rm. B505A, Fullhope Plaza, No. 12 Hong Kong Central Rd. Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205 India Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-22290061 Fax: 91-80-22290062 Japan Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 France Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands Waegenburghtplein 4 NL-5152 JR, Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 05/28/04 DS21810C-page 28 2004 Microchip Technology Inc.