2004 Microchip Technology Inc. DS21810C-page 1
MCP6271/2/3/4/5
Features
• 2 MHz Gain Bandwidth Product (typ.)
• Supply Current: IQ = 170 µA (typ.)
• Supply Voltage: 2.0V to 5.5V
• Rail-to-Rail Input/Output
• Extended Temperature Range: -40°C to +125°C
• Available in Single, Dual and Quad Packages
• Single with Chip Select (CS) (MCP6273)
• Dual with Chip Select (CS) (MCP6275)
Applications
• Automotive
• Port ab le Equi pm ent
• Photo Diode Pre-amps
• Analog Filters
• Notebooks and PDAs
• Battery-Pow e red Sys tems
Available Tools
• SPICE Macro Model (at www.microchip.com)
•FilterLab
® Software (at www.microchip.com)
Typical Applications
Description
The Microchip Technology Inc. MCP6271/2/3/4/5 family
of operational amplifiers (op amps) provide wide
bandwidth for the current. This family has a 2 MHz gain
bandwidth product (GBWP) and a 65° phase margin.
This family also operates from a single supply voltage
as low as 2.0V, while drawing 170 µA (typ.) quiescent
current. Additionally, the MCP6271/2/3/4/5 supports
rail-to-rail input and output swing, with a common mode
input voltage ra nge of VDD +300mV to V
SS – 300 mV.
This family of operational amplifiers is designed with
Microchip’ s advanced CMOS process.
The MCP6275 has a chip select input (CS) for dual op
amps in an 8-pin package and is manufactured by
cascading two op amps (the output of op amp A
connected to the non-inverting input of op amp B). The
chip select input puts the device in Low Power mode.
The MCP6271 /2/3 /4/5 family ope rate s in th e Exte nde d
Temperature Range of -40°C to +125°C, with a power
supply range of 2.0V to 5.5V.
Package Types
AB
CS
R1R2R3R4
2
3
5
6
7
VIN
VOUT
Cascaded Gain with Chip Select
MCP6275
1
VIN_
MCP6271
VDD
1
2
3
4
8
7
6
5
-
+
NC
NC
NC
VIN+
VSS
MCP6272
PDIP, SOIC, MSOP
MCP6274
1
2
3
4
14
13
12
11
-+-
+
10
9
8
5
6
7
+
--
+
PDIP, SOIC, TSSOP
1
2
3
4
8
7
6
5
-
+-
+
VOUT
MCP6273
1
2
3
4
8
7
6
5
-
+
VINA_
VINA+
VSS
VOUTA
VOUTB
VDD
VINB_
VINB+
VSS
VIN+
VIN_
NC CS
VDD
VOUT
NC
VOUTA
VINA_
VINA+
VDD VSS
VOUTB
VINB_
VINB+
VOUTC
VINC_
VINC+
VOUTD
VIND_
VIND+
PDIP, SOIC, MSOP
PDIP, SOIC, MSOP
MCP6275
PDIP, SOIC, MSOP
1
2
3
4
8
7
6
5
+-
VINA_
VINA+
VSS
VOUTA / VINB+
VOUTB
VDD
VINB_
CS
-+
170 µA, 2 M Hz Rail-to-Rail Op Amp
MCP6271/2/3/4/5
DS21810C-page 2 2004 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
All Inputs and Outputs ...................VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short Circuit Current .............................. .. ..continuous
Current at Input Pins ................ .. .... .... .... ......... .. .... .... ...±2 mA
Current at Output and Supply Pins ............................ ±30 mA
Storage Temperature................. .. .. .. .. .. .... ..... .-65°C to +150°C
Junction Temperature (TJ) ..........................................+150°C
ESD Protection On All Pins (HBM/MM)................≥ 4 kV/400V
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
PIN FUNCTION TABLE
Name Function
VIN+, V INA+, VINB+, VINC+, VIND+ Non-inverting Inputs
VIN_, VINA_, VINB_, VINC_, VIND_Inverting Inputs
VDD Positive Power Supply
VSS Negative Power Supply
VOUT, VOUTA, VOUTB, VOUTC,
VOUTD
Outputs
NC No Internal Connection
CS Chip Select
VOUTA/VINB+ Output of op amp A and
non-inverting input of op
amp B (MCP6275)
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, R L = 10 kΩ
to VDD/2 and VOUT ≈VDD/2.
Parameters Sym Min Typ Max Units Conditions
Input Of fset
Input Offset Voltage VOS -3.0 — +3.0 mV VCM = VSS (Note 1)
Input Offset Voltage
(Extended Tem perat ure) VOS -5.0 — +5.0 mV TA= -40°C to +125°C,
VCM = VSS (Note 1)
Input Offset Temperature Drift ∆VOS/∆TA—±1.7—µV/°CT
A= -40°C to +125°C,
VCM = VSS (Note 1)
Power Supply Rejection PSRR 70 90 — dB VCM = VSS (Note 1)
Input Bias Cu r r e nt and Impedance
Input Bias Current IB— ±1.0 — pA Note 2
At Temperature IB— 50 200 pA TA= +85°C (Note 2)
At Temperature IB—2 5nAT
A= +125°C (Note 2)
Input Offset Current IOS — ±1.0 — pA Note 3
Common Mode Input Impedance ZCM —10
13||6 — Ω||pF Note 3
Differential Input Impedance ZDIFF —10
13||3 — Ω||pF Note 3
Common Mode (Note 4)
Common Mode Input Range VCMR VSS −0.3 — VDD +0.3 V Note 4
Common Mode Rejection Ratio CMRR 70 85 — dB VCM = -0.3V to 2.5V, VDD = 5V
Common Mode Rejection Ratio CMRR 65 80 — dB VCM = -0.3V to 5.3V, VDD = 5V
Note 1: The MCP6275’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
2: The current at the MCP6275’s VINB– pin is specified by IB only.
3: This specification does not apply to the MCP6275’s VOUTA/VINB+ pin.
4: The MCP6275’s VINB– pin (o p am p B ) h as a c om m on m ode rang e ( VCMR) of VSS + 100 mV to
VDD – 100 m V. The MCP62 75’s VOUTA/VINB+ pin (op amp B) has a voltage r ange spe cified by V OH and VOL.
2004 Microchip Technology Inc. DS21810C-page 3
MCP6271/2/3/4/5
AC ELECTRICAL SPECIFICATIONS
TEMPERATURE SPECIFICATIONS
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 90 110 — dB VOUT = 0.2V to VDD - 0.2V,
VCM =V
SS, Note 1
Output
Maximum Output Voltage Swing VOL, VOH VSS +15 — V
DD −15 mV
Output Short-Circuit Current ISC —±25—mA
Power Supply
Supply Voltage VDD 2.0 — 5.5 V
Quiescent Current per Amplifier IQ100 170 240 µA IO = 0
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 2.0 — MHz
Phase Margin at Unity Gain PM — 65 — °
Slew Rate SR — 0.9 — V/µs
Noise
Input Noise Voltage Eni —3.5 — µVp-p f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —20 — nV/√Hz f = 1 kHz
Input Noise Current Density ini —3—fA/√Hz f = 1 kHz
Electrical Characteristics: Unless otherwise indicated, VDD = +2.0V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Temperat ure Range TA-40 — +125 °C Note
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-PDIP θJA —85—°C/W
Thermal Resistance, 8L-SOIC θJA — 163 — °C/W
Thermal Resistance, 8L-MSOP θJA — 206 — °C/W
Thermal Resistance, 14L-PDIP θJA —70 —°C/W
Thermal Resistance, 14L-SOIC θJA —120 —°C/W
Thermal Resistance, 14L-TSSOP θJA —100 —°C/W
Note: The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, R L = 10 kΩ
to VDD/2 and VOUT ≈VDD/2.
Parameters Sym Min Typ Max Units Conditions
Note 1: The MCP6275’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
2: The current at the MCP6275’s VINB– pin is specified by IB only.
3: This specification does not apply to the MCP6275’s VOUTA/VINB+ pin.
4: The MCP6275’s VINB– pin (o p am p B ) h as a c om m on m ode rang e ( VCMR) of VSS + 100 mV to
VDD – 100 m V. The MCP62 75’s VOUTA/VINB+ pin (op amp B) has a voltage r ange spe cified by V OH and VOL.
MCP6271/2/3/4/5
DS21810C-page 4 2004 Microchip Technology Inc.
MCP6273/MCP6275 CHIP SELECT (CS) SPECIFICATIONS
Electrical Characteris tics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logi c Threshold, Low VIL VSS —0.2V
DD V
CS Input Current, Low ICSL —0.01— µACS = VSS
CS High Specifications
CS Logi c Threshold, High VIH 0.8 VDD —V
DD V
CS Input Current, High ICSH —0.7 2 µACS = VDD
GND Current IQ—-0.7— µACS = VDD
Amplifier Output Leakage — — 0.01 — µA CS = VDD
Dynamic Specifications (Note 1)
CS Low to Valid Amplifier
Output, Turn-on Time tON —410µsCS Low ≤ 0.2 VDD, G = +1 V/V,
VIN = V DD/2, VOUT = 0.9 VDD/2,
VDD = 5.0V
CS High to Amplifier Output
High-Z tOFF —0.01— µsCS High ≥ 0.8 VDD, G = +1 V/V,
VIN = V DD/2, VOUT = 0.1 VDD/2
Hysteresis VHYST —0.6— VV
DD = 5V
Note 1: The input condition (VIN) specified applies to both op amp A and B of the MCP6275. The dynamic
specification is tested at the output of op amp B (VOUTB).
2004 Microchip Technology Inc. DS21810C-page 5
MCP6271/2/3/4/5
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Bias Current with
TA = +85°C.
FIGURE 2-3: Input Offset Volt age vs.
Common Mode Input Voltage with VDD = 2.0V.
FIGURE 2-4: Input Offset Voltage Drift.
FIGURE 2-5: Input Bias Current with
TA = +125°C.
FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 5.5V.
Note: The g r ap hs and t ables prov id ed followi ng thi s n ote are a st a tis tic al s umm ar y based on a limite d number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
-3.0
-2.4
-1.8
-1.2
-0.6
0.0
0.6
1.2
1.8
2.4
3.0
Input Offset Voltage (mV)
Percentage of Occurrences
832 Samples
VCM = VSS
0%
4%
8%
12%
16%
20%
24%
28%
32%
0 102030405060708090100
Input Bias Current (pA)
Percentage of Occurrences
422 Samples
TA = +85 °C
-100
-50
0
50
100
150
200
250
300
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 2.0 V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0%
2%
4%
6%
8%
10%
12%
14%
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
10
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
832 Samples
VCM = VSS
TA = -40°C to +125°C
0%
4%
8%
12%
16%
20%
24%
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Input Bias Current (nA)
Percentage of Occurrences
422 Samples
TA = +125 °C
-100
-50
0
50
100
150
200
250
300
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5 V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
MCP6271/2/3/4/5
DS21810C-page 6 2004 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-7: Input Offset Volt age vs.
Output Voltage.
FIGURE 2-8: CMRR, PSRR vs.
Frequency with VDD = 5.0V.
FIGURE 2-9: Input Bias, Input Offset
Currents vs. Common Mode Input Voltage with
TA = +85°C.
FIGURE 2-10: Input Bias, Input Offset
Currents vs. Ambient Temperature.
FIGURE 2-11: CMRR, PSRR vs. Ambient
Temperature.
FIGURE 2-12: Input Bias, Input Offset
Currents vs. Common Mode Input Voltage with
TA = +125°C.
-100
-50
0
50
100
150
200
250
300
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage (µV)
VDD = 2.0V
VCM = VSS
Representative Part
VDD = 5.5V
20
30
40
50
60
70
80
90
100
110
1.E+00 1.E+ 01 1.E+02 1. E+03 1.E+0 4 1.E+05 1.E+06
Frequency (Hz)
CMRR, PSRR (dB)
VDD = 5.0V
1 10k 100k 1M10010 1k
PSRR+
PSRR-
CMRR
-25
-15
-5
5
15
25
35
45
55
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(pA)
TA = +85°C
VDD = 5.5V
Input Bias Current
Input Of f s e t Current
1
10
100
1,000
10,000
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias, Offset Currents
(pA)
Input Bias Current
Input Offset Current
VCM = VDD
VDD = 5.5V
60
70
80
90
100
110
120
-50 -25 0 25 50 75 100 12
5
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR
VCM = VSS
CMRR
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
0.00.51.01.52.02.53.03.54.04.55.05.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(nA)
TA = +125 °C
VDD = 5.5V
Input Bias Current
Input Offset Current
2004 Microchip Technology Inc. DS21810C-page 7
MCP6271/2/3/4/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-13: Quiescent Current vs.
Power Supply Voltage.
FIGURE 2-14: Open-Loop Gain, Phase vs.
Frequency.
FIGURE 2-15: Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-16: Output Voltage Headroom
vs. Output Current Magnitude.
FIGURE 2-17: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
FIGURE 2-18: Sl ew Rate vs . Ambien t
Temperature.
0
50
100
150
200
250
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5.5
Power Supply Voltage (V)
Quiescent Current
(µA/amplifier)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
-20
0
20
40
60
80
100
120
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Frequen cy (Hz)
Open-Loop Gain (dB)
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
Gain
Phase
0.1 1 10 100 1k 10k 100k 1M 10M 100M
0.1
1
10
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequen cy (Hz)
Maximum Output Voltage
Swing (VP-P)
VDD = 2.0V
1k 10k 100k 1M
VDD = 5.5V
10M
1
10
100
1000
0.01 0.1 1 10
Output Current Magnitude (mA)
Ouput Voltage Headroom (mV)
VOL - VSS
VDD - VOH
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Gain-Bandwidth Product
(MHz)
50
55
60
65
70
75
80
Phase Margin (°)
Gain Bandwidth Produc t
VDD = 5.5V
VDD = 2.0V
VDD = 2.0V
VDD = 5.5V
Phase Margin
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/µs)
Rising Edge, VDD = 2.0V
Rising Edge, VDD = 5.5V
Fallin g Edge, VDD = 2.0V
Falling Edge, VDD = 5.5V
MCP6271/2/3/4/5
DS21810C-page 8 2004 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-19: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-20: Output Short-Circuit Current
vs. Power Supply Voltage.
FIGURE 2-21: Quiescent Current vs. Chip
Select (CS) Voltage with VDD = 2.0V (MCP6273
and MCP6275 only).
FIGURE 2-22: Input Noise Voltage Density
vs. Common Mode Input Voltage at 1 kHz.
FIGURE 2-23: Channel-to-Channel
Separation vs. Frequency (MCP6272 and
MCP6274).
FIGURE 2-24: Quiescent Current vs. Chip
Select (CS) Voltage with VDD = 5.5V (MCP6273
and MCP6275 only).
10
100
1,000
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
Input Noise Voltage Density
(nV/Hz)
0.1 10010 1k 100k10k 1M1
0
5
10
15
20
25
30
35
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Ouptut Short Circuit Current
(mA)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
50
100
150
200
250
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Chip Select Voltage (V)
Quiescent Current (µA)
Hysteresis
Op-Amp shuts off here
Op-Amp turns on here
VDD = 2.0 V
CS swept
high to low CS swept
low to high
0
5
10
15
20
25
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/¥Hz)
f = 1 kHz
100
110
120
130
140
1 10 100
Frequency (kHz)
Channel-to-Channel Separation
(dB)
0
100
200
300
400
500
600
700
0.00.51.01.52.02.53.03.54.04.55.05.5
Chip-Select Voltage (V)
Quiescent Current (µA)
Hysteresis
Op-Amp toggles On/Off here
VDD = 5.5V
CS swept
low to high
CS swept
high to l ow
2004 Microchip Technology Inc. DS21810C-page 9
MCP6271/2/3/4/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-25: Large Signal Non-inverting
Pulse Response.
FIGURE 2-26: Small Signal Non-inverting
Pulse Response.
FIGURE 2-27: Chip Select (CS) to
Amplifier Output Response Time with VDD = 2.0V
(MCP6273 and MCP6275 only).
FIGURE 2-28: Large Signal Inverting Pulse
Response.
FIGURE 2-29: Small Signal Inverting Pulse
Response.
FIGURE 2-30: Chip Select (CS) to
Amplifier Output Response Time with VDD = 5.5V
(MCP6273 and MCP6275 only).
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-5 0 5 10 15 20 25 30 35 40 45
Time (5 µ s /div)
Output Voltage (V)
G = +1V/V
VDD = 5.0V
Time (2 µs/div)
Output Voltage (10 mV/div)
G = +1V/V
0.0
0.5
1.0
1.5
2.0
2.5
-5.0 0.0 5.0 10. 0 15.0 20.0 25. 0 30.0 35.0 40 .0 45.0
Time (5 µ s /div)
Chip-Select, Output Voltages
(V)
VOUT Output On
Output H igh-Z
VDD = 2.0V
G = +1V/V
VIN = VSS
CS Voltage
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-5 0 5 10 15 20 25 30 35 40 45
Time (5 µ s /div)
Output Voltage (V)
G = -1V/V
VDD = 5.0V
Time (2 µs/div)
Output Voltage (10 mV/div)
G = -1V/V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-5 0 5 1 0 15 20 25 30 35 40 4 5
Time (5 µs/div)
Chip-Select, Output Voltages
(V)
VOUT
Output OnOutpu t High-Z
VDD = 5.5V
G = +1V/V
VIN = VSS
CS Voltage
MCP6271/2/3/4/5
DS21810C-page 10 2004 Microchip Technology Inc.
3.0 APPLICATION INFORMATION
The MCP6271/2/3/4/5 family of op amps is manufac-
tured using Micro chip’s st ate-of-the-art CMOS process,
specifically designed for low-cost, low-power and
general-purpose applications. The low supply voltage,
low quiescent current and wide bandwidth makes the
MCP6271/2/3/4/5 ideal for battery-powered
applications.
3.1 Rail-to-Rail Input
The MCP6271/2/3/4/5 op amps are designed to
prevent pha se rev ersal w hen t he inpu t pins excee d the
supply voltages. Figure 3-1 shows the input voltage
exceeding the supply voltage without any phase
reversal.
FIGURE 3-1: The MCP6271/2/3/4/5 Show
No Phase Reversal.
The input stage of the MCP6271/2/3/4/5 op amp uses
two di ffer ential in put sta ges in p arallel . One op erates at
low co mmon mode input v oltage (VCM) and the othe r at
high V CM. With this topology, the device operates with
VCM up to 300 mV above VDD and 300 mV below VSS.
The Input Offset Voltage is measured at
VCM =V
SS – 300 mV and VDD + 300 mV to ensure
proper operation.
Input voltages that exceed the input voltage range
(VSS – 0.3V to VDD + 0.3V at 25°C) can cause
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 3-2.
FIGURE 3-2: Input Current Limiting
Resistor (RIN).
3.2 Rail-to-Rail Output
The output voltage range of the MCP6271/2/3/4/5 op
amp is VDD –15mV (min.) and V
SS +15mV (max.)
when RL=10kΩ is connected to VDD/2 and
VDD = 5.5V. Refer to Figure 2-16 for more information.
3.3 MCP6273/5 Chip Select (CS)
The MCP6273 and MCP6275 are single and dual op
amps with chip select (CS), respectively. When CS is
pulled h igh, the supply current drops to 0.7 µA (typ) an d
flows through the CS pin to VSS. When this happens,
the amplifier output is put into a high-impedance state.
By pulli ng CS low , the am plifier is e nabled. If the CS pin
is left floating, the amplifier may not operate properly.
Figur e 3-3 shows the output volt age and su pply current
response to a CS pulse .
FIGURE 3-3: Timing Diagram for the Chip
Select (CS) pin on the MCP6273 and MCP6275.
-1
0
1
2
3
4
5
6
-15 -14 -1 3 -12 -11 -10 -9 -8 -7 -6 -5
Time (1 ms/div)
Input, Output Voltage (V)
VDD = 5.0V
G = +2 V/V
VIN VOUT
RIN VSS Minimum expected VIN
()–
2 mA
--------------------------------------------------------------------------------------
≥
RIN Maximum expected VIN
()VDD
–
2 mA
----------------------------------------------------------------------------------------
≥
VIN
RIN VOUT
–
+
MCP6271
VIL
Hi-Z
ton
VIH
CS
toff
VOUT
-0.7 µA, typ
Hi-Z
IVSS
ICS 0.7 µA, typ 0.7 µA, typ
-0.7 µA, typ
-170 µA, typ
10 nA, typ
2004 Microchip Technology Inc. DS21810C-page 11
MCP6271/2/3/4/5
3.4 Cascaded Dual Op Amps
(MCP6275)
The MCP6275 is a dual op amp with chip select (CS).
The chip sel ec t inp ut is av ai lab le o n w hat would be the
non-inverting input of a standard dual op amp (pin 5).
This feature is provided by connecting the output of op
amp A to the non-inve rting input of op amp B, as shown
in Figure 3-4. The chip select input, which can be con-
nec ted to a m icroc ontroll er I/O li ne, puts the d evice in
Low Power mode. Refer to Section 3.3 “MCP6273/5
Chip Select (CS)”.
FIGURE 3-4: Cascaded Gain Amplifier.
The key issue to note from this configuration is that the
output of op amp A is loaded by the input impedance.
The input impedance of the op amp is typically
1013Ω6 pF, as specified in the DC specification t able
(Refer to Secti on 3.5 “Capacitive Loads” for furthe r
details regarding capacitive loads).
The common mode input range of these op amps is
specified in the data sheet as VSS – 300 mV and
VDD + 300 mV. However, since the output of op amp A
is limited to VOL and VOH (20 mV from the rails with a
10 kΩ load), the n on-i nv erti ng i npu t range of op amp B
is limited to the common mode input range of
VSS + 20 mV and VDD –20mV.
3.5 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage-feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensit ive to c apa citiv e load s, thoug h all g ain s show th e
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 3-5) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The band-
wid th will be g enerally low er than the bandwidth with no
capacitive load.
FIGURE 3-5: Output Resistor, RISO
stabilizes large cap acitive loads.
Figure 3-6 gives recommended RISO values for differ-
ent capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit 's noise gain. For non-inverti ng gains, GN an d the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 3-6: Recommended RISO values
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation and simula-
tions with the MCP6271/2/3/4/5 SPICE macro model
are very helpful.
AB
CS
2
3
5
6
7
VINA+
VOUTB
MCP6275
1
VINA–
VOUTA/VINB+VINB–
VIN
RISO VOUT
CL
–
+
MCP6271
10
100
1,000
10 100 1,000 10,00
0
Normalize d Load Capaci tan ce; CL / GN (pF)
Recommended RISO (Ω)
GN = 1 V/V
GN = 2 V/V
GN ≥ 4 V/V
MCP6271/2/3/4/5
DS21810C-page 12 2004 Microchip Technology Inc.
3.6 Supply Bypass
With this family of operational amplifiers, the power
suppl y pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
prov ide large, slow curr ents. This b ulk cap acitor can be
shared with other parts.
3.7 PCB Surface Leakage
In applications where low input bias current is critical,
printed circuit board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
betwee n nearby traces is 1012Ω. A 5 V dif ference would
cause 5 pA, if current-to-flow. This is greater than the
MCP6271/2/3/4/5 family’s bias current at 25°C (1 pA,
typ.).
The easiest way to reduce surface leakage is to use a
guard ring around se ns itive pins (or tr ac es) . The gua rd
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is illustrated in
Figure 3-7.
FIGURE 3-7: Example Guard Ring Layout
for Inverting Gain.
1. For Inverting (Figure 3-7) and Transimpedance
Amplifiers (convert current to voltage, such as
photo detectors):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground ).
b. Connect the inverting pin (VIN–) to the inp ut
with a wire that does not touch the PCB
surface.
2. Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (VIN–). This bias es th e g uard ri ng t o th e
common mode input voltage.
3.8 Application Circuits
3.8.1 ACTIVE FULL-WAVE RECTIFIER
The MCP6271/2/3/4/5 fami ly of am pl ifi ers can be u sed
in applic ations su ch as an Acti ve Full-W av e Rectifi er or
an Absolute Value circuit, as shown in Figure 3-8. The
amplifier and feedback loops in this active voltage
rectifier circuit eliminate the diode drop problem that
exists in a passive voltage rectifier . This circuit behaves
as a follower (the output follows the input) as long as
the input signal is more positive than the reference
voltage. If the input signal is more negative than the
reference voltage, however, the circuit behaves as an
inverting amplifier. Therefore, the output voltage will
always be above the reference voltage, regardless of
the input signal.
FIGURE 3-8: Active Full-wave Rectifier.
Guard Ring
VSS
VIN–V
IN+
–
+
MCP6272
–
+
MCP6272
VIN
VOUT
VREF
VREF
R1
R3
R4
R5
R2
A
B
D1
D2
VREF VREF
time time
Input Output
R5R1
R2
------
=
R1R2R3R4
===
2004 Microchip Technology Inc. DS21810C-page 13
MCP6271/2/3/4/5
3.8.2 NON-INVERTING INTEGRATOR
The non-inverting integrator shown in Figure 3-9 is easy
to build. It saves one op amp over the typical Miller
Integrator plus inverting amplifier configuration. The
phase accuracy of this integrator depends on the
matching of the input and feedback resistors, and the
capacitor’s time constants. Rf is used to provide
feedback at frequencies << 1/(2 πRC).
FIGURE 3-9: Non-Inverting Integrator.
3.8.3 CASCADED OP AMPS
APPLICATIONS
The MCP6275 provides the flexibility of low power
mode for dual op amps in an 8-pin package. The
MCP6275 eliminates the added cost and space in a
battery-powered application by using two single op
amps with chip select lines or a 10-pin device with a
chip select line for each op amp. The only inherent
limitation to this device is that the two op amps are
internally cascaded. Therefore, this device cannot be
used in circuits that require active or passive elements
between the two op amps. However, there are several
applications where this op amp configuration with a
chip select line becomes suitable. The circuits below
show possible applications for this device.
3.8.3.1 Load Isolation
With the cascaded op amp configuration, op amp B can
be used to isolate the load from op amp A. In applica-
tions w here op amp A is dri ving c apa citiv e or low resis -
tive loads in the feedback loop (such as an integrator
or filter circuit) the op amp may not have sufficient
source cu rren t to driv e the lo ad . In this c as e, op amp B
can be used as a buffer.
FIGURE 3-10: Isolating the Load of a
Buffer.
3.8.3.2 Cascaded Gain
Figure 3-11 shows a cascaded gain circuit configura-
tion with chip select. Op amps A and B are configured
in a no n-inve rting a mplifi er con fig uration . In th is co nfig-
uration, it is important to note that the input offset volt-
age of op amp A is amplified by the gain of op amp A
and B, as shown below:
Therefore, it is recommended that you set most of the
gain with op amp A and use op amp B with relatively
small gain, or as a unity-gain buffer.
+
_
MCP6271
C1
C2
R1
R2
VIN VOU
T
Rf
AB
MCP6275
CS
VOUTB
VOUT VINGAGBVOSAGAGBVOSBGB
++=
Where:
GA = op amp A gain
GB = op amp B gain
VOSA = op amp A offset voltage
VOSB = op amp B offset voltage
MCP6271/2/3/4/5
DS21810C-page 14 2004 Microchip Technology Inc.
FIGURE 3-11: Cascaded Gain Circuit
Configuration.
3.8.3.3 Difference Amplifier
Figure 3-12 shows op amp A configured as a differ ence
amplifier with chip select. In this configuration, it is
recommended that well-matched resistors (0.1%) be
used to increase the common mode rejection ratio
(CMRR). Op amp B can be used to provide additional
gain and isolate the load from the difference amplifier.
FIGURE 3-12: Dif fer en c e Amplif ie r Circ uit .
3.8.3.4 Integrator with Active Compensation
and a Chip Select
Figure 3-13 uses an active c om pen sa tor (op amp B) to
compensate for the non-ideal characteristics intro-
duced at higher frequency integration. The alternative
is to use a passive element (such as a resistor) for com-
pensati on. However , the quality of compensation would
not be constant since the AC characteristics of an
amplifier vary over temperature and process. This
circuit uses op amp B as a unity-gain buffer to isolate
the integration capacitor C1 from op amp A and drives
the cap acito r with a low-i mped ance so urce. Since bo th
amplifiers are matched very well, it provides a higher
quality of integration.
FIGURE 3-13: Integrator Circuit with Active
Compensation.
3.8.3.5 Second-Order MFB with an extra
pole-zero pair
Figure 3-14 is a second-order multiple feedback low-
pass filter with chip select. Use the Filterlab® softwar e
from Microchip to determine the R and C values for op
amp A’s second-order filter. Op amp B can be used to
add a pole-zero pair using C3 and R6.
FIGURE 3-14: Second-Order Multiple
Feedback Low-Pass Filter with an Extra Pole-
Zero Pair and Chi p Sele ct .
AB
CS
R4R3R2R1
VIN
VOUT
MCP6275
AB
CS
R2R1
VIN2
VIN1
R2
R1
VOUT
R4R3
MCP6275
A
CS
B
VIN VOUT
R1C1
MCP6275
AB
CS
R1
C1
R5
VIN VOUT
C2R4
R3R2
R6C3
MCP6275
2004 Microchip Technology Inc. DS21810C-page 15
MCP6271/2/3/4/5
3.8.3.6 Second-Order Sallen-Key with an
Extra Pole-Zero Pair
Figure 3-15 is a second-order Sallen-Key low-pass
filter with chip select. Use the Filterlab® software from
Microchip to determine the R and C values for the op
amp A’s s econd -orde r filter. Op amp B can be used to
add a pole-zero pair us ing C3 and R5.
FIGURE 3-15: Second Order Sallen-Key
Low-Pass Filter with an Extra Pole-Zero Pair and
a Chip Select.
3.8.3.7 Capacitorless Second Order
Low-Pass filter with Chip Select
The low-pass filter shown in Figure 3-16 does not
requ ire ext ernal capaci tors and use s only th ree ex ter-
nal resistors, while the op amp’s GBWP sets the corner
frequency . R1 and R2 are used to se t the circuit gain. R3
is used to set the Q. To avoid gain-peaking in the
frequency response, Q needs to be low (lower values
need to be selected for R3). Note that the amplifier
bandwidth varies greatly over temperature and
process. This configuration, however, provides a low-
cost solution for applications with high bandwidth.
FIGURE 3-16: Capacitorless Second-Order
Low-Pass Filter with Chip Select Circuit.
AB
CS
R2
C1
R1
VIN
VOUT
R4R3
C2
C3R5
MCP6275
AB
CS
VREF
VIN
VOUT
R2R1
R3
MCP6275
MCP6271/2/3/4/5
DS21810C-page 16 2004 Microchip Technology Inc.
4.0 DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6271/2/3/4/5 family of op amps.
4.1 SPICE Macro Model
The latest version of the SPICE Macro Model for the
MCP6271/2/3/4/5 op amp is available on our web site
at www.mic rochip.com . This model i s intend ed to be an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. See the
model file for information on its capabilities.
Bench testing is a ve ry important part of any design and
cannot be replaced with simulations. Also, simulation
results using th is macro model ne ed to be vali da ted b y
comparing them to the data sheet specifications and
characteristic curves.
4.2 FilterLab® Software
The FilterLab software is an innovative tool that
simplifies analog active-filter (using op amps) design.
Available at no cost from our web site
(www.microchip.com), the FilterLab active-filter
software design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
2004 Microchip Technology Inc. DS21810C-page 17
MCP6271/2/3/4/5
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Le ad SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
Legend: XX...X Customer specific information*
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Micro chip p art num ber can not be ma rked on on e line, it will
be carried ov er to the ne xt li ne thus lim iti ng th e nu mb er of av ai lab le c hara ct ers
for customer specific information.
*Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
MCP6271
E/P256
0406
MCP6271
E/SN0406
256
8-Le ad MSOP Example:
XXXXXX
YWWNNN
6271
406256
MCP6271/2/3/4/5
DS21810C-page 18 2004 Microchip Technology Inc.
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6274) Example:
14-Lead TSSOP (MCP6274) Example:
14-Lead S OIC (150 mil) (MCP6274) Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXX
YYWWNNN
XXXXXX
YYWW
NNN
MCP6274-E/P
0409057
6274ST
0409
057
XXXXXXXXXX MCP6274ESL
0409057
2004 Microchip Technology Inc. DS21810C-page 19
MCP6271/2/3/4/5
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
D
A
A1
L
c
(F)
α
A2
E1
E
p
B
n 1
2
φ
β
5°
5° -
-
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
.037 REFFFootprint (Reference)
exceed .010" (0.254mm) per side.
Notes:
Drawing No. C04-111
*Controlling Parameter
Mold Draft Angle Top
Mold Draft Angle Bottom
Foot Angle
Lead Width
Lead Thickness
β
α
c
B
φ
.003
.009
.006
.012
Dimension Limits
Overall Height
Molded Package Thickness
Molded Package Width
Overall Length
Foot Length
Standoff
Overall Width
Number of Pins
Pitch
A
L
E1
D
A1
E
A2
.016 .024
.118 BSC
.118 BSC
.000
.030
.193 TYP.
.033
MIN
p
n
Units
.026 BSC
NOM
8
INCHES
0.95 REF
-
-
.009
.016
0.08
0.22
0°
0.23
0.40
8°
MILLIMETERS*
0.65 BSC
0.85
3.00 BSC
3.00 BSC
0.60
4.90 BSC
.043
.031
.037
.006
0.40
0.00
0.75
MIN
MAX NOM
1.10
0.80
0.15
0.95
MAX
8
--
-
15°5° -
15°5° -
JEDEC Equivalent: MO-187
0° - 8°
5°
5° -
-
15°
15°
--
--
MCP6271/2/3/4/5
DS21810C-page 20 2004 Microchip Technology Inc.
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dime nsion Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E . 300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
2004 Microchip Technology Inc. DS21810C-page 21
MCP6271/2/3/4/5
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Foot A ngle φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Molded Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 88
n
Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equiva lent : MS- 012
Drawing No. C04-057
§ Significant Characteristic
MCP6271/2/3/4/5
DS21810C-page 22 2004 Microchip Technology Inc.
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
n
D
1
2
eB
β
E
c
A
A1
B
B1
L
A2
p
α
Units INCHES* MILLIMETERS
Dimen sion Li mits MIN NOM MAX MIN NOM MAX
Number of P ins n14 14
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Wid th E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overal l Length D .740 .75 0 .760 18.8 0 19.05 19.30
T ip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.8 7 9.40 10.92
Mold Draft Angle Top α5 10 15 5 10 15
β5 10 15 5 10 15
Mold Draft Angle Bottom
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
§ Significant Characteristic
2004 Microchip Technology Inc. DS21810C-page 23
MCP6271/2/3/4/5
14-Lead Plasti c Small Outline (SL) – Narrow, 150 mil (SOIC)
Foot A ngle φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.510.380.25.020.015.010hChamfer Distance 8.818.698.56.347.342.337DOverall Length 3.993.903.81.157.154.150E1Mold ed Pa ckag e Width 6.205.995.79.244.236.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Molded Package Thick ness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 1414
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
h
L
c
β
45°
φ
α
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
§ Significant Characteristic
MCP6271/2/3/4/5
DS21810C-page 24 2004 Microchip Technology Inc.
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
840840
φ
Foot A ngle
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.300.250.19.012.010.007B1Lead Width 0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Le ngth 5.105.004.90.201.197.193DMolded Package Length 4.504.404.30.177.173.169E1M old ed Pa ckag e Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002A1Standoff § 0.950.900.85.037.035.033A2Mold ed Pa ckag e Thick ness 1.10.043AOverall Height 0.65.026
p
Pitch 1414
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits
L
β
c
φ
2
1
D
n
B
p
E1
E
α
A2A1
A
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
§ Significant Characteristic
2004 Microchip Technology Inc. DS21810C-page 25
MCP6271/2/3/4/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
PART NO. X/XX
PackageTemperature
Range
Device
Device: MCP6271: Single Operational Amplifier
MCP6271T: Single Operational Amplifier
(Tape and Reel) (SOIC, MSOP)
MCP6272: Dual Operational Amplifiers
MCP6272T: Dual Operational Amplifiers
(Tape and Reel) (SOIC, MSOP)
MCP6273: Single Operational Amplifier with
Chip Select
MCP6273T: Single Operational Amplifier with Chip
Select (Tape and Reel) (SOIC, MSOP)
MCP6274: Quad Operational Amplifiers
MCP6274T: Quad Operational Amplifiers
(Tape and Reel) (SOIC, TSSOP)
MCP6275: Dual Operational Amplifier with Chip
Select
MCP6275T: Dual Operational Amplifier with Chip
Select (Tape and Reel) (SOIC, MSOP)
Temperature Range: E = -40°C to +125°C
Package: MS = Plastic MSOP, 8-lead
P = Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC, (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
ST = Plastic TSSOP (4.4mm Body), 14-lead
Examples:
a) MCP6271-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6271-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6271-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6271T-E/SN: Tape and Reel,
Ext ended Tempe ratu r e,
8LD SOIC package.
a) MCP6272-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6272-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6272-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6272T-E/SN: Tape and Reel,
Ext ended Tempe ratu r e,
8LD SOIC package.
a) MCP6273-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6273-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6273-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6273T-E/SN: Tape and Reel,
Ext ended Tempe ratu r e,
8LD SOIC package.
a) MCP6274-E/P: Extended Temperature,
14LD PDIP package.
b) MCP6274T-E/SL: Tape and Reel,
Ext ended Tempe ratu r e,
14LD SOIC package.
c) MCP6274-E/SL: Extended Temperature,
14LD SOIC package.
d) MCP6274-E/ST: Extended Temperature,
14LD TSSOP package.
a) MCP6275-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6275-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6275-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6275T-E/SN: Tape and Reel,
Ext ended Tempe ratu r e,
8LD SOIC package.
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip. com /cn) to receive the most current information on our products.
MCP6271/2/3/4/5
DS21810C-page 26 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. DS21810C-page 27
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microc hip Technology Incorporated with respect
to the accuracy or use of such inf orm ation, or inf ringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, micro ID, MPLAB, PIC, PICmicro,
PICSTART, PR O MATE, Po w erSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Tec hnology Incor porated in the U.S.A. and other countries.
AmpLab, FilterLab, MXD EV, MXLAB, PICMASTER, SEEV AL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzy LAB, In-Circ uit Serial
Programm ing, ICSP, ICEPIC, Migratable Memory, MPASM ,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Tec hnology Incor porated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Inco rporated, Pr inted in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that i t s family of products is one of the most secure families of its kind on the market today, when used in t he
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We a t Microc hip are committed to continuously improving the c ode prot ect ion features of our
products. Attempts to break Microchip’ s code protection f eature may be a violati on of the Digital Millennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bi t MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, micro peripherals, nonv olatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21810C-page 28 2004 Microchip Technology Inc.
WORLDWIDE SALES AND SERVICE
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05/28/04