November 2009 Rev 16 1/59
1
NAND128-A NAND256-A
128-Mbit or 256-Mbit, 528-byte/264-word page,
3 V, SLC NAND flash memories
Features
■High density NAND flash memories
– Up to 256-Mbit memory array
– Up to 32-Mbit spare area
– Cost effective solutions for mass storage
applications
●NAND interface
– x8 or x16 bus width
– Multiplexed address/d ata
– Pinout compatibility f or all densities
■Supply voltage
–V
DD = 2.7 to 3.6 V
■Page size
– x8 device: (512 + 16 spare) bytes
– x16 device: (256 + 8 spare) words
■Block size
– x8 device: (16 K + 512 spare) bytes
– x16 device: (8 K + 256 spare) words
■Page read/program
– Random access: 12 µs (max)
– Sequential access: 50 ns (min)
– Page prog ram time: 200 µs (typ)
■Copy back program mode
– Fast page copy without ex ternal buffering
■Fast block erase
– Block erase time: 2 ms (typical)
■Status register
■Electronic signature
■Chip enable ‘don’t care’
– Simple interface with microcontroller
■Security features
–OTP area
– Serial number (unique ID)
■Hardware data protection
– Program/erase locked during power
transitions
■Data integrity
– 100,00 0 pr ogram/erase cycles
– 10 years data retention
■RoHS compliance
– Lead-free co mponents are compliant with
the RoHS directive
■Development tools
– Error correction code software and
hardw are models
– Bad blo c ks managemen t and wear lev e ling
algorithms
– File system OS native ref e rence software
– Hardware simulation models
TSOP48 12 x 20 mm
FBGA
VFBGA55 8 x 10 x 1.05 mm
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Contents NAND128-A, NAND256-A
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Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Inputs/outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9 Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.11 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4 Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 Pointer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
NAND128-A, NAND256-A Contents
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6.4 Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.5 Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.7 Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.7.1 Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.7.2 P/E/R controller bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.7.3 Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.8 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2 Block replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.6.1 Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.6.2 IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 36
9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.1 Ready/busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 48
10.2 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Appendix A Hardware interface e xamples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
List of tables NAND128-A, NAND256-A
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List of tables
Table 1. NAND128-A and NAND256-A device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Product description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Address insertion, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Address insertion, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Address definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Copy back program addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 13. Block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 14. Program, erase times and program erase endurance cycles. . . . . . . . . . . . . . . . . . . . . . . 36
Table 15. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7
Table 16. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 17. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 18. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 19. AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 21. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 51
Table 22. VFBGA55 8 x 10 x 1.05 mm - 6 x 8 + 7 ball arra y, 0.8 mm pitch, package mechan ical data53
Table 23. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 24. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
NAND128-A, NAND256-A List of figures
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List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. TSOP48 connections, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. TSOP48 connections, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. VFBGA55 connections, x8 devices (top view through package) . . . . . . . . . . . . . . . . . . . . 12
Figure 6. VFBGA55 connections, x16 devices (top view through package) . . . . . . . . . . . . . . . . . . . 13
Figure 7. Memory array organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Pointer operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Pointer operations for programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Read (A, B, C) operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11. Read block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Sequential row read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Sequential row read block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. Page program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Copy back operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Block erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 18. Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19. Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 20. Equivalent testing circuit for AC characteristics measurement. . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. Command Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 22. Address Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 23. Data Input Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 24. Sequential data output after read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 25. Read status register AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 26. Read electronic signature AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 27. Page read A/read B operation AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 28. Read C operation, one page AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 29. Page program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7
Figure 30. Block erase AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 31. Reset AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 32. Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 33. Ready/busy load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 34. Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 49
Figure 35. Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 36. TSOP48 - 48 lead plastic thin sm all ou tlin e, 12 x 20 mm, pa ck ag e ou tlin e . . . . . . . . . . . . 51
Figure 37. VFBGA55 8 x 10 mm - 6 x 8 active ball array, 0.8 mm pitch, package outline. . . . . . . . . . 52
Figure 38. Connection to microcontroller, without glue logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 39. Connection to microcontroller, with glue logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 40. Building storage modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Description NAND128-A, NAND256-A
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1 Description
The NAND flash 528-byte/264-word page is a family of non-volatile flash memories that
uses the single level cell (SLC) NAND technology, referred to as the SLC small page family.
The de vices are eit her 128 Mbits or 256 Mbit s and operat e with 3 V v oltage supply. The siz e
of a page is either 528 bytes (512 + 16 spare) or 264 words (256 + 8 spare) depending on
whether the device has a x8 or x16 bus width.
The address lines are multiplexed with the data input/output signals on a multiplexed x8 or
x16 input/output bus. This interface reduces the pin count and makes it possible to migrate
to other densities without changing the footprint.
Each block can be programmed and erased up to 100,000 cycles. To extend the lifetime of
NAND flash devices it is strongly recommended to implement an error correction code
(ECC). A Write Protect pin is available to provide hardware prot ection against program and
erase operations.
The devices feature an open- drain ready/busy output that identifies if the program/erase/
read (P/E/R) controller is currently active. The use of an open-drain output allows the
Ready/Busy pins from several memories to be connected to a single pull-up resistor.
A Copy Back command is available to optimize the management of defective blocks. When
a page prog ram oper ation f ails, the data can be prog rammed in anot her page without ha ving
to resend the data to be programmed.
Table 1 lists the individual part numbers of the device.
The NAND128-A devices are only available in the TSOP48 (12 x 20 mm), while the
NAND256-A devices are a vailable in both the TSOP48 and the VFBGA55 (8 x 10 x
1.05 mm) packages.
The devices are available in two different versions:
●No option (Chip Enable ‘care’, sequential row read enabled): the sequential row read
feature allo ws to download up to all the pa ges in a block with one read command and
addressing only the first page to read
●With Chip Enable ‘don’t care’ feature. This enables the sharing of the bus between
more active memories that are sim ultaneou sly active as Chip Enable tra nsitions d uring
latency do not stop read oper a t ions. Program and erase ope rations are not inter rupted
by Chip Enable transitions.
Table 1. NAND128-A and NAND256-A device summary
Reference Part number
NAND128-A NAND128W3A
NAND256-A(1)
1. x16 organization only available for MCP.
NAND256W3A
NAND256W4A
NAND128-A, NAND256-A Description
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and come with the following security features:
●OTP (one time programmable) area, which is a restricted access area where sensitive
data/code can be stored permanently. The access sequence and further details about
this feature are subject to an NDA (non disclosure agreement)
●Serial number (unique id entifier), which enab les each de vice to be uniquely identified. It
is subject to an NDA and is, therefore, not described in the datasheet.
For more details about these security features, contact your nearest Numonyx sales office.
For information on how to order these devices refer to Table 23: Ordering information
scheme. Devices are shipped from the factory with block 0 always valid and the memory
content bits in valid blocks erased to ’1’.
See Table 2 for all the devices available in the family.
Table 2. Product description
Reference
Part number
Density
Bus width
Page size
Block size
Memory array
Operating voltage
Timings
Package
Rand access max
Seq access min
Page program typ
Block erase typ
NAND128-A NAND128W3A 128
Mbits x8 512+16
bytes 16K+51
2 bytes
32 pages
x 1024
blocks
2.7 to 3.6V 12 µs 50 ns 200 µs 2 ms
TSOP48
NAND256-A(1) NAND256W3A 256
Mbits
x8 512+16
bytes 16K+51
2 bytes 32 pages
x 2048
blocks
TSOP48
VFBGA55
NAND256W4A x16 256+8
words 8K+256
words
1. x16 organization only available for MCP.
Description NAND128-A, NAND256-A
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Figure 1. Logic diagram
AI07557C
W
I/O8-I/O15, x16
VDD
NAND flash
E
VSS
WP
AL
CL
RB
R
I/O0-I/O7, x8/x16
Table 3. Signal names
Symbol Function Direction
I/O8-15 Data input/outputs for x16 devices I/O
I/O0-7 Data input/outp uts, address inputs, or command inputs for x8 and x16
devices I/O
AL Address Latch Enable Input
CL Command Latch Enable Input
EChip Enable Input
RRead Enable Input
RB Ready/Busy (open-drain output) Output
WWrite Enable Input
WP Write Protect Input
VDD Supply voltage Supply
VSS Ground Ground
NC Not connected internally –
DU Do not use –
NAND128-A, NAND256-A Description
9/59
Figure 2. Logic block diagram
Address
register/counter
Command
interface
logic
P/E/R controller,
high voltage
generator
WP
I/O buffers & latches
I/O8-I/O15, x16
E
W
AI07561c
R
Y decoder
Page buffer
NAND flash
memory array
X Decoder
I/O0-I/O7, x8/x16
Command register
CL
AL
RB
Description NAND128-A, NAND256-A
10/59
Figure 3. TSOP48 connections, x8 devices
I/O3
I/O2
I/O6
R
RB
NC
I/O4
I/O7
AI07585C
NAND flash
(x8)
12
1
13
24 25
36
37
48
E
I/O1
NC
NC
NC
NC
NC
NC
NC
WP
W
NC
NC
NC
VSS
VDD
AL
NC
NC
CL
NC
I/O5
NC
NC
NC
I/O0
NC
NC
NC
NC
NC
VDD
NC
NC
NC
VSS
NC
NC
NC
NC
NAND128-A, NAND256-A Description
11/59
Figure 4. TSOP48 connections, x16 devices
I/O3
I/O9
I/O2
I/O6
R
RB
NC
I/O14
I/O12
I/O10
I/O4
I/O7
AI07559C
NAND flash
(x16)
12
1
13
24 25
36
37
48
I/O8
E
I/O1
I/O11
NC
NC
NC
NC
NC
NC
NC
WP
W
NC
NC
NC
VSS
VDD
AL
NC
NC
CL
NC
I/O13
I/O15
I/O5
VSS
NC
VSS
I/O0
NC
NC
NC
NC
NC
VDD
Description NAND128-A, NAND256-A
12/59
Figure 5. VFBGA55 connections, x8 devices (top view through package)
AI09366b
I/O7
WP
I/O4I/O3
NC VDD
I/O5VDD
NC
H
VSS
I/O6
D
E
CL
C
NC
NC
BDU
NC
W
NC
A
87654321
NCNC
NC NC
G
F
E
I/O0
AL
NC NC
NC
NCNC NC NCNC
NCNC
VSS
NCNC
NC NC
RB
I/O2
NC
DU
I/O1
R
NC
NC
NC
VSS
DU
DU
DUDU
DU
M
L
K
J
NAND128-A, NAND256-A Description
13/59
Figure 6. VFBGA55 connections, x16 devices (top view through packa ge)
AI09365b
I/O15
WP
I/O4I/O11
I/O10 VDD
I/O6VDD
I/O3
H
VSS
I/O13
D
E
CL
C
NC
NC
BDU
NC
W
NC
A
87654321
NCNC
NC NC
G
F
E
I/O1
AL
NC NC
NC
NCNC NC I/O7I/O5
I/O14I/O12
VSS
NCNC
NC NC
RB
I/O2
I/O0
DU
I/O9
R
NC
NC
I/O8
VSS
DU
DU
DUDU
DU
M
L
K
J
Memory array organization NAND128-A, NAND256-A
14/59
2 Memory array organization
The memory array comprises NAND structures where 16 cells are connected in series.
The memory array is organized in blocks where each block cont ains 32 pages. The array is
split into two ar eas, the main area and the spare area. The main area of t he array stores
data, whereas the spa re area is typically used to store er ror correction codes , softwar e flags
or bad bl ock identification.
In x8 device s the p ages are split into a main are a with tw o half p ages of 256 b yt es each and
a spare area of 16 bytes. In the x16 devices the pages are split into a 256-word main area
and an 8-word spare area. Refer to Figure 7: Me m ory array organizati on .
2.1 Bad blocks
The NAND flash 528-byte/264-word page devices may contain bad blocks, that is blocks
that contain one or more invalid bits whose reliability is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
The bad block information is written prior to shipping (refer to Section 2.1: Bad blocks for
more details).
Table 4 shows the minimum number of valid blocks in each device. The values shown
include both the bad bloc ks that are present when the device is shipped and the bad blocks
that could develop later on.
These blocks need to be managed using bad blocks management, block replacement or
error correction codes (refer to Section 7: Software algorithms).
Table 4. Valid blocks
Density of device Minimum Maximum
256 Mbits 2008 2048
128 Mbits 1004 1024
NAND128-A, NAND256-A Memory array organization
15/59
Figure 7. Memory array organization
AI07587
Block = 32 pages
Page = 528 bytes (512+16)
512 bytes
512 bytes
Spare area
2nd half page
(256 bytes)
16
bytes
Block
8 bits
16
bytes
8 bits
Page
Page buffer, 512 bytes
1st half page
(256 bytes)
Block = 32 pages
Page = 264 words (256+8)
256 words
256 words
Spare area
Main area
8
words
16 bits
8
words 16 bits
Page buffer, 264 words
Block
Page
x8 DEVICES x16 DEVICES
Signal descriptions NAND128-A, NAND256-A
16/59
3 Signal descriptions
See Figure 1: Logic diagram and Table 3: Signal names for a brief overview of t he signals
connected to this device.
3.1 Inputs/outputs (I/O0-I/O7)
Input/o utputs 0 to 7 input the selected address, output the data during a read operation or
input a command or data du ring a write oper ation. The inputs are latched o n the rising edge
of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outp uts are
disabled.
3.2 Inputs/outputs (I/O8-I/O15)
Input/outputs 8 to 15 are only available in x16 devices. They output the data during a read
operation or input data during a write operation. Command and address inputs only require
I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
3.3 Address Latch Enable (AL)
Address Latch Enab le activ ates the latching of the address inputs in th e command interf ace.
When AL is high, the inputs are latched on the rising edge of Write Enable.
3.4 Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is high, the inputs are latched on the rising edge of Write Enable.
3.5 Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Lo w, VIL, the device is selected.
While the device is busy programming or erasing, Chip Enable transiti ons to High (VIH) are
ignored and the device does not go into standby mode.
While the device is busy reading:
●the Chip Enable input should be held Low during the whole b usy time (tBLBH1) for
de vices that do not feature the Chip Enable don’t care option. Otherwise, the read
operation in progress is interrupted and the device goes into standby mode.
●for devices that feature the Chip Enable don’t care option, the Chip Enable going High
during the b usy time (tBLBH1) will not interrupt the read operation and the de vice will not
go into standby mode.
NAND128-A, NAND256-A Signal descriptions
17/59
3.6 Read Enable (R)
Read Enable, R, controls the sequential data output during read operations. Data is valid
tRLQV after the falling edge of R. The falling edge of R also increments the internal column
address counter by one.
3.7 Write Enable (W)
The Write Enable input, W, controls writing to the Command Interface, Input Address and
Data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10 µs (min) is required before the
Command Interf ace is ready t o accept a command. It is recommende d to keep Write Enab le
high during the recovery time.
3.8 Write Protect (WP)
The Write Pro te ct pin is an inpu t th at provides hardware protection against unwanted
program or erase operations. When Write Protect is Low, VIL, the device does not accept
any program or erase operations.
It is recommended to k e ep the Write Prot ect pin L ow, VIL, during po w er-up an d po we r-do wn.
3.9 Ready/Busy (RB)
The Ready/Busy output , RB, is an op en-drain out put that can b e used to identi fy if the P/E/R
controller is currently active.
When Ready/Busy is Low, VOL, a read, program or erase oper ation is in progr ess. When the
operat ion completes Ready/Busy goes High, VOH.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low then indicates that one or more of the
memories is busy.
Refer to the Section 10.1: Ready/busy signal electrical characteristics for details on how to
calculate the value of the pull-up resis tor.
3.10 VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply f or all operations (read, program and erase).
An internal v oltage detector di sables all functions when ev er VDD is belo w the VLKO threshold
(see paragraph Figure 35: Data protection) to protect the device from any involuntary
program/erase operations during power-transitions.
Each device in a system should ha v e VDD decoupled with a 0.1 µF capacitor. The PCB trac k
widths should be sufficient to carry the required program and erase curre nts
Signal descriptions NAND128-A, NAND256-A
18/59
3.11 VSS ground
Ground, VSS, is the reference for the power supply. It must be connected to the system
ground.
NAND128-A, NAND256-A Bus operations
19/59
4 Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see Table 5: Bus operations for a summary.
4.1 Command input
Command input bus operations give commands to the memory. Commands are accepted
when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low,
and Read Enable is High. They are latched on the rising edge of the Write Enable signal.
Only I/O0 to I/O7 input com m a nd s.
See Figure 21: Command Latch AC waveforms and Table 14: Program, erase times and
program erase endurance cycles for details of the timing s requ ire m ents.
4.2 Address input
Address input bus oper ations input the memory address. Three bus cycles are required to
input the addresses (refer to Tables Table 6: Address insertion, x8 devices and Table 7:
Address insertion, x16 devices).
The addresses a re accepted when Chip Enable is Low, Address Latch Enab le is High,
Command Latch Enable is Low, and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 input addresses.
See Figure 22: Address Latch AC waveforms and Table 14: Program, erase times and
program erase endurance cycles for details of the timing s requ ire m ents.
4.3 Data input
Data input bus operations input the data to be programmed.
Data is accepted only when Chip Enable is Lo w, Address Latch Enable is Low, Command
Latch Enab le is Lo w, and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal and is inp ut sequentially using the Write Enable signal.
See Figure 23: Data Input Latch AC waveforms and Table 14: Program, er ase times and
program erase endurance cycles and Table 20: AC charact eristics for operations for details
of the timings requirements.
Bus operations NAND128-A, NAND256-A
20/59
4.4 Data output
Data output bus operations read the data in the memory array, the status register, the
electronic signature, and the serial number.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
See Figure 24: Sequential data output after read AC waveforms and Table 20: AC
characteristics for operatio ns for details of the timings requirements.
4.5 Write protect
Write protect bus ope rations protect the memory against program or erase operations.
When the Write Protect signal is Low the device does not accept program or erase
operat ions, theref ore , the contents of the memory arra y cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection, even during power-up.
4.6 Standby
When Chip Enable is High the memory enters standby mode: the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5. Bus operations
Bus operation E AL CL R WWP I/O0 - I/O7 I/O8 - I/O15(1)
1. Only for x16 devices.
Command input VIL VIL VIH VIH Rising X(2)
2. WP must be VIH when issuing a program or erase command.
Command X
Address input VIL VIH VIL VIH Rising X Address X
Data input VIL VIL VIL VIH Rising X Data input Data input
Data output VIL VIL VIL Falling VIH X Data output Data output
Write protect X X X X X VIL XX
Standby VIH XX X X X X X
Table 6. Address insertion, x8 devices(1)(2)
1. A8 is set Low or High by the 00h or 01h command (see Section 6.1: Pointer operations).
2. Any additional address input cycles are ignored.
Bus
Cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1st A7 A6 A5 A4 A3 A2 A1 A0
2nd A16 A15 A14 A13 A12 A11 A10 A9
3rd A24 A23 A22 A21 A20 A19 A18 A17
NAND128-A, NAND256-A Bus operations
21/59
Table 7. Address insertion, x16 devices(1)(2)(3)
1. A8 is ’don’t care’ in x16 devices.
2. Any additional address input cycles are ignored.
3. The 01h command is not used in x16 devices.
Bus
Cycle I/O8-
I/O15 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1st XA7 A6 A5 A4 A3 A2 A1 A0
2nd XA16 A15 A14 A13 A12 A11 A10 A9
3rd XA24 A23 A22 A21 A20 A19 A18 A17
Table 8. Address definitions
Address Definition
A0 - A7 Column address
A9 - A26 Page address
A9 - A13 Address in block
A14 - A26 Block address
A8 A8 is set Low or High by the 00h or 01h command, and is ’don’t care’ in x16 devices
Command set NAND128-A, NAND256-A
22/59
5 Command set
All bus write operations to the device ar e interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is High. De vice operations are selected by writing
specific commands to the command register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The commands are summarized in Table 9.
Table 9. Commands
Command Bus write operations(1)(2)
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or
input/output data are not shown.
2. Any undefined command sequence is ignored by the device.
Command accepted
during busy
1st cycle 2nd cycle 3rd cycle
Read A 00h – –
Read B 01h(2) – –
Read C 50h – –
Read Electronic Signature 90h – –
Read Status Register 70h – – Yes
Page Program 80h 10h –
Copy Back Program 00h 8Ah 10h
Block Erase 60h D0h –
Reset FFh – – Yes
NAND128-A, NAND256-A Device operations
23/59
6 Device operations
6.1 Pointer operations
As the NAND flash memories contain two different areas for x16 devices and three different
areas f or x8 de vices (see Figure 8) the read com mand codes (00h, 01h, 50h) act as pointers
to the different areas of the memory arra y (they select the most significant column address).
The Read A and Read B commands a ct as pointers to the main memory area. Their use
depends on the bus width of the device.
●In x16 devices the Read A command (0 0h) set s th e p ointer to Are a A ( the who le of the
main area), tha t is words 0 to 255.
●In x8 de vices the Read A comma nd (00h) sets the p ointer to Area A (the fir st half of the
main area), that is bytes 0 to 255, and the Read B command (01h) sets the pointer to
Area B (the second half of the main area), that is bytes 256 to 511.
In both the x8 and x1 6 devices the Read C command (50h) acts as a pointer to Area C (th e
spare memory area), that is bytes 512 to 527 or words 256 to 263.
Once the Read A and Read C commands have been issued the pointer remains in the
respective areas until another pointer code is issued. However, the Read B command is
effective for only one operation, once an operation has been executed in Area B the pointer
returns automatically to Area A.
The pointer ope ration s can also be used bef or e a prog ram op era tion, that is the appropriate
code (00h, 01h or 50h) can be issued before the program command 80h is issue d (see
Figure 9: Pointer operations for programming).
Figure 8. Pointer operations
AI07592
Area A
(00h)
A
Area B
(01h) Area C
(50h)
Bytes 0- 255 Bytes 256-511 Bytes 512
-527
CB
Pointer
(00h,01h,50h)
Page Buffer
Area A
(00h)
A
Area C
(50h)
Words 0- 255 Words 256
-263
C
Pointer
(00h,50h)
Page Buffer
x8 Devices x16 Devices
Device operations NAND128-A, NAND256-A
24/59
Figure 9. Pointer operations for programming
6.2 Read memory array
Each operation to read the memory area starts with a pointer operation as shown in the
Section 6.1: Pointer operations . Once the area ( main or sp are) has be en select ed using th e
Read A, Read B or Read C commands thre e bu s cycles are required to input the address of
the data to be read.
The device defaults to Read A mode after power-up or a reset operation.
When reading the follo wing spare area addresses:
●A0 to A3 (x8 devices)
●A0 to A2 (x16 devices)
set the start address of the spare area, while the following addresses are ignored:
●A4 to A7 (x8 devices)
●A3 to A7 (x16 devices)
Once the Read A or Read C commands have been issued they do no t need to be reissued
for subsequent read operations as the pointer remains in the respective area. However, the
Read B command is effective for only one operation; once an operation has been executed
in Area B the pointer returns automatically to Area A. Another Read B command is required
to start another read operation in Area B.
Once a read command is issued two types of op erations are available: random read and
page read.
●Random read
Each time the command i s issued the first read is random read.
●Page rea d
After the r andom read access the page data is tra nsferred to the page buffer in a tim e
of tWHBH (refer to Table 20: AC characteristics for oper ations for the value). Once the
transfer is complete the Ready/Busy signal goes High. The data can then be read out
sequentially (from t he selected column address to the last column address) by pulsing
the Read Enable signal.
●Sequential row read
After the data in last column of the page is output, if the Read Enable signal is pulsed
ai07591
I/O Address
Inputs Data Input 10h
80h
Areas A, B, C can be programmed depending on how much data is input. Subsequent 00h commands can be omitted.
AREA A
00h Address
Inputs Data Input 10h
80h
00h
I/O Address
Inputs Data Input 10h
80h
Areas B, C can be programmed depending on how much data is input. The 01h command must be re-issued before each program.
AREA B
01h Address
Inputs Data Input 10h
80h
01h
I/O Address
Inputs Data Input 10h
80h
Only Areas C can be programmed. Subsequent 50h commands can be omitted.
AREA C
50h Address
Inputs Data Input 10h
80h
50h
NAND128-A, NAND256-A Device operations
25/59
and Chip Enab le remains Lo w, then the ne xt page is automa tically loaded into t he page
buffer and the read oper ation continues. A sequential row read operation can only be
used to read within a b loc k. I f the b loc k ch anges a new read command must be issue d.
Ref er to Figure 12: Sequent ial ro w read o pera tions and Figure 13: Sequential row rea d
block diagrams for details about sequential row read operations. To terminate a
sequential row read operation, set to High the Chip Enable signal for more than tEHEL.
Sequential row read is not av ailable when th e Chip Enable don’t care option is e nab le d.
Figure 10. Read (A, B, C) operations
Figure 11. Read block diagrams
1. The highest address d epends on the device density.
CL
E
W
AL
R
I/O
RB
00h/
01h/ 50h
ai07595c
Busy
Command
Code
Address Input Data Output (sequentially)
tBLBH1
(read)
AI07596
A0-A7
A9-A26(1)
Area A
(1st half page)
Read A command, x8 devices
Area B
(2nd half page) Area C
(spare) Area A
(main area) Area C
(spare)
A0-A7
Read A command, x16 devices
A0-A7
Read B command, x8 devices
Area A
(1st half page) Area B
(2nd half page) Area C
(spare)
A0-A3 (x8)
A0-A2 (x16)
Read C command, x8/x16 devices
Area A Area A/ B Area C
(spare)
A9-A26(1)
A9-A26(1)
A9-A26(1)
A4-A7 (x8), A3-A7 (x16) are don't care
Device operations NAND128-A, NAND256-A
26/59
Figure 12. Sequential row read operations
Figure 13. Sequential row read bloc k diagrams
I/O
RB
Address inputs
ai07597
1st
page output
Busy
tBLBH1
(Read busy time)
00h/
01h/ 50h
Command
code
2nd
page output Nth
page output
BusyBusy
tBLBH1 tBLBH1
AI07598
Block
Area A
(1st half Page)
Read A command, x8 devices
Area B
(2nd half Page) Area C
(Spare) Area A
(main area) Area C
(Spare)
Read A command, x16 devices
Read B command, x8 devices Read C command, x8/x16 devices
Area A Area A/ B Area C
(Spare)
Area A
(1st half Page) Area B
(2nd half Page) Area C
(Spare)
1st page
2nd page
Nth page
1st page
2nd page
Nth page
1st page
2nd page
Nth page
1st page
2nd page
Nth page
Block
Block
Block
NAND128-A, NAND256-A Device operations
27/59
6.3 Page program
The page prog ram o peration is t he standard op eration to p rogram data to the memo ry arra y.
The main area of the memory array is programmed by page, however partial page
programming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be
programmed.
The maximum number of consecutive partial page program operations allowed in the same
page is three. After exceeding this a Block Erase command must be issued before any
further program operation s can take place in that page.
Before starting a page program operation a pointer operation can be performed to point to
the area to be pro grammed. Refer to Section 6.1: Pointer operations and Figure 9: Pointer
operations for programming for details.
Each page program operation cons ists of the following five steps (see Figure 14: P age
program operation):
1. One bus cycle is required to setup the Page Program command
2. Four bus cycles are then required to input the program address (refer to Table 6:
Address insertion, x8 devices)
3. The data is then input (up to 528 bytes/ 264 words) and loaded into the page buffer
4. One bus cycle is required to issue the confirm command to start the P/E/R controller.
5. The P/E/R controller then programs the data into the array.
Once the prog ram operation has started the status register can be read using the Read
Status Register command. During program operations the status register only flags errors
for bits set to '1' that have not been successfully programmed to '0'.
During the program operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
Once the prog r am oper a tion has co mplete d the P/E/ R contro ller bit SR6 is set t o ‘1’ and t he
Ready/Busy signal goes High.
The device remains in read status register mode until another v alid command is written to
the command interface.
Figure 14. Page program operation
1. Before starting a page program operation a pointer operation can be performed. Refer to Section 6.1:
Pointer operations for details.
I/O
RB
Address Inputs SR0
ai07566
Data Input 10h 70h
80h
Page Program
Setup Code Confirm
Code Read Status Register
Busy
tBLBH2
(Program Busy time)
Device operations NAND128-A, NAND256-A
28/59
6.4 Copy back program
The copy back program operation copies the data stored in one page and reprogram it in
another page.
The cop y bac k prog ram o peration d oes not require exte rnal memory and so the operation is
faster and more efficient because the reading and loading cycles are not required. Th e
operat ion is particularly useful when a portion of a bloc k is update d and the re st of the b lock
needs to be copied to the newly assigne d block.
If the copy bac k program operation f ails an error is signalled in the status register. Howev er,
as the standard exte rnal ECC cannot be used with the copy back operation bit error due to
charge loss cannot be detected. For this reason it is recommended to limit the n umber of
copy back operations on the same data and or to improve the performance of the ECC.
The copy back program operation requires the following three steps:
1. The source page mu st be read using the Read A command (one bus write cycle to
setup the command and then 4 bus write cycles to input the source page address).
This operation copies all 264 words/ 528 b ytes from the page into the page buf fer.
2. When the device returns to the ready state (Ready/Busy High), the second bus write
cycle of the command is given with the 4 bus cycles to input the target page address.
Refer to Table 10 for the addresses that must be the same for the source and target
pages.
3. Then the confirm command is issued to start the P/E/R controller.
After a copy back program operation, a partial-page prog ram is not allowed in the target
page until the block has been erased. See Figure 15 for an example of the copy back
operation.
Figure 15. Copy back operation
Table 10. Copy back program addresses
Density Same address for source and target pages
128 Mbits A23
256 Mbits A24
I/O
RB
Source
Address Inputs SR0
ai07590b
8Ah 70h00h
Copy Back
Code
Read
Code Read Status Register
Target
Address Inputs
tBLBH1
(Read Busy time)
10h
Busy
tBLBH2
(Program Busy time)
NAND128-A, NAND256-A Device operations
29/59
6.5 Block erase
Erase operations are done one block at a time. An erase operation sets all of th e bits in the
addressed block to ‘1’. All previous da ta in the block is lost.
An erase operation consists of the following three steps (refer to Figure 16: Block erase
operation):
1. One bus cycle is required to set up the Block Erase command.
2. Only two bus cycles are required to input the bloc k address. The first cycle (A0 to A7) is
not required as only addresses A14 to A26 (highest address depends on device
density) are v alid , A9 to A13 ar e ignored. In t he last addre ss cycle I/O2 to I /O7 must be
set to VIL.
3. One bus cycle is required to issue the confirm command to start the P/E/R controller.
Once the erase operation has completed the status register can be checked for errors.
Figure 16. Block erase operation
6.6 Reset
The Reset command resets the command interface and status register. If the Reset
command is issued during any operation, the operation is aborted. If it was a program or
erase operation that was aborted, the contents of the memory locations being modified are
no longer valid as the data is partially programmed or erased.
If the device has already been reset then the ne w Reset command is not accepted.
The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value
of tBLBH4 depends on the oper ation that the de vice w as p erf o rming when the command was
issued (refer to Table 20: AC characteristics for operations for the values.)
6.7 Read status register
The device contains a status register which provides information on the current or previous
program or erase operation. the various bits in the status register convey information and
errors on the operation .
the status register is read by issuing the read status register command. the status register
information is present on the output data b us (I/O0-I/O7) on the falling edge of chip enable
or read enable, whichever occurs last. when several memories are connected in a syst em,
the use of chip enable and read enable signals allows the syst em to poll each device
separate ly, even when the ready/busy pins are common-wired. it is not necessary to toggle
the chip enable or read enable signals to update the contents of the status register.
I/O
RB
Block Address
Inputs SR0
ai07593
D0h 70h
60h
Block Erase
Setup Code Confirm
Code Read Status Register
Busy
tBLBH3
(Erase Busy time)
Device operations NAND128-A, NAND256-A
30/59
After the read st atus register command has been issu ed, the device remains in read status
register mode unt il anothe r command is issued. t herefore if a r ead stat us regi ster co mmand
is issued during a random rea d cycle a new read command m ust be issued t o contin ue with
a page read.
The status register bits are summarized in Tab le 11: Status register bits, to which y ou should
refer in conjunction with the following sections.
6.7.1 Write protection bit (SR7)
The write protection bit identifies if the device is protected or not. If the write protection bit is
set to ‘1’ the device is not protected and program or erase operations are allowed. I f the
write protection bit is set to ‘0’ the device is protecte d and program or erase operations are
not allowed.
6.7.2 P/E/R controller bit (SR6)
The program/erase/read controller bit indicates whether the P/E/R controller is active or
inactive . When the P/E/R controller bit is set to ‘0’, the P/E/R controller is active (device is
busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is ready).
6.7.3 Error bit (SR0)
T he erro r bit identif ies if any errors ha ve been detect ed by the P/E/R controller. The error bit
is set to ’1’ when a program or er ase operation has failed to write the correct data to the
memory. If the error bit is set to ‘0’ the operation has completed successfully.
SR5, SR4, SR3, SR2 and SR1 are reserved.
6.8 Read electronic signature
Th e de v ic e c on ta in s a manu facture r code and device code . To read these codes the f ollo wing
two steps are required:
1. First use one bus write cycle to issue the Read Electronic Signature command (90h),
followed by an address inpu t of 00h.
2. The n, perform two b us read oper ation s. The first one re ads the man uf a cturer co de and
the second reads the device code. Further bus read operations are ignored.
Table 11. Status register bits
Bit Name Logic level Definition
SR7 Write protection '1' Not protect e d
'0' Protected
SR6 Program/erase/read
controller '1' P/E/R C inactive, device ready
'0' P/E/R C active, device busy
SR5, SR4, SR3,
SR2, SR1 Reserved ’don’t care’
SR0 Generic error ‘1’ Error – operation failed
‘0’ No error – operation successful
Software algorithms NAND128-A, NAND256-A
32/59
7 Software algorithms
This section gives inf ormation on the software algorithms that Numonyx reco mmends to
implement to mana ge the bad blocks and extend the lifetime of the NAND device.
NAND flash memories are prog rammed and erased by Fowler-Nordheim tunneling using a
high voltage. Exposing the device to a high voltage for extended periods can cause the
oxide layer t o be damaged. For this reason, the number of program and erase cycles is
limited (see Table 14: Program, erase times and program erase endurance cycles for the
values) and it is recommended to implement garbage collection, a wear-leveling algorithm
and an error correction code to extend the number of program and erase cycles and
increase the data retention.
F or the int egr ation of NAND memories into an applica tion, Numon yx pro vides a full ran ge of
software solutions such as file systems, sector managers, drivers, and code management.
Contact the near est Numonyx sales office or visit www. numonyx.com fo r more details.
7.1 Bad block management
Devices with bad blocks have the same quality level and the same AC and DC
characteristics as devices where all the blocks are valid. A bad block does not affect the
performance of valid blocks because it is isolated from the bit line and common source line
by a select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The bad
block information is written prior to shipping. Any block where the 6th byte (x8 devices)/1st
word (x16 devices), in the spare area of the 1st page, does not contain FFh is a bad block.
The bad block information must be read before any erase is attempted as the bad block
inf o rmation ma y be e r ased. For the system to b e ab le t o recognize the bad bloc ks base d on
the original inf ormation it is recommended to create a bad b loc k tab le f ollowing the f lowchart
shown in Fig ure 17: Bad block management flowchart.
7.2 Block replacement
Ov er th e lifetime of t he device addi tional bad bloc ks may develop. In this case the block has
to be replaced by copying the data to a valid block. These additional bad blocks can be
identified as attempts to progr am or erase them outputs errors to the status register.
As the failure of a page pr ogram operation does not aff ect the data in other pages in the
same block, t he block can be rep laced by re-programming the curr ent data and copying the
rest of the re placed bl ock to an a v ailab le v alid b lock. The Cop y Bac k Progr am command can
be used to copy the data to a valid block.
Refer to Sectio n 6.4: Copy back program for more details.
NAND128-A, NAND256-A Software algorithms
33/59
Refer to Table 13 for the recommended procedure to follow if an error occurs during an
operation.
Figure 17. Bad block management flowchart
Table 13. Block failure
Operation Recommended procedure
Erase Block replacement
Program Block replacement or ECC
Read ECC
AI07588C
START
END
NO
YES
YES
NO
Block Address =
Block 0
Data
= FFh?
Last
block?
Increment
Block Address
Update
Bad Block table
Software algorithms NAND128-A, NAND256-A
34/59
7.3 Garbage collection
When a data page needs to be modified, it is faster to write to the firs t available page, and
the previous page is mark ed as invalid. After several updates it is necessary to remove
invalid pages to free some memory space.
To free this memory space and allow further program operations it is recommended to
implement a garbage collection algorithm. In a garbage collection software the valid pages
are copied into a free area and the block containing the invalid pages is erased (see
Figure 18: Garbage collection).
Figure 18. Garbage collection
7.4 Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a wear- leveling algorithm
to monitor and sprea d the number of write cycles per b lock.
In memories that do not use a wear-leveling algorithm not all blocks get used at the same
rate. Blocks with long-lived data do not endure as many write cycles as the blocks with
frequently-changed data.
The wear-leveling algorithm ensures that equal use is made of all the available write cycles
for each b lock. There ar e two wear-leveling levels:
●First level wear-leveling: new data is programmed to the free blocks that have had the
fewest write cycles.
●Second level wear-leveling: long-lived data is copied to an other block so that the
original block can be used for more frequently-changed data.
The second level wear-leveling is triggered when the difference between the maximum and
the minimum number of write cycles per block reaches a specif ic threshold.
Valid
Page
Invalid
Page Free
Page
(Erased)
Old Area
AI07599B
New Area (After GC)
NAND128-A, NAND256-A Software algorithms
35/59
7.5 Error correction code
An error correction code (ECC) can be implemented in the NAND flash memories to identify
and correct errors in the data.
The recommendati on is to implement 23 bits of ECC for every 4096 bits in the device.
Figure 19. Error detection
7.6 Hardware simulation models
7.6.1 Behavioral simulation models
Denali Software Corporation models are platform-independent functional models designed
to assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logic beha vior and timings of NAND flash d e vices, and, theref o re, allo w
software to be dev eloped before hardware.
7.6.2 IBIS simulations models
IBIS (I/O buffer information specification) models describe the behavior of the I/O buffers
and electrical characteristics of flash devices.
These models provide information such as AC characteristics, rise/fall times, and package
mechanical data, all of which are measured or simula ted at v oltage and te mperatur e ranges
wider than those allowed by target specifications.
IBIS models simulate PCB connections and can resolve compatibility issues when
upgrading devices. They can be imported into SPICETOOLS.
New ECC generated
during read
XOR previous ECC
with new ECC
All results
= zero?
22 bit data = 0
YES
11 bit data = 1
NO
1 bit data = 1
Correctable
Error ECC Error
No Error
ai08332
>1 bit
= zero?
YES
NO
Program and erase times and endurance cycles NAND128-A, NAND256-A
36/59
8 Program and erase times and endurance cycles
The progr am and eras e times and the number of program / erase cycles per b lock ar e shown
in Table 14.
Table 14. Program, erase times and program erase endurance cycles
Parameters NAND flash Unit
Min Typ Max
Page program time 200 500 µs
Block erase time 23ms
Program/er ase cycles (per block) 100,000 cycles
Data retention 10 years
NAND128-A, NAND256-A Maximum ratings
37/59
9 Maximum ratings
Stressing the device above the ratings listed in Table 15: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum ratings condit ions for
extended periods may affect device reliability.
Table 15. Absolute maxim um ratings
Symbol Parameter Value Unit
Min Max
TBIAS Temperature under bias – 50 125 °C
TSTG Storage temperature – 65 150 °C
TLEAD Lead temperature during soldering (1)
1. Compatibility with lead-free soldering processes in accordance with RoHS specifications. Not exceeding
250 °C for more than 10 s, and peaking at 260 °C.
260 °C
VIO(2)
2. Minimum voltage may undershoot to –2 V for less than 20 ns during transitions on input and I/O pins.
Maximum voltage may overshoot to VDD + 2 V for less than 20 ns during transitions on I/O pins.
Input or output voltage – 0.6 4.6 V
VDD Supply voltage – 0.6 4.6 V
DC and AC parameters NAND128-A, NAND256-A
38/59
10 DC and AC parameters
This section summarizes the operating and measurement conditions and the DC and AC
characteristics of the device . The parameter s in the DC and AC char acteristics tab les in this
section are deriv ed fr om tests performed under the me asurement co nditions summariz ed in
Table 16. Designers should check that the operating conditions in their circuit match the
measurement co nditions when relying on the quoted parameters.
Table 16. Operating and AC measurement conditions
Parameter NAND flash Units
Min Max
Supply voltage (VDD) 3 V devices 2.7 3.6 V
Ambient (TA) Grade 6 –40 85 °C
Load capacitance (CL) (1 TTL GATE
and CL)3 V devices (2.7 - 3.6 V) 50 pF
3 V devices (3.0 - 3.6V) 100 pF
Input pulses voltages 3 V devices 0.4 2.4 V
Input and output timing ref. voltages 3 V devices 1.5 V
Input rise and fall times 5 ns
Output circuit resistors, Rref 8.35 kΩ
Table 17 . Capacitance(1)(2)
1. TA = 25 °C, f = 1 MHz. CIN and CI/O are not 100% tested.
2. Input/output capacitances double on stacked devices.
Symbol Parameter Test condition Typ Max Unit
CIN Input capacitance VIN = 0 V 10 pF
CI/O Input/output capacitance VIL = 0 V 10 pF
NAND128-A, NAND256-A DC and AC parameters
39/59
Figure 20. Equiv alent testing circuit for AC c haracteristics measurement
Ai11085
NAND Flash
CL
2Rref
VDD
2Rref
GND
GND
DC and AC parameters NAND128-A, NAND256-A
40/59
Table 18. DC characterist ics(1)
1. Leakage currents double on stacked devices.
Symbol Parameter Test conditions Min Typ Max Unit
IDD1
Operating current
Sequential
read tRLRL minimum
E=VIL, IOUT = 0 mA –1020mA
IDD2 Program – – 10 20 mA
IDD3 Erase – – 10 20 mA
IDD4 Standby current (TTL) E = VIH,
WP = 0 V/VDD
– – 1 mA
– – 2 mA
IDD5 Standby current (CMOS) E = V DD-0.2
WP = 0 V/VDD
–10 50 µA
–20 100 µA
ILI Input leakage current VIN = 0 to VDDmax – – ±10 µA
ILO Output leakage current VOUT= 0 to
VDDmax – – ±10 µA
VIH Input High voltage –2.0 – VDD+0.3 V
VIL Input Low v o l tage –−0.3 –0.8 V
VOH Output High voltage level IOH = −400 µA 2.4 – - V
VOL Output Low voltage level IOL = 2.1 mA – – 0.4 V
IOL (RB)Output Low current (RB) VOL = 0.4 V 810 mA
VLKO VDD supply voltage
(erase and program lockout) – – – 1.7 V
NAND128-A, NAND256-A DC and AC parameters
41/59
t
Table 19. AC characteristics for command, address, data input
Symbol Alt.
symbol Parameter 3 V devices Unit
tALLWL tALS Address Latch Low to Write Enable Lo w AL setup time Min 0 ns
tALHWL Address Latch High to Write Enable Low
tCLHWL tCLS Command Latch High to Write Enable Low CL setup time Min 0ns
tCLLWL Co mmand Latch Low to Write Enable Low
tDVWH tDS Data Valid to Write Enable High Data setup time Min 20 ns
tELWL tCS Chip Enable Low to Write Enable Low E setup time Min 0ns
tWHALH tALH Write Enable High to Address Latch High AL hold time Min 10 ns
tWHALL Write Enable High to Address Latch Low
tWHCLH tCLH Write Enable High to Command Latch High CL hold time Min 10 ns
tWHCLL Write Enable High to Command Latch Low
tWHDX tDH Write Enable High to Data Transition Data hold time Min 10 ns
tWHEH tCH Write Enable High to Chip Enable High E hold time Min 10 ns
tWHWL tWH Write Enable High to Write Enable Low W High hold time Min 15 ns
tWLWH tWP Write Enable Low to Write Enable High W pulse width Min 25(1) ns
tWLWL tWC Write Enable Low to Write Enable Low Write cycle time Min 50 ns
1. If tELWL is less than 10 ns, tWLWH must be minimum 35 ns, otherwise, tWLWH may be minimum 25 ns.
DC and AC parameters NAND128-A, NAND256-A
42/59
Table 20. AC characteristics for operations(1)
Symbol Alt.
symbol Parameter 3 V devices Unit
tALLRL1 tAR Address Latch Low to
Read Enable Low Read electronic signature Min 10 ns
tALLRL2 Read cycle Min 10 ns
tBHRL tRR Ready/Busy High to Read Enable Low Min 20 ns
tBLBH1
Ready/Busy Low to
Ready/Busy High
Read busy time, 128-Mbit, 256-Mbit,
dual die Max 12 µs
tBLBH2 tPROG Program busy time Max 500 µs
tBLBH3 tBERS Erase busy time Max 3ms
tBLBH4 Reset busy time, during ready Max 5µs
tWHBH1 tRST Write Enable High to
Ready/Busy High
Reset busy time, during read Max 5µs
Reset busy time, during program Max 10 µs
Reset busy time, during erase Max 500 µs
tCLLRL tCLR Command Latch Low to Read Enable Low Min 10 ns
tDZRL tIR Data Hi-Z to Read Enable Low Min 0ns
tEHQZ tCHZ Chip Enable High to Output Hi-Z Max 20 ns
tELQV tCEA Chip Enable Low to Output Valid Max 45 ns
tRHRL tREH Read Enable High to
Read Enable Low Read Enable High hold time Min 15 ns
tRHQZ tRHZ Read Enable High to Output Hi-Z Max 30 ns
TEHQX TOH Chip Enable High or Read Enable High to Output Hold Min 10 ns
TRHQX
tRLRH tRP Read Enable Low to Read
Enable High Read Enable pulse width Min 25 ns
tRLRL tRC Read Enable Low to Read
Enable Low Read cycle time Min 50 ns
tRLQV tREA Read Enable Low to
Output Valid Read Enable access time Max 35 ns
Read ES access time(1)
tWHBH tRWrite Enable High to
Ready/Busy High Read busy time, 128-Mbit, 256-Mbit
dual die Max 12 µs
tWHBL tWB Write Enable High to Ready/Busy Low Max 100 ns
tWHRL tWHR Write Enable High to Read Enable Low Min 60 ns
tWLWL tWC Write Enable Lo w to Write
Enable Low Write cycle time Min 50 ns
1. ES = electronic signature.
NAND128-A, NAND256-A DC and AC parameters
43/59
Figure 21. Command Latch AC wave forms
Figure 22. Address Latch AC waveforms
ai08028
CL
E
W
AL
I/O
tCLHWL
tELWL
tWHCLL
tWHEH
tWLWH
tALLWL tWHALH
Command
tDVWH tWHDX
(CL Setup time) (CL Hold time)
(Data Setup time) (Data Hold time)
(ALSetup time) (AL Hold time)
(E Setup time) (E Hold time)
ai08029b
CL
E
W
AL
I/O
tWLWH
tELWL tWLWL
tCLLWL
tWHWL
tALHWL
tDVWH
tWLWL
tWLWH tWLWH
tWHWL
tWHDX
tWHALL
tDVWH
tWHDX
tDVWH
tWHDX
tWHALL
Adrress
cycle 1
tWHALL
(AL Setup time)
(AL Hold time)
Adrress
cycle 3
Adrress
cycle 2
(CL Setup time)
(Data Setup time)
(Data Hold time)
(E Setup time)
DC and AC parameters NAND128-A, NAND256-A
44/59
Figure 23. Data Input Latch AC waveforms
Figure 24. Sequential data output after read AC waveforms
1. CL = Low, AL = Low, W = High.
tWHCLH
CL
E
AL
W
I/O
tALLWL tWLWL
tWLWH
tWHEH
tWLWH
tWLWH
Data In 0 Data In 1 Data In
Last
tDVWH
tWHDX
tDVWH
tWHDX
tDVWH
tWHDX
i08030
(Data Setup time)
(Data Hold time)
(ALSetup time)
(CL Hold time)
(E Hold time)
tEHQX
tEHQZ
NAND128-A, NAND256-A DC and AC parameters
45/59
Figure 25. Read status register AC waveform
Figure 26. Read electronic signatur e AC waveform
1. Refer to Table 12: Electronic signature for the values of the manufacturer and device codes.
tEHQX
90h 00h Man.
code Device
code
CL
E
W
AL
R
I/O
tRLQV
Read Electronic
Signature
Command
1st Cycle
Address Manufacturer and
Device Codes
ai08039b
(Read ES Access time)
tALLRL1
DC and AC parameters NAND128-A, NAND256-A
46/59
Figure 27. Page read A/read B operation AC waveform
Figure 28. Read C operation, one page AC wa veform
1. A0-A7 is the address in the spare memory area, where A0-A3 are valid and A4-A7 are ‘don’t care’.
CL
E
W
AL
R
I/O
RB
tWLWL
tWHBL
tALLRL2
00h or
01h
Data
NData
N+1 Data
N+2 Data
Last
tWHBH tRLRL
tEHQZ
tRHQZ
ai08033d
Busy
Command
Code Address N Input Data Output
from Address N to Last Byte or Word in Page
Add.N
cycle 1 Add.N
cycle 3
Add.N
cycle 2
(Read Cycle time)
tRLRH
tBLBH1
tRHQX
tEHQX
CL
E
W
AL
R
I/O
RB
tWHALL
Data M Data
Last
tALLRL2
ai08035c
tWHBH
tBHRL
50h Add. M
cycle 1 Add. M
cycle 3
Add. M
cycle 2
Busy
Command
Code Address M Input Data Output from M to
Last Byte or Word in Area C
NAND128-A, NAND256-A DC and AC parameters
47/59
Figure 29. Page program AC waveform
Figure 30. Block erase AC waveform
CL
E
W
AL
R
I/O
RB
SR0
ai08037b
N
Last 10h
70h
80h
Page Program
Setup Code Confirm
Code Read Status Register
tWLWL tWLWL tWLWL
tWHBL
tBLBH2
Page
Program
Address Input Data Input
Add.N
cycle 1 Add.N
cycle 3
Add.N
cycle 2
(Write Cycle time)
(Program Busy time)
D0h60h SR0
70h
ai08038c
tWHBL
tWLWL
tBLBH3
Block Erase
Setup Command Block Erase
CL
E
W
AL
R
I/O
RB
Confirm
Code Read Status Register
Block Address
Input
(Erase Busy time)
(Write Cycle time)
Add.
cycle 1 Add.
cycle 2
DC and AC parameters NAND128-A, NAND256-A
48/59
Figure 31. Reset AC waveform
10.1 Ready/busy signal electrical c h aracteristics
Figures Figure 32, Figure 33, and Figure 34 show the electrical characteristics for the
Ready/Busy signal. The value req uired for the resistor RP can be calculated using the
following equation:
Therefore,
where IL is the sum of the input currents of all the devices tied to the Ready/Busy signal. RP
max is determined by the maximum value of tr.
Figure 32. Ready/Busy AC waveform
W
R
I/O
RB
tBLBH4
AL
CL
FFh
ai08043
(Reset Busy time)
RPmin VDDmax VOLmax
–()
IOL IL
+
-------------------------------------------------------------=
RPmin 3V() 3.2V
8mA IL
+
---------------------------=
NI3087B
busy
VOH
ready VDD
VOL
tftr
NAND128-A, NAND256-A DC and AC parameters
49/59
Figure 33. Ready/busy load circuit
Figure 34. Resistor value versus waveform timings for Ready/Busy signal
1. T = 25 °C.
AI07563B
RP
VDD
VSS
RB
DEVICE
Open Drain Output
ibusy
DC and AC parameters NAND128-A, NAND256-A
50/59
10.2 Data protection
The Numonyx NAND device is designed to guarantee data protection during power
transitions.
A VDD detection cir cuit disables all NAND operations , if VDD is below the VLKO threshold.
In the VDD range from VLKO to the lower limit of nominal range, the WP pin should be kept
Low (VIL) to guarantee hardwa re protection during power transitions as shown in the below
figure.
Figure 35. Data prot ection
Ai11086
VLKO
VDD
W
Nominal Range
Locked
Locked
NAND128-A, NAND256-A Package mechanical
51/59
11 Package mechanical
To meet environmental requirement s, Numonyx off ers these devices in RoHS compliant
packages, which have a lead-free second-level interconnect. The category of second-level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inn er box label.
RoHS compliant specifications are available at www.numonyx.com.
Figure 36. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline
1. Drawing is not to scale.
Table 21. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package
mechanical data
Symbol Millimeters Inches
Typ Min Max Typ Min Max
A1.200.047
A1 0.10 0.05 0.15 0.004 0.002 0.006
A2 1.00 0.95 1.05 0.039 0.037 0.041
B 0.22 0.17 0.27 0.009 0.007 0.011
C 0.10 0.21 0.004 0.008
CP 0.08 0.003
D1 12.00 11.90 12.10 0.472 0.468 0.476
E 20.00 19.80 20.20 0.787 0.779 0.795
E1 18.40 18.30 18.50 0.724 0.720 0.728
e0.50– –0.020– –
L 0.60 0.50 0.70 0.024 0.020 0.028
L1 0.80 0.031
a3°0°5°3°0°5°
TSOP-G
B
e
DIE
C
LA1 α
E1
E
A
A2
1
24
48
25
D1
L1
CP
Package mechanical NAND128-A, NAND256-A
52/59
Figure 37. VFBGA55 8 x 10 mm - 6 x 8 active ball array, 0.8 mm pitch, package
outline
1. Drawing is not to scale.
D1
D
e
b
SD
BGA-Z61
ddd
A2
A1
A
SE E2
FE1
E1 E
D2
FE
FD1
FD
NAND128-A, NAND256-A Package mechanical
53/59
Table 22. VFBGA55 8 x 10 x 1.05 mm - 6 x 8 + 7 ball array, 0.8 mm pitch, package
mechanical data
Symbol Millimeters Inches
Typ Min Max Typ Min Max
A1.050.041
A1 0.25 0.010
A2 0.65 0.026
b 0.45 0.40 0.50 0.018 0.016 0.020
D 8.00 7.90 8.10 0.315 0.311 0.319
D1 4.00 0.157
D2 5.60 0.220
ddd 0.10 0.004
E 10.00 9.90 10.10 0.394 0.390 0.398
E1 5.60 0.220
E2 8.80 0.346
e 0.80 0.031
FD 2.00 0.079
FD1 1.20 0.047
FE 2.20 0.087
FE1 0.60 0.024
SD 0.40 0.016
SE 0.40 0.016
Ordering information NAND128-A, NAND256-A
54/59
12 Ordering information
1. x16 organization only available for MCP.
Note: Not all combinations are necessarily available . For a list of available devices or for further
information on any aspect of these products, please contact your nearest Numonyx sales
office.
Table 23. Ordering information scheme
Example: NAND128 W 3 A 2 B ZA 6 E
Device type
NAND flash memory
Density
128 = 128 Mbits
256 = 256 Mbits
Operatin g voltage
W = VDD = 2.7 to 3.6 V
Bus width
3 = x8
4 = x16(1)
1.
Family identifier
A = 528-byte/264-word page
Device options
0 = No options (Chip Enable ‘care’; sequential row read enabled)
2 = Chip Enable ‘don't care’ enabled
A = Au tomotive testing
Pro duct version
A = first version
B = second version
C = third version
Package
N = TSOP48 12 x 20 mm
ZA = VFBGA55 8 x 10 x 1.05 mm
Temperature range
6 = −40 to 85 °C
Option
E = RoHS compliant package, standard packing
F = RoHS compliant package, tape and reel packing
NAND128-A, NAND256-A Hardware interface examples
55/59
Appendix A Hardware interface examples
NAND flash devices can be connected to a microcontroller system bus for code and data
storage. For microcontrollers that have an embedded NAND controller the NAND flash can
be connected wit hout the addit ion of glue logi c (see Figure 38). Ho we ver, a minimum of glue
logic is required for ge neral purpose microcontrollers that do not have an embedded NAND
controller. The glue logic usually consists of a flip-flop to hold the Chip Enable, Address
Latch Enable, and Command Latch Enable signals stable during command and address
latch operations, and some logic gates to simplify the firmware or make the design more
robust.
Figure 39 provides an example of how to connect a NAND flash to a general purpose
microcontroller. The additional OR gates allo w the microcontroller’s Output Enable and
Write Enable signals to be used for other peripherals. The OR gate between A3 and CSn
maps the flip-flop and NAND I/O in different address spaces inside the same chip select
unit, which improves the setup and hold times and simplifies the firmware. The structure
uses the microc o nt ro ller DMA (dire c t me m ory access) engines to op tim ize the transfer
between the NAND flash and the system RAM.
F o r any interface with glue logic, the extra delay caused by the gates and flip-flop must be
take n into account. This dela y m ust be added t o the microcontr oller’s AC charact eristics and
register settings to get the NAND fl ash setup and hold times.
For mass storage applications (hard disk emulations or systems where a huge amount of
storage is required) NAND flash memories can be connected together to build storage
modules (see Figure 40).
Figure 38. Connection to microcontroller, without glue logic
AI08045b
R
W
I/O
E
AL
CL
W
G
CSn
AD(24:16)
Microcontroller
NAND
Flash
DQ
WP
RBPWAITEN
AD17
AD16
VDD
VDD or VSS
or General Purpose I/O
Hardware interface examples NAND128-A, NAND256-A
56/59
Figure 39. Connection to microc ontroller, with glue logic
Figure 40. Building storage modules
AI07589
R
W
I/O
E
AL
CL
CLK
D2
D1
D0 Q0
Q1
Q2
W
G
CSn
A3
A0
A1
A2
Microcontroller NAND Flash
DQ
D flip-flop
AI08331
WNAND Flash
Device 1
G
E
1
CL
AL NAND Flash
Device 3
NAND Flash
Device 2 NAND Flash
Device n+1
NAND Flash
Device n
E
2
E
3
E
n
E
n+1
I/O0-I/O7 or
I/O0-I/O15
RB
NAND128-A, NAND256-A Revision history
57/59
13 Revision history
Table 24. Document revision history
Date Version Revision details
06-Jun-2003 1 Initial release
07-Aug-2003 2 Design phase
27-Oct-2003 3 Engineering phase
03-Dec-2003 4
Document promoted from Target Specification to Preliminary Data status.
VCC changed to VDD and ICC to IDD.
Changed title of Table 2: Product description and page program typical
timing for NANDXXXR3A devices corrected. Table 1: NAND128-A and
NAND256-A device summary, inserted on page 2.
13-Apr-2004 5
WSOP48 and VFBGA55 packages added, VFBGA63 (9 x 11 x 1mm)
removed.
Figure 19: Cache Program Operation, modified and note 2 modified. Note
removed for tWLWH timing in Table 19: AC characteristics for command,
address, data input. Meaning of tBLBH4 modified, partly replaced by
tWHBH1 and tWHRL min for 3 V devices modified in Table 20: AC
characteristics for operations.
References removed from Section 13: Revision history section and
reference made to ST website instead.
Figure 5: VFBGA55 connections, x8 devices (top view through pac kage),
Figure 6: VFBGA55 connections, x16 devices (top view through
package), Figure 27 : Page read A/read B operation AC waveform and
Figure 30: Block erase AC waveform modified. Section 6.8: Read
electronic signature clarified and Figure 26: Read electronic signature AC
waveform, modified. Note 2 to Figure 28: Read C operation, one page AC
waveform removed. Only 00h pointer operations are valid bef ore a cache
program operation. Note added to Figure 30: Block erase AC waveform.
Small text changes.
28-May-2004 6
TFBGA55 package added (mechanical data to be announced). 512-Mbit
dual die devices added. Figure 19 ., Cache Program Operatio n modified.
Package code changed for TFBGA63 8.5 x 15 x 1.2 mm, 6x8 ball array,
0.8 mm pitch (1-Gbit dual die devices) in Table 23: Ordering information
scheme.
02-Jul-2004 7
Cache Program removed from document. TFBGA55 package
specifications added (Figure 40., TFBGA55 8 x 10mm - 6x8 active ball
array - 0.80mm pitch, Package Outline and Table 25., TFBGA55 8 x
10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data).
Test conditions modified for VOL and VOH parameters.
01-Oct-2004 8
Section 6.5: Block erase last address cycle modified. Definition of a bad
bloc k modified in Section 7.1: Bad bloc k management. RoHS compliance
added to Section 1: Description. Figure 2: Logic block diagram modified.
Document promoted from Preliminary Data to Full Datasheet status.
03-Dec-2004 9 Automatic Page 0 Read at power-up option no longer available.
PC Demo board with simulation software removed from list of available
deve l o pment tools. Section 3.5: Chip Enable (E) paragraph cl arifie d.
Revision history NAND128-A, NAND256-A
58/59
13-Dec-2004 10 Rref pa rameter added to the description of the family clarified in the
Section 1: Description.
25-Feb-2005 11
WSOP48 replaced with USOP48 package,
VFBGA63 (8.5 x 15 x 1mm) replaced with VFBGA63 (9 x 11 x 1mm)
package,
TFBGA63 (8.5 x 15 x 1mm) replaced with TFBGA63 (9 x 11 x 1.2mm)
package.
Changes to Table 20: AC characteristics for operations.
23-June-2005 12
tEHBH, tEHEL, tRHBL removed throughout document. TFBGA63 and TFBGA55
packages removed throughout document. Sequential row read removed
throughout document.
TEHQX and TRHQX added throughout document. Section 10.2: Data
protection section and Figure 20: Equivalent testing circuit for AC
characteristics measurement added.
Modified Section 3.7: Write Enable (W), Section 3.5: Chip Enable (E),
Section 6.2: Read memory array, Section 6.3: Page program,
Section 6.8: Read electronic signature, Section 7.1: Bad block
management and Section 12: Ordering information.
Figure 10: Read (A, B, C) operations and Figure 26: Read electronic
signature AC waveform modified.
09-Aug-2005 13 Note added to Figure 3: TSOP48 connections, x8 devices and Figure 4:
TSOP48 connections, x16 devices regardin g th e U SOP pa ckage.
20-Jun-2008 14 Removed all information pertaining to the 512-Mbit and 1-Gbit devices.
Applied Numonyx branding.
13-Aug-2008 15 Remov ed all the inf ormation pertaining the 1.8 V devices (VDD = 1.7 to
1.95 V) and the USOP48 and VFBGA63 packages. Added the sequential
row read option throughout the document.
30-Nov-2009 16
Added secur ity features on the cover page and in Section 1: Description.
Updated Figure 32: Ready/Busy AC wav eform and Figure 34: Resistor
value versus waveform timings for Ready/Busy signal. Ref e re nces to
ECOPACK removed and replaced by RoHS compliance. Modified
dimension A2 of the VFBGA55 package in Table 22. Added automotive
testing optio n in Table 23: Ordering information scheme.
Table 24 . Document revision history (con tinued)
Date Version Revision details
NAND128-A, NAND256-A
59/59
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