ADS828E/1K - Texas Instruments

ADS828

10-Bit, 75MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

●HIGH SNR: 58dB

●LOW POWER: 325mW

●+3V/+5V LOGIC I/O COMPATIBLE

●INTERNAL/EXTERNAL REFERENCE OPTION

●SINGLE-ENDED OR DIFFERENTIAL ANALOG

INPUT

●PROGRAMMABLE INPUT RANGE:

1Vp-p or 2Vp-p

●LOW DNL: 0.4LSB

●SINGLE +5V SUPPLY OPERATION

●POWER DOWN: 20mW

●SSOP-28 PACKAGE

APPLICATIONS

●HDTV VIDEO DIGITIZING

●MEDICAL IMAGING

●COMMUNICATIONS

●TEST EQUIPMENT

DESCRIPTION

The ADS828 is a pipeline, CMOS analog-to-digital con-

verter that operates from a single +5V power supply. This

converter provides excellent performance with a single-

ended input and can be operated with a differential input for

added spurious performance. This high performance con-

verter includes a 10-bit quantizer, high bandwidth track/

hold, and a high accuracy internal reference. It also allows

for the user to disable the internal reference and utilize

external references. This external reference option provides

excellent gain and offset matching when used in multi-

channel applications or in applications where full scale

range adjustment is required.

The ADS828 employs digital error correction techniques to

provide excellent differential linearity for demanding im-

aging applications. Its low distortion and high SNR give the

extra margin needed for medical imaging, communications,

video, and test instrumentation. The ADS828 offers power

dissipation of 325mW and also provides a power-down

mode, thus reducing power dissipation to only 20mW.

The ADS828 is specified at a maximum sampling frequency

of 75MHz and a single-ended input range of 1.5V to 3.5V.

The ADS828 is available in a SSOP-28 package and is pin

compatible with the 10-bit, 40MHz ADS822 and ADS825,

and the 10-bit, 60MHz ADS823 and ADS826.

10-Bit

Pipelined

A/D Core

Internal

Reference

Optional External

Reference

Timing

Circuitry

Error

Correction

Logic

3-State

Outputs

T/H

CLK VDRV

ADS828

OEPDInt/Ext

•

INV

ADS828

SBAS126A – MARCH 2001

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ADS828

2SBAS126A

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

PACKAGE SPECIFIED

DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER(1) MEDIA

ADS828E SSOP-28 324 –40°C to +85°C ADS828E ADS828E Rails

" " " " " ADS828E/1K Tape and Reel

NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces

of ADS828E/1K” will get a single 1000-piece Tape and Reel.

PACKAGE/ORDERING INFORMATION

+VS....................................................................................................... +6V

Analog Input............................................................. –0.3V to (+VS + 0.3V)

Logic Input ............................................................... –0.3V to (+VS + 0.3V)

Case Temperature ......................................................................... +100 °C

Junction Temperature .................................................................... +150°C

Storage Temperature..................................................................... +150°C

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 75MHz, convert command clock = +3V, external reference unless

otherwise noted.

ADS828E

PARAMETER CONDITIONS MIN TYP MAX UNITS

RESOLUTION 10 Guaranteed Bits

SPECIFIED TEMPERATURE RANGE Ambient Air –40 to +85 °C

ANALOG INPUT

Standard Single-Ended Input Range 2Vp-p 1.5 3.5 V

Optional Single-Ended Input Range 1Vp-p 2 3 V

Common-Mode Voltage 2.5 V

Optional Differential Input Range 2Vp-p 2 3 V

Analog Input Bias Current 1µA

Input Impedance 1.25 || 5 MΩ || pF

Track-Mode Input Bandwidth –3dBFS 300 MHz

CONVERSION CHARACTERISTICS

Sample Rate 10k 75M Samples/s

Data Latency 5 Clk Cyc

DYNAMIC CHARACTERISTICS

Differential Linearity Error (largest code error)

f = 1MHz ±0.4 ±1.0 LSB

f = 10MHz ±0.4 LSB

No Missing Codes Guaranteed

Integral Nonlinearity Error, f = 1MHz ±1.0 ±3.0 LSBs

Spurious Free Dynamic Range(1) Referred to Full Scale

f = 1MHz 70 dBFS(2)

f = 10MHz 68 dBFS

Two-Tone Intermodulation Distortion(3)

f = 9.5MHz and 9.9MHz (–7dB each tone) –62 dBc

Signal-to-Noise Ratio (SNR) Referred to Full Scale

f = 1MHz 58 dB

f = 10MHz 55 57 dB

Signal-to-(Noise + Distortion) (SINAD) Referred to Full Scale

f = 1MHz 57 dB

f = 10MHz 50 57 dB

Effective Number of Bits(4), f = 1MHz 9.3 Bits

Output Noise Input Grounded 0.2 LSBs rms

Aperture Delay Time 3ns

Aperture Jitter 1.2 ps rms

Overvoltage Recovery Time 2ns

Full-Scale Step Acquisition Time 5ns

ADS828 3

SBAS126A

ELECTRICAL CHARACTERISTICS (Cont.)

At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 75MHz, convert command clock = +3V, external reference unless

otherwise noted.

CMOS

Straight Offset Binary

ADS828E

PARAMETER CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUTS

Logic Family TTL, +3V/5V CMOS Compatible

Convert Command Start Conversion Rising Edge of Convert Clock

High Level Input Current(5) (VIN = 5V) 100 µA

Low Level Input Current (VIN = 0V) 10 µA

High Level Input Voltage +2.0 V

Low Level Input Voltage +0.8 V

Input Capacitance 5pF

DIGITAL OUTPUTS

Logic Family

Logic Coding

Low Output Voltage (IOL = 50µA) VDRV = 5V +0.1 V

Low Output Voltage, (IOL = 1.6mA) +0.2 V

High Output Voltage, (IOH = 50µA) +4.9 V

High Output Voltage, (IOH = 0.5mA) +4.8 V

Low Output Voltage (IOL = 50µA) VDRV = 3V +0.1 V

High Output Voltage, (IOH = 50µA) +2.8 V

3-State Enable Time OE = L 20 40 ns

3-State Disable Time OE = H 2 10 ns

Output Capacitance 5pF

ACCURACY

(Internal Reference, 2Vp-p, Unless Otherwise Noted)

fS = 2.5MHz

Zero Error (Referred to –FS) at 25°C±0.5 ±3.0 %FS

Zero Error Drift (Referred to –FS) 1.5 ppm/°C

Midscale Offset Error at 25 °C±0.29 %FS

Gain Error(6) at 25°C±1.5 ±2.5 %FS

Gain Error Drift(6) 32.3 ppm/°C

Gain Error(7) at 25°C±0.75 ±1.5 %FS

Gain Error Drift(7) 4.6 ppm/°C

Power Supply Rejection of Gain ∆ VS = ±5% 68 dB

REFT Tolerance Deviation from Ideal 3.5V ±10 ±25 mV

REFB Tolerance Deviation From Ideal 1.5V ±10 ±25 mV

External REFT Voltage Range REFB + 0.8 3.5 VS – 1.25 V

External REFB Voltage Range 1.25 1.5 REFT – 0.8 V

Reference Input Resistance 1.6 kΩ

POWER SUPPLY REQUIREMENTS

Supply Voltage: +VSOperating +4.75 +5.0 +5.25 V

Supply Current: +ISOperating 68 mA

Output Driver Supply Current (VDRV) 9mA

Power Dissipation: VDRV = 5V External Reference 340 385 mW

VDRV = 3V External Reference 325 mW

VDRV = 5V Internal Reference 355 mW

VDRV = 3V Internal Reference 345 mW

Power Down Operating 20 mW

Thermal Resistance,

SSOP-28 89 °C/W

NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) Two-tone

intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental

envelope. (4) Effective number of bits (ENOB) is defined by (SINAD – 1.76) /6.02. (5) A 50kΩ pull-down resistor is inserted internally. (6) Includes internal

reference. (7) Excludes internal reference.

ADS828

4SBAS126A

TIMING DIAGRAM

5 Clock Cycles

Data Invalid

CONV

N–5N–4N–3N–2N–1 N N+1 N+2

Data Out

Clock

Analog In N

N+1 N+2 N+3 N+4 N+5 N+6 N+7

SYMBOL DESCRIPTION MIN TYP MAX UNITS

tCONV Convert Clock Period 13.3 100µsns

tLClock Pulse Low 6.4 6.7 ns

tHClock Pulse High 6.4 6.7 ns

tDAperture Delay 3 ns

t1Data Hold Time, CL = 0pF 3.9 ns

t2New Data Delay Time, CL = 15pF max 12 ns

PIN DESIGNATOR DESCRIPTION

1 GND Ground

2 Bit 1 Data Bit 1 (D9) (MSB)

3 Bit 2 Data Bit 2 (D8)

4 Bit 3 Data Bit 3 (D7)

5 Bit 4 Data Bit 4 (D6)

6 Bit 5 Data Bit 5 (D5)

7 Bit 6 Data Bit 6 (D4)

8 Bit 7 Data Bit 7 (D3)

9 Bit 8 Data Bit 8 (D2)

10 Bit 9 Data Bit 9 (D1)

11 Bit 10 Data Bit 10 (D0) (LSB)

12 OE Output Enable. HI = high impedance state.

LO = normal operation (internal pull-

down resistor)

13 PD Power Down. HI = power down; LO = normal

14 CLK Convert Clock Input

15 +VS+5V Supply

16 GND Ground

17 RSEL Input Range Select. HI = 2Vp-p; LO = 1Vp-p

18 INT/EXT Reference Select. HI = external; LO = internal

19 REFB Bottom Reference

20 ByB Bottom Ladder Bypass

21 ByT Top Ladder Bypass

22 REFT Top Reference

23 CM Common-Mode Voltage Output

24 IN Complementary Input (–)

25 IN Analog Input (+)

26 GND Ground

27 +VS+5V Supply

28 VDRV Output Logic Driver Supply Voltage

PIN DESCRIPTIONS

PIN CONFIGURATION

Top View SSOP

GND

Bit 1 (MSB)

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9

Bit 10 (LSB)

CLK

VDRV

GND

REFT

ByT

ByB

REFB

INT/EXT

RSEL

GND

ADS828

ADS828 5

SBAS126A

TYPICAL CHARACTERISTICS

At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 75MHz, external reference, VDRV +3V, unless otherwise noted.

–20

–40

–60

–80

–100 07.5 15 22.5 37.530

SPECTRAL PERFORMANCE

(Differential Input, 2Vp-p, Internal Reference)

Magnitude (dB)

Frequency (MHz)

= 10MHz

SFDR = 70dBFS

SNR = 58.4dBFS

–20

–40

–60

–80

–100 07.5 15 22.5 37.530

SPECTRAL PERFORMANCE

(Differential Input, 2Vp-p, Internal Reference)

Magnitude (dB)

Frequency (MHz)

= 20MHz

SFDR = 70dBFS

SNR = 57.6dBFS

–20

–40

–60

–80

–100 07.5 15 22.5 37.530

SPECTRAL PERFORMANCE

(Single-Ended, 2Vp-p, Internal Reference)

Magnitude (dB)

Frequency (MHz)

= 10MHz

SFDR = 64.6dBFS

SNR = 55.5dBFS

–20

–40

–60

–80

–100 07.5 15 22.5 37.530

SPECTRAL PERFORMANCE

(Single-Ended Input, 2Vp-p, Internal Reference)

Magnitude (dB)

Frequency (MHz)

= 20MHz

SFDR = 62.3dBFS

SNR = 55.2dBFS

–20

–40

–60

–80

–100 07.5 15 22.5 37.530

SPECTRAL PERFORMANCE

(Single-Ended, 1Vp-p, Internal Reference)

Magnitude (dB)

Frequency (MHz)

= 10MHz

SFDR = 61.9dBFS

SNR = 51.2dBFS

–20

–40

–60

–80

–100 07.5 15 22.5 37.530

SPECTRAL PERFORMANCE

(Single-Ended, 1Vp-p, Internal Reference)

Magnitude (dB)

Frequency (MHz)

fIN = 20MHz

SFDR = 61.6dBFS

SNR = 51dBFS

ADS828

6SBAS126A

TYPICAL CHARACTERISTICS (Cont.)

At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 75MHz, external reference, VDRV +3V, unless otherwise noted.

55–50 –25 025 50 75 100

SNR

SFDR

= 10MHz

SFDR, SNR (dBFS)

Temperature (°C)

DYNAMIC PERFORMANCE vs TEMPERATURE

0.50

0.40

0.30

0–50 –25 025 50 75 100

DLE (LSB)

Temperature (°C)

DIFFERENTIAL LINEARITY ERROR

vs TEMPERATURE

fIN = 1MHz

365

355

345

335

325–50 –25 025 50 75 100

VDRV = 5V

Power Dissipation (mw)

Temperature (°C)

POWER DISSIPATION vs TEMPERATURE

0.5

0.25

0.00

–0.25

–0.5 0256 512 768 1024

Output Code

DNL (LSB)

DIFFERENTIAL LINEARITY ERROR

= 1MHz

1.0

0.5

0.0

–0.5

–1.0 0256 512 768 1024

Output Code

INL (LSB)

INTEGRAL LINEARITY ERROR

fIN = 1MHz

–20

–40

–60

–80

–100 07.5 15 22.5 37.530

TWO-TONE INTERMODULATION DISTORTION

(Differential Input, 2Vp-p)

Magnitude (dB)

Frequency (MHz)

= 9.5MHz at –7dBFS

= 9.9MHz at –7dBFS

IMD(3) = –62dBc

ADS828 7

SBAS126A

TYPICAL CHARACTERISTICS (Cont.)

At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 75MHz, external reference, VDRV +3V, unless otherwise noted.

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0

Input Amplitude(dBfS)

SFDR(dBFS, dBc)

SWEPT POWER SFDR

(DIFFERENTIAL INPUT, 2Vpp)

fIN = 10MHz

dBFS

dBc

800k

700k

600k

500k

400k

300k

200k

100k

OUTPUT NOISE HISTOGRAM (DC Input)

Counts

N-2 N-1 N N+1 N+2

Output Code

ADS828

8SBAS126A

APPLICATION INFORMATION

THEORY OF OPERATION

The ADS828 is a high-speed, CMOS A/D converter which

employs a pipelined converter architecture consisting of

9 internal stages. Each stage feeds its data into the digital

error correction logic ensuring excellent differential linear-

ity and no missing codes at the 10-bit level. The output data

becomes valid on the rising clock edge (see Timing Dia-

gram). The pipeline architecture results in a data latency of

5 clock cycles.

The analog input of the ADS828 is a differential track and

hold (see Figure 1). The differential topology along with

tightly matched capacitors produce a high level of ac-

performance while sampling at very high rates.

The ADS828 allows its analog inputs to be driven either

single-ended or differentially. The typical configuration for

the ADS828 is for the single-ended mode in which the input

track-and-hold performs a single-ended-to-differential con-

version of the analog input signal.

Both inputs (IN, IN) require external biasing using a com-

mon-mode voltage that is typically at the mid-supply level

(+VS/2).

The following application discussion focuses on the single-

ended configuration. Typically, its implementation is easier

to achieve and the rated specifications for the ADS828 are

characterized using the single-ended mode of operation.

DRIVING THE ANALOG INPUT

The ADS828 achieves excellent ac performance either in the

single-ended or differential mode of operation. The selection

for the optimum interface configuration will depend on the

individual application requirements and system structure.

For example, communications applications often process a

band of frequencies that do not include DC, whereas in

imaging applications, the previously restored DC level must

be maintained correctly up to the A/D converter. Features on

the ADS828 such as the input range select (RSEL pin) or the

option for an external reference, provide the needed flexibil-

ity to accommodate a wide range of applications. In any

case, the ADS828 should be configured such that the appli-

cation objectives are met while observing the headroom

requirements of the driving amplifier in order to yield the

best overall performance.

INPUT CONFIGURATIONS

AC-Coupled, Single-Supply Interface

Figure 2 shows the typical circuit for an ac-coupled analog

input configuration of the ADS828 while all components are

powered from a single +5V supply.

With the RSEL pin connected high, the full-scale input

range is set to 2Vp-p. In this configuration, the top and

bottom references (REFT, REFB) provide an output voltage

of +3.5V and +1.5V, respectively. Two resistors ( 2x 1.0kΩ)

are used to create a common-mode voltage (VCM) of ap-

proximately +2.5V to bias the inputs of the driving amplifier

A1. Using the OPA680 on a single +5V supply, its ideal

common-mode point is at +2.5V, which coincides with the

recommended common-mode input level for the ADS828.

This obviates the need of a coupling capacitor between the

amplifier and the converter. Even though the OPA680 has an

ac gain of +2, the dc gain is only +1 due to the blocking

capacitor at resistor RG.

The addition of a small series resistor (RS) between the

output of the op amp and the input of the ADS828 will be

beneficial in almost all interface configurations. This will

decouple the op amp’s output from the capacitive load and

avoid gain peaking, which can result in increased noise. For

best spurious and distortion performance, the resistor value

should be kept below 100Ω. Furthermore, the series resistor,

in combination with the 10pF capacitor, establishes a pas-

sive low-pass filter, limiting the bandwidth for the wideband

noise thus, help improving the SNR performance.

AC-Coupled, Dual Supply Interface

The circuit provided in Figure 3 shows typical connections

for the analog input in case the selected amplifier operates

on dual supplies. This might be necessary to take full

advantage of very low distortion operational amplifiers, like

the OPA642. The advantage is that the driving amplifier can

be operated with a ground referenced bipolar signal swing.

This will keep the distortion performance at its lowest since

the signal range stays within the linear region of the op amp

and sufficient headroom to the supply rails can be main-

tained. By capacitively coupling the single-ended signal to

the input of the ADS828, its common-mode requirements

can easily be satisfied with two resistors connected between

the top and bottom reference.

FIGURE 1. Simplified Circuit of Input Track-and-Hold with

Timing Diagram.

φ1

φ1φ2φ1

φ1φ1

φ1

φ2

φ1φ2φ1

φ2

OUT

Op Amp

Bias V

Op Amp

Bias V

Input Clock (50%)

Internal Non-overlapping Clock

ADS828 9

SBAS126A

FIGURE 2. AC-Coupled Input Configuration for a 2Vp-p Full-Scale Range and a Common-Mode Voltage, VCM, at +2.5V Derived

From The Internal Top (REFT) and Bottom Reference (REFB).

FIGURE 3. AC-Coupling the Dual Supply Amplifier OPA642 to the ADS828 for a 2Vp-p Full-Scale Input Range.

For applications requiring the driving amplifier to provide a

signal amplification, with a gain ≥ 5, consider using decom-

pensated voltage-feedback op amps, like the OPA643, or

current-feedback op amps like the OPA681 and OPA658.

DC-coupled with Level Shift

Several applications may require that the bandwidth of the

signal path include DC, in which case, the signal has to be

DC-coupled to the A/D converter. In order to accomplish

this, the interface circuit has to provide a DC level shift to

the analog input signal. The circuit shown in Figure 4

employs a dual op amp, A1, to drive the input of the

ADS828 and level shift the signal to be compatible with the

selected input range. With the RSEL pin tied to the supply

and the INT/EXT pin to ground, the ADS828 is configured

for a 2Vp-p input range and uses the internal references. The

complementary input (IN) may be appropriately biased

using the +2.5V common-mode voltage available at the

CM pin. One-half of amplifier A1 buffers the REFB pin and

drives the voltage divider R1, R2. Because of the op amp’s

noise gain of +2V/V, assuming RF = RIN, the common-mode

voltage (VCM) has to be re-scaled to +1.25. This results in

the correct DC level of +2.5V for the signal input (IN). Any

DC voltage differences between the IN and IN inputs of the

ADS828 effectively produces an offset, which can be cor-

rected for by adjusting the resistor values of the divider, R1

and R2. The selection criteria for a suitable op amp should

include the supply voltage, input bias current, output voltage

swing, distortion, and noise specification. Note that in this

example, the overall signal phase is inverted. To re-establish

the original signal polarity, it is always possible to inter-

change the IN and IN connections.

+VIN 0V

–VIN

OPA680

VIN

402Ω

1.0kΩ

402Ω

ADS828

50Ω

10pF

0.1µF

INT/EXT GND

REFT

+3.5V

1.0kΩ

50Ω

VCM +2.5V

REFB

+1.5V

0.1µF

RSEL +VS

+5V

OPA642

402Ω

1.0kΩ

402Ω

ADS828

24.9Ω

1.0kΩ

100pF

0.1µF

0.1µFIN

REFB

+1.5V INT/EXT GND

REFT

+3.5V RSEL +V

+5V

–5V

ADS828

10 SBAS126A

FIGURE 4. DC-Coupled Interface Circuit with Level Shifting Using Dual Current-Feedback Amplifier OPA2681.

FIGURE 5. Transformer Coupled Input.

FIGURE 6. Equivalent Reference Circuit with Recommended

Reference Bypassing.

SINGLE-ENDED-TO-DIFFERENTIAL CONFIGURATION

(Transformer Coupled)

If the application requires a signal conversion from a single-

ended source to feed the ADS828 differentially, a RF trans-

former might be a good solution. The selected transformer

must have a center tap in order to apply the common-mode

DC voltage necessary to bias the converter inputs.

AC grounding the center tap will generate the differential

signal swing across the secondary winding. Consider a step-

up transformer to take advantage of a signal amplification

without the introduction of another noise source. Further-

more, the reduced signal swing from the source may lead to

an improved distortion performance.

The differential input configuration may provide a notice-

able advantage of achieving good SFDR performance over a

wide range of input frequencies. In this mode, both inputs of

the ADS828 see matched impedances, and the differential

signal swing can be reduced to half of the swing required for

single-ended drive. Figure 5 shows the schematic for the

suggested transformer-coupled interface circuit. The compo-

nent values of the R-C low-pass may be optimized depend-

ing on the desired roll-off frequency. The resistor across the

secondary side (RT) should be calculated using the equation

RT = n2 x RG to match the source impedance (RG) for good

power transfer and Voltage Standing Wave Ratio (VSWR).

REFERENCE OPERATION

Figure 6 depicts the simplified model of the internal refer-

ence circuit. The internal blocks are the bandgap voltage

reference, the drivers for the top and bottom reference, and

the resistive reference ladder. The bandgap reference circuit

2Vp-p

NOTE: R

= R

, G = –1

200Ω

1kΩ

ADS828

50Ω

10pF

0.1µF

CM (+2.5V)

INT/EXT

499Ω

= +1.25V

REFB

(+1.5V) REFT

(+3.5V)

1/2

OPA2681

1/2

OPA2681

1kΩ

50Ω0.1µF

0.1µF

RSEL +V

+5V

VIN IN

IN CM

22Ω

47pF

+10µF0.1µF

INT/EXTRSEL

+5V

ADS828

1:n

0.1µF

ADS828

REFT ByT CM ByB REFB

Bypass Capacitors: 0.1µF || 2.2µF each

Bandgap Reference and Logic

REF

400Ω400Ω400Ω400Ω

+1+1

50kΩ50kΩ

INT/EXTRSEL

ADS828 11

SBAS126A

FIGURE 8. Configuration Example for External Reference Operation.

FIGURE 7. Alternative Circuit to Generate CM Voltage.

includes logic functions that allows setting the analog input

swing of the ADS828 to either a 1Vp-p or 2Vp-p full-scale

range by simply tying the RSEL pin to a Low or High

potential, respectively. While operating the ADS828 in the

external reference mode, the buffer amplifiers for the REFT

and REFB are disconnected from the reference ladder.

As shown, the ADS828 has internal 50kΩ pull-up resistors

at the range select pin (RSEL) and reference select pin

(INT/EXT). Leaving these pins open configures the ADS828

for a 2Vp-p input range and external reference operation.

Setting the ADS828 up for internal reference mode requires

to bringing the INT/EXT pin low.

The reference buffers can be utilized to supply up to 1mA

(sink and source) to external circuitry. The resistor ladder of

the ADS828 is divided into several segments and has two

additional nodes, ByT and ByB, which are brought out for

external bypassing only (Figure 6). To ensure proper opera-

tion with any reference configurations, it is necessary to

provide solid bypassing at all reference pins in order to keep

the clock feedthrough to a minimum. All bypassing capaci-

tors should be located as close to their respective pins as

possible.

The common-mode voltage available at the CM-pin may be

used as a bias voltage to provide the appropriate offset for

the driving circuitry. However, care must be taken not to

appreciably load this node, which is not buffered and has a

high impedance. An alternative way of generating a com-

mon-mode voltage is given in Figure 7. Here, two external

precision resistors (tolerance 1% or better) are located

between the top and bottom reference pins. The common-

mode voltage, CMV, will appear at the midpoint.

EXTERNAL REFERENCE OPERATION

For even more design flexibility, the internal reference can

be disabled and an external reference voltage be used. The

utilization of an external reference may be considered for

applications requiring higher accuracy, improved tempera-

ture performance, or a wide adjustment range of the

converter’s full-scale range. Especially in multichannel

applications, the use of a common external reference has the

benefit of obtaining better matching of the full-scale range

between converters.

The external references can vary as long as the value of the

external top reference REFTEXT stays within the range of

(VS – 1.25V) and (REFB + 0.8V), and the external bottom

reference REFBEXT stays within 1.25V and (REFT – 0.8V).

See Figure 8.

DIGITAL INPUTS AND OUTPUTS

Clock Input Requirements

Clock jitter is critical to the SNR performance of high speed,

high resolution A/D converters. Clock jitter leads to aperture

jitter (tA), which adds noise to the signal being converted. The

ADS828 samples the input signal on the rising edge of the

CLK input. Therefore, this edge should have the lowest

possible jitter. The jitter noise contribution to total SNR is

REFT

+3.5V

ADS828

CMV

+2.5V

REFB

+1.5V

1.0kΩR2

1.0kΩ

0.1µF0.1µF

ADS828

INT/EXT

REFT ByT GND ByB REFB

4 x 0.1µF || 2.2µFExternal Top Reference

REFT = REFB +0.8V to +3.75V

+VS

RSEL GND

+5V

External Bottom Reference

REFB = REFT –0.8V to +1.25V

A - Short for 1Vp-p Input Range

B - Short for 2Vp-p Input Range (Default)

CMV

+2.5V

ADS828

12 SBAS126A

JitterSNR trmssignaltormsnoise

IN A

=ƒ

20 1

log π

FIGURE 9. Recommended Bypassing for the Supply Pins.

+FS –1LSB (IN = +3V, IN = +2V) 11 1111 1111

+1/2 Full Scale 11 0000 0000

Bipolar Zero (IN = IN = CMV) 10 0000 0000

–1/2 Full Scale 01 0000 0000

–FS (IN = +2V, IN = +3V) 00 0000 0000

STRAIGHT OFFSET BINARY

DIFFERENTIAL INPUT (SOB)

TABLE II. Coding Table for Differential Input Configuration

and 2Vp-p Full-Scale Range.

+FS –1LSB (IN = REFT) 11 1111 1111

+1/2 Full Scale 11 0000 0000

Bipolar Zero (IN = CMV) 10 0000 0000

–1/2 Full Scale 01 0000 0000

–FS (IN = REFB) 00 0000 0000

SINGLE-ENDED INPUT STRAIGHT OFFSET BINARY

(IN = CMV) (SOB)

TABLE I. Coding Table for Single-Ended Input Configura-

tion with IN Tied to the Common-Mode Voltage

(CMV).

given by the following equation. If this value is near your

system requirements, input clock jitter must be reduced.

where: ƒIN is input signal frequency

tA is rms clock jitter

Special consideration should be given to clock jitter, particu-

larly in undersampling applications. The clock input should

be treated as an analog input in order to achieve the highest

level of performance. Any overshoot or undershoot of the

clock signal may cause degradation of performance. When

digitizing at high sampling rates, the clock should have 50%

duty cycle (tH = tL), along with fast rise and fall times of 2ns

or less. The clock input of the ADS828 can be driven with

either 3V or 5V logic levels. Using low-voltage logic (3V)

may lead to improved AC performance of the converter.

Digital Outputs

The output data format of the ADS828 is in positive Straight

Offset Binary code, see Tables I and II. This format can

easily be converted into the Binary Two’s Complement code

by inverting the MSB.

It is recommended to keep the capacitive loading on the data

lines as low as possible (≤ 15pF). Higher capacitive loading

will cause larger dynamic currents as the digital outputs are

changing. Those high current surges can feed back to the

analog portion of the ADS828 and affect the performance. If

necessary, external buffers or latches close to the converter’s

output pins may be used to minimize the capacitive loading.

They also provide the added benefit of isolating the ADS828

from any digital noise activities on the bus coupling back

high frequency noise.

Digital Output Driver (VDRV)

The ADS828 features a dedicated supply pin for the output

logic drivers, VDRV, which is not internally connected to

the other supply pins. By setting the voltage at VDRV to

+5V or +3V, the ADS828 produces corresponding logic

levels and can directly interface to the selected logic family.

The output stages are designed to supply sufficient current to

drive a variety of logic families. However, it is recom-

mended to use the ADS828 with +3V logic supply. This will

lower the power dissipation in the output stages due to the

lower output swing and reduce current glitches on the supply

line, which may affect the ac performance of the converter.

In some applications, it might be advantageous to decouple

the VDRV pin with additional capacitors or a pi-filter.

GROUNDING AND DECOUPLING

Proper grounding and bypassing, short lead length, and the

use of ground planes are particularly important for high

frequency designs. Multilayer PC boards are recommended

for best performance since they offer distinct advantages like

minimizing ground impedance, separation of signal layers

by ground layers, etc. The ADS828 should be treated as an

analog component. Whenever possible, the supply pins should

be powered by the analog supply. This will ensure the most

consistent results since digital supply lines often carry high

levels of noise which otherwise would be coupled into the

converter and degrade the achievable performance. All ground

connections on the ADS828 are internally joined together,

obviating the design of split ground planes. The ground pins

(1, 16, 26) should directly connect to an analog ground

plane, which covers the PC board area around the converter.

While designing the layout, it is important to keep the analog

signal traces separated from any digital lines to prevent noise

coupling onto the analog signal path. Because of its high

sampling rate the, ADS828 generates high frequency current

transients and noise (clock feedthrough) that are fed back

into the supply and reference lines. This requires that all

supply and reference pins be sufficiently bypassed. Figure 9

shows the recommended decoupling scheme for the ADS828.

In most cases, 0.1µF ceramic chip capacitors at each pin are

adequate to keep the impedance low over a wide frequency

range. Their effectiveness largely depends on the proximity

to the individual supply pin. Therefore, they should be

located as close to the supply pins as possible. In addition,

a larger bipolar capacitor (1µF to 22µF) should be placed on

the PC board in proximity of the converter circuit.

27 26

GND

ADS828

0.1µF0.1µF

15 16

GND

10µF

+5V

VDRV

0.1µF

+3/+5V

PACKAGE OPTION ADDENDUM

www.ti.com 21-May-2010

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

ADS828E ACTIVE SSOP DB 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

ADS828E/1K ACTIVE SSOP DB 28 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

ADS828E/1KG4 ACTIVE SSOP DB 28 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

ADS828EG4 ACTIVE SSOP DB 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS828E/1K SSOP DB 28 1000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS828E/1K SSOP DB 28 1000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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