MF1521-03 Power Supply IC S1F81100 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from anther government agency. (c)SEIKO EPSON CORPORATION 2003, All rights reserved. Intel is registered trademark of Intel Corporation. XScale is trademark of Intel Corporation. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. Configuration of product number DEVICES S1 F 81100 F 00A0 00 Packing specifications 00: Besides tape & reel 0A: TCP BL 2 directions 0B: Tape & reel Back 0C: TCP BR 2 directions 0D: TCP BT 2 directions 0E: TCP BD 2 directions 0F: Tape & reel FRONT 0G: TCP BT 4 directions 0H: TCP BD 4 directions 0J: TCP SL 2 directions 0K: TCP SR 2 directions 0L: Tape & reel LEFT 0M: TCP ST 2 directions 0N: TCP SD 2 directions 0P: TCP ST 4 directions 0Q: TCP SD 4 directions 0R: Tape & reel RIGHT 99: Specs not fixed Specifications Shape (F : QFP) Model number Model name (F : Power Supply) Product classification (S1:Semiconductors) CONTENTS 1. DESCRIPTION.................................................................................................................................... 1 1.1 Features ..................................................................................................................................... 1 1.2 Block Diagram............................................................................................................................ 2 1.3 Package Dimensions and Pin Assignment................................................................................ 4 1.4 Pin Descriptions ......................................................................................................................... 6 1.5 Mask Options ............................................................................................................................. 8 2. INPUT VOLTAGE AND INITIAL RESET............................................................................................ 9 2.1 Input Voltage .............................................................................................................................. 9 2.1.1 Main Battery <VIN>....................................................................................................... 9 2.1.2 Sub-Battery <VBAK> ..................................................................................................... 9 2.1.3 Constant Voltage for Internal Circuits <VD1> ............................................................... 9 2.1.4 Reference Voltage for Internal Circuits <VREF>......................................................... 10 2.1.5 Voltage for External Interface Pins <BATT_VCC>...................................................... 10 2.2 Initial Reset............................................................................................................................... 12 2.2.1 Reset Input Pin <XRST>............................................................................................ 12 2.2.2 Reset Output Pin <nRESET> .................................................................................... 12 2.3 Test Pin <XTEST0>.................................................................................................................. 12 3. REGULATOR AND OPERATION .................................................................................................... 13 3.1 CH-1 (VCC1) Output Voltage..................................................................................................... 14 3.1.1 Main Regulator (PWM Controller).............................................................................. 14 3.1.2 Sub-Regulator (Backup Regulator)............................................................................ 14 3.1.3 Light-Load Mode Function ......................................................................................... 15 3.1.4 Soft Start Function ..................................................................................................... 16 3.1.5 Output Voltage Setting Function ................................................................................ 16 3.1.6 Power OFF Function .................................................................................................. 19 3.1.7 Power Good Function ................................................................................................ 20 3.1.8 CH-1 (VCC1) Mask Options of Output Voltage ........................................................... 20 3.1.9 CH-1 (VCC1) Output Voltage Proof Function.............................................................. 20 3.2 CH-2 (VCC2) Output Voltage..................................................................................................... 21 3.2.1 Main Regulator (PWM Controller).............................................................................. 21 3.2.2 Sub-Regulator (Backup Regulator)............................................................................ 21 3.2.3 Light-Load Mode Function ......................................................................................... 22 3.2.4 Soft Start Function ..................................................................................................... 23 3.2.5 Short-Circuit Proof Function....................................................................................... 23 3.2.6 Power OFF Function .................................................................................................. 23 3.2.7 Power Good Function ................................................................................................ 24 3.2.8 CH-2 (VCC2) Mask Options Concerning Output Voltage............................................ 24 3.3 CH-3 (VCC3) Output Voltage..................................................................................................... 25 3.3.1 Main Regulator (PWM Controller).............................................................................. 25 3.3.2 Sub-Regulator (Backup Regulator)............................................................................ 25 3.3.3 Light-Load Mode Function ......................................................................................... 26 3.3.4 Soft Start Function ..................................................................................................... 27 3.3.5 Short-Circuit Proof Function....................................................................................... 27 3.3.6 Power OFF Function .................................................................................................. 27 3.3.7 Power Good Function ................................................................................................ 28 3.3.8 CH-3 (VCC3) Mask Options Concerning Output Voltage............................................ 28 Rev.1.4 EPSON i 3.4 3.5 CH-4 (VCC4) Output Voltage..................................................................................................... 29 3.4.1 Main Regulator (Series Regulator) ............................................................................ 29 3.4.2 Power OFF Function .................................................................................................. 29 Output Timing of Regulator on Initial Startup........................................................................... 30 4. OPERATION MODES....................................................................................................................... 31 4.1 Description of Each Operation Mode....................................................................................... 31 4.2 Sleep Mode .............................................................................................................................. 31 4.2.1 Transitioning to and Canceling the Sleep Mode ........................................................ 31 4.2.2 Transitioning to and Canceling the Sleep Mode When CH-1 Voltage Change is Made ....................................................................................................................... 32 4.2.3 Transitioning to and Canceling the Sleep Mode When CH-1 Voltage Change is not Made................................................................................................................. 33 4.2.4 Mask Options Associated with the Sleep Mode ........................................................ 34 4.3 Deep Sleep Mode .................................................................................................................... 36 4.3.1 Transitioning to and Canceling the Deep Sleep Mode .............................................. 36 4.3.2 Mask Options Associated with the Deep Sleep Mode............................................... 37 4.4 Ultra-Power-Saving Mode........................................................................................................ 38 5. I2C CONTROLLER ........................................................................................................................... 39 5.1 Description ............................................................................................................................... 39 5.1.1 Basic Specifications ................................................................................................... 39 5.1.2 Start and Stop Conditions .......................................................................................... 39 5.1.3 Data Transfer (command format)............................................................................... 40 5.1.4 Behavior During Malfunction Conditions.................................................................... 41 5.2 Control Address & Control Data List........................................................................................ 42 6. AUXILIARY FUNCTIONS AND OPERATIONS............................................................................... 46 6.1 Oscillator Circuit/Clock Selecting Function .............................................................................. 46 6.2 Output Voltage Determining Function...................................................................................... 47 6.3 Input Voltage Determining Function.........................................................................................48 6.4 General-Purpose I/O Ports ...................................................................................................... 49 6.4.1 Description ................................................................................................................. 49 6.4.2 Mask Options Associated with the General-Purpose I/O Ports................................. 50 7. BASIC EXTERNAL CONNECTION DIAGRAMS ............................................................................ 51 8. ELECTRICAL CHARACTERISTICS ............................................................................................... 53 9. PACKAGE ........................................................................................................................................ 66 10. PAD LAYOUT ................................................................................................................................... 68 11. TERMINAL EQUIVALENT CIRCUIT................................................................................................ 70 APPENDIX SELECTION OF PWM CONTROLLER'S EXTERNAL COMPONENTS ........................ 72 ii EPSON Rev.1.4 S1F81100 Technical Manual 1. DESCRIPTION The S1F81100 is a power IC for the system equipped with a 4-channel regulator. Batteries such as lithium ion batteries are used to generate each output voltage via external devices. The 4-channel regulator consisting of PWM controller with 3 channels and series regulator with 1 channel are independent of each other and can be controlled separately. On this series, an I2C controller (for the slave function), input and output voltage detecting functions, general-purpose I/O pins, etc. are provided. Moreover, this series exhibits power saving performance by effectively using the normal, Sleep, Deep Sleep and ultra-energy-saving modes provided as operation mode according to the situation. The S1F81100 is also equipped with an I/O pin dedicated for interface to Intel's PXA250/210 (XScaleTM) processor, and is most suitable for use as a power supply unit for mobile devices such as PDAs equipped with an XScaleTM and smart-phone. Product number Shipping forms S1F81100D0**000 Die form QFP12-48 Package S1F81100F0**000 QFN7-48 Package S1F81100F5**000 Note: The above * is replaced with a serial number depending on the option. Product List The following optional products (including those under development) are currently prepared for the S1F81100. For the mask options, refer to Section 1.5. Table 1.1 Product List Model S1F81100F0E1000 * S1F81100F0F0000 * Under development 1.1 Package QFP12-48 QFP12-48 [No.1] CH-2 3.3V 3.3V Mask Option [No.2] CH-3 3.3V 2.5V [others] standard standard Features The features of the S1F81100 include the following: Input voltage: Regulator: 3.3V to 5.5V (if at least either VCC2 or VCC3 is 3.3V) (Note 1) 2.8V to 5.5V (if both VCC2 and VCC3 are 2.5V or lower) Note 1: When VIN falls to around 3.3V, output falls below 3.3V. 4-channel VIN CH-1 (VCC1): PWM controller High-speed synchronized rectification type PWM controller (Connected to an external component to configure a switching regulator.) Features include a fast response circuit using a current/voltage returning system, more compact external components thanks to a fast clock, and a sub-regulator (mask options). Output voltage 1.5/1.4/1.3/1.2/1.1/1.0/0.9/0.8V Select one value from above via the I2C controller. Accuracy: within 5% Main Sleep mode OFF Output current Operating mode Max.: 500mA Sub [mask options] Max.: 20mA CH-2 (VCC2): PWM controller High-speed synchronized rectification type PWM controller (Connected to an external component to configure a switching regulator.) Features include a fast response circuit using a current/voltage returning system, a short-circuit-proof circuit, more compact external components thanks to a fast clock, and a sub-regulator. 3.3/2.5/1.8V: One is to be selected from the mask options (1.8V is under development). Output voltage Accuracy: within 5% Rev.1.4 EPSON 1 S1F81100 Technical Manual Output current Main Sub Deep Sleep mode Operating mode Max.: 10mA OFF Max.: 1A CH-3 (VCC3): PWM controller High-speed synchronized rectification type PWM controller (Connected to an external component to configure a switching regulator.) Features include a fast response circuit using a current/voltage returning system, a short-circuit-proof circuit, more compact external components thanks to a fast clock, and a sub-regulator. Output voltage 3.3/2.5/1.8V: One is to be selected from the mask options (1.8V is under development). Accuracy: within 5% Main Deep Sleep mode OFF Output current Operating mode Max.: 1A Sub Max.: 10mA CH-4 (VCC4): Series regulator Low power consumption type series regulator Output voltage 1.5/1.4/1.3/1.2/1.1/1.0/0.9/0.8V...Same voltage as in CH-1 setting Sleep mode OFF Output current Operating mode 20mA (@VCC3 = 3.3V), 5mA (@VCC3 = 2.5V) Shutdown current: Typ.: 0.7A(@VIN = 4.0V) Current consumption: Normal mode 2mA(Typ.) Sleep mode 100A(Typ.) External interface: Built-in interfaces in the I2C controller (SCL, SDA and AD_EN; for the slave function only). Output voltage detecting function: 1 channel (nVCC_FLT) The output of power good circuit will be LOW if one of CH1 to CH3 output is out of defined value. Input voltage detecting function: 1 channel (nBAT_FLT) The LOW output is applied if the detected input voltage fails to comply with the specs. Resetting function: 1 channel (XRST(I),nRESET(O)) Sleep function: 1 channel (PWR_EN,WUP) 1.2 Block Diagram The following is a block diagram of the S1F81100. [****] : Input Power Terminal [****] : Backup Power Terminal [****] : GND Terminal **** : VIN Level I/O Terminal **** : VCC1 Level I/O Terminal **** : VCC2 Level I/O Terminal **** : VCC3 Level I/O Terminal **** : VCC4 Level I/O Terminal **** : BATT_VCC Level I/O Terminal **** : Analog Terminal Fig.1.2.1 Notation of Pin Voltage Levels in Fig.1.2.2. 2 EPSON Rev.1.4 S1F81100 Technical Manual S1F81100 [VIN] [VIN1] [VSS] CLKIN CH-1 PWM cont. Series Reg. OSC Power-Good Soft start Err. Dtct. etc. SDA AD_EN P03 P02 CH-2 nBAT_FLT nVCC_FLT Reset Cont. VIN Dtct. VOUT Dtct. Power Manager P00 nRESET PWM cont. Series Reg. Power-Good Soft start Err. Dtct. etc. WUP SW1OL SSCAP1 FB2M SW2OH SW2OL SSCAP2 [VIN3] CH-3 PWM cont. Power-Good Soft start Err. Dtct. etc. Sleep Cont. VCC2 [VSS2] Series Reg. PWR_EN SW1OH [VIN2] P01 XRST FB1M [VSS1] I2C Controller SCL VCC1 VD1 Int. Power Reg. VREF Ref. Power Reg. CH-4 Test Cont. Backup Switch VCC3 FB3M SW3OH SW3OL SSCAP3 [VSS3] VCC4 FB4 XSDWN XTEST0 BATT_V CC [VBAK] Fig.1.2.2 S1F81100 Block Diagram Rev.1.4 EPSON 3 S1F81100 Technical Manual 1.3 Package Dimensions and Pin Assignment [QFP12-48] 90.4 70.1 36 90.4 25 9 0.4 24 70.1 37 INDEX 48 13 1 12 0.1 1.40.1 1.7Max. 0.5 0.18 +0.1 -0.05 0.1250.05 0 10 0.50.2 1 Unit: mm Fig.1.3.1 QFP12-48 Package Diagram Table 1.3.1 QFP12-48 Pin Assignment Pin # Pin name Pin # Pin name Pin # Pin name Pin # Pin name 1 13 FB4 25 VD1 37 XPOR(N.C.) FB3M 2 14 VCC4 26 VBAK 38 P02 SW3OL 3 27 BATT_VCC 39 P03 15 VIN VSS3 4 16 XRST 28 PWR_EN 40 VCC2 VCC1 5 17 XTEST0 29 WUP 41 VIN2 VIN1 6 18 XSDWN 30 nRESET 42 SW2OH SW1OH 7 19 AD_EN 31 nBAT_FLT 43 FB2M FB1M 8 20 TCLK(N.C.) 32 nVCC_FLT 44 SW2OL SW1OL 9 21 CLKIN 33 P00 45 VSS2 VSS1 10 22 VSS 34 P01 46 VCC3 SSCAP3 11 23 TIREF(N.C.) 35 SCL 47 VIN3 SSCAP2 12 24 VREF 36 SDA 48 SW3OH SSCAP1 4 EPSON Rev.1.4 S1F81100 Technical Manual [QFN7-48] 7 0.42 +0.18 -0.18 6.75 7 6.75 0.42 +0.18 -0.18 Ma x 0.01 +0.04 -0.01 0.65 +0.15 0.85 +0.15 12 24 0.4 +0.05 -0.1 5 .0 +0 0.2 0.23 +0.07 -0.05 25 2- 12 0. 0. 17 + - 0 0.0 .0 6 4 13 36 1 48 37 0.5 Fig.1.3.2 QFN7-48 Package Diagram Table 1.3.2 QFN7-48 Pin Assignment Pin # 1 2 3 4 5 6 7 8 9 10 11 12 Rev.1.4 Pin name FB3M SW3OL VSS3 VCC1 VIN1 SW1OH FB1M SW1OL VSS1 SSCAP3 SSCAP2 SSCAP1 Pin # Pin name Pin # Pin name Pin # Pin name 13 FB4 25 VD1 37 XPOR(N.C.) 14 VCC4 26 VBAK 38 P02 15 VIN 27 BATT_VCC 39 P03 16 XRST 28 PWR_EN 40 VCC2 17 XTEST0 29 WUP 41 VIN2 18 XSDWN 30 nRESET 42 SW2OH 19 AD_EN 31 nBAT_FLT 43 FB2M 20 TCLK(N.C.) 32 nVCC_FLT 44 SW2OL 21 CLKIN 33 P00 45 VSS2 22 VSS 34 P01 46 VCC3 23 TIREF(N.C.) 35 SCL 47 VIN3 24 VREF 36 SDA 48 SW3OH EPSON 5 S1F81100 Technical Manual 1.4 Pin Descriptions Table 1.4.1(a) Pin Descriptions [Power supply/controlling pins] Pin name I/O Level VIN VSS VBAK - VD1 VREF BATT_VCC nVCC_FLT O nBAT_FLT O nRESET O PWR_EN I WUP O CLKIN I XRST I XTEST0 I XSDWN I P00 to 01 I/O P02 to 03 I/O SCL I SDA I/O AD_EN I [CH-1 Related Pins] Pin name I/O VIN1 SW1OH O SW1OL O SSCAP1 FB1M I VCC1 I VSS1 6 BATT_VCC BATT_VCC BATT_VCC BATT_VCC BATT_VCC VCC2 VIN VIN VIN VCC2 VIN VCC2 VCC2 VIN Function Voltage (+) input pin Voltage (-) input pin Interface power supply input (Short-circuited to VCC2 outside IC) Internal constant voltage output pin Reference voltage output pin Interface power supply (Short-circuited to VCC2 outside IC) Output voltage detection result output pin Input voltage detection result output pin System reset signal output pin Sleep state setting input pin Sleep state flag output pin External clock input pin Resetting input pin Testing input pin Ultra-power-saving mode setting input pin General-purpose I/O pin General-purpose I/O pin I2C clock input pin I2C data I/O pin I2C Address enabling input pin Function Voltage (+) input pin P-ch power MOS transistor drive signal output pin N-ch power MOS transistor drive signal output pin CH-1 soft start setting pin Output current feedback input pin Output voltage feedback input pin [sub-regulator output pin] Voltage (-) input pin EPSON Rev.1.4 S1F81100 Technical Manual Table 1.4.1(b) Pin Description [CH-2 Related Pins] Pin name I/O VIN2 SW2OH O SW2OL O SSCAP2 FB2M I VCC2 I VSS2 [CH-3 Related Pins] Pin name I/O VIN3 SW3OH O SW3OL O SSCAP3 FB3M I VCC3 I VSS3 [CH-4 Related Pins] Pin name I/O VCC4 O FB4 I Function Voltage (+) input pin P-ch power MOS transistor drive signal output pin N-ch power MOS transistor drive signal output pin CH-2 soft start setting pin Output current feedback input pin Output voltage feedback input pin [sub-regulator output pin] Voltage (-) input pin Function Voltage (+) input pin P-ch power MOS transistor drive signal output pin N-ch power MOS transistor drive signal output pin CH-3 soft start setting pin Output current feedback input pin Output voltage feedback input pin [sub-regulator output pin] Voltage (-) input pin Function VCC4 voltage output pin Feedback input pin Notes: The following pins are dedicated to test use. Always indicate as N.C. when using. Operation without the indication of N.C. cannot be guaranteed. XPOR, TCLK, TIREF Rev.1.4 EPSON 7 S1F81100 Technical Manual 1.5 Mask Options This section describes the mask options. These can be combined freely according to the user's needs. Refer to the following chapter for further information on each mask options. [No.1] CH-2(VCC2) Output voltage 1. 3.3V 2. 2.5V 3. 1.8V (under development) [No.2] CH-3(VCC3) Output voltage 1. 3.3V 2. 2.5V 3. 1.8V (under development) [No.3] Sleep mode one-touch recovery function 1. Disable 2. Enable [No.4] Sleep mode Ch-2 main regulator operation 1. ON 2. OFF [No.5] Sleep mode Ch-3 main regulator operation 1. ON 2. OFF [No.6] Deep Sleep mode Ch-2 sub-regulator operation 1. Enable (CH-2 sub-regulator, ON in Deep Sleep mode) 2. Disable (CH-2 sub-regulator, OFF in Deep Sleep mode) *1 [No.7] CH-1(VCC1) Sub-regulator function 1. Disable 2. Enable *1 8 is for standard specification. In the Deep Sleep mode, CH-2 output stops and VCC2 potential lowers down to the GND level. For this reason, once the unit enters the Deep Sleep mode, it can be restored from this mode only by LOW level input via the XRST pin. When power is externally supplied to VCC2 (CH-2) in the Deep Sleep mode, input via PWR_EN is also accepted. EPSON Rev.1.4 S1F81100 Technical Manual 2. INPUT VOLTAGE AND INITIAL RESET This chapter describes the input voltage specifications and the initial reset specifications of the S1F81100. 2.1 Input Voltage The S1F81100 requires power supply for its operation and internally generates internal constant voltage VD1 and internal reference voltage VREF from its main battery. The external interface I/O voltage BATT_VCC and VBAK pins are required to be short-circuited to the VCC2 outside the S1F81100. This section describes the detailed specifications for each. VIN VD1 Regulator VIN1 VIN2 Other Peripheral Circuits VIN3 Main Battery VD1 CH-1 CH-2 CH-3 CH-4 (oscillation, I 2C digital circuit etc.) VSS1 VCC1 VSS2 VCC2 VSS3 VCC3 VSS VCC4 BATT_VCC VBAK Fig.2.1.1 Power Supply System Block Diagram 2.1.1 Main Battery <VIN> The input voltage range of the S1F81100's main battery is as follows: 3.3 to 5.5V If at least either VCC2 or VCC3 is 3.3 V. 2.8 to 5.5V If both VCC2 and VCC3 are 2.5V or lower. The S1F81100 is activated if a single power supply with the voltage of the above range is provided between VIN and VSS and generates 4-channel output voltage as well as constant voltage VD1 for the internal circuits. 2.1.2 Sub-Battery <VBAK> Short-circuit the VBAK pin of the S1F81100 to the VCC2 outside the S1F81100. 2.1.3 Constant Voltage for Internal Circuits <VD1> The S1F81100 generates constant voltage VD1 for the internal circuits from its main battery, eliminating the need for external input of such voltage. To stabilize the voltage, connect a 0.1F external capacitor to the VD1 pin. Notes: Driving an external load with internal constant voltage VD1 is not allowed. Rev.1.4 EPSON 9 S1F81100 Technical Manual 2.1.4 Reference Voltage for Internal Circuits <VREF> The S1F81100 generates reference voltage VREF for the internal circuits from its main battery. Voltage VREF is used as the reference voltage for operations of the internal circuits such as the PWM controller, and is generated in the S1F81100. This voltage does not have to be input externally. To stabilize the output voltage, connect a 0.1F external capacitor to the VREF pin. While the LOW level is input to the XRST pin, VREF voltage is at the same potential as VIN. Notes: Driving an external load with internal reference voltage VREF is not allowed. 2.1.5 Voltage for External Interface Pins <BATT_VCC> The S1F81100 is equipped with the following external interface pins (which are provided for interface to the external processor): (Output) Output voltage level detecting pin nVCC_FLT nBAT_FLT (Output) Input voltage level detecting pin PWR_EN (Input) Sleep state setting pin WUP (Output) Sleep state output pin nRESET (Output) Reset output pin Short-circuit the power BATT_VCC for driving the above interface pins to the VCC2 outside the S1F81100. Fig.2.1.5.2 shows the external connection diagram. 10 EPSON Rev.1.4 S1F81100 Technical Manual CH-2 Regulator VCC2 VBAK BATT_V CC nVCC_FLT nBAT_FLT PWR_EN S1F81100 WUP nRESET Fig.2.1.5.1 The Internal Configuration of BATT_VCC Pin CH-2 Regulator VCC2 VIN VBAK VIN2 VIN3 BATT_VCC Processor VIN1 nVCC_FLT VSS nBAT_FLT VSS1 PWR_EN VSS2 WUP S1F81100 VSS3 nRESET Fig.2.1.5.2 External Connection Diagram of BATT_VCC and VBAK Pins Rev.1.4 EPSON 11 S1F81100 Technical Manual 2.2 Initial Reset The S1F81100 requires initial reset to initialize its circuits. The following is the initial reset factor: (1) External initial reset via the XRST pin. Initial reset initializes the internal circuit of the IC. To initialize the circuits, be sure to perform one of these actions. During the initial reset period, the LOW level signal is output from the nRESET pin. Fig.2.2.1 shows the initial reset circuit diagram. XRST Counter Circuit nRESET Power Good Circuit Input Voltage Detection Circuit Fig.2.2.1 Initial Reset Circuit Diagram 2.2.1 Reset Input Pin <XRST> Initial reset can be performed by externally setting the reset (XRST) input pin to LOW level (VSS). After this, the internal circuits stay in the initial reset state until outputs of all the four channels are activated. Keep the XRST pin at LOW level for a period of 50s or longer so that initial resetting can be performed. Notes: While the LOW level is input to the XRST pin, VREF voltage must be set to the same voltage as VIN. 2.2.2 Reset Output Pin <nRESET> The S1F81100 can output a reset signal to external devices via the nRESET pin. The nRESET signal starts outputting the LOW level signal as soon as the S1F81100 unit has entered the initial reset state, and keeps the LOW level (initial reset state) until all output voltages of the four channels are activated. When all the output voltages are activated and the input level of the XRST pin attains the HIGH level (VIN level), the output level of the reset output signal nRESET becomes HIGH (BATT_VCC, VCC2 level). After the input voltage is turned ON, the nRESET signal maintains the LOW level for around 60 ms after all 4 channels are activated. 2.3 Test Pin <XTEST0> This pin is used for testing ICs before shipping. In normal operation, XTEST0 should be connected to VIN. 12 EPSON Rev.1.4 S1F81100 Technical Manual 3. REGULATOR AND OPERATION The S1F81100 has a regulator with 4 channels (CH-1, CH-2, CH-3 and CH-4) optimally configured for Intel's PXA250/210 processors. CH-1, CH-2 and CH-3 are mounted with PWM controller as a main regulator. PWM controllers can output stable voltage by configuring a switching regulator connecting external power MOS transistor and coil, etc. Moreover, each is equipped with a series regulator as a sub (backup) regulator. The current consumption of the system is controllable based on the load condition by simply setting the sub-regulator to operate when the load is light. CH-4 is a series regulator and can output voltage independently. This chapter provides detailed descriptions of each regulator. CORE power (VCC) for PXA250/210 CH-1 (VCC1) Select 1 value from 1.5/1.4/1.3/1.2/1.1/1.0/0.9/0.8V: I2C controller Main regulator: PWM controller Sleep mode: OFF, Operating load: 500mA (Max.), Maximum conversion efficiency: about 80%. Sub-regulator: series regulator [Select available/unavailable in mask options] Peripheral power (VCCQ) for PXA250/210 CH-2 (VCC2) 3.3/2.5/1.8V: Select 1 value from mask options. Main regulator: PWM controller Deep Sleep mode: OFF, Operating load: 1A (Max.), Maximum conversion efficiency: about 90%. Sub-regulator: series regulator Memory power (VCCN) for PXA250/210 CH-3 (VCC3) 3.3/2.5/1.8V: Select 1 value from mask options. Main regulator: PWM controller Deep Sleep mode: OFF, Operating load: 1A (Max.), Maximum conversion efficiency: about 90%. Sub-regulator: series regulator PLL power (PLL_VCC) for PXA250/210 CH-4 (VCC4) 1.5/1.4/1.3/1.2/1.1/1.0/0.9/0.8V (Output value same with the VCC1 set value) Series regulator Sleep mode: OFF, Operating load: 20mA (Max.) (@VCC3 = 3.3V) 5mA (Max.) (@VCC3 = 2.5V) Rev.1.4 EPSON 13 S1F81100 Technical Manual 3.1 CH-1 (VCC1) Output Voltage This section describes CH-1, a variable output type PWM controller. Fig.3.1.1 shows CH-1's internal and external configurations. S1F81100 VCC1 Power Good Mask Option VIN1 Sub-regulator (backup) TP1 CMP. SW1OH Error - AMP + PWM Waveform Drive Circuit PG1 CL1 FB1M SW1OL VSS1 TN1 SD1 CC1 POFF1 LMD1 Power Manager VS1n Output Voltage Control Circuit SSCAP1 Soft Start CS1 Fig.3.1.1 CH-1 Regulator Configuration 3.1.1 Main Regulator (PWM Controller) The main regulator of CH-1 is a variable output type PWM controller. External components can be connected to it to form a switching regulator to allow constant voltage to be generated and output from input voltage VIN (VIN1) and internal constant voltage VD1. [Configuration of CH-1 Switching Regulator] Synchronized rectification type switching regulator. Clock Approximately 1 MHz (when the internal oscillator circuit is used) Required external components: P-ch power MOS transistor TP1 N-ch power MOS transistor TN1 Schottky diode SD1 Coil: 10H CL1 Stabilizing capacitor (100F) CC1 Capacitor for soft start CS1 The output value is variable; it can be externally set via the output voltage value selected with one of the VS17 to 10 registers of the I2C controller. See section 5.2 for details of the VS17 to 10 register. 3.1.2 Sub-Regulator (Backup Regulator) CH-1 can mount series regulator as a sub-regulator from mask options. Output value is the same with the main regulator set value. 14 EPSON Rev.1.4 S1F81100 Technical Manual Sub-regulator of CH-1 is generated from VCC3 voltage. Therefore, sub-regulator of CH-1 is not activated when CH-3 is in power OFF state. 3.1.3 Light-Load Mode Function This function is enabled only when use of sub-regulator of CH-1 is selected from mask options. In normal operation (normal mode), the main regulator and the sub-regulator are both operating. During operation of the application, some conditions do not require a large load current. In this case, the mode can be switched to [Light-load mode]. In light-load mode, the main regulator is OFF and only the sub-regulator is ON. Therefore, the current consumed by the main regulator can be restrained, effectively saving power for the application. Switching between the normal and light-load mode is optional in the application. The switching methods of the 2 modes are as follows: [Switching from normal to light-load mode] To switch from normal to light-load mode, set the value of the LMD1 register to "1" via the I2C controller. Consequently, the main regulator of CH-1 is turned OFF and only the sub-regulator operates. Only the voltage of the sub-regulator is outputted. [Switching from light-load to normal mode] To switch from light-load to normal mode, set the value of the LMD1 register to "0" via the I2C controller. Fig.3.1.3.1 shows the normal and light-load states and the switching method. Notes: The sub-regulator is not activate when CH-3 is in power OFF state since the sub-regulator of CH-1 is generated from VCC3. [CH-1] Normal Mode Main Regulator ON Light-load Mode From Normal to Light-load Set LMD1 register to 1 via I2C. Sub-Regulator ON From Light-load to Normal Set LMD1 register to 0 via I2C. Main Regulator OFF Sub-Regulator ON Fig.3.1.3.1 Switching between normal/light-load mode in CH-1 Rev.1.4 EPSON 15 S1F81100 Technical Manual 3.1.4 Soft Start Function With a capacitor connected to the SSCAP1 pin, CH-1 provides a soft start function that adjusts the rise time of the power when it is turned on. After a lapse of soft start time, voltage output of CH-1 starts Fig.3.1.4.1 shows the relation between the soft start time and the soft start capacitor capacity (CS1). When voltage output of CH-1 is used as CORE power supply for the PXA250/210 (XScaleTM) processor, the CORE voltage must rise to 10 ms, Max. after the PWR_EN input attains the HIGH level. For this reason, 0.01F is recommended as the Max. CS1. Soft Start Time v. s. CSn (Typ.) CSn [F] Fig.3.1.4.1 The Relation between the Soft Start Time and the Soft Start Capacitor Capacity (CS1). 3.1.5 Output Voltage Setting Function Output voltage of CH-1 can be selected from eight values via the I2C controller externally. The optimal output voltage can be set according to the operations of the driving device while the application is operating. See Table.3.1.5.1 for voltages that can be set. After the input voltage rises and after the initial reset signal is input from the XRST pin, 1.5V is applied. There are 2 methods of changing the voltage value: (1) Consecutive transition: Changes the voltage value while in normal mode via I2C. (2) Step transition: Changes the voltage value after transition to Sleep mode and then canceling it. The following describes the respective operation. Consecutive transition S1F81100 can change voltage value by consecutive transition by following the procedures below. 1 Rewrite the VS17 to 10 register value via the I2C controller and set a new voltage value. 2 Write "0" in the XC1TRG register via the I2C controller. 3 The VS17 to 10 register value is loaded to CH-1 regulator at this point and CH-1 output voltage changes. When conducting consecutive transition, CH-1 output voltage value is controllable only via I2C controller. See section 5.2 for details of the VS17 to 10 and XC1TRG registers. Step transition S1F81100 can change voltage value by step transition by following the procedures below: 1 Rewrite the VS17 to 10 register value via the I2C controller and set a new voltage value. 2 The PWR_EN pin is externally controlled to the LOW level to set the S1F81100 unit to Sleep state. 3 After the unit enters the Sleep state, the S1F81100 unit sets the WUP pin output to the HIGH level. 4 After the WUP pin is externally detected, the PWR_EN pin is set back to the HIGH level, and the S1F81100 is instructed to cancel the Sleep state. 5 The S1F81100 starts recovering from the Sleep state. 6 The WUP signal attains the LOW level. 7 When returning to the normal state, VCC1 attains the new voltage value. If no new voltage value is set in step 1 above (that is, if the specified voltage is the same as the previous value), 16 EPSON Rev.1.4 S1F81100 Technical Manual the WUP signal level does not attain the HIGH level in step 3 above. See section 5.2 for details of the VS17 to 10 register. Notes: When transitioning to Sleep state without changing the voltage value (without rewriting the VS17 to 10 register value), setting the PWR_EN pin to LOW does not change the output level of the WUP pin. The example of controlling the CH-1 output voltage by step transition is shown below. Connect with a processor mounted with master function of the I2C controller and control the output voltage by software control. Fig.3.1.5.1 shows the example of connection with the Intel's mobile processor PXA250/210. Only the signals related to changing of CH-1 output voltage is shown in the diagram. Fig.3.1.5.2 shows a timing chart illustrating the CH-1 output voltage control. Table.3.1.5.2 describes the procedures of software control from the processor side. By setting and conducting software control on the controller side following the procedure in the table, VCC1 voltage output value of S1F81100 is changed. Table 3.1.5.1 VS17 to 10 Set Value and VCC1 Output Voltage Corresponding Table VS17 to 10 VCC1 VS17 to 10 VCC1 11111*** B 11110*** B 11101*** B 11100*** B 11011*** B 11010*** B 11001*** B 11000*** B 10111*** B 10110*** B 10101*** B 10100*** B 10011*** B 10010*** B 10001*** B 10000*** B Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited 1.5V 1.5V 1.4V 1.3V 01111*** B 01110*** B 01101*** B 01100*** B 01011*** B 01010*** B 01001*** B 01000*** B 00111*** B 00110*** B 00101*** B 00100*** B 00011*** B 00010*** B 00001*** B 00000*** B 1.2V 1.2V 1.1V 1.0V 0.9V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V PXA250/210 S1F81100 VCC VCC1 SDA SCL PWR_EN GP[n] SDA SCL PWR_EN WUP (Note: GP[n] indicates general-purpose input port.) Fig.3.1.5.1 Connection example and PXA250/210 (only parts related to VCC1 control) Rev.1.4 EPSON 17 S1F81100 Technical Manual VS17 to 10 [Digital] A B PWR_EN [Digital] WUP [Digital] less than 1s less than 1s nVCC_FLT [Digital] less than 1s VCC1 less than 1s A B The values in the chart are all typical values for reference. Fig.3.1.5.2 CH-1 Output Voltage Control Timing on Step Transition 18 EPSON Rev.1.4 S1F81100 Technical Manual Table 3.1.5.2 Software Control Procedure for Changing VCC1 Output Voltage Status Normal Operation State Normal Operation Processor ex. PXA250/210 Power IC S1F81100 Operation (software/hardware control) Operation PWR_EN Pin Output: HIGH Level Voltage Output VCC1/VCC4 Output turned ON. WUP Pin Output: LOW level [Setting] Enable input interruption of GP[n]. c I2C Communication d Start transition to Sleep (PWR_EN Pin Control) e CORE Voltage OFF [Software Control] I2C Rewrites the VS17 to VS10 Command register of the power supply IC via the I2C controller and sets the new voltage value. Transition to Starts transition to Sleep State. PWR_EN Sleep Signal [Software Control] L Sets the output of PWR_EN pin to LOW Level to transit to Sleep state. Sleep Voltage Output VCC1/VCC4 Output OFF. X Sets the output of WUP pin to HIGH level at the same time. WUP Signal H f Sleep State Cancellation Sleep Start g CORE Voltage Output ON Receives interruption signal at Cancellation GP[n] pin and starts cancellation of Sleep state. H [Software (Hardware) Control] Sets the output of PWR_EN pin to HIGH level to cancel Sleep. Normal Operation PWR_EN Signal Voltage Output WUP Signal Normal Operation State Normal Operation PWR_EN Pin Output: HIGH Level Voltage Output VCC1/VCC4 Output ON. Outputs the newly set voltage value from this point. Sets output of the WUP pin to LOW L level at the same time. VCC1/VCC4 Output ON. WUP Pin Output: LOW Level 3.1.6 Power OFF Function The voltage output of CH-1 can be turned off (powered off) via the I2C controller. Writing "1" in the POFF1 register assigned to the I2C controller's register causes the CH-1 output to be turned off (powered off) and pulled down internally. The POFF1 register value attains "0" again through one of the following steps, and then voltage output is turned ON (powered on). (1) Write "0" in the POFF1 register via the I2C controller. (2) Perform initial reset. (3) Turn the input level of the PWR_EN pin to LOW once to cause the Sleep state, then assign the HIGH level again to the PWR_EN pin to allow recovery from the Sleep state. See section 5.2 for details of the POFF1 register. Rev.1.4 EPSON 19 S1F81100 Technical Manual 3.1.7 Power Good Function CH-1 has a Power Good function. The Power Good function refers to a function that monitors the output voltage value inside the S1F81100 unit and determines if it is normal or not. If a state approximately 10% or more below the typical output voltage exceeds approximately 10ms, it is determined to be "abnormal output." The result of the Power Good judgement can be read via the PG1 plug (read-only) of the I2C controller. Moreover, it can be monitored by output level of nVCC_FLT pin. The Power Good function can be deactivated by writing "0" in the VFLT register on the I2C controller. See section 5.2 for details of the PG1 flag and VFLT registers. See section 6.2 for details of the nVCC_FLT pin. 3.1.8 CH-1 (VCC1) Mask Options of Output Voltage The following items are provided as mask options related to CH-1 output voltage. [No.7] CH-1 Sub-regulator function 1. Disable 2. Enable The mask options can be used to enable/disable the CH-1 sub-regulator function. During operation, if a state which does not require a large load current for CH-1 exists, select "Enable" and if not, select "Disable" 3.1.9 CH-1 (VCC1) Output Voltage Proof Function The CH-1 output is provided with a built-in output proof function. When output voltage is continuously reduced by 10% of the set output voltage approx. 110ms or more, the CH-1 switching regulator circuit operation stops. The output voltage reduction detection circuit serves as the CH-1 power good detection circuit as well. Output proof detection time: 110 20 [ms] Restore from the short-circuit proof mode is possible by input via the RESET pin (XRST). 20 EPSON Rev.1.4 S1F81100 Technical Manual 3.2 CH-2 (VCC2) Output Voltage This section describes CH-2, a PWM controller. Fig.3.2.1 shows CH-2's internal and external configurations. S1F81100 VCC2 Power Good Subregulator(backup) VIN2 TP2 CMP. SW2OH Error - AMP + PWM Waveform Drive Circuit PG2 CL2 FB2M SW2OL VSS2 TN2 SD2 CC2 POFF2 LMD2 Power Manager SSCAP2 Soft Start CS2 Fig.3.2.1 CH-2 Regulator Configuration 3.2.1 Main Regulator (PWM Controller) The main regulator of CH-2 is a PWM controller. External components can be connected to it to form a switching regulator to allow a constant voltage to be generated and output from input voltage VIN (VIN2) and internal constant voltage VD1. [Configuration of CH-2 Switching Regulator] Synchronized rectification type switching regulator. Clock Approximately 1 MHz (when the internal oscillator circuit is used) Required external components: P-ch power MOS transistor TP2 N-ch power MOS transistor TN2 Schottky diode SD2 Coil: 10H CL2 Stabilizing capacitor (100F) CC2 Capacitor for soft start CS2 The output value is fixed to that set from the mask options. 3.2.2 Sub-Regulator (Backup Regulator) CH-2 has a series regulator which serves as its sub-regulator. For output value, a value approximately 0.1V lower than the value set of the main regulator is outputted. Rev.1.4 EPSON 21 S1F81100 Technical Manual 3.2.3 Light-Load Mode Function In normal operation (normal mode), the main regulator and the sub-regulator are both operating. During operation of the application, some conditions do not require a large load current. In this case, the mode can be switched to [Light-load mode]. In light-load mode, the main regulator is OFF and only the sub-regulator is on. Therefore, the current consumed by the main regulator can be restrained, effectively saving power for the application. Switching between the normal and light-load mode is optional in the application. The switching methods of the 2 modes are as follows: [Switching from normal to light-load mode] To switch from the normal to the light-load mode, set the value of the LMD2 register to "1" via the I2C controller. Consequently, the main regulator of the CH-2 is turned OFF and only the sub-regulator operates. Only the voltage of the sub-regulator is outputted. [Switching from light-load to normal mode] There are 2 methods to switch from light-load to normal mode. (1) Set LMD2 register to "0" via I2C controller. (2) Use the automatic switching function by overload detection of the sub-regulator. The above automatic switching function is a function which automatically turns on the main regulator and switches to the normal mode when overload was detected in the sub-regulator caused by the increase of the load current (exceeding approximately 30mA) during the light -load mode. Fig.3.2.3.1 shows the normal and light-load modes and the switching method. Notes: For the output voltage value of the sub-regulator, a voltage about 0.1 V lower than the value selected from the mask options is output. [CH-2] Normal Mode Main Regulator ON Light-load Mode From Normal to Light-load Set LMD2 register to 1 via I2C. OFF Sub-Regulator Sub-Regulator ON Main Regulator From Light-load to Normal (1) Set LMD2 register to 0 via I2C. (2) Use the auto-switching function by over load detection. ON Fig.3.2.3.1 Switching between Normal/Light-load Mode in CH-2 22 EPSON Rev.1.4 S1F81100 Technical Manual 3.2.4 Soft Start Function With a capacitor connected to the SSCAP2 pin, CH-2 provides a soft start function that adjusts the rise time of the power when it is turned on. This function effectively works to prevent a system malfunction that may occur due to rush current when the power is activated. Fig.3.2.4.1 shows the relation between the soft start time and the soft start capacitor capacity (CS2). Soft Start Time v. s. CSn (Typ.) CSn [F] Fig.3.2.4.1 The Relation between the Soft Start Time and the Soft Start Capacitor Capacity (CS2). 3.2.5 Short-Circuit Proof Function The S1F81100 is provided with a built-in output proof function. When output voltage is continuously reduced below the detected value approx. 110ms or more, the CH-2 switching regulator circuit operation stops. Restore from the short-circuit proof mode is possible by input via the reset pin (XRST). For further information about it, see 3.2.6. Output reduction detection CH-2 output set value Output reduction detected value 3.3V 2.3V 0.2V 2.5V 1.9V 0.2V Output proof detection time 110 20 [ms] Notes: Take short-circuit proof countermeasures other than above to increase the security of the application. 3.2.6 Power OFF Function The voltage output of CH-2 can be turned off (powered off) via the I2C controller. Writing "1" in the POFF2 register assigned to the I2C controller's register causes the CH-2 output to be turned off (powered off) and pulled down internally. Moreover, as mentioned in section 3.2.5, when short-circuit proof function was activated and CH-2 voltage output was turned off, this register is automatically rewritten to "1" in the IC. The POFF2 register value attains "0" again through one of the following steps, and then voltage output is turned ON. (1) Perform initial reset. See section 5.2 for details of the POFF2 register. Notes: When CH-2 voltage output is turned OFF, I2C controller cannot be used. Rev.1.4 EPSON 23 S1F81100 Technical Manual 3.2.7 Power Good Function CH-2 has a Power Good function. The Power Good function refers to a function that monitors the output voltage value inside the S1F81100 unit and determines if it is normal or not. If a state approximately 10% or more below the typical output voltage exceeds approximately 10ms, it is determined to be "abnormal output." The result of the Power Good judgement can be read via the PG2 flag (read-only) of the I2C controller. Moreover, it can be monitored by output level of nVCC_FLT pin. The Power Good function can be deactivated by writing "0" in the VFLT register on the I2C controller. See section 5.2 for details of the PG2 flag and VFLT registers. See section 6.2 for details of the nVCC_FLT pin. 3.2.8 CH-2 (VCC2) Mask Options Concerning Output Voltage The following items are provided as mask options related to CH-2 output voltage. [No.1] CH-2(VCC2) Output voltage 1. 3.3V 2. 2.5V 3. 1.8V (under development) One CH-2 output voltage value is selectable from 3.3V, 2.5V and 1.8V from mask options. [No.4] Sleep mode CH-2 main regulator operation 1. ON 2. OFF The ON/OFF operation of CH-2 main regulator in Sleep mode is selectable from mask options. Selecting "Operation ON" if a large load current is required for CH-2 during Sleep mode and "Operation OFF" if a large load current is not required and restraining power consumption during Sleep mode as much as possible increases operating efficiency. When the LMD2 register is previously set at "1," the main regulator in Sleep mode will be in "Operation OFF" state regardless of this mask option. See section 5.2 for details of the LMD2 register. [No.6] Deep Sleep mode CH-2 sub-regulator operation 1. Enable (CH-2 sub-regulator, ON in Deep Sleep mode) 2. Disable (CH-2 sub-regulator, OFF in Deep Sleep mode) The ON/OFF operation of CH-2 sub-regulator in the Deep Sleep mode is selectable from mask options. Selecting "OFF" stops CH-2 output and reduces the VCC2 potential down to the GND level. For this reason, once the unit enters the Deep Sleep mode, it can be restored from this mode only by LOW level input via the XRST pin. When power is externally supplied to VCC2 (CH-2) in the Deep Sleep mode, input via PWR_EN is also accepted. 24 EPSON Rev.1.4 S1F81100 Technical Manual 3.3 CH-3 (VCC3) Output Voltage This section describes CH-3, a PWM controller. Fig.3.3.1 shows CH-3's internal and external configurations. S1F81100 VCC3 Power Good Sub-regulator (backup) VIN3 TP3 CMP. SW3OH Error - AMP + PWM Waveform Drive Circuit PG3 CL3 FB3M SW3OL VSS3 TN3 SD3 CC3 POFF3 LMD3 Power Manager SSCAP3 Soft Start CS3 Fig.3.3.1 CH-3 Regulator Configuration 3.3.1 Main Regulator (PWM Controller) The main regulator of CH-3 is a PWM controller. External components can be connected to it to form a switching regulator to allow a constant voltage to be generated and output from input voltage VIN (VIN3) and internal constant voltage VD1. [Configuration of CH-3 Switching Regulator] Synchronized rectification type switching regulator. Clock Approximately 1 MHz (when the internal oscillator circuit is used) Required external components: P-ch power MOS transistor TP3 N-ch power MOS transistor TN3 Schottky diode SD3 Coil: 10H CL3 Stabilizing capacitor (100F) CC3 Capacitor for soft start CS3 The output value is fixed to that set from the mask options. 3.3.2 Sub-Regulator (Backup Regulator) CH-3 has a series regulator which serves as its sub-regulator. For output value, a value approximately 0.1V lower than the value set of the main regulator is outputted. Rev.1.4 EPSON 25 S1F81100 Technical Manual 3.3.3 Light-Load Mode Function In normal operation (normal mode), the main regulator and the sub-regulator are both operating. During operation of the application, some conditions do not require a large load current. In this case, the mode can be switched to [Light-load mode]. In light-load mode, the main regulator is OFF and only the sub-regulator is on. Therefore, the current consumed by the main regulator can be restrained, effectively saving power for the application. Switching between the normal and light-load mode is optional in the application. The switching methods of the 2 modes are as follows: [Switching from normal to light-load mode] To switch from the ordinary to the light-load mode, set the value of the LMD3 register to "1" via the I2C controller. Consequently, the main regulator of the CH-3 is turned OFF and only the sub-regulator operates. Only the voltage of the sub-regulator is outputted. [Switching from light-load to normal mode] There are 2 methods to switch from light-load to normal mode. (1) Set LMD3 register to "0" via I2C controller. (2) Use the automatic switching function by overload detection of the sub-regulator. The above automatic switching function is a function which automatically turns on the main regulator and switches to the normal mode when overload was detected in the sub-regulator caused by the increase of the load current (exceeding approximately 30mA) during the light-load mode. Fig.3.3.3.1 shows the normal and light-load modes and the switching method. Notes: For the output voltage value of the sub-regulator, a voltage about 0.1V lower than the value selected from the mask options is output. [CH-3] Normal Mode Main Regulator ON Light-load Mode From Normal to Light-load Set LMD3 register to 1 via I2C. Sub-Regulator ON Main Regulator OFF Sub-Regulator From Light-load to Normal (1) Set LMD3 register to 0 via I2C. (2) Use the auto-switching function by over load detection. ON Fig.3.3.3.1 Switching between normal/light-load mode in CH-3 26 EPSON Rev.1.4 S1F81100 Technical Manual 3.3.4 Soft Start Function With a capacitor connected to the SSCAP3 pin, CH-3 provides a soft start function that adjusts the rise time of the power when it is turned on. This function effectively works to prevent a system malfunction that may occur due to rush current when the power is activated. Fig.3.3.4.1 shows the relation between the soft start time and the soft start capacitor capacity (CS3). Soft Start Time v. s. CSn (Typ.) CSn [F] Fig.3.3.4.1 The Relation between the Soft Start Time and the Soft Start Capacitor Capacity (CS3). 3.3.5 Short-Circuit Proof Function The S1F81100 is provided with a built-in output proof function. When output voltage is continuously reduced below the detected value approx. 110ms or more, the CH-2 switching regulator circuit operation stops. Restore from the short-circuit proof mode is possible by input via the reset pin (XRST). For further information about it, see 3.2.6. Output reduction detection CH-2 output set value Output reduction detected value 3.3V 2.3V 0.2V 2.5V 1.9V 0.2V Output proof detection time 110 20 [ms] Notes: Take short-circuit proof countermeasures other than above to increase the security of the application. 3.3.6 Power OFF Function The voltage output of CH-3 can be turned off (powered off) via the I2C controller. Writing "1" in the POFF3 register assigned to the I2C controller's register causes the CH-3 output to be turned off (powered off) and pulled down internally. Moreover, as mentioned in section 3.3.4, when short-circuit proof function was activated and CH-3 voltage output was turned off, this register is automatically written over to "1" in the IC. The POFF3 register value attains "0" again through one of the following steps, and then voltage output is turned on. (1) Perform initial reset. (2) Write "0" in the POFF3 register via the I2C controller. See section 5.2 for details of the POFF3 register. Rev.1.4 EPSON 27 S1F81100 Technical Manual 3.3.7 Power Good Function CH-3 has a Power Good function. The Power Good function refers to a function that monitors the output voltage value inside the S1F81100 unit and determines if it is normal or not. If a state approximately 10% or more below the typical output voltage exceeds approximately 10ms, it is determined to be "abnormal output." The result of the Power Good judgement can be read via the PG3 flag (read-only) of the I2C controller. Moreover, it can be monitored by output level of nVCC_FLT pin. The Power Good function can be deactivated by writing "0" in the VFLT register on the I2C controller. See section 5.2 for details of the PG3 flag and VFLT registers. See section 6.2 for details of the nVCC_FLT pin. 3.3.8 CH-3 (VCC3) Mask Options Concerning Output Voltage The following items are provided as mask options related to CH-3 output voltage. [No.2] CH-3(VCC3) Output voltage 1. 3.3V 2. 2.5V 3. 1.8V (under development) One CH-3 output voltage value is selectable from 3.3V, 2.5V and 1.8V from mask options. [No.5] Sleep mode CH-3 main regulator operation 1. ON 2. OFF The ON/OFF operation of CH-3 main regulator in Sleep mode is selectable from mask options. Selecting "Operation ON" if a large load current is required for CH-3 during Sleep mode and "Operation OFF" if a large load current is not required and restraining power consumption during Sleep mode as much as possible increases operating efficiency. When setting LMD3 register to "1" previously, the main regulator in Sleep mode will be in "Operation OFF" state regardless of this mask options. See section 5.2 for details of the LMD3 register. 28 EPSON Rev.1.4 S1F81100 Technical Manual 3.4 CH-4 (VCC4) Output Voltage This section describes CH-4, a series regulator. Fig.3.4.1 shows CH-4's internal and external configurations. S1F81100 FB4 VCC4 Power Manager POFF4 Fig.3.4.1 CH-4 Regulator Configuration 3.4.1 Main Regulator (Series Regulator) CH-4 is a push/pull type series regulator that generates constant voltage via CH-3's output voltage VCC3. Short-circuit the VCC4 and FB4 pins outside the IC and use after mounting the following required components. The following lists the required components. Required external components: Capacitor 22F CH-4 output voltage value is the same with the voltage value set in CH-1. CH-4 output is turned off in the following conditions: (1) When CH-3 is turned off (2) When set to Sleep mode (depends on the mask options). (3) When set to Deep Sleep mode (4) When "1" was written in POFF4 register via the I2C controller (see section 3.4.2) 3.4.2 Power OFF Function The voltage output of CH-4 can be turned OFF (powered OFF) via the I2C controller. Writing "1" in the POFF4 register assigned to the I2C controller's register causes the CH-4 output to be turned off (powered off) and pulled down internally. The POFF4 register value attains "0" again through one of the following steps, and then voltage output is turned on. (1) Perform initial reset. (2) Turn the input level of the PWR_EN pin to LOW once to cause the Sleep state, then assign the HIGH level again to the PWR_EN pin to allow recovery from the Sleep state. (3) Write "0" in the POFF4 register via the I2C controller. See the section 5.2 for details of the POFF4 register. Rev.1.4 EPSON 29 S1F81100 Technical Manual 3.5 Output Timing of Regulator on Initial Startup Describes about the regulator output after the initial startup (input voltage power-on). CH-2 and CH-3 are the first ones to rise after input voltage (VIN) power-on. After the Power Good function of each CH has determined that their output values are within the "specified range" for CH-2 and CH-3, CH-1 and CH-4 voltages start to rise. Subsequently, if the Power Good function determines that the output value is within the "specified range" for CH-1 (CH-4 does not have a Power Good function), the output voltage determining function considers the voltage to be "normal output voltage." Then, set the output level of nVCC_FLT pin to HIGH. The initial reset state in the IC cancels in approximately 60ms. At the same time, set the output level of nRESET pin to HIGH and instruct reset cancellation to the external processor, etc. See section 6.2 for output voltage determining function. See section 2.2 for initial reset. Fig.3.5.1 shows a timing chart illustrating the initial startup. VIN VCC2/VCC3 70ms VCC1/VCC4 5ms nVCC_FLT [Digital] less than 1s nRESET [Digital] 60ms The values in the diagram are all typical values for approximation. Fig.3.5.1 Initial Startup Timing 30 EPSON Rev.1.4 S1F81100 Technical Manual 4. OPERATION MODES The SIF81100 provides the following operation modes (operation statuses). (1) Normal mode (2) Sleep mode (3) Deep Sleep mode (4) Ultra-Power-Saving mode The Normal mode refers to a state in which the IC operates normally. Each of the other three modes can be set using the control external to the IC or the control via the I2C controller. Because each of these three modes ensures power saving as compared to the Normal mode, it is possible to develop low-power consumption type products by efficiently set a mode when the application is operating. This chapter describes the Sleep, Deep Sleep and Ultra-Power-Saving modes in detail. 4.1 Description of Each Operation Mode The S1F81100 enters the Sleep or Deep Sleep mode when the PWR_EN pin is set to LOW during operation. The switching between Sleep and Deep Sleep modes is accomplished by the EDS register in the I2C controller. The S1F81100 enters the Ultra-Power-Saving mode when the input level of the XSDWN pin is set to LOW. In these modes, a part or all of the voltage outputs and IC's internal circuits can be turned OFF. Thus, using the mode appropriate for each individual situation allows the S1F81100 to deliver power saving performance. Table 4.1.1 shows the ON/OFF states of the internal circuits in each mode. Table 4.1.1 Regulator Operations in Each Mode CH-1 Main CH-2 Main Sub CH-3 Main Sub CH-4 Main Others (analog/logic) PWM controller PWM controller Series regulator PWM controller Series regulator Series regulator Normal mode ON ON OFF Deep Sleep mode OFF Ultra-PowerSaving mode OFF ON or OFF OFF OFF OFF or ON OFF Sleep mode Mask Option -2 ON ON Mask Option -4 ON ON or OFF OFF OFF Mask Option -3 ON ON OFF OFF ON OFF OFF OFF ON ON ON OFF For Mask Option -2, see Section 4.2.4. (Option 4) For Mask Option -3, see Section 4.2.4. (Option 5) For Mask Option -4, see Section 4.3.4. (Option 6) 4.2 Sleep Mode The S1F81100 enters the Sleep mode when the PWR_EN pin is set to LOW during operation. In the Sleep mode, CH-1 is turned OFF. In this mode the power consumed by the S1F81100 is lower compared to the Normal mode. 4.2.1 Transitioning to and Canceling the Sleep Mode This section describes how to transition to and cancel the Sleep mode. The timing chart for transitioning to and canceling the Sleep mode varies depending on whether or not CH-1 output voltage change is made. See sections 4.2.2 and 4.2.3. Transitioning to Sleep Mode To transition to the Sleep mode, set the EDS register to 0 (default) and input level of the PWR_EN pin to LOW using the I2C controller in the Normal mode. When the S1F81100 enters the Sleep mode, CH-1: Voltage output is turned OFF. CH-2: Depending on the mask option setting, the main regulator is turned OFF. Rev.1.4 EPSON 31 S1F81100 Technical Manual CH-3: Depending on the mask option setting, the main regulator is turned OFF. CH-4: Voltage output is turned OFF. In the Sleep mode, current consumption is reduced due to deactivation of CH-1. Therefore, setting the unit to enter the Sleep mode via application software when VCC1 voltage is no longer required contributes to higher efficiency of the unit as the current consumption of the entire system is reduced. Canceling Sleep Mode To cancel the Sleep mode, set the input level of the PWR_EN pin to HIGH. In the Sleep mode, the internal register holds the same settings as ones before a transition to the Sleep mode. When the Sleep mode is canceled, the S1F81100 is restored to the same state as it was before a transition to the Sleep mode. 4.2.2 Transitioning to and Canceling the Sleep Mode When CH-1 Voltage Change is Made As described in Section 4.1, to change the CH-1 output voltage using the step transition, it is required to transition to and cancel the Sleep mode after setting the VS17 to 10 register. This involves the software and hardware control as described in Section 3.1.5. Control the software and hardware on your application following the description in Table 3.1.5.2. Fig.4.2.2.1 shows its timing chart. See section 5.2 for details of the VS17 to 10 register. VS17 to 10 [Digital] A B PWR_EN [Digital] WUP [Digital] less than 1s less than 1s nVCC_FLT [Digital] less than 1s VCC1 less than 1s A B The values in the figure indicate the typical values that serve as guide. Fig.4.2.2.1 Sleep Mode Control Timing when Changing CH-1 Output Voltage Using Step Transition 32 EPSON Rev.1.4 S1F81100 Technical Manual 4.2.3 Transitioning to and Canceling the Sleep Mode When CH-1 Voltage Change is not Made A transition to Sleep mode not aiming at changing the CH-1 output voltage (VS17 to 10 register value not changed) does not involve the change in the WUP signal in contrast to the conditions under which the output voltage change is made. Fig.4.2.3.1 shows its timing chart. Table 4.2.3.1 shows the flow for controlling the software. Follow that flow to control the software on your application. VS17 to 10 [Digital] A PWR_EN [Digital] WUP [Digital] nVCC_FLT [Digital] less than 1s VCC1 A less than 1s A The values in the figure indicate the typical values that serve as guide. Fig.4.2.3.1 Sleep Mode Control Timing when CH-1 Voltage Change is not Made Rev.1.4 EPSON 33 S1F81100 Technical Manual Table 4.2.3.1 Steps for Controlling Software When the VCC1 Output Voltage Change is not Made Status Normal operation state Normal operation Processor ex. PXA250/210 Operation (software/hardware-controlled) PWN_EN pin output: HIGH level Power supply IC S1F81100 Operation Voltage output VCC1/VCC4 outputs turned ON. WUP pin output: LOW level [Setting] Enable the input interrupt of the GP[n] pin. [Software control] Rewrites the VS17 to VS10 register of the power supply IC via the I2C controller and sets the new voltage value. c I2C communication d Start transitioning to Sleep (PWR_EN pin control) e CORE voltage OFF I2C command Transition to Start transition to Sleep. PWR_EN Sleep signal [Software control] L Sets the output of PWR_EN pin to LOW Level to transit to Sleep state. Sleep Voltage output X VCC1/VCC4 outputs OFF. (WUP pin held LOW.) (Stay in Sleep until an interrupt occurs.) [Interrupt occurred!] f Sleep State Cancellation Sleep Start Start canceling Sleep. Cancellation PWR_EN signal [Software (hardware)control] H Sets the output of PWR_EN pin to HIGH level to cancel Sleep. g CORE voltage output Normal mode Voltage output VCC1/VCC4 outputs ON. Normal mode PWR_EN pin output: HIGH level Voltage output VCC1/VCC4 outputs ON. ON Normal operation state WUP pin output: LOW level 4.2.4 Mask Options Associated with the Sleep Mode The S1F81100 provides the following mask options that are associated with the Sleep mode. [No.3] One-touch recovery function for the Sleep mode 1. Disable 2. Enable This mask option can be used to enable/disable the one-touch recovery function. The one-touch recovery function enables the S1F81100 unit to recover from the Sleep or Deep Sleep mode to the Normal mode by inputting a LOW-level signal to the P02 pin when the input level of the PWR_EN pin is held at LOW with the S1F81100 set in the Sleep or Deep Sleep mode. This function works effectively, for example, when the sub-battery is exhausted after maintaining the application in the Deep Sleep mode for a long period of time and it is no longer possible to set the PWR_EN pin to HIGH. See section 5.2 for details of the IOP02 register. 34 EPSON Rev.1.4 S1F81100 Technical Manual Fig.4.2.4.1 outlines the one-touch recovery function. Note: To use the one-touch recovery function, you must set the P02 port to "INPUT" using the IOP02 register. In addition, you must set the input level to HIGH before entering the Sleep mode. Normal Mode Sleep Mode Normal Mode PWR_EN [Digital] P02 [Digital] Even though PWR_EN is kept LOW level input, sleep mode is canceled by onetouch recovery function. nVCC_FLT [Digital] VCC1 Fig.4.2.4.1 Description of One-Touch Recovery Function [No.4] CH-2 main regulator operation for the Sleep mode 1. ON 2. OFF This mask option can be used to turn the CH-2 main regulator for the Sleep mode ON or OFF. The mask option works effectively by selecting ON when the CH-2 requires a large load current in the Sleep mode or selecting OFF when the CH-2 does not require a large load current and the power consumption during the Sleep mode should be reduced as low as possible. Setting the LMD2 register to 1 forces the main regulator to turn OFF during the Sleep mode independently of this mask option. See section 5.2 for details of the LMD2 register. [No.5] CH-3 main regulator operation for the Sleep mode 1. ON 2. OFF This mask option can be used to turn the CH-3 main regulator for the Sleep mode ON or OFF. The mask option works effectively by selecting On when the CH-3 requires a large load current in the Sleep mode or selecting OFF when the CH-2 does not require a large load current and the power consumption during the Sleep mode should be reduced as low as possible. Setting the LMD3 register to 1 forces the main regulator to turn OFF during the Sleep mode independently of this mask option. See section 5.2 for details of the LMD3 register. Rev.1.4 EPSON 35 S1F81100 Technical Manual 4.3 Deep Sleep Mode The S1F81100 enters the Deep Sleep mode when the PWR_EN pin is set to LOW during operation with the EDS register set to "1". In the Deep Sleep mode, CH-1 to CH-4 are turned OFF. In this mode the power consumed by the S1F81100 is significantly lower compared to the Sleep mode. 4.3.1 Transitioning to and Canceling the Deep Sleep Mode This section describes how to transition to and cancel the Deep Sleep mode. Fig.4.3.1.1 shows a timing chart when transitioning to and canceling the Deep Sleep mode. Transitioning to Deep Sleep Mode To transition to the Deep Sleep mode, set the EDS register to "1" and input level of the PWR_EN pin to LOW using the I2C controller in the Normal mode. When the S1F81100 enters the Deep Sleep mode, CH-1: Voltage output is turned OFF. CH-2: Voltage output is turned OFF. Depending on the mask option setting, the sub-regulator is turned on. CH-3: Voltage output is turned OFF. CH-4: Voltage output is turned OFF. In the Deep Sleep mode, CH-1 to CH-4 are turned OFF, thereby current consumption is less than that for the Sleep mode. Therefore, setting the unit to enter the Deep Sleep mode via application software when all voltage output are no longer required contributes to reduction of current consumption of the entire system, resulting in higher efficiency of the unit. The unit can be restored from the Deep Sleep mode by LOW level input via the XRST pin. Canceling Deep Sleep Mode When the VCC2 (CH-2) is powered by the sub-regulator or external power supply in the Deep Sleep mode, this mode can be canceled by setting the input level of the PWR_EN pin to HIGH. When it is canceled, the S1F81100 is restored to the same state as it was before a transition to the Deep Sleep mode. It can be also canceled by the LOW level input to the XRST pin. In this case, each register in the S1F81100 will be initialized. 36 EPSON Rev.1.4 S1F81100 Technical Manual VS17 to 10 [Digital] A PWR_EN [Digital] WUP [Digital] nVCC_FLT [Digital] less than 1s less than 1s VCC1/VCC4 A A VCC2/VCC3 The values in the figure indicate the typical values that serve as guide. Fig.4.3.1.1 Deep Sleep Mode Control Timing 4.3.2 Mask Options Associated with the Deep Sleep Mode The S1F81100 provides the following mask options that are associated with the Deep Sleep mode. [No.3] One-touch recovery function for the Sleep mode 1. Disable 2. Enable See section 4.2.2. (In the Deep Sleep mode, the S1F81100 operates in the same way as in the Sleep mode.) [No.6] CH-2 sub-regulator operation for the Deep Sleep mode 1. Enable (CH-2 sub-regulator, ON in Deep Sleep mode) 2. Disable (CH-2 sub-regulator, OFF in Deep Sleep mode) The ON/OFF operation of CH-2 sub-regulator in the Deep Sleep mode is selectable from mask options. Selecting "OFF" stops CH-2 output and reduces the VCC2 potential down to the GND level. For this reason, once the unit enters the Deep Sleep mode, it can be restored from this mode only by LOW level input via the XRST pin. When power is externally supplied to VCC2 (CH-2) in the Deep Sleep mode, input via PWR_EN is also accepted. Rev.1.4 EPSON 37 S1F81100 Technical Manual 4.4 Ultra-Power-Saving Mode The S1F81100 provides an Ultra-Power-Saving mode. This mode stops the functions of the entire IC functionality to minimize power consumption. The current consumption in this mode is on the order of a few microamperes. This mode is useful for shipping the product or for maintaining applications what are not to be used for a long period of time. To set the Ultra-Power-Saving mode, set the input level of the XSDWN pin to LOW. Maintaining the input level at LOW allows the S1F81100 to stay in the Ultra-Power-Saving mode. To recover from the Ultra-Power-Saving mode, follow the procedures below. (1) Set the input level of the XRST pin to LOW. (2) Set the input level of the XSDWN pin to HIGH. (3) Set the input level of the XRST pin to HIGH. Setting the XSDWN pin back to HIGH with the XRST pin held HIGH, the IC's internal circuitry becomes unstable. Thus, this input state should not be used. Fig.4.4.1 shows a timing chart when transitioning to and canceling the Ultra-Power-Saving mode. XSDWN [Digital] XRST [Digital] UltraPowerSaving mode Normal mode Reset Ultra-Power-Saving mode Unstable state Normal mode Reset Fig.4.4.1 Timing for Transitioning and Canceling the Ultra-Power-Saving Mode 38 EPSON Rev.1.4 S1F81100 Technical Manual 5. I2C CONTROLLER Being a system power supply IC, the S1F81100 is equipped with an I2C controller having a slave function for enhancing operability for operation from external devices. Sending specified commands to the I2C controller enables data inside the IC to be read and written, allowing detailed setting of the regulators and auxiliary circuits. This section provides detailed descriptions of the I2C controller. 5.1 Description The I2C controller refers to the controller complying with the standard two-wire system serial interface specifications advocated by Phillips. S1F81100 products are licensed by Phillips. This section describes its communications mechanism. 5.1.1 Basic Specifications The basic specifications of the I2C controller mounted on the S1F81100 are as follows: Address: 000100xB (Bit length: 7 bits. LSB: Can be set with the AD_EN pin.) ) Transmission speed: Maximum 400 kHz Pins used SDA: Data I/O pin SCL: Clock input pin AD_EN: Address enabling pin (LSB Select pin) Voltage level (SDA, SCL) VCC2 level (AD_EN) VIN level Reading/writing in the register assigned to the I2C controller enables this IC to be externally configured with detailed settings or updated operating conditions and to be subject to operation control as well as internal state monitoring. The function of the I2C controller of the S1F81100 is limited to the slave function. Thus, control is only possible externally, from the master side. Note: While VCC2 is OFF, the I2C controller cannot be used. 5.1.2 Start and Stop Conditions In the transmission procedure involving the I2C controller, it is necessary to raise the controller-specific conditions, Start and Stop, upon starting and stopping communications respectively. Fig.5.1.2.1 shows a chart of these timings. Fig.5.1.2.1 Start and Stop Conditions for I2C Controller 1) When SCL is at HIGH, SDA turns from HIGH to LOW. This forms a Start condition. 2) When SCL is at HIGH, SDA turns from LOW to HIGH. This forms a Stop condition. Since this model only provides the slave function, the above Start or Stop conditions cannot be generated on this controller. Be sure to generate them on the master side. Both the Start and Stop conditions can be generated at a desired timing. Rev.1.4 EPSON 39 S1F81100 Technical Manual 5.1.3 Data Transfer (command format) Fig.5.1.3.1 shows the command format for data transmission. Address Transmit/ Receive 1 byte Transmit/ Receive 1 byte Data-X0H Transmit/ Receive 1 byte ..... Data-X1H Stop Data-X5H ..... SDA(ACK) .... .... .... .... SCL .... SDA(DATA) R/W Transmit/ Receive 1 byte Start Start condition Stop condition Fig.5.1.3.1 S1F81100 Command Format for I2C Controller Fig.5.1.3.2 shows a detailed chart of command sending/receiving timings. SDA(DATA) D7 [A6] D6 [A5] D5 [A4] D4 [A3] D3 [A2] D2 [A1] D1 [A0] D0 [R/W] 1 2 3 4 5 6 7 8 SDA(ACK) SCL 9 Fig.5.1.3.2 Send and Receive Single Byte Timing Starting Transmission Generating the Start condition described above from the master side starts transmission. Slave Address After a Start condition is generated, the slave address should be specified and sent from the master side. This slave address is composed of seven bits and is assigned a unique value for each IC. For the S1F81100, a 7-bit slave address (000100xB) is assigned by Philips. The LSB is specified by the input level of the AD_EN pin. When AD_EN = 0: The slave address is set to 0001000B. When AD_EN = 1: The slave address is set to 0001001B. This allows the AD_EN pin to be used as an Enable pin for the I2C. The slave address must be input from the master side starting with the MSB (A6). The address is stored in the slave (S1F81100) at the falling edge of the clock input in SCL. See section 4.1.3.2. Read/Write Specification Bit Immediately after the slave address has been specified, a bit to specify the transmission direction follows that indicates either read or write. The relationship between the bit value and the transmission direction is as follows: Bit value "0": Receiving from the master (S1F81100) (write). Bit value "1": Transmitting from the slave (S1F81100) (read). The read/write specification bit is input from the master side following the LSB (A0). This bit is stored in the S1F81100 at the rising edge of the clock input in SCL. See section 5.1.3.2. 40 EPSON Rev.1.4 S1F81100 Technical Manual ACK Signal after Transferring Slave Address and Read/Write Specification Bit When the slave address and read/write specification bit is transferred from the master, the slave (S1F81100) checks the following: Transfer format Slave address value When they are properly stored, the slave sends an ACK (active LOW) to the master. This ACK output timing is synchronized with the rising edge of the clock input in SCL. See section 5.1.3.2. When ACK is output, the S1F81100 considers that transfer of the slave address and read/write specification bit has completed. Control Address, Control Data and ACK Signal Upon completion of transfer of the slave address and read/write specification bit, the slave (S1F81100) starts a control data read or write. The operation varies depending on the read/write specification bit. If "read" is specified, internal data is output (read)from the slave (S1F81100) to the master. If "write" is specified, data is input (written)from the master to the slave (S1F81100). Control data transfer starts from the X0H control address (see Table 5.2.1). For the sequence of data and data read timing, see Fig.5.1.3.2. When transmission of X0H is successfully completed, the ACK signal should be sent from the master to the slave (S1F81100) for "read" and from the S1F81100 to the master for "write." When an ACK is output, the single-byte (X0H) data transfer terminates. After this, the control address is automatically incremented on the S1F81100, then transfer of X1H starts. The subsequent byte transfer takes place in the same fashion; the control address is incremented sequentially upon completion of each one byte. After the last X5H control address is transferred, the control address returns to X0H and data transfer starts again. To successfully terminate the transmission via the I2C bus, it is required to use the following command format as well as to generate the Stop condition. For a read: The last ACK to be sent from the slave to the master can be either ACK (SDA LOW) or non-ACK (SDA HIGH). For a write: The last ACK to be sent from the master to the slave must be non-ACK (SDA HIGH). Terminating Transmission Generating the Stop condition described above from the master side terminates transmission. Transmission cannot be successfully terminated unless the last ACK for both read and write operations conforms to the command format. Note: Data transfer continues looping until a Stop condition is issued from the master side. So be sure to generate a Stop condition on the master side when the transmission terminates. 5.1.4 Behavior During Malfunction Conditions The following describes typical malfunctions along with the conditions that cause them. [Case 1] A Stop condition has started before transmission starts. The I2C controller does not operate. [Case 2] Transmission has started with a Start condition but a Start condition is generated again during the transmission (that is, before generation of a Stop condition). Transmission start from the beginning, that is, from specification of the slave address, then jumps to the X0H control address to start the rest of the transmission. [Case-3] When an ACK (SDA LOW) is issued from the master at the timing of ACK for a read operation, the S1F81100 continues the read operation. At the end of the read operation, be sure to transmit a non-ACK (SDA HIGH). If the read operation is terminated with an ACK transmitted (SCL stopped), the S1F81100 is no longer able to generate a Start condition since transmission fails to terminate successfully. In such a case, activate the clock (SCL) once to generate a non-ACK to get the unit back to normal. Rev.1.4 EPSON 41 S1F81100 Technical Manual 5.2 Control Address & Control Data List The I2C controller of the S1F81100 has the control addresses and control data (registers/flags) listed in Table 5.2.1. Table 5.2.1 Control Address/Data for I2C Addr. X0H X1H X2H X3H X4H X5H Name R/W Init Name R/W Init Name R/W Init Name R/W Init Name R/W Init Name R/W Init D7 VS17 R/W 1 RT17 R/W 1 XEECKH R/W 1 EDS R/W 0 EBFT R/W 1 IOP03 R/W 0 D6 VS16 R/W 0 RT16 R/W 1 RT26 R/W 1 RT36 R/W 1 LMD3 R/W 0 DTP03 R/W 0 D5 VS15 R/W 0 RT15 R/W 1 RT25 R/W 1 RT35 R/W 1 POFF3 R/W 0 IOP02 R/W 0 Register D4 D3 VS14 VS13 R/W R/W 1 0 RT14 RT13 R/W R/W 1 1 XC1TRG EOSH W R/W 1 RT34 RT33 R R/W 1 1 PG3 EVFT R R/W 1 DTP02 IOP01 R/W R/W 0 0 Comment D2 VS12 R/W 1 RT12 R/W 1 LMD1 R/W 0 RT32 R 1 LMD2 R/W 0 DTP01 R/W 0 D1 VS11 R/W 1 RT11 R/W 1 POFF1 R/W 0 POFF4 R/W 0 POFF2 R/W 0 IOP00 R/W 0 D0 VS10 R/W 0 RT10 R/W 1 PG1 R R PG2 R DTP00 R/W 0 VCC1 voltage control General-purpose register VCC1 setup register VCC4 setup register and other controls VCC2/VCC3 setup registers and other controls General-purpose I/O port control The following describes the respective registers. VS17 to VS10 VCC1 output voltage setting register Default: VS17 to VS10 = 096H = 10010110B 1.5V This is the VCC1 output voltage setting register for CH-1. The S1F81100 allows the user to select from eight output values, 1,5, 1.4, 1.3, 1.2, 1.1, 1.0, 0.9 and 0.8 V. The output voltage value can be modified programmably based on the 8-bit register value specified with VS17 to VS10. Example: (1) Setting for 1.3 V output: 130D =10000010B =082H: With VS17 to VS10 set to 082H, VCC1 = 1.3V. (2) Setting for 1.1 V output: 110D =01101110B=06EH: With VS17 to VS10 set to 06EH, VCC1 = 1.1V. (3) Setting for 1.0 V output: 100D =01100100B =064H: With VS17 to VS10 set to 064H, VCC1 = 1.0V. (4) Setting for 0.8 V output: 080D =01010000B =050H: With VS17 to VS10 set to 050H, VCC1 = 0.8V. If values other than the above examples are set for VS17 to VS10, the output value follows Table 5.2.1. 42 EPSON Rev.1.4 S1F81100 Technical Manual Table 5.2.1 VS17 to VS10 Settings and VCC1 Output Voltage VS17 to 10 VCC1 VS17 to 10 VCC1 11111*** B 11110*** B 11101*** B 11100*** B 11011*** B 11010*** B 11001*** B 11000*** B 10111*** B 10110*** B 10101*** B 10100*** B 10011*** B 10010*** B 10001*** B 10000*** B Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited 1.5V 1.5V 1.4V 1.3V 01111*** B 01110*** B 01101*** B 01100*** B 01011*** B 01010*** B 01001*** B 01000*** B 00111*** B 00110*** B 00101*** B 00100*** B 00011*** B 00010*** B 00001*** B 00000*** B 1.2V 1.2V 1.1V 1.0V 0.9V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V An asterisk (*) in the table indicates an optional value. As shown in Table 5.2.1, the S1F81100 decodes the upper five bits (VS17 to VS13), ignoring the lower three bits (VS12 to VS10). The lower three bits can, therefore, be used as a general-purpose register. POFFn (n=1 to 4): CH-n Power OFF control register 1 Output OFF (Power OFF) 0 Output ON (Power ON) (Default) These are the registers for ON/OFF control of the CH-1 to CH-4 regulators. If these registers are set to "0," output is disabled even during normal operation. If the PWR_EN pin is assigned the LOW level (set to the Sleep state) when these registers are set to "0," they are automatically initialized to enable voltage output when recovering from the Sleep state. When a short-circuit protection function operates on the CH-2 (or CH-3), a "1" is written into the POFF2 (or POFF3) register, turning the output OFF. See sections 3.1.6, 3.2.6, 3.3.6 and 3.4.2 for details of the Power OFF function. The POFFn registers are read/write-enabled. PGn (n = 1 to 3): CH-n Power Good detecting flag 1 Within the specified range. 0 Outside the specified range. This flag indicates the Power Good detection result for each of the CH-1 to CH-3 regulators. If the flag value turns to "0," the "0" level is maintained until this register is read once by the I2C controller. After the register is read, the level turns to "1." Thus, the register can determine which output is abnormal when the nVCC_FLT pin output drops to "0." The Power Good function operates even on an unstable state (including voltage output rise or fall for each CH). This may cause the PGn to misinterpret an output as "0" (outside the specified range) to be written into the flag. It is, therefore, required to read the PGn flag twice or more before using the Power Good function. At the initial startup, this must be done. See sections 3.1.7, 3.2.7 and 3.3.7 for details of the Power Good function. The PGn flag is read only. LMDn (n=2, 3): Mode Select (Normal or Light-Load mode) register 1 Light-Load mode 0 Normal mode (Default) These are the registers for selecting whether the main (PWM controller) or the sub-controller (backup LDO) is to be used for each of the CH-2 and CH-3 regulators. Rev.1.4 EPSON 43 S1F81100 Technical Manual State "0" (Normal mode) that provides a high output current is effective when a high load current is required. State "1" puts the S1F81100 in the Light-Load mode. This significantly reduces the operating current consumption of the S1F81100 unit. Furthermore, greater efficiency is achieved by setting this state in an operating mode that does not require a high load current. If overload detection activates the automatic switching function, this register automatically turns to "0." See sections 3.2.3 and 3.3.3 for details of the Normal and Light-Load modes, respectively. The LMDn registers are read/write-enabled. LMD1 (*When CH-1 sub-regulator is set to OFF by the mask option.) CH-1 Power OFF control register 1 Output OFF. 0 Output ON. (Default) This register operates similarly to the POFF1 register. See section 3.1.6 for details of the Power OFF function. The LMD1 register is read/write-enabled. (*When CH-1 sub-regulator is set to On by the mask option.) Mode Select (Normal or Light-Load mode) register 1 Light-Load mode 0 Normal mode (Default) This is the register for selecting whether the Normal or Light-Load mode is to be used for the CH-1 regulator. State "0" (Normal mode) that provides a high output current is effective when a high load current is required. State "1" puts the S1F81100 in the Light-Load mode. This significantly reduces the operating current consumption of the S1F81100 unit. Furthermore, greater efficiency is achieved by setting this state in an operating mode that does not require a high load current. If overload detection activates the automatic switching function, this register automatically turns to "0." See section 3.1.3 for details of the Normal and Light-Load modes. The LMD1 register is read/write-enabled. Deep Sleep mode setting register 1 Deep Sleep mode enabled. 0 Deep Sleep mode disabled (Default) This is for specifying if the Deep Sleep mode is to be used or not. If the LOW level is input for the RWR_EN pin with this register set to "1," the S1F81100 transits to the Deep Sleep mode and the voltage outputs from VCC1 through VCC4 are all switched OFF. This function is effectively used to control the power consumption to a level even lower than that in the Sleep mode. The "0" state is equivalent to the ordinary Sleep mode. The EDS register is read/write-enabled. EDS Input voltage determining function activating register 1 Input voltage determining function enabled. (Default) 0 Input voltage determining function disabled. This is the register for enabling/disabling the input voltage determining function. When set to "1," this register activates input voltage determining function, enabling it to monitor if the input voltage is within the specified range or not. If it is detected to be within the range, the outputs from the nBAT_FLT pins will be at the HIGH level, and if it is outside the range, the outputs will be LOW. When set to "0," this register deactivates the input voltage determining function, and the outputs from the nBAT_FLT pins will always be HIGH. See section 6.3 for details of the input voltage determining function. The EBFT register is read/write-enabled. EBFT Output voltage determining function activating register 1 Output voltage determining function enabled. (Default) 0 Output voltage determining function disabled. This is the register for enabling/disabling the output voltage determining function (Power Good). When set to "1," this register activates the CH-1 to CH-3 regulators' Power Good function, enabling them to detect if the respective output voltages are within the specified range or not. If all are within the range, the EVFT 44 EPSON Rev.1.4 S1F81100 Technical Manual outputs from the nVCC_FLT pins will be at the HIGH level, and if the output voltage from one or more of CH-1 to CH -3 is outside the range, the outputs will be LOW. When set to "0," this register deactivates the Power Good function, and the outputs from the nVCC_FLT pins will always be HIGH. See section 6.2 for details of the output voltage determining function. The EVFT register is read/write-enabled. External clock input enabling register 1 External clock input disabled. (Default) 0 External clock input enabled. This is the register for enabling/disabling the external clock input. When set to "1," this register specifies the clock (approx. 1 MHz) generated by CR oscillation inside the S1F81100 to be used as the reference clock. The reference clock is used as the operating clock for the PWM controller. When set to "0," this register enables an external clock to be input from the CLKIN pin, making it possible for the external clock to be used as the reference. See section 6.1 for details of the external clock. The XEECKH register is read/write-enabled. XEECKH Internal oscillator circuit activating register 1 Oscillator circuit enabled. (Default) 0 Oscillator circuit disabled. This is the register for activating/deactivating the S1F81100's internal oscillator circuit. If the register is set for disabling the oscillator circuit, the value of the current consumed by the S1F81100 can be lowered. Note, however, that this setting eliminates the reference clock and disables operation. Therefore, it is necessary to set the XEECKH register to "0" and input the external clock from the CLKIN pin prior to setting it to "0." See section 6.1 for details of the oscillator circuit. The EOSH registers are read/write-enabled. EOSH IOP0n (n=0 to 3) P0n port I/O setting registers 1 Output 0 Input (Default) These are the registers for setting the I/O properties of the P0n pins (general-use ports). The pins function as input pins when the relevant register is set to "0," and as output pins when set to "1." See section 6.4 for the P0n pins. The IOP0n registers are read/write-enabled. DTP0n (n=0 to 3) P0n port data registers 1 HIGH 0 LOW These are the P0n pin data registers. If the IOP0n registers are set to "input," the P0n pin output levels can be read from these registers. If the IOP0n registers are set to "output," data set for these registers are output from the P0n pins. See section 6.4 for the P0n pins. The DTP0n registers are read/write-enabled. CH-1 voltage change register 1 No Change 0 Trigger Change This is the register that directs a voltage change for the CH-1 regulator. When this bit is set to 0 by the I2C controller, the values set in VS17 to VS10 registers are loaded into the CH-1 regulator. If the values currently output to the CH-1 differ from those set in the VS17 to VS10 registers, the output voltage value is changed. When it is set to "1", those values are not loaded and a voltage change is not performed. See section 3.1.5 for details of the voltage change trigger, The XC1TRG register is read only. XC1TRG Rev.1.4 EPSON 45 S1F81100 Technical Manual 6. AUXILIARY FUNCTIONS AND OPERATIONS The S1F81100 has the following auxiliary functions that can be set via the I2C controller. 1. Oscillator circuit/clock selecting function 2. Output voltage determining function 3. Input voltage determining function 4. General-purpose I/O ports The following provides detailed descriptions of these functions. 6.1 Oscillator Circuit/Clock Selecting Function The oscillator circuit generates the clock required for operations of the PWM controllers of CH-1 to CH-3. This is a CR oscillator circuit that does not require external components, and internally generates approximately 1 MHz clock (Typ.). This circuit also provides the clock selecting function. The XEECKH register in the I2C controller can be used to select the clock from the internally generated clock and the clock externally input from the CLKIN pin. As the CLKIN voltage level is VCC2, the clock cannot be externally selected with CH-2 output set OFF. With the external clock selected, the S1F81100's internal oscillator circuit can be deactivated. This way, power consumption on the IC can be reduced. This setting can also be selected using the EOSH register of the I2C controller. Fig.6.1.1 is its circuit diagram. CLKIN XEECKH Reference clock Oscillator circuit EOSH Fig.6.1.1 Clock Selecting Function Block Diagram See section 5.2 for details of the XEECKH and EOSH registers. 46 EPSON Rev.1.4 S1F81100 Technical Manual 6.2 Output Voltage Determining Function The S1F81100 has an output voltage determining function. This function exposes the reversed value of the output level of the nVCC_FLT pin to the external devices when at least one of the regulators' Power Good circuits for CH-1 to CH-3 is determined to be "outside the specified range" during its operation. For the nVCC_FLT pins, the output level will be as follows: If the voltage is normal: HIGH level If the voltage is abnormal: LOW level For the nVCC_FLT pins, the voltage level will be BATT_VCC. For determining the output voltages of the respective regulators, see sections 3.1.7, 3.2.7, and 3.3.7. With this function, external components can detect the output level of this pin so that the application can be set to the Sleep mode, etc. as required. It is also possible to enable or disable this function by using the EVFT register of the I2C controller. Fig.6.2.1 shows a block diagram of the output voltage determining function. S1F81100 EVFT Power Good (CH-1) PG1 Power Good (CH-2) PG2 Power Good (CH-3) nVCC_FLT PG3 Fig.6.2.1 Output Determining Function Block Diagram See section 5.2 for details of the EVFT register. Rev.1.4 EPSON 47 S1F81100 Technical Manual 6.3 Input Voltage Determining Function The S1F81100 has an input voltage determining function. This function internally determines on the IC the voltage input to the VIN pin and exposes the reversed value of the output level of the nBAT_FLT pin to the external devices when the input value is determined to be "outside the specified range." For the nBAT_FLT pins, the output level will be as follows: If the voltage is normal: HIGH level If the voltage is abnormal: LOW level For the nBAT_FLT pins, the voltage level will be BATT_VCC. With this function, external components can detect the output level of this pin so that the application can be set to the Sleep mode, etc. as required. It is also possible to enable or disable this function by using the EBFT register of the I2C controller. Fig.6.3.1 shows a block diagram of the input voltage determining function. S1F81100 EBFT nBAT_FLT Input voltage determining circuit Fig.6.3.1 Input Voltage Detecting Function Block Diagram See section 5.2 for details of the EBFT register. 48 EPSON Rev.1.4 S1F81100 Technical Manual 6.4 General-Purpose I/O Ports The S1F81100 has four general-purpose I/O ports, P00 to P03. Fig.6.4.1 shows the configuration of the general-purpose I/O ports. IOP0n P0n DTP0n Fig.6.4.1 General-purpose I/O Port Block Diagram 6.4.1 Description With the IOP00 to IOP03 registers of the I2C controller, you can select the I/O properties of the respective pins. Similarly, with the DTP00 to DTP03 registers, input data of the P00 to P03 ports can be read or output data can be set for these pins. See section 5.2 for details of the IOP00 to IOP03 and DTP00 to DTP03 registers. When these pins are set to "input," the pull-up resistance installed on the pin functions to set the HIGH level input state even in the disconnected state. If these ports are set to "output", the complementary output specifications are applied. The voltage levels of the P00 to P03 ports are as follows: P00 and P01: VCC2 level P02 and P03: VIN level Note: P00 and P01 pins do not function with the CH-2 set to OFF. Rev.1.4 EPSON 49 S1F81100 Technical Manual 6.4.2 Mask Options Associated with the General-Purpose I/O Ports The S1F81100 provides the following mask options that are associated with the general-purpose I/O ports. [No.3] One-touch recovery function for the Sleep mode 1. Disable 2. Enable This mask option can be used to enable/disable the one-touch recovery function. The one-touch recovery function enables the S1F81100 unit to recover from the Sleep or Deep Sleep mode to the Normal mode by inputting a LOW-level signal to the P02 pin when the input level of the PWR_EN pin is held at LOW with the S1F81100 set in the Sleep or Deep Sleep mode. This function works effectively, for example, when the sub-battery is exhausted after maintaining the application in the Deep Sleep mode for a long period of time and it is no longer possible to set the PWR_EN pin to HIGH. See section 5.2 for details of the IOP02 register. Fig.6.4.2.1 outlines the one-touch recovery function. Note: To use the one-touch recovery function, you must set the P02 port to "INPUT" using the IOP02 register. In addition, you must set the input level to HIGH before entering the Sleep mode. Normal Mode Sleep Mode Normal Mode PWR_EN [Digital] P02 [Digital] Even though PWR_EN is kept LOW level input, sleep mode is canceled by onetouch recovery function. nVCC_FLT [Digital] VCC1 Fig.6.4.2.1 Outline of One-Touch Recovery Function 50 EPSON Rev.1.4 S1F81100 Technical Manual 7. BASIC EXTERNAL CONNECTION DIAGRAMS *1 CH-1 *1 CH-2 *1 PWR_EN nVDD_FAULT nBAT_FAULT GP(n) nRESET CH-3 PWR_EN nVCC_FLT nBAT_FLT WUP nRESET VCC2 FB4 VCC4 CC4 S1F81100 Processor (ex.PXA250/210) VCC VCCQ VCCN PLL_VCC VCC2 SSCAP1 SSCAP2 SSCAP3 CS3 CS2 CS1 BATT_V CC VBAK CLKIN SDA SCL SDA SCL AD_EN P03 P02 P01 P00 VIN XSDWN XTEST0 VD1 VREF BAT1 CP1 + CR1 CD1 VSS XRST Ext. Reset Controller [For *1 in figure, see Fig.7.2.] Fig.7.1 Basic External Connection Diagram (1) Rev.1.4 EPSON 51 S1F81100 Technical Manual VCCn For CH-n (n=1 to 3) VINn TPn SWnOH CLn VCCn FBnM TNn SWnOL + SDn VSSn CCn + CP0n Fig.7.2 Basic External Connection Diagram (2) Table 7.1 External Component List (for reference) Symbol CL1 to 3 TP1 to 3 TN1 to 3 SD1 to 3 CC1 to 3 CC4 CS1 CS2 to 3 CD1 CR1 CP1 CP01 to 03 BAT1 Components Choke-type coil P-ch power MOS transistor N-ch power MOS transistor Schottky diode Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Lithium battery Parameter 10H 100F 22F 0.0068F 0.01F 0.1F 0.1F 100F 47F (2.8)3.3 to 5.5V Coments *1 *2 *3 *4 *5 (Recommended Components) *1 SUMIDA/CR43-100(@Imax=500mA), SUMIDA/CR54-100(@Imax=1A) *2 SANYO/CPH6315, HITACHI/HAT1043M *3 SANYO/CPH6415, HITACHI/HAT2053M *4 HITACHI/HRW0702A(@Imax=500mA), SANYO/SBS004, TOSHIBA/CMS06(@Imax=1A) *5 NEC-TOKIN/ESVB20J107M 52 EPSON Rev.1.4 S1F81100 Technical Manual 8. ELECTRICAL CHARACTERISTICS Absolute maximum ratings Parameter Input voltage (1) Input voltage (2) Input voltage (3) Allowable total output current Operating temperature Storage temperature Soldering temperature/time Allowable package loss Symbol VIN VI2 VI3 Applicable VIN *1 *2 Rating -0.5 to +7.0 -0.5 to +4.5 -0.5 to +7.0 Unit V V V IVIN - 10 mA Topr Tstg - -40 to +85 -65 to +150 C C Tsol - 260C, 10s - PD - 250 mW *1: VD1 *2: All pins except for input voltages (1) and (2). Recommended operating range Parameter Input voltage range Rev.1.4 Symbol VIN,VIN1,VIN2, VIN3 Condition 3.3V output is selected for either CH-2 or CH-3. Output of less than 2.5V is selected for both CH-2 and CH-3. EPSON Min. 3.3 Typ. - Max. 5.5 Unit V 2.8 - 5.5 V 53 S1F81100 Technical Manual Regulator characteristics [CH-1 characteristics] (Conditions applied unless otherwise specified) VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V, VCC2=3.3V, VCC3=3.3V, CS1=0.01F, IOUT1=100mA, Ta=25C Parameter Symbol Condition Normal operation (main and sub regulators) Output voltage VCC1 VCC1=0.8V VCC1=0.9V VCC1=1.0V VCC1=1.1V VCC1=1.2V VCC1=1.3V VCC1=1.4V VCC1=1.5V IS1H VSW1On=0.9VIN1 Output current with SW1OH and SW1OL pins held HIGH IS1LH VSW1OH=0.1VIN1 Output current with SW1OH pin held LOW IS1LL VSW1OL=0.1VIN1 Output current with SW1OL pin held LOW Input stability dVCC1-input 2.8V<VIN1<5.5V, IOUT1=100mA VCC1=1.5V Load stability dVCC1-load 10A<IOUT1<500mA VCC1=1.5V Output voltage dVCC1/dTaVCC1 IOUT1=100mA, -40C<Ta<+85C temperature coefficient VCC1=1.5V Power Good detection VPG1 VCC1=0.8V voltage VCC1=0.9V VCC1=1.0V VCC1=1.1V VCC1=1.2V VCC1=1.3V VCC1=1.4V VCC1=1.5V Maximum conversion EFF1 VCC1=1.5V efficiency IOUT1=500mA Sub-regulators only Output voltage VCC1L VCC1=0.8V VCC1=0.9V VCC1=1.0V VCC1=1.1V VCC1=1.2V VCC1=1.3V VCC1=1.4V VCC1=1.5V Input stability dVCC1L-input 1.8V<VCC3<5.5V, IOUT1=2mA VCC1=1.5V Load stability dVCC1L-load 10A<IOUT1<20mA VCC1=1.5V Output voltage dVCC1/dTaVCC1 IOUT1=2mA, -40C<Ta<+85C temperature coefficient VCC1=1.5V 54 EPSON Min. Typ. Max. Unit 0.76 0.86 0.95 1.05 1.14 1.24 1.33 1.43 15 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 40 0.84 0.95 1.05 1.16 1.26 1.37 1.47 1.58 65 V mA -90 -65 -40 mA -55 -45 -35 mA - 2.5 5.0 mV - 5 15 mV -500 -430 - ppm/C 0.68 0.77 0.85 0.94 1.02 1.11 1.19 1.28 - 0.72 0.81 0.90 0.99 1.08 1.17 1.26 1.35 80 0.76 0.86 0.95 1.05 1.14 1.24 1.33 1.43 - V 0.76 0.86 0.95 1.05 1.14 1.24 1.33 1.43 - 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 12 0.84 0.95 1.05 1.16 1.26 1.37 1.47 1.58 22 mV - 1 5 mV -500 -430 - ppm/C % V Rev.1.4 S1F81100 Technical Manual [CH-2 characteristics] (Conditions applied unless otherwise specified) VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V, VCC1=1.5V, VCC3=3.3V, CS2=0.1F, IOUT2=100mA, Ta=25C Parameter Symbol Condition Normal operation (main and sub regulators) Output voltage VCC2 VCC2=1.8V VCC2=2.5V VCC2=3.3V IS2H VSW2On=0.9VIN2 Output current with SW2OH and SW2OL pins held HIGH IS2LH VSW2OH=0.1VIN2 Output current with SW2OH pin held LOW IS2LL VSW2OL=0.1VIN2 Output current with SW2OL pin held LOW Input stability dVCC2-input VCC2=3.3V 3.4<VIN2<5.5V,IOUT2=300mA Any other conditions except VCC2=3.3V 2.8<VIN2<5.5V,IOUT2=300mA Load stability dVCC2-load 10A<IOUT2<1A Output voltage dVCC2/dTaVCC2 IOUT2=100mA, -40C<Ta<+85C temperature coefficient Maximum duty ratio MaxDuty2 Short circuit detection VSHRT2 voltage Short circuit detection TSHRT2 time Power Good detection VPG2 VCC2=1.8V voltage VCC2=2.5V VCC2=3.3V Maximum conversion EFF2 VCC3=3.3V efficiency IOUT2=600mA Sub-regulators only Output voltage VCC2L VCC2=1.8V VCC2=2.5V VCC2=3.3V Input stability dVCC2L-input 3.3V<VIN2<5.5V, IOUT2=2mA Load stability dVCC2L-load 10A<IOUT2<10mA Output voltage dVCC2/dTaVCC2 IOUT2=2mA, -40C<Ta<+85C temperature coefficient Overload detection current Rev.1.4 EPSON Min. Typ. Max. Unit 1.71 2.38 3.14 15 1.80 2.50 3.30 40 1.89 2.63 3.47 65 V mA -90 -65 -40 mA -55 -45 -35 mA - 40 100 mV - 40 100 mV -500 10 -430 30 - mV ppm/C 100 - - 0.3 % V - - 1 ms 1.53 2.13 2.81 - 1.62 2.25 2.97 90 1.71 2.38 3.14 - V 1.61 2.28 3.04 -500 1.70 2.40 3.20 7 12 -430 1.79 2.53 3.37 12 35 - mV mV ppm/C 14 30 - mA % V 55 S1F81100 Technical Manual [CH-3 characteristics] (Conditions applied unless otherwise specified) VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V, VCC1=1.5V, VCC2=3.3V, CS3=0.1F, IOUT3=100mA, Ta=25C Parameter Symbol Condition Normal operation (main and sub regulators) Output voltage VCC3 VCC3=1.8V VCC3=2.5V VCC3=3.3V IS3H VSW3On=0.9VIN3 Output current with SW3OH and SW3OL pins held HIGH IS3LH VSW3OH=0.1VIN3 Output current with SW3OH pin held LOW IS3LL VSW3OL=0.1VIN3 Output current with SW3OL pin held LOW Input stability dVCC3-input VCC3=3.3V 3.4V<VIN3<5.5V, IOUT3=300mA Any other conditions except VCC3=3.3V 2.8V<VIN3<5.5V, IOUT3=300mA Load stability dVCC3-load 10A<IOUT3<1A Output voltage dVCC3/dTaVCC3 IOUT3=100mA, -40C<Ta<+85C temperature coefficient Maximum duty ratio MaxDuty3 Short circuit detection VSHRT3 voltage Short circuit detection TSHRT3 time Power Good detection VPG3 VCC3=1.8V voltage VCC3=2.5V VCC3=3.3V Maximum conversion EFF3 VCC3=3.3V efficiency IOUT3=600mA Sub-regulators only Output voltage VCC3L VCC3=1.8V (IOUT3=2mA) VCC3=2.5V (IOUT3=2mA) VCC3=3.3V (IOUT3=2mA) Input stability dVCC3L-input 3.3V<VIN3<5.5V, IOUT3=2mA Load stability dVCC3L-load 10A<IOUT3<10mA Output voltage dVCC3/dTaVCC3 IOUT2=2mA, -40C<Ta<+85C temperature coefficient Overload detection current 56 EPSON Min. Typ. Max. Unit 1.71 2.38 3.14 15 1.80 2.50 3.30 40 1.89 2.63 3.47 65 V mA -90 -65 -40 mA -55 -45 -35 mA - 40 100 mV - 40 100 mV -500 10 -430 30 - mV ppm/C 100 - - 0.3 % V - - 1 ms 1.53 2.13 2.81 - 1.62 2.25 2.97 90 1.71 2.38 3.14 - V 1.61 2.28 3.04 -500 1.70 2.40 3.20 7 12 -430 1.79 2.53 3.37 12 35 - mV mV ppm/C 14 30 - mA % V Rev.1.4 S1F81100 Technical Manual [CH-4 characteristics] (Conditions applied unless otherwise specified) VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V, VCC1=1.5V, VCC2=3.3V, VCC3=3.3V, IOUT4=2mA, Ta=25C Parameter Output voltage VCC4 Input stability dVCC4-input Load stability dVCC4-load Output voltage temperature coefficient dVCC4/dTaVCC4 Rev.1.4 Symbol Condition VCC4=0.8V VCC4=0.9V VCC4=1.0V VCC4=1.1V VCC4=1.2V VCC4=1.3V VCC4=1.4V VCC4=1.5V 1.8V<VCC3<5.5V, IOUT4=2mA VCC4=1.5V 10A<IOUT4<20mA VCC4=1.5V IOUT4=2mA, -40C<Ta<+85C VCC4=1.5V EPSON Min. 0.76 0.86 0.95 1.05 1.14 1.24 1.33 1.43 - Typ. 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 12 Max. 0.84 0.95 1.05 1.16 1.26 1.37 1.47 1.58 22 Unit V - 1 5 mV -500 -430 - ppm/C mV 57 S1F81100 Technical Manual Miscellaneous characteristics [I/O characteristics] (Conditions applied unless otherwise specified) VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V, VCC2=2.5V, VBAT=VCC2, BATT_VCC=VCC2, Ta=25C Parameter Symbol Pin name HIGH-level input voltage VIH1 PWR_EN VIH2 P00,P01,CLKIN VIH3 SCL,SDA VIH4 AD_EN,P02,P03 VIH5 XRST VIH6 XSDWN LOW-level input voltage VIL1 PWR_EN VIL2 P00,P01,CLKIN VIL3 SCL,SDA VIL4 AD_EN,P02,P03 VIL5 XRST VIL6 XSDWN HIGH -level input current IIH1 PWR_EN IIH2 P00,P01,CLKIN IIH3 SCL,SDA IIH4 AD_EN,P02,P03 IIH5 XRST IIH61 XSDWN IIH62 XSDWN LOW -level input current IIL1 PWR_EN IIL2 P00,P01,CLKIN IIL3 SCL,SDA IIL4 AD_EN,P02,P03 IIL5 XRST IIL6 XSDWN HIGH -level output IOH1 WUP,nVCC_FLT, current nBAT_FLT,nRESET IOH2 P00,P01 IOH3 SDA P02,P03 IOH4 LOW -level output IOL1 WUP,nVCC_FLT, current nBAT_FLT,nRESET IOL2 P00,P01 IOL3 SDA P02,P03 IOL4 58 Condition VIH1=VBAT VIH2=VCC2 VIH3=VCC2 VIH4=VIN VIH5=VIN VIH6=VIN VIH6=0.8VIN VIL1=VSS VIL2=VSS VIL3=VSS VIL4=VSS VIL5=VSS VIL6=VSS VOH1=0.9VBAT Min. 0.8VBAT 0.8VCC2 0.8VCC2 0.8VIN 0.9VIN 0.9VIN 0 0 0 0 0 0 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -4 5 5 0 8 8 0.2 1 Typ. -2.5 7.5 7.5 12 12 0.7 2 Max. VBAT VCC2 VCC2 VIN VIN VIN 0.2VBAT 0.2VCC2 0.2VCC2 0.2VIN 0.1VIN 0.1VIN 0 0 0 0 0 0 -1 10 10 0.5 16 16 1.2 3 Unit V V V V V V V V V V V V A A A A A A A A A A A A A mA VOH2=0.9VCC2 VOH3=0.9VCC2 VOH4=0.9VIN VOL1=0.1VBAT 1 0 3 -4 2 4.5 -2.5 3 0.5 6 -1 mA A mA mA VOL2=0.1VCC2 VOL3=0.1VCC2 VOL4=0.1VIN -4 -30 -8 -2.5 -15 -6 -1 -5 -4 mA mA mA EPSON Rev.1.4 S1F81100 Technical Manual [Current consumption characteristics] (Conditions applied unless otherwise specified) VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V, VCC1=VCC4=1.5V, VCC2=2.5V, VCC3=3.3V, Ta=25C Parameter In Normal mode Iexe Symbol In Sleep mode (1) Isleep1 In Sleep mode (2) Isleep2 In Deep Sleep mode Ids Condition IOUT1=1A, IOUT2=1A IOUT3=1A, IOUT4=1A IOUTB=1A CH-1,2,3: Main regulator turned ON IOUT2=1A, IOUT3=1A IOUTB=1A CH-2,3: Main regulator turned ON IOUT2=1A, IOUT3=1A IOUTB=1A CH-2,3: Main regulator turned OFF IOUTB=1A Min. - Typ. 2 Max. 3 Unit mA - 1.4 2 mA - 100 130 A - 50 70 A [Miscellaneous characteristics] (Conditions applied unless otherwise specified) VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V, VCC1=VCC4=1.5V, VCC2=2.5V, VCC3=3.3V, VD1=2.2V, Ta=25C Parameter BATT_VCC output voltage Input voltage abnormal detection voltage Built-in oscillator circuit frequency response Input frequency Symbol VSVD Condition IOUTB=1mA In Normal and Sleep modes In Deep Sleep mode - fOSH - 0.8 1 1.2 MHz fCLK - 0.8 1 1.2 MHz VBAT Min. 2.65 Typ. VCC2 VBAK 2.80 Max. 2.95 Unit V V V NOTES Use of the S1F81100 under conditions beyond the absolute maximum rating may cause malfunction or permanent damage to it. Although the S1F81100 may temporarily operate as intended, such use can significantly impair the reliability. The characteristics are not guaranteed if the S1F81100 is used outside the recommended operating range. Radiation-resistant design has not been provided for this chip. Although the S1F81100 is inherently short circuit proof, we recommend that you provide an overcurrent protection to enhance application safety. Rev.1.4 EPSON 59 S1F81100 Technical Manual Examples of Main Characteristics (typical values) - Current consumption vs. input voltage (Iexe) (Isleep1) (Isleep2) (Ids) (Istop) VIN (V) VIN (V) (A) (A) VIN (V) VIN (V) (A) VIN (V) 60 EPSON Rev.1.4 S1F81100 Technical Manual Output voltage vs. input voltage (Light-Load mode) (CH-2/CH-3: For 2.5V output) CH2 input stability (LDO) @ sample No.1 3 2.8 2.6 2.4 VCC2 (V) 2.2 2 1.8 1.6 1.4 1.2 1 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VIN (V) (CH-2/CH-3: For 3.3V output) CH3 input stability (LDO) @ sample No.8 4.00 3.80 3.60 3.40 VCC3 (V) 3.20 3.00 2.80 2.60 2.40 2.20 2.00 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VIN (V) Rev.1.4 EPSON 61 S1F81100 Technical Manual (CH-1/CH-4: For 1.1V output) CH4 input stability (LDO) @ sample No.1 2.000 1.800 1.600 1.400 VCC4 (V) 1.200 1.000 0.800 0.600 0.400 0.200 0.000 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VCC3 (V) 62 EPSON Rev.1.4 S1F81100 Technical Manual Examples of Transient Response Characteristics (typical values) - Output voltage rising waveform (CH-1: For 1.1V output) CH1 starting waveform 100mA load Ch1 cycle No cycle Ch1 frequency No cycle - Load fluctuation (CH-1: For 1.1V output) Load response 250mA load --> No load Load response No load --> 300mA load Ch 1 cycle Ch1 cycle Low resolution No cycle Ch 1 frequency Ch1frequency Low resolution No cycle No load No load IL=300mA IL=250mA (CH-2: For 2.5V output) Load response 300mA load --> No load Load response No load --> 300mA No load Rev.1.4 IL=300mA Ch1 frequency Ch1 frequency Insufficient amplitute Low resolution IL=300mA EPSON No load 63 S1F81100 Technical Manual Reference Data (typical values) Conversion efficiency vs. output current (CH-1: Conversion efficiency vs. load current) S1F81100 VCC1 efficiency v.s. Iload 100 VCC1 conversion efficiency [%] 90 80 70 60 50 40 30 at VCC1=0.8V VCC1=0.8V VCC1=1.2V at VCC1=1.2V at VCC1=1.5V VCC1=1.5V at 20 10 0 0 100 200 300 400 500 600 700 Iload [mA] [Measured Condition] VIN=3.6V, VSS=0V, Ta=25C P-ch Power MOS (TP1): SANYO/CPH6315 N-ch Power MOS (TN1): SANYO/CPH6415 Schottky Diode (SD1): SANYO/SBS004 Coil (CL1): SUMIDA/CR43-100 Capacitor (CC1): NEC-TOKIN/ESVB20J107M 64 EPSON Rev.1.4 S1F81100 Technical Manual Conversion efficiency vs. output current (CH-2 and CH-3: Conversion efficiency vs. load current) S1F81100 VCCn efficiency v.s. Iload 100 90 VCCn conversion efficiency [%] 80 70 60 50 40 30 20 at at VCCn=3.3V VCCn=3.3V at VCCn=2.5V VCCn=2.5V at 10 0 0 200 400 600 800 1000 1200 Iload [mA] [Measured Condition] VIN=3.6V, VSS=0V, Ta=25C P-ch Power MOS (TPn): SANYO/CPH6315 N-ch Power MOS (TNn): SANYO/CPH6415 Schottky Diode (SDn): SANYO/SBS004 Coil (CLn): SUMIDA/CR54-100 Capacitor (CCn): NEC-TOKIN/ESVB20J107M Note: n=2,3 Rev.1.4 EPSON 65 S1F81100 Technical Manual 9. PACKAGE <QFP12-48> 90.4 70.1 36 90.4 25 9 0.4 24 70.1 37 INDEX 48 13 1 12 0.18 +0.1 -0.05 0.1 1.40.1 1.7Max. 0.5 0.1250.05 0 10 0.50.2 1 Unit: mm Fig.9.1 QFP12-48 Package 66 EPSON Rev.1.4 S1F81100 Technical Manual <QFN7-48> 7 0.42 +0.18 -0.18 6.75 7 6.75 0.42 +0.18 -0.18 Ma x 0.01 +0.04 -0.01 0.65 +0.15 0.85 +0.15 12 24 0.4 +0.05 -0.1 5 .0 +0 0.2 0.23 +0.07 -0.05 25 2- 12 0. 0. 17 + -0 0.0 .0 6 4 13 36 1 48 37 0.5 Fig.9.2 QFN7-48 Package Rev.1.4 EPSON 67 S1F81100 Technical Manual 10. PAD LAYOUT F8110D0** unit: mm Fig.10.1 Pad Layout 68 EPSON Rev.1.4 S1F81100 Technical Manual Table 10.1 Pad Coordinates (Unit: m) Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Rev.1.4 Pad Name VBAK (DUMMY PAD) BATT_VCC PWR_EN (DUMMY PAD) WUP nRESET nBAT_FLT nVCC_FLT (DUMMY PAD) P00 P01 (DUMMY PAD) SCL SDA (DUMMY PAD) XPOR(N.C.) (DUMMY PAD) P02 P03 VCC2 VIN2 (DUMMY PAD) SW2OH FB2M SW2OL (DUMMY PAD) VSS2 (DUMMY PAD) VCC3 VIN3 (DUMMY PAD) (DUMMY PAD) SW3OH (DUMMY PAD) (DUMMY PAD) FB3M X Y Pad # 1336 587 470 356 238 124 7 -107 -224 -338 -453 -571 -684 -807 -1144 -1289 -1520 1557 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 -1273 -1160 -1042 1324 1211 1071 889 405 263 126 -16 -156 -287 -403 -516 -634 -862 -980 -1093 -1211 -1324 -1557 EPSON Pad Name (DUMMY PAD) (DUMMY PAD) SW3OL (DUMMY PAD) VSS3 VCC1 VIN1 (DUMMY PAD) SW1OH FB1M SW1OL (DUMMY PAD) VSS1 (DUMMY PAD) SSCAP3 SSCAP2 SSCAP1 (DUMMY PAD) (DUMMY PAD) FB4 VCC4 VIN (DUMMY PAD) (DUMMY PAD) (DUMMY PAD) XRST XTEST0 XSDWN (DUMMY PAD) AD_EN TCLK(N.C.) CLKIN (DUMMY PAD) VSS TIREF(N.C.) VREF VD1 X Y -926 -813 -695 -500 -383 -152 -11 127 268 410 550 663 781 894 1012 1128 1243 1520 -1557 -1321 -1203 -1090 -859 -741 -628 -510 -397 -263 -149 -32 82 200 340 486 627 744 858 975 1440 69 S1F81100 Technical Manual 11. TERMINAL EQUIVALENT CIRCUIT S1F81100 I/O Terminal equivalent Circuit [Input] BATT_VCC BATT_VCC (PAD) PWR_EN VCC2 VCC2 VIN VIN (PAD) SCL,CLKIN (PAD) XRST,AD_EN XTEST0,XSDWN Fig.11.1(a) Terminal Equivalent Circuit 70 EPSON Rev.1.4 S1F81100 Technical Manual S1F81100 I/O Terminal equivalent Circuit [Output] BATT_V CC (VCC2) (PAD) S1F81100 I/O Terminal equivalent Circuit [I/O] VCC2 (CTRL) (PAD) P00,P01,SDA VIN (CTRL) (PAD) P02,P03 Fig.11.1(b) Terminal Equivalent Circuit Rev.1.4 EPSON 71 S1F81100 Technical Manual APPENDIX SELECTION OF PWM CONTROLLER'S EXTERNAL COMPONENTS This section provides information regarding the selection of external components for the PWM controller to configure the switching regulators with respect to the CH-1, CH-2 and CH-3 in the S1F81100. Please use the information in this section as a basis of component selection. Note: For details of the specifications of the recommended components listed below, see their documents. Input capacitors (CP01, CP02, CP03) The key selection criteria for the input capacitors is their allowable ripple current values included in their specification values. First, the maximum load current on your application should be determined before selecting a capacitor with an allowable ripple current specification value that is at least equal to or greater than the determined maximum load current. Power MOS transistors (TP1, TP2, TP3, TN1, TN2, TN3) Select Power MOS transistors that have low on-resistance and small gate capacity for both P- and N-channels. Higher on-resistance means greater power loss in the power MOS transistors when the switching regulator in operation, which can impair conversion efficiency. The greater the gate capacity, the higher the charge and discharge power when the switching regulator in operation, which can also impair conversion efficiency. Schottky diodes (SD1, SD2, SD3) Select a Schottky diode that has forward current capability equal to or greater than the maximum load current value on your application or has a low forward voltage. Coils (inductors) (CL1, CL2, CL3) Select a coil with a low dc-resistance and a large rated current. Larger dc-resistance means greater power loss in the inductors when the switching regulator in operation, which can impair conversion efficiency. To prevent the inductors from being saturated, it is required to select a rated current that is far greater than the current value to use. If an inductor saturates, the ripple current increased, which may cause the outputs to become unstable. We, therefore, recommend that you select the rated current approximately twice the load current value on the application. The recommended inductance is 10 H. Regulator output capacitors (CC1, CC2, CC3) For a regulator output capacitor, an aluminum or tantalum capacitor of approximately 100F. Due to the internal circuit configurations, use of a low ESR capacitor may not ensure that the S1F81100 provides normal voltage outputs. We, therefore, recommend that you select a capacitor that has approximately 200 m of ESR. (To solve such output anomalies, an improved component is under development) Examples of Component Selection Type P-ch power MOS transistor N-ch power MOS transistor Schottky diode Inductor Regulator output capacitor 72 Maker SANYO HITACHI SANYO HITACHI HITACHI SANYO TOSHIBA SUMIDA NEC TOKIN EPSON Model Number CPH6315 HAT1043M CPH6415 HAT2053M HRW0702A SBS004 CMS06 CR43-100 CR54-100 CR75-100 ESV20J107M Rev.1.4 International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. HEADQUARTERS EPSON (CHINA) CO., LTD. 150 River Oaks Parkway San Jose, CA 95134, U.S.A. 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Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone: +34-93-544-2490 FAX: +34-93-544-2491 Scotland Design Center Integration House, The Alba Campus Livingston West Lothian, EH54 7EG, SCOTLAND Phone: +44-1506-605040 FAX: +44-1506-605041 IC Marketing Department IC Marketing & Engineering Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5816 FAX: +81-(0)42-587-5624 ED International Marketing Department 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 FAX: +81-(0)42-587-5117 S1F81100 Technical Manual SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.com/ First issue September, 2002 Printed March, 2003 in Japan H A