General Description
The MAX7312 2-wire-interfaced expander provides 16-bit
parallel input/output (I/O) port expansion in SMBus™ and
I2C applications. The MAX7312 consists of input port
registers, output port registers, polarity inversion regis-
ters, configuration registers, a bus timeout register, and
an I2C-compatible serial interface logic, compatible with
SMBus. The system master can invert the MAX7312 input
data by writing to the active-high polarity inversion regis-
ter. The system master can enable or disable bus timeout
by writing to the bus timeout register.
Any of the 16 I/O ports can be configured as an input or
an output. A power-on reset (POR) initializes the 16 I/Os
as inputs. Three address select pins configure the part
to one of 64 slave ID addresses.
The MAX7312 supports hot insertion. All port pins, the
INT output, SDA, SCL, and the slave address inputs
AD0-2 remain high impedance in power-down (Vt= 0V)
up to 6V.
The MAX7312 is available in 24-pin SO, SSOP, TSSOP,
and thin QFN packages and is specified over the -40°C
to +125°C automotive temperature range.
For applications requiring I/Os with integrated 100kΩ
pullup resistors, refer to the MAX7311 data sheet.
Applications
Servers/Blades
RAID Systems
Medical Equipment
Instrumentation and Test Measurement
Networking
Features
♦400kbps I2C-Compatible Serial Interface
♦2V to 5.5V Operation
♦5V Overvoltage Tolerant I/Os
♦Supports Hot Insertion
♦16 I/O Pins that Default to Inputs on Power-Up
♦Open-Drain Interrupt Output (INT)
♦Bus Timeout for Lock-Up-Free Operation
♦Noise Filter on SCL/SDA Inputs
♦64 User-Selectable Slave ID Addresses
♦Low Standby Current (2.9µA typ)
♦Polarity Inversion
♦4mm ✕4mm, 0.8mm Thin QFN Package
♦-40°C to +125°C Operation
MAX7312
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3057; Rev 3; 4/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
SMBus is a trademark of Intel Corp.
I,
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EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE PKG
CODE
MAX7312AWG -40°C to +125°C 24 Wide SO —
MAX7312AAG -40°C to +125°C 24 SSOP —
MAX7312ATG -40°C to +125°C 24 Thin QFN
(4mm x 4mm) T2444-4
MAX7312AUG -40°C to +125°C 24 TSSOP —
TOP VIEW
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
V+
SDA
SCL
AD0I/O0
AD2
AD1
I/O15
I/O14
I/O13
I/O12I/O4
I/O3
I/O2
I/O1
16
15
14
13
9
10
11
12
I/O11
I/O10
I/O9
I/O8GND
I/O7
I/O6
I/O5
TSSOP/SSOP/SO
MAX7312
INT
THIN QFN
MAX7312ATG
19
20
21
22
12 3456
18 17 16 15 14 13
23
24
12
11
10
9
8
7
SCL
V+
SDA
INT
AD2
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
AD0
I/O15
I/O13
I/O12
I/O11
AD1
I/O10
I/O8
I/O9
GND
I/O6
I/O7
I/O14
Pin Configurations
MAX7312
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V+= 2V to 5.5V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at V+= 3.3V, TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+to GND ................................................................-0.3V to +6V
I/O0–I/O15 as Inputs ....................................(GND - 0.3V) to +6V
SCL, SDA, AD0, AD1, AD2, INT...................(GND - 0.3V) to +6V
Maximum V+Current ......................................................+250mA
Maximum GND Current ...................................................-250mA
DC Input Current on I/O0–I/O15 .......................................±20mA
DC Output Current on I/O0–I/O15 ....................................±80mA
Continuous Power Dissipation (TA= +70°C)
24-Pin Wide SO (derate 11.8mW/°C above +70°C) ....941mW
24-Pin SSOP (derate 8.0mW/°C above +70°C) ...........640mW
24-Pin TSSOP (derate 12.2mW/°C above +70°C) .......975mW
24-Pin Thin QFN (derate 20.8mW/°C above +70°C) .1668mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
Supply Voltage V+2 5.5 V
V+ = 2V 23 35
V+ = 3.3V 43 60Supply Current I+All I/Os unloaded,
fSCL = 400kHz
V+ = 5.5V 80 120
µA
V+ = 2V 2.3 11
V+ = 3.3V 2.9 12Standby Current ISTBY All I/Os unloaded,
fSCL = 0
V+ = 5.5V 3.8 15.5
µA
Power-On Reset Voltage VPOR 1.4 1.7 V
SCL, SDA
Input Voltage Low VIL 0.3 x V+V
Input Voltage High VIH 0.7 x V+V
Low-Level Output Voltage VOL ISINK = 6mA 0.4 V
Leakage Current IL-1 +1 µA
Input Capacitance 10 pF
I/O_
Input Voltage Low VIL 0.8 V
Input Voltage High VIH 1.8 V
Input Leakage Current TA = -40°C to +85°C -1 +1 µA
V+ = 2V, VOL = 0.5V 8.5 17
V+ = 3.3V, VOL = 0.5V 17 32
Low-Level Output Current ISINK
V+ = 5V, VOL = 0.5V 43
mA
V+ = 3.3V, VOH = 2.4V 29 41
High Output Current ISOURCE V+ = 5V, VOH = 4.5V 31 mA
AD0, AD1, AD2
Input Voltage Low VIL 0.3 x V+V
Input Voltage High VIH 0.7 x V+V
MAX7312
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
_______________________________________________________________________________________ 3
Note 1: All parameters are 100% production tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2: Minimum SCL clock frequency is limited by the MAX7312 bus timeout feature, which resets the serial bus interface if either
SDA or SCL is held low for a minimum of 25ms. Disable bus timeout feature for DC operation.
Note 3: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL
signal) in order to bridge the undefined region SCL’s falling edge.
Note 4: CB= total capacitance of one bus line in pF.
Note 5: The maximum tFfor the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tFis
specified at 250ns. This allows series protection resistors to be connected between the SDA and SCL pins and the
SDA/SCL bus lines without exceeding the maximum specified tF.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
DC ELECTRICAL CHARACTERISTICS (continued)
(V+= 2V to 5.5V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at V+= 3.3V, TA= +25°C.) (Note 1)
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
Leakage Current -1 +1 µA
Input Capacitance 4pF
INT
Low-Level Output Current IOL VOL = 0.4V 6 mA
AC ELECTRICAL CHARACTERISTICS
(V+= 2V to 5.5V, TA= -40°C to +125°C, unless otherwise noted.) (Note 1)
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency fSCL (Note 2) 400 kHz
Bus Timeout tTIMEOUT 29 61 ms
Bus Free Time Between STOP
and START Conditions tBUF Figure 2 1.3 µs
Hold Time (Repeated) START
Condition tHD
,
STA Figure 2 0.6 µs
Repeated START Condition
Setup Time tSU,STA Figure 2 0.6 µs
STOP Condition Setup Time tSU
,
STO Figure 2 0.6 µs
Data Hold Time tHD
,
DAT Figure 2 (Note 3) 0.9 µs
Data Setup Time tSU
,
DAT Figure 2 100 ns
SCL Low Period tLOW Figure 2 1.3 µs
SCL High Period tHIGH Figure 2 0.7 µs
V+ < 3.3V 500
SDA Fall Time tFFigure 2 (Notes 4, 5) V+ ≥ 3.3V 250 ns
Pulse Width of Spike Suppressed tSP (Note 6) 50 ns
PORT TIMING
Output Data Valid tPV Figure 7 3 µs
Input Data Setup Time 27 µs
Input Data Hold Time 0µs
INTERRUPT TIMING
Interrupt Valid tIV Figure 9 30.5 µs
Interrupt Reset tIR Figure 9 2 µs
MAX7312
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
4 _______________________________________________________________________________________
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
MAX7312 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
1007525 500-25
10
20
30
40
50
60
70
80
90
100
0
-50 125
fSCL = 400kHz
ALL I/Os UNLOADED
V+ = 3.3V
V+ = 5V
V+ = 2V
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
MAX7312 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
1007525 500-25
1
2
3
4
5
6
7
8
9
0
-50 125
SCL = V+
ALL I/Os UNLOADED
V+ = 3.3V
V+ = 5V
V+ = 2V
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX7312 toc03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (μA)
5.04.53.5 4.03.02.5
10
20
30
40
50
60
70
80
90
100
0
2.0 5.5
fSCL = 400kHz
ALL I/Os UNLOADED
I/O SINK CURRENT
vs. OUTPUT LOW VOLTAGE
MAX7312 toc04
VOL (V)
ISINK (mA)
0.50.40.30.20.1
2
4
6
8
10
12
14
16
18
20
22
24
0
00.6
V+ = 2V
TA = +125°C
TA = +25°C
TA = -40°C
I/O SINK CURRENT
vs. OUTPUT LOW VOLTAGE
MAX7312 toc05
VOL (V)
ISINK (mA)
0.50.40.30.20.1
5
10
15
20
25
30
35
40
45
50
0
0 0.6
V+ = 3.3V
TA = +125°C
TA = -40°C
TA = +25°C
I/O SINK CURRENT
vs. OUTPUT LOW VOLTAGE
MAX7312 toc06
VOL (V)
ISINK (mA)
0.40.30.20.1
5
10
15
20
25
30
35
40
45
50
0
00.5
V+ = 5V
TA = +125°C
TA = -40°C
TA = +25°C
I/O OUTPUT LOW VOLTAGE
vs. TEMPERATURE
MAX7312 toc07
TEMPERATURE (°C)
VOL (mV)
10075-25 025 50
50
100
150
200
250
300
350
400
0
-50 125
V+ = 5V, ISINK = 10mA
V+ = 2V, ISINK = 10mA
V+ = 2V, ISINK = 1mA V+ = 5V, ISINK = 1mA
I/O SOURCE CURRENT
vs. OUTPUT HIGH VOLTAGE
MAX7312 toc08
V+ - VOH (V)
ISOURCE (mA)
0.60.50.40.30.20.1
5
10
15
20
25
0
0 0.7
V+ = 2V
TA = +125°C
TA = +25°C
TA = -40°C
I/O SOURCE CURRENT
vs. OUTPUT HIGH VOLTAGE
MAX7312 toc09
V+ - VOH (V)
ISOURCE (mA)
0.60.50.3 0.40.20.1
5
10
15
20
25
30
35
40
45
50
0
00.7
V+ = 3.3V
TA = +125°C
TA = +25°C
TA = -40°C
MAX7312
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
_______________________________________________________________________________________ 5
Pin Description
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
I/O SOURCE CURRENT
vs. OUTPUT HIGH VOLTAGE
MAX7312 toc10
V+ - VOH (V)
ISOURCE (mA)
0.60.50.3 0.40.20.1
5
10
15
20
25
30
35
40
45
50
0
0
V+ = 5V
TA = +125°C
TA = +25°C
TA = -40°C
I/O HIGH VOLTAGE vs. TEMPERATURE
MAX7312 toc11
TEMPERATURE (°C)
V+ - VOH (V)
1007550250-25
100
200
300
400
500
0
-50 125
V+ = 5V, ISOURCE = 10mA
V+ = 2V, ISOURCE = 10mA
PIN
TSSOP/
SSOP/SO
THIN
QFN
NAME FUNCTION
122INT Interrupt Output (Open Drain)
2 23 AD1 Address Input 1
3 24 AD2 Address Input 2
4–11 1–8 I/O0–I/O7 Input/Output Port 1
12 9 GND Supply Ground
13–20 10–17 I/O8–I/O15 Input/Output Port 2
21 18 AD0 Address Input 0
22 19 SCL Serial Clock Line
23 20 SDA Serial Data Line
24 21 V+Supply Voltage. Bypass with a 0.047µF capacitor to GND.
— PAD Exposed
pad Exposed Pad on Package Underside. Connect to GND.
MAX7312
Detailed Description
The MAX7312 general-purpose input/output (GPIO)
peripheral provides up to 16 I/O ports, controlled
through an I2C-compatible serial interface. The
MAX7312 consists of input port registers, output port
registers, polarity inversion registers, configuration reg-
isters, and a bus-timeout register. Upon power-on, all
I/O lines are set as inputs. Three slave ID address select
pins, AD0, AD1, and AD2, choose one of 64 slave ID
addresses, including the eight addresses supported by
the Phillips PCA9555. Table 1 is the register address
table. Tables 2–6 show detailed register information.
Serial Interface
Serial Addressing
The MAX7312 operates as a slave that sends and
receives data through a 2-wire interface. The interface
uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master, typically a microcon-
troller, initiates all data transfers to and from the
MAX7312, and generates the SCL clock that synchro-
nizes the data transfer (Figure 2).
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
6 _______________________________________________________________________________________
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
INPUT/OUTPUT
PORT 1
SMBus
CONTROL
8 BIT
READ PULSE
WRITE PULSE
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
INPUT/OUTPUT
PORT 2
8 BIT
READ PULSE
WRITE PULSE
INT
POWER-ON
RESET
INPUT
FILTER
N
V+
SDA
SCL
AD2
AD1
AD0
GND
MAX7312
Figure 1. MAX7312 Block Diagram
SCL
SDA
START CONDITIONSTOP CONDITION
REPEATED START CONDITION
START CONDITION
tSU, DAT
tHD, DAT
tLOW
tHD, STA
tHIGH
tRtF
tSU, STA
tHD, STA
tSU, STO
tBUF
Figure 2. 2-Wire Serial Interface Timing Diagram
Each transmission consists of a START condition sent by
a master, followed by the MAX7312 7-bit slave address
plus R/Wbit, a register address byte, 1 or more data
bytes, and finally a STOP condition (Figure 3).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit, which the
recipient uses as a handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX7312, the
MAX7312
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
_______________________________________________________________________________________ 7
SDA
SCL S
START
CONDITION
P
STOP
CONDITION
Figure 3. START and STOP Conditions
SDA
SCL
DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED
Figure 4. Bit Transfer
SCL
SDA
BY TRANSMITTER
CLOCK PULSE FOR ACKNOWLEDGMENT
START CONDITION
SDA
BY RECEIVER
12 89
S
Figure 5. Acknowledge
MAX7312
MAX7312 generates the acknowledge bit since the
MAX7312 is the recipient. When the MAX7312 is trans-
mitting to the master, the master generates the
acknowledge bit.
Slave Address
The MAX7312 has a 7-bit-long slave address (Figure 6).
The 8th bit following the 7-bit slave address is the R/W
bit. Set this bit low for a write command and high for a
read command.
Slave address pins AD2, AD1, and AD0 choose 1 of 64
slave ID addresses (Table 7).
Data Bus Transaction
The command byte is the first byte to follow the 8-bit
device slave address during a write transmission
(Table 1, Figure 7). The command byte is used to deter-
mine which of the following registers are written or read.
Writing to Port Registers
Transmit data to the MAX7312 by sending the device
slave address and setting the LSB to a logic zero. The
command byte is sent after the address and deter-
mines which registers receive the data following the
command byte (Figure 7).
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
8 _______________________________________________________________________________________
SDA
SDA
A6 A5 A4 A3 A2 A1 A0
MSB LSB
ACKR/W
PROGRAMMABLE
Figure 6. Slave Address
COMMAND BYTE
ADDRESS (HEX) FUNCTION PROTOCOL POWER-UP
DEFAULT
0x00 Input port 1 Read byte XXXX XXXX
0x01 Input port 2 Read byte XXXX XXXX
0x02 Output port 1 Read/write byte 1111 1111
0x03 Output port 2 Read/write byte 1111 1111
0x04 Port 1 polarity inversion Read/write byte 0000 0000
0x05 Port 2 polarity inversion Read/write byte 0000 0000
0x06 Port 1 configuration Read/write byte 1111 1111
0x07 Port 2 configuration Read/write byte 1111 1111
0x08 Timeout register Read/write byte 0000 0001
0xFF Factory reserved. (Do not write to this register.) — —
Table 1. Command Byte Register
123456789
SCL
SDA S A0000001 76543210A76543210A0A
SLAVE ADDRESS
COMMAND BYTE PORT 1 DATA PORT 2 DATA
R/W ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
START
CONDITION
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
tPV
tPV
WRITE TO PORT
DATA OUT PORT 1
READ FROM PORT 2
Figure 7. Writes to Output Registers Through Write Byte Protocol
Eight of the MAX7312’s nine registers are configured to
operate as four register pairs: input ports, output ports,
polarity inversion ports, and configuration ports. After
sending 1 byte of data to one register, the next byte is
sent to the other register in the pair. For example, if the
first byte of data is sent to output port 2, then the next
byte of data is stored in output port 1. An unlimited
number of data bytes can be sent in one write transmis-
sion. This allows each 8-bit register to be updated inde-
pendently of the other registers.
Reading Port Registers
To read the device data, the bus master must first send
the MAX7312 address with the R/Wbit set to zero, fol-
lowed by the command byte, which determines which
register is accessed. After a restart, the bus master
must then send the MAX7312 address with the R/Wbit
set to 1. Data from the register defined by the com-
mand byte is then sent from the MAX7312 to the master
(Figures 8, 9).
MAX7312
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
_______________________________________________________________________________________ 9
S 0 A A S 1 A A NA P
SLAVE ADDRESS SLAVE ADDRESS MSB DATA LSB MSB DATA LSBCOMMAND BYTE
R/W R/W
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
MASTER TRANSMITTER BECOMES
MASTER RECEIVER AND SLAVE
RECEIVER BECOMES SLAVE TRANSMITTER
DATA FROM LOWER OR
UPPER BYTE OF REGISTER
DATA FROM LOWER OR
UPPER BYTE OF REGISTER
TRANSFER OF DATA CAN BE STOPPED AT ANY TIME BY A STOP CONDITION.
Figure 8. Read from Register
123456789
SCL
SLAVE ADDRESS PORT 1 DATA PORT 2 DATA PORT 1 DATA PORT 2 DATAS1777700001PA A A A
R/W
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE
FROM MASTER NONACKNOWLEDGE
FROM MASTER
tIV tIR
READ FROM PORT 1
READ FROM PORT 2
DATA INTO PORT 1
DATA INTO PORT 2
INT
TRANSFER OF DATA CAN BE STOPPED ANYTIME BY A STOP CONDITION. WHEN THE
STOP CONDITION OCCURS, DATA PRESENT AT THE LAST ACKNOWLEDGE PHASE IS
VALID (OUTPUT MODE) AND COMMAND BYTE HAS PREVIOUSLY BEEN SET TO REGISTER 00.
Figure 9. Read from Input Registers
MAX7312
Data is clocked into a register on the falling edge of the
acknowledge clock pulse. After reading the first byte,
additional bytes may be read and reflect the content in
the other register in the pair. For example, if input port 1
is read, the next byte read is input port 2. An unlimited
number of data bytes can be read in one read trans-
mission, but the final byte received must not be
acknowledged by the bus master.
Interrupt (
INT
)
The open-drain interrupt output, INT, activates when
one of the port pins changes states and only when the
pin is configured as an input. The interrupt deactivates
when the input returns to its previous state or the input
register is read (Figure 9). A pin configured as an out-
put does not cause an interrupt. Each 8-bit port register
is read independently; therefore, an interrupt caused
by port 1 is not cleared by a read of port 2’s register.
Changing an I/O from an output to an input may cause
a false interrupt to occur if the state of that I/O does not
match the content of the input port register.
Input/Output Port
When an I/O is configured as an input, FETs Q1 and Q2
are off (Figure 10), creating a high-impedance input. All
inputs are overvoltage protected to 5.5V, independent
of supply voltage. When a port is configured as an out-
put, either Q1 or Q2 is on, depending on the state of the
output port register. When V+powers up, an internal
power-on reset sets all registers to their respective
defaults (Table 1).
Input Port Registers
The input port registers (Table 2) are read-only ports.
They reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or
an output by the respective configuration register. A
read of the input port 1 register latches the current
value of I/O0–I/O7. A read of the input port 2 register
latches the current value of I/O8–I/O15. Writes to the
input port registers are ignored.
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
10 ______________________________________________________________________________________
DSET Q
CLR
Q
DSET Q
CLR
Q
DATA FROM
SHIFT REGISTER
WRITE
CONFIGURATION
PULSE
DATA FROM
SHIFT REGISTER
WRITE PULSE
READ PULSE
OUTPUT PORT
REGISTER
DSET Q
CLR
Q
POLARITY INVERSION
REGISTER
POLARITY
REGISTER
DATA
DSET Q
CLR
Q
INPUT PORT
REGISTER
CONFIGURATION
REGISTER
Q1
Q2
DATA FROM
SHIFT REGISTER
WRITE POLARITY
PULSE
POWER-ON
RESET
TO INT
INPUT PORT
REGISTER DATA
VSS
VDD
I/O PIN
OUTPUT PORT
REGISTER DATA
Figure 10. Simplified Schematic of I/Os
Output Port Registers
The output port registers (Table 3) set the outgoing
logic levels of the I/Os defined as outputs by the
respective configuration register. Reads from the out-
put port registers reflect the value that is in the flip-flop
controlling the output selection, not the actual I/O value.
Polarity Inversion Registers
The polarity inversion registers (Table 4) enable polarity
inversion of pins defined as inputs by the respective
port configuration registers. Set the bit in the polarity
inversion register to invert the corresponding port pin’s
polarity. Clear the bit in the polarity inversion register to
retain the corresponding port pin’s original polarity.
Configuration Registers
The configuration registers (Table 5) configure the
directions of the I/O pins. Set the bit in the respective
configuration register to enable the corresponding port
as an input. Clear the bit in the configuration register to
enable the corresponding port as an output.
Bus Timeout
Set register 0x08 LSB (bit 0) to enable the bus timeout
function (Table 6) or clear it to disable the bus timeout
function. Enabling the timeout feature resets the
MAX7312 serial bus interface when SCL stops either high
or low during a read or write. If either SCL or SDA is low
for more than 29ms after the start of a valid serial transfer,
the interface resets itself and sets up SDA as an input.
The MAX7312 then waits for another START condition.
Standby
The MAX7312 goes into standby when the I2C bus is
idle. Standby supply current is typically 2.9µA.
Applications Information
Hot Insertion
The I/O ports I/O0–I/O15 interrupt output INT, and serial
interfaces SDA, SCL, AD0-2 remain high impedance
with up to 6V asserted on them when the MAX7312 is
powered down (V+ = 0V). The MAX7312 can therefore
be used in hot-swap applications.
Power-Supply Consideration
The MAX7312 operates from a supply voltage of 2V to
5.5V. Bypass the power supply to GND with a 0.047µF
capacitor as close to the device as possible. For the QFN
version, connect the underside exposed pad to GND.
MAX7312
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
______________________________________________________________________________________ 11
I7 I6 I5 I4 I3 I2 I1 I0
BIT I15 I14 I13 I12 I11 I10 I9 I8
Table 2. Registers 0x00, 0x01—Input Port Registers
O7 O6 O5 O4 O3 O2 O1 O0
BIT O15 O14 O13 O12 O11 O10 O9 O8
Power-up default 1 1111111
Table 3. Registers 0x02, 0x03—Output Port Registers
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
BIT I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8
Power-up default 0 0000000
Table 4. Registers 0x04, 0x05—Polarity Inversion Registers
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
BIT I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8
Power-up default 1 1 1 1 1 1 1 1
Table 5. Registers 0x06, 0x07—Configuration Registers
BIT 76543210
Power-up default 00000001
Table 6. Register 0x08—Timeout Register
MAX7312
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
12 ______________________________________________________________________________________
AD2 AD1 AD0 A6 A5 A4 A3 A2 A1 A0 ADDRESS (HEX)
GNDSCLGND0010000 0x20
GND SCL V+0010001 0x22
GNDSDAGND0010010 0x24
GND SDA V+0010011 0x26
V+SCLGND0010100 0x28
V+SCL V+0010101 0x2A
V+SDAGND0010110 0x2C
V+SDA V+0010111 0x2E
GNDSCLSCL0011000 0x30
GNDSCLSDA0011001 0x32
GNDSDASCL0011010 0x34
GNDSDASDA0011011 0x36
V+SCLSCL0011100 0x38
V+SCLSDA0011101 0x3A
V+SDASCL0011110 0x3C
V+SDASDA0011111 0x3E
GNDGNDGND0100000 0x40
GND GND V+0100001 0x42
GND V+GND0100010 0x44
GND V+V+0100011 0x46
V+GNDGND0100100 0x48
V+GND V+0100101 0x4A
V+V+GND0100110 0x4C
V+V+V+0100111 0x4E
GNDGNDSCL0101000 0x50
GNDGNDSDA0101001 0x52
GND V+SCL0101010 0x54
GND V+SDA0101011 0x56
V+GNDSCL0101100 0x58
V+GNDSDA0101101 0x5A
V+V+SCL0101110 0x5C
V+V+SDA0101111 0x5E
Table 7. MAX7312 Address Map
MAX7312
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
______________________________________________________________________________________ 13
AD2 AD1 AD0 A6 A5 A4 A3 A2 A1 A0 ADDRESS (HEX)
SCLSCLGND1010000 0xA0
SCL SCL V+1010001 0xA2
SCLSDAGND1010010 0xA4
SCL SDA V+1010011 0xA6
SDASCLGND1010100 0xA8
SDA SCL V+1010101 0xAA
SDASDAGND1010110 0xAC
SDA SDA V+1010111 0xAE
SCLSCLSCL1011000 0xB0
SCLSCLSDA1011001 0xB2
SCLSDASCL1011010 0xB4
SCLSDASDA1011011 0xB6
SDASCLSCL1011100 0xB8
SDASCLSDA1011101 0xBA
SDASDASCL1011110 0xBC
SDASDASDA1011111 0xBE
SCLGNDGND1100000 0xC0
SCL GND V+1100001 0xC2
SCL V+GND1100010 0xC4
SCL V+V+1100011 0xC6
SDAGNDGND1100100 0xC8
SDA GND V+1100101 0xCA
SDA V+GND1100110 0xCC
SDA V+V+1100111 0xCE
SCLGNDSCL1101000 0xD0
SCLGNDSDA1101001 0xD2
SCL V+SCL1101010 0xD4
SCL V+SDA1101011 0xD6
SDAGNDSCL1101100 0xD8
SDAGNDSDA1101101 0xDA
SDA V+SCL1101110 0xDC
SDA V+SDA1101111 0xDE
Table 7. MAX7312 Address Map (continued)
Chip Information
TRANSISTOR COUNT: 12,994
PROCESS: BiCMOS
MAX7312
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
14 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
SOICW.EPS
PACKAGE OUTLINE, .300" SOIC
1
1
21-0042 B
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
TOP VIEW
FRONT VIEW
MAX
0.012
0.104
0.019
0.299
0.013
INCHES
0.291
0.009
E
C
DIM
0.014
0.004
B
A1
MIN
0.093A
0.23
7.40 7.60
0.32
MILLIMETERS
0.10
0.35
2.35
MIN
0.49
0.30
MAX
2.65
0.050
0.016L0.40 1.27
0.5120.496D
D
MINDIM
D
INCHES
MAX
12.60 13.00
MILLIMETERS
MIN MAX
20 AC
0.447 0.463 AB11.7511.35 18
0.398 0.413 AA10.5010.10 16
N MS013
SIDE VIEW
H 0.4190.394 10.00 10.65
e 0.050 1.27
D 0.6140.598 15.20 2415.60 AD
D 0.7130.697 17.70 2818.10 AE
H
E
N
D
A1
B
e
A
0∞-8∞
C
L
1
VARIATIONS:
MAX7312
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
______________________________________________________________________________________ 15
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
SSOP.EPS
PACKAGE OUTLINE, SSOP, 5.3 MM
1
1
21-0056 C
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
7.90
H
L
0∞
0.301
0.025
8∞
0.311
0.037
0∞
7.65
0.63
8∞
0.95
MAX
5.38
MILLIMETERS
B
C
D
E
e
A1
DIM
A
SEE VARIATIONS
0.0256 BSC
0.010
0.004
0.205
0.002
0.015
0.008
0.212
0.008
INCHES
MIN MAX
0.078
0.65 BSC
0.25
0.09
5.20
0.05
0.38
0.20
0.21
MIN
1.73 1.99
MILLIMETERS
6.07
6.07
10.07
8.07
7.07
INCHES
D
D
D
D
D
0.239
0.239
0.397
0.317
0.278
MIN
0.249
0.249
0.407
0.328
0.289
MAX MIN
6.33
6.33
10.33
8.33
7.33
14L
16L
28L
24L
20L
MAX N
A
D
eA1 L
C
HE
N
12
B
0.068
TSSOP4.40mm.EPS
PACKAGE OUTLINE, TSSOP 4.40mm BODY
21-0066
1
1
I
MAX7312
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 16
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
