1N4735A-T50R - ON SEMICONDUCTOR

EFM32 Tiny Gecko Series 1 Family

EFM32TG11 Family Data Sheet

The EFM32 Tiny Gecko Series 1 MCUs are the world’s most

energy-friendly microcontrollers, featuring new connectivity interfa-

ces and rich analog features.

EFM32TG11 includes a powerful and efficient 32-bit ARM® Cortex®-M0+ and provides

robust security via a unique cryptographic hardware engine supporting AES, ECC, SHA,

and True Random Number Generator (TRNG). New features include a CAN bus control-

ler, highly robust capacitive sensing, and LESENSE/PCNT enhancements for smart en-

ergy meters. These features, combined with ultra-low current active mode and short

wake-up time from energy-saving modes, make EFM32TG11 microcontrollers well suited

for any battery-powered application, as well as other systems requiring high performance

and low-energy consumption.

Example applications:

ENERGY FRIENDLY FEATURES

• ARM Cortex-M0+ at 48 MHz

• Ultra low energy operation:

• 37 µA/MHz in Energy Mode 0 (EM0)

• 1.30 µA EM2 Deep Sleep current

• CAN 2.0 Bus Controller

• Low energy analog peripherals: ADC,

DAC, OPAMP, Comparator, Segment

LCD

• Hardware cryptographic engine supports

AES, ECC, SHA, and TRNG

• Robust capacitive touch sense

• Footprint compatible with select EFM32

packages

• 5 V tolerant I/O

• Smart energy meters

• Industrial and factory automation

• Home automation and security

• Entry-level wearables

• Personal medical devices

• IoT devices

32-bit bus

Lowest power mode with peripheral operational:

EM2 – Deep Sleep

EM1 - Sleep EM4H - Hibernate EM4S - Shutoff

EM0 - Active EM3 - Stop

Core / Memory

Flash Program

Memory

RAM Memory

ARM CortexTM M0+ processor with

MPU

Debug Interface

w/ MTB

LDMA

Controller

Energy Management

Brown-Out

Detector

DC-DC

Converter

Voltage

Regulator

Voltage/Temp

Monitor

Power-On Reset

Clock Management

High Frequency

RC Oscillator

Ultra Low Freq.

RC Oscillator

Low Frequency

Crystal Oscillator

Low Frequency

RC Oscillator

Auxiliary High

Freq. RC Osc.

High Frequency

Crystal Oscillator

PLL

Analog Interfaces

Low Energy LCD

Controller

Operational

Amplifier

ADC

VDAC

Analog

Comparator

Capacitive

Sensing

Backup Domain

Peripheral Reflex System

Serial Interfaces

UART

I2C

I/O Ports Timers and Triggers

Low Energy

Sensor IF

Timer/Counter

Low Energy Timer

Watchdog Timer

CRYOTIMER

External

Interrupts

Pin Reset

General

Purpose I/O

Pin Wakeup Real Time Counter

and Calendar

Pulse Counter

USART

Low Energy

UARTTM

CAN

Other

CRYPTO

CRC

True Random

Number Generator

SMU

silabs.com | Building a more connected world. Preliminary Rev. 0.5

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

1. Feature List

The EFM32TG11 highlighted features are listed below.

•ARM Cortex-M0+ CPU platform

• High performance 32-bit processor @ up to 48 MHz

• Memory Protection Unit

• Wake-up Interrupt Controller

•Flexible Energy Management System

• 37 μA/MHz in Active Mode (EM0)

• 1.30 μA EM2 Deep Sleep current (8 kB RAM retention and

RTCC running from LFRCO)

•Integrated DC-DC buck converter

•Backup Power Domain

• RTCC and retention registers in a separate power domain,

available in all energy modes

• Operation from backup battery when main power absent/

insufficient

•Up to 128 kB flash program memory

•Up to 32 kB RAM data memory

•Communication Interfaces

• CAN Bus Controller

• Version 2.0A and 2.0B up to 1 Mbps

• 4 × Universal Synchronous/Asynchronous Receiver/ Trans-

mitter

• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S/LIN

• Triple buffered full/half-duplex operation with flow control

• Ultra high speed (24 MHz) operation on one instance

• 1 × Universal Asynchronous Receiver/ Transmitter

• 1 × Low Energy UART

• Autonomous operation with DMA in Deep Sleep Mode

•2 × I2C Interface with SMBus support

• Address recognition in EM3 Stop Mode

•Up to 67 General Purpose I/O Pins

• Configurable push-pull, open-drain, pull-up/down, input fil-

ter, drive strength

• Configurable peripheral I/O locations

• 5 V tolerance on select pins

• Asynchronous external interrupts

• Output state retention and wake-up from Shutoff Mode

•Up to 8 Channel DMA Controller

•Up to 8 Channel Peripheral Reflex System (PRS) for auton-

omous inter-peripheral signaling

•Hardware Cryptography

• AES 128/256-bit keys

• ECC B/K163, B/K233, P192, P224, P256

• SHA-1 and SHA-2 (SHA-224 and SHA-256)

• True Random Number Generator (TRNG)

•Hardware CRC engine

• Single-cycle computation with 8/16/32-bit data and 16-bit

(programmable)/32-bit (fixed) polynomial

•Security Management Unit (SMU)

• Fine-grained access control for on-chip peripherals

•Integrated Low-energy LCD Controller with up to 8 × 32

segments

• Voltage boost, contrast and autonomous animation

• Patented low-energy LCD driver

•Ultra Low-Power Precision Analog Peripherals

• 12-bit 1 Msamples/s Analog to Digital Converter (ADC)

• On-chip temperature sensor

• 2 × 12-bit 500 ksamples/s Digital to Analog Converter

(VDAC)

• Up to 2 × Analog Comparator (ACMP)

• Up to 4 × Operational Amplifier (OPAMP)

• Robust current-based capacitive sensing with up to 38 in-

puts and wake-on-touch (CSEN)

• Up to 62 GPIO pins are analog-capable. Flexible analog pe-

ripheral-to-pin routing via Analog Port (APORT)

• Supply Voltage Monitor

EFM32TG11 Family Data Sheet

Feature List

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 2

•Timers/Counters

• 2 × 16-bit Timer/Counter

• 3 or 4 Compare/Capture/PWM channels (4 + 4 on one

timer instance)

• Dead-Time Insertion on one timer instance

• 2 × 32-bit Timer/Counter

• 32-bit Real Time Counter and Calendar (RTCC)

• 32-bit Ultra Low Energy CRYOTIMER for periodic wakeup

from any Energy Mode

• 16-bit Low Energy Timer for waveform generation

• 16-bit Pulse Counter with asynchronous operation

• Watchdog Timer with dedicated RC oscillator

•Low Energy Sensor Interface (LESENSE)

• Autonomous sensor monitoring in Deep Sleep Mode

• Wide range of sensors supported, including LC sensors and

capacitive buttons

• Up to 16 inputs

•Ultra efficient Power-on Reset and Brown-Out Detector

•Debug Interface

• 2-pin Serial Wire Debug interface

• 4-pin JTAG interface

• Micro Trace Buffer (MTB)

•Pre-Programmed UART Bootloader

•Wide Operating Range

• 1.8 V to 3.8 V single power supply

• Integrated DC-DC, down to 1.8 V output with up to 200 mA

load current for system

• Standard (-40 °C to 85 °C TA) and Extended (-40 °C to 125

°C TJ) temperature grades available

•Packages

• QFN32 (5x5 mm)

• TQFP48 (7x7 mm)

• QFN64 (9x9 mm)

• TQFP64 (10x10 mm)

• QFN80 (9x9 mm)

• TQFP80 (12x12 mm)

EFM32TG11 Family Data Sheet

Feature List

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 3

2. Ordering Information

Table 2.1. Ordering Information

Ordering Code

Flash

(kB)

RAM

(kB)

DC-DC

Con-

verter LCD GPIO Package Temp Range

EFM32TG11B520F128GM80-A 128 32 Yes Yes 67 QFN80 -40 to +85°C

EFM32TG11B520F128GQ80-A 128 32 Yes Yes 63 QFP80 -40 to +85°C

EFM32TG11B520F128IM80-A 128 32 Yes Yes 67 QFN80 -40 to +125°C

EFM32TG11B520F128IQ80-A 128 32 Yes Yes 63 QFP80 -40 to +125°C

EFM32TG11B540F64GM80-A 64 32 Yes Yes 67 QFN80 -40 to +85°C

EFM32TG11B540F64GQ80-A 64 32 Yes Yes 63 QFP80 -40 to +85°C

EFM32TG11B540F64IM80-A 64 32 Yes Yes 67 QFN80 -40 to +125°C

EFM32TG11B540F64IQ80-A 64 32 Yes Yes 63 QFP80 -40 to +125°C

EFM32TG11B520F128GM64-A 128 32 Yes Yes 53 QFN64 -40 to +85°C

EFM32TG11B520F128GQ64-A 128 32 Yes Yes 50 QFP64 -40 to +85°C

EFM32TG11B520F128IM64-A 128 32 Yes Yes 53 QFN64 -40 to +125°C

EFM32TG11B520F128IQ64-A 128 32 Yes Yes 50 QFP64 -40 to +125°C

EFM32TG11B540F64GM64-A 64 32 Yes Yes 53 QFN64 -40 to +85°C

EFM32TG11B540F64GQ64-A 64 32 Yes Yes 50 QFP64 -40 to +85°C

EFM32TG11B540F64IM64-A 64 32 Yes Yes 53 QFN64 -40 to +125°C

EFM32TG11B540F64IQ64-A 64 32 Yes Yes 50 QFP64 -40 to +125°C

EFM32TG11B520F128GQ48-A 128 32 Yes Yes 34 QFP48 -40 to +85°C

EFM32TG11B520F128IQ48-A 128 32 Yes Yes 34 QFP48 -40 to +125°C

EFM32TG11B540F64GQ48-A 64 32 Yes Yes 34 QFP48 -40 to +85°C

EFM32TG11B540F64IQ48-A 64 32 Yes Yes 34 QFP48 -40 to +125°C

EFM32TG11B520F128GM32-A 128 32 Yes Yes 22 QFN32 -40 to +85°C

EFM32TG11B520F128IM32-A 128 32 Yes Yes 22 QFN32 -40 to +125°C

EFM32TG11B540F64GM32-A 64 32 Yes Yes 22 QFN32 -40 to +85°C

EFM32TG11B540F64IM32-A 64 32 Yes Yes 22 QFN32 -40 to +125°C

EFM32TG11B320F128GM64-A 128 32 No Yes 56 QFN64 -40 to +85°C

EFM32TG11B320F128GQ64-A 128 32 No Yes 53 QFP64 -40 to +85°C

EFM32TG11B320F128IM64-A 128 32 No Yes 56 QFN64 -40 to +125°C

EFM32TG11B320F128IQ64-A 128 32 No Yes 53 QFP64 -40 to +125°C

EFM32TG11B340F64GM64-A 64 32 No Yes 56 QFN64 -40 to +85°C

EFM32TG11B340F64GQ64-A 64 32 No Yes 53 QFP64 -40 to +85°C

EFM32TG11B340F64IM64-A 64 32 No Yes 56 QFN64 -40 to +125°C

EFM32TG11B340F64IQ64-A 64 32 No Yes 53 QFP64 -40 to +125°C

EFM32TG11 Family Data Sheet

Ordering Information

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 4

Ordering Code

Flash

(kB)

RAM

(kB)

DC-DC

Con-

verter LCD GPIO Package Temp Range

EFM32TG11B320F128GQ48-A 128 32 No Yes 37 QFP48 -40 to +85°C

EFM32TG11B320F128IQ48-A 128 32 No Yes 37 QFP48 -40 to +125°C

EFM32TG11B340F64GQ48-A 64 32 No Yes 37 QFP48 -40 to +85°C

EFM32TG11B340F64IQ48-A 64 32 No Yes 37 QFP48 -40 to +125°C

EFM32TG11B120F128GM64-A 128 32 No No 56 QFN64 -40 to +85°C

EFM32TG11B120F128GQ64-A 128 32 No No 53 QFP64 -40 to +85°C

EFM32TG11B120F128IM64-A 128 32 No No 56 QFN64 -40 to +125°C

EFM32TG11B120F128IQ64-A 128 32 No No 53 QFP64 -40 to +125°C

EFM32TG11B140F64GM64-A 64 32 No No 56 QFN64 -40 to +85°C

EFM32TG11B140F64GQ64-A 64 32 No No 53 QFP64 -40 to +85°C

EFM32TG11B140F64IM64-A 64 32 No No 56 QFN64 -40 to +125°C

EFM32TG11B140F64IQ64-A 64 32 No No 53 QFP64 -40 to +125°C

EFM32TG11B120F128GQ48-A 128 32 No No 37 QFP48 -40 to +85°C

EFM32TG11B120F128IQ48-A 128 32 No No 37 QFP48 -40 to +125°C

EFM32TG11B140F64GQ48-A 64 32 No No 37 QFP48 -40 to +85°C

EFM32TG11B140F64IQ48-A 64 32 No No 37 QFP48 -40 to +125°C

EFM32TG11B120F128GM32-A 128 32 No No 24 QFN32 -40 to +85°C

EFM32TG11B120F128IM32-A 128 32 No No 24 QFN32 -40 to +125°C

EFM32TG11B140F64GM32-A 64 32 No No 24 QFN32 -40 to +85°C

EFM32TG11B140F64IM32-A 64 32 No No 24 QFN32 -40 to +125°C

EFM32TG11 Family Data Sheet

Ordering Information

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 5

EFM32 –

1 B F G R

Tape and Reel (Optional)

Revision

Pin Count

Package – M (QFN), Q (QFP)

Flash Memory Size in kB

Memory Type (Flash)

Feature Set Code

T520 128 M 80

Temperature Grade – G (-40 to +85 °C), I (-40 to +125 °C)

Performance Grade – B (Basic)

Family – T (Tiny)

Series

Energy Friendly Microcontroller 32-bit

Gecko

Device Configuration

Figure 2.1. Ordering Code Key

EFM32TG11 Family Data Sheet

Ordering Information

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 6

Table of Contents

1. Feature List ................................2

2. Ordering Information ............................4

3. System Overview .............................10

3.1 Introduction...............................10

3.2 Power ................................11

3.2.1 Energy Management Unit (EMU) .....................11

3.2.2 DC-DC Converter ..........................11

3.2.3 EM2 and EM3 Power Domains ......................11

3.3 General Purpose Input/Output (GPIO)......................12

3.4 Clocking ................................12

3.4.1 Clock Management Unit (CMU) ......................12

3.4.2 Internal and External Oscillators......................12

3.5 Counters/Timers and PWM .........................12

3.5.1 Timer/Counter (TIMER) ........................12

3.5.2 Wide Timer/Counter (WTIMER) ......................12

3.5.3 Real Time Counter and Calendar (RTCC) ..................12

3.5.4 Low Energy Timer (LETIMER) ......................13

3.5.5 Ultra Low Power Wake-up Timer (CRYOTIMER) ................13

3.5.6 Pulse Counter (PCNT) .........................13

3.5.7 Watchdog Timer (WDOG) ........................13

3.6 Communications and Other Digital Peripherals ...................13

3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) .........13

3.6.2 Universal Asynchronous Receiver/Transmitter (UART) ..............13

3.6.3 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) .........13

3.6.4 Inter-Integrated Circuit Interface (I2C) ....................13

3.6.5 Controller Area Network (CAN) ......................14

3.6.6 Peripheral Reflex System (PRS) .....................14

3.6.7 Low Energy Sensor Interface (LESENSE) ..................14

3.7 Security Features.............................14

3.7.1 GPCRC (General Purpose Cyclic Redundancy Check) ..............14

3.7.2 Crypto Accelerator (CRYPTO) ......................14

3.7.3 True Random Number Generator (TRNG) ..................14

3.7.4 Security Management Unit (SMU) .....................14

3.8 Analog ................................14

3.8.1 Analog Port (APORT) .........................15

3.8.2 Analog Comparator (ACMP) .......................15

3.8.3 Analog to Digital Converter (ADC) .....................15

3.8.4 Capacitive Sense (CSEN) ........................15

3.8.5 Digital to Analog Converter (VDAC) ....................15

3.8.6 Operational Amplifiers .........................15

3.8.7 Liquid Crystal Display Driver (LCD).....................15

3.9 Reset Management Unit (RMU) ........................15

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3.10 Core and Memory ............................16

3.10.1 Processor Core ...........................16

3.10.2 Memory System Controller (MSC) ....................16

3.10.3 Linked Direct Memory Access Controller (LDMA) ...............16

3.10.4 Bootloader ............................16

3.11 Memory Map ..............................17

3.12 Configuration Summary ..........................18

4. Electrical Specifications ..........................19

4.1 Electrical Characteristics ..........................19

4.1.1 Absolute Maximum Ratings .......................19

4.1.2 Operating Conditions .........................20

4.1.3 Thermal Characteristics ........................22

4.1.4 DC-DC Converter ..........................23

4.1.5 Backup Supply Domain ........................25

4.1.6 Current Consumption .........................26

4.1.7 Wake Up Times ...........................33

4.1.8 Brown Out Detector (BOD) .......................34

4.1.9 Oscillators .............................35

4.1.10 Flash Memory Characteristics ......................41

4.1.11 General-Purpose I/O (GPIO) ......................42

4.1.12 Voltage Monitor (VMON) ........................44

4.1.13 Analog to Digital Converter (ADC) ....................45

4.1.14 Analog Comparator (ACMP) ......................47

4.1.15 Digital to Analog Converter (VDAC) ....................50

4.1.16 Capacitive Sense (CSEN) .......................53

4.1.17 Operational Amplifier (OPAMP) .....................55

4.1.18 LCD Driver ............................58

4.1.19 Pulse Counter (PCNT) ........................59

4.1.20 Analog Port (APORT) .........................59

4.1.21 I2C ...............................60

4.1.22 USART SPI ............................63

4.2 Typical Performance Curves .........................64

4.2.1 Supply Current ...........................65

4.2.2 DC-DC Converter ..........................70

5. Pin Definitions ..............................72

5.1 EFM32TG11B5xx in QFP80 Device Pinout ....................72

5.2 EFM32TG11B5xx in QFN80 Device Pinout ....................75

5.3 EFM32TG11B5xx in QFP64 Device Pinout ....................78

5.4 EFM32TG11B3xx in QFP64 Device Pinout ....................80

5.5 EFM32TG11B1xx in QFP64 Device Pinout ....................82

5.6 EFM32TG11B5xx in QFN64 Device Pinout ....................84

5.7 EFM32TG11B3xx in QFN64 Device Pinout ....................86

5.8 EFM32TG11B1xx in QFN64 Device Pinout ....................88

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 8

5.9 EFM32TG11B5xx in QFP48 Device Pinout ....................90

5.10 EFM32TG11B3xx in QFP48 Device Pinout ...................92

5.11 EFM32TG11B1xx in QFP48 Device Pinout ...................94

5.12 EFM32TG11B5xx in QFN32 Device Pinout ...................96

5.13 EFM32TG11B1xx in QFN32 Device Pinout ...................98

5.14 GPIO Functionality Table ........................100

5.15 Alternate Functionality Overview ......................104

5.16 Analog Port (APORT) Client Maps .....................119

6. TQFP80 Package Specifications .......................129

6.1 TQFP80 Package Dimensions .......................129

6.2 TQFP80 PCB Land Pattern ........................131

6.3 TQFP80 Package Marking ........................132

7. QFN80 Package Specifications........................133

7.1 QFN80 Package Dimensions ........................133

7.2 QFN80 PCB Land Pattern .........................135

7.3 QFN80 Package Marking .........................137

8. TQFP64 Package Specifications .......................138

8.1 TQFP64 Package Dimensions .......................138

8.2 TQFP64 PCB Land Pattern ........................140

8.3 TQFP64 Package Marking ........................141

9. QFN64 Package Specifications........................142

9.1 QFN64 Package Dimensions ........................142

9.2 QFN64 PCB Land Pattern .........................144

9.3 QFN64 Package Marking .........................146

10. TQFP48 Package Specifications .......................147

10.1 TQFP48 Package Dimensions .......................147

10.2 TQFP48 PCB Land Pattern ........................149

10.3 TQFP48 Package Marking ........................150

11. QFN32 Package Specifications .......................151

11.1 QFN32 Package Dimensions .......................151

11.2 QFN32 PCB Land Pattern ........................153

11.3 QFN32 Package Marking ........................155

12. Revision History.............................156

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3. System Overview

3.1 Introduction

The Tiny Gecko Series 1 product family is well suited for any battery operated application as well as other systems requiring high per-

formance and low energy consumption. This section gives a short introduction to the MCU system. The detailed functional description

can be found in the Tiny Gecko Series 1 Reference Manual. Any behavior that does not conform to the specifications in this data sheet

or the functional descriptions in the Tiny Gecko Series 1 Reference Manual are detailed in the EFM32TG11 Errata document.

A block diagram of the Tiny Gecko Series 1 family is shown in Figure 3.1 Detailed EFM32TG11 Block Diagram on page 10. The dia-

gram shows a superset of features available on the family, which vary by OPN. For more information about specific device features,

consult Ordering Information.

Analog Peripherals

Clock Management

HFRCO + DPLL

ARM Cortex-M0+ Core

Watchdog

Timer

RESETn

Digital Peripherals

Input Mux

Digital Port Mapper

Port I/O Configuration

Analog Comparator

12-bit ADC

Temp

Sense

VDD

Internal

Reference

AUXHFRCO

LFXO

ULFRCO

HFXO

LFRCO

Analog Port (APORT)

Energy Management

DVDD

VREGVDD

VREGSW

bypass

AVDD

DECOUPLE

IOVDD0

Voltage

Monitor

VDAC

Op-Amp

Capacitive

Touch

Mux & FB

HFXTAL_P

HFXTAL_N

LFXTAL_P

LFXTAL_N

Voltage

Regulator

DC-DC

Converter

Brown Out /

Power-On

Reset

Management

Unit

Debug Signals

(shared w/GPIO)

Serial Wire

Debug /

Programming

IOVDD0

CAN

LESENSE

CRC

CRYPTO

I2C

LEUART

PCNT

CRYOTIMER

LETIMER

Low-Energy LCD, up to 8x32

configuration

BU_VIN

BU_VOUT

BU_STAT

Backup Domain To

GPIO

USART / UART

RTCC

TIMER / WTIMER

Up to 128 KB ISP Flash

Program Memory

Up to 32 KB RAM

Memory Protection Unit

LDMA Controller

Security Management

TRNG

PFn

Port F

Drivers

PEn

Port E

Drivers

PDn

Port D

Drivers

PCn

Port C

Drivers

PBn

Port B

Drivers

PAn

Port A

Drivers

Figure 3.1. Detailed EFM32TG11 Block Diagram

EFM32TG11 Family Data Sheet

System Overview

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 10

3.2 Power

The EFM32TG11 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only

a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator

can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capaci-

tor.

The EFM32TG11 device family includes support for internal supply voltage scaling, as well as two different power domain groups for

peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.

AVDD and VREGVDD need to be 1.8 V or higher for the MCU to operate across all conditions; however the rest of the system will

operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.

Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB

components, supplying up to a total of 200 mA.

3.2.1 Energy Management Unit (EMU)

The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and

features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM

blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multi-

ple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has

fallen below a chosen threshold.

3.2.2 DC-DC Converter

The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2

and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Protection features include programmable

current limiting, short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input

voltage is too low for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a

low resistance switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive out-

put current transients.

3.2.3 EM2 and EM3 Power Domains

The EFM32TG11 has three independent peripheral power domains for use in EM2 and EM3. Two of these domains are dynamic and

can be shut down to save energy. Peripherals associated with the two dynamic power domains are listed in Table 3.1 EM2 and EM3

Peripheral Power Subdomains on page 11. If all of the peripherals in a peripheral power domain are unused, the power domain for

that group will be powered off in EM2 and EM3, reducing the overall current consumption of the device. Other EM2, EM3, and EM4-

capable peripherals and functions not listed in the table below reside on the primary power domain, which is always on in EM2 and

EM3.

Table 3.1. EM2 and EM3 Peripheral Power Subdomains

Peripheral Power Domain 1 Peripheral Power Domain 2

ACMP0 ACMP1

PCNT0 CSEN

ADC0 VDAC0

LETIMER0 LEUART0

LESENSE I2C0

APORT I2C1

- IDAC

- LCD

EFM32TG11 Family Data Sheet

System Overview

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 11

3.3 General Purpose Input/Output (GPIO)

EFM32TG11 has up to 67 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or

input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO

pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to

several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-

als. The GPIO subsystem supports asynchronous external pin interrupts.

3.4 Clocking

3.4.1 Clock Management Unit (CMU)

The Clock Management Unit controls oscillators and clocks in the EFM32TG11. Individual enabling and disabling of clocks to all periph-

eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility

allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and

oscillators.

3.4.2 Internal and External Oscillators

The EFM32TG11 supports two crystal oscillators and fully integrates four RC oscillators, listed below.

• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-

ence for the MCU. Crystal frequencies in the range from 4 to 48 MHz are supported. An external clock source such as a TCXO can

also be applied to the HFXO input for improved accuracy over temperature.

• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.

• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system. The HFRCO employs fast startup at minimal

energy consumption combined with a wide frequency range. When crystal accuracy is not required, it can be operated in free-run-

ning mode at a number of factory-calibrated frequencies. A digital phase-locked loop (DPLL) feature allows the HFRCO to achieve

higher accuracy and stability by referencing other available clock sources such as LFXO and HFXO.

• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC with a wide fre-

quency range.

• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-

tal accuracy is not required.

• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-

sumption in low energy modes.

3.5 Counters/Timers and PWM

3.5.1 Timer/Counter (TIMER)

TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the

PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one

of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output

reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width

modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional

dead-time insertion available in timer unit TIMER_0 only.

3.5.2 Wide Timer/Counter (WTIMER)

WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM

outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to

4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a

buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed thresh-

old value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by

the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.

3.5.3 Real Time Counter and Calendar (RTCC)

The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a

Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-

tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. The RTCC in-

cludes 128 bytes of general purpose data retention, allowing easy and convenient data storage in all energy modes down to EM4H.

EFM32TG11 Family Data Sheet

System Overview

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 12

3.5.4 Low Energy Timer (LETIMER)

The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This

allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed

while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-

forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con-

figured to start counting on compare matches from the RTCC.

3.5.5 Ultra Low Power Wake-up Timer (CRYOTIMER)

The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal

oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events

and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-

rupt periods, facilitating flexible ultra-low energy operation.

3.5.6 Pulse Counter (PCNT)

The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The

clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from

among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2

Deep Sleep, and EM3 Stop.

3.5.7 Watchdog Timer (WDOG)

The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed

monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can

also monitor autonomous systems driven by PRS.

3.6 Communications and Other Digital Peripherals

3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)

The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous

UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-

porting:

• ISO7816 SmartCards

• IrDA

•I2S

3.6.2 Universal Asynchronous Receiver/Transmitter (UART)

The Universal Asynchronous Receiver/Transmitter is a subset of the USART module, supporting full duplex asynchronous UART com-

munication with hardware flow control and RS-485.

3.6.3 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)

The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow

UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication

possible with a minimum of software intervention and energy consumption.

3.6.4 Inter-Integrated Circuit Interface (I2C)

The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and

supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10

kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The

interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans-

fers. Automatic recognition of slave addresses is provided in active and low energy modes.

EFM32TG11 Family Data Sheet

System Overview

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 13

3.6.5 Controller Area Network (CAN)

The CAN peripheral provides support for communication at up to 1 Mbps over CAN protocol version 2.0 part A and B. It includes 32

message objects with independent identifier masks and retains message RAM in EM2. Automatic retransmittion may be disabled in

order to support Time Triggered CAN applications.

3.6.6 Peripheral Reflex System (PRS)

The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.

Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-

erals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT)

can be applied by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.

3.6.7 Low Energy Sensor Interface (LESENSE)

The Low Energy Sensor Interface LESENSETM is a highly configurable sensor interface with support for up to 16 individually configura-

ble sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and

measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a

programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is

available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy

budget.

3.7 Security Features

3.7.1 GPCRC (General Purpose Cyclic Redundancy Check)

The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The sup-

ported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the

needs of the application.

3.7.2 Crypto Accelerator (CRYPTO)

The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. Tiny Gecko Series 1

devices support AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), and SHA-1 and SHA-2

(SHA-224 and SHA-256).

Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.

Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.

The CRYPTO module allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger

signals for DMA read and write operations.

3.7.3 True Random Number Generator (TRNG)

The TRNG module is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with

NIST800-22 and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key genera-

tion).

3.7.4 Security Management Unit (SMU)

The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the

Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to

the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and

can optionally generate an interrupt.

3.8 Analog

EFM32TG11 Family Data Sheet

System Overview

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3.8.1 Analog Port (APORT)

The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog modules on a flexible selection of pins.

Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are

grouped by X/Y pairs.

3.8.2 Analog Comparator (ACMP)

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-

er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption

is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The

ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the

programmable threshold.

3.8.3 Analog to Digital Converter (ADC)

The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output

sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.

The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of

sources, including pins configurable as either single-ended or differential.

3.8.4 Capacitive Sense (CSEN)

The CSEN module is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a switches

and sliders. The CSEN module uses a charge ramping measurement technique, which provides robust sensing even in adverse condi-

tions including radiated noise and moisture. The module can be configured to take measurements on a single port pin or scan through

multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the combined ca-

pacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an averaging filter,

as well as digital threshold comparators to reduce software overhead.

3.8.5 Digital to Analog Converter (VDAC)

The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500

ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per single-

ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications

such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low

frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any

CPU intervention. The VDAC is available in all energy modes down to and including EM3.

3.8.6 Operational Amplifiers

The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and

are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple

common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to

rail output. They can be used in conjunction with the VDAC module or in stand-alone configurations. The opamps save energy, PCB

space, and cost as compared with standalone opamps because they are integrated on-chip.

3.8.7 Liquid Crystal Display Driver (LCD)

The LCD driver is capable of driving a segmented LCD display with up to 8x32 segments. A voltage boost function enables it to provide

the LCD display with higher voltage than the supply voltage for the device. A patented charge redistribution driver can reduce the LCD

module supply current by up to 40%. In addition, an animation feature can run custom animations on the LCD display without any CPU

intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame Counter interrupt that can wake-up

the device on a regular basis for updating data.

3.9 Reset Management Unit (RMU)

The RMU is responsible for handling reset of the EFM32TG11. A wide range of reset sources are available, including several power

supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.

EFM32TG11 Family Data Sheet

System Overview

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3.10 Core and Memory

3.10.1 Processor Core

The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:

• ARM Cortex-M0+ RISC processor

• Memory Protection Unit (MPU) supporting up to 8 memory segments

• Micro-Trace Buffer (MTB)

• Up to 128 kB flash program memory

• Up to 32 kB RAM data memory

• Configuration and event handling of all modules

• 2-pin Serial-Wire debug interface

3.10.2 Memory System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable

from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code

is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a

read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-

ergy modes EM0 Active and EM1 Sleep.

3.10.3 Linked Direct Memory Access Controller (LDMA)

The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This

reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-

phisticated operations to be implemented.

3.10.4 Bootloader

All devices come pre-programmed with a UART bootloader. This bootloader resides in flash and can be erased if it is not needed. More

information about the bootloader protocol and usage can be found in AN0003: UART Bootloader. Application notes can be found on the

Silicon Labs website (www.silabs.com/32bit-appnotes) or within Simplicity Studio in the [Documentation] area.

EFM32TG11 Family Data Sheet

System Overview

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 16

3.11 Memory Map

The EFM32TG11 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.

Figure 3.2. EFM32TG11 Memory Map — Core Peripherals and Code Space

EFM32TG11 Family Data Sheet

System Overview

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 17

Figure 3.3. EFM32TG11 Memory Map — Peripherals

3.12 Configuration Summary

The features of the EFM32TG11 are a subset of the feature set described in the device reference manual. The table below describes

device specific implementation of the features. Remaining modules support full configuration.

Table 3.2. Configuration Summary

Module Configuration Pin Connections

USART0 IrDA, SmartCard US0_TX, US0_RX, US0_CLK, US0_CS

USART1 I2S, SmartCard US1_TX, US1_RX, US1_CLK, US1_CS

USART2 IrDA, SmartCard, High-Speed US2_TX, US2_RX, US2_CLK, US2_CS

USART3 I2S, SmartCard US3_TX, US3_RX, US3_CLK, US3_CS

TIMER0 with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 - TIM1_CC[3:0]

WTIMER0 with DTI WTIM0_CC[2:0], WTIM0_CDTI[2:0]

WTIMER1 - WTIM1_CC[3:0]

EFM32TG11 Family Data Sheet

System Overview

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4. Electrical Specifications

4.1 Electrical Characteristics

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:

• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.

• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,

unless stated otherwise.

Refer to 4.1.2.1 General Operating Conditions for more details about operational supply and temperature limits.

4.1.1 Absolute Maximum Ratings

Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of

the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure

to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-

bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.

Table 4.1. Absolute Maximum Ratings

Parameter Symbol Test Condition Min Typ Max Unit

Storage temperature range TSTG -50 — 150 °C

Voltage on any supply pin VDDMAX -0.3 — 3.8 V

Voltage ramp rate on any

supply pin

VDDRAMPMAX — — 1 V / µs

DC voltage on any GPIO pin VDIGPIN 5V tolerant GPIO pins1 2 3-0.3 — Min of 5.25

and IOVDD

LCD pins3-0.3 — Min of 3.8

and IOVDD

Standard GPIO pins -0.3 — IOVDD+0.3 V

Total current into VDD power

lines

IVDDMAX Source — — 200 mA

Total current into VSS

ground lines

IVSSMAX Sink — — 200 mA

Current per I/O pin IIOMAX Sink — — 50 mA

Source — — 50 mA

Current for all I/O pins IIOALLMAX Sink — — 200 mA

Source — — 200 mA

Junction temperature TJ-G grade devices -40 — 105 °C

-I grade devices -40 — 125 °C

Note:

1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.

2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source

below the valid operating range (e.g. IOVDD shorted to VSS), the pin voltage maximum is IOVDD + 0.3 V, to avoid exceeding the

maximum IO current specifications.

3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register.

Pins with over-voltage tolerance disabled have the same limits as Standard GPIO.

EFM32TG11 Family Data Sheet

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4.1.2 Operating Conditions

When assigning supply sources, the following requirements must be observed:

• VREGVDD must be greater than or equal to AVDD, DVDD and all IOVDD supplies.

• VREGVDD = AVDD

• DVDD ≤ AVDD

• IOVDD ≤ AVDD

EFM32TG11 Family Data Sheet

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4.1.2.1 General Operating Conditions

Table 4.2. General Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Operating ambient tempera-

ture range6

TA-G temperature grade -40 25 85 °C

-I temperature grade -40 25 125 °C

AVDD supply voltage2VAVDD 1.8 3.3 3.8 V

VREGVDD operating supply

voltage2 1

VVREGVDD DCDC in regulation 2.4 3.3 3.8 V

DCDC in bypass, 50mA load 1.8 3.3 3.8 V

DCDC not in use. DVDD external-

ly shorted to VREGVDD

1.8 3.3 3.8 V

VREGVDD current IVREGVDD DCDC in bypass, T ≤ 85 °C — — 200 mA

DCDC in bypass, T > 85 °C — — 100 mA

DVDD operating supply volt-

age

VDVDD 1.62 — VVREGVDD V

IOVDD operating supply volt-

age

VIOVDD All IOVDD pins51.62 — VVREGVDD V

DECOUPLE output capaci-

tor3 4

CDECOUPLE 0.75 1.0 2.75 µF

HFCORECLK frequency fCORE VSCALE2, MODE = WS1 — — 48 MHz

VSCALE2, MODE = WS0 — — 25 MHz

VSCALE0, MODE = WS1 — — 20 MHz

VSCALE0, MODE = WS0 — — 10 MHz

HFCLK frequency fHFCLK VSCALE2 — — 48 MHz

VSCALE0 — — 20 MHz

HFSRCCLK frequency fHFSRCCLK VSCALE2 — — 48 MHz

VSCALE0 — — 20 MHz

HFBUSCLK frequency fHFBUSCLK VSCALE2 — — 48 MHz

VSCALE0 — — 20 MHz

HFPERCLK frequency fHFPERCLK VSCALE2 — — 48 MHz

VSCALE0 — — 20 MHz

HFPERBCLK frequency fHFPERBCLK VSCALE2 — — 48 MHz

VSCALE0 — — 20 MHz

HFPERCCLK frequency fHFPERCCLK VSCALE2 — — 48 MHz

VSCALE0 — — 20 MHz

EFM32TG11 Family Data Sheet

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Parameter Symbol Test Condition Min Typ Max Unit

Note:

1. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for

other loads can be calculated as VDVDD_min+ILOAD * RBYP_max.

2. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.

3. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val-

ue stays within the specified bounds across temperature and DC bias.

4. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV / usec for approximately 20 usec. During this transi-

tion, peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70

mA (with a 2.7 µF capacitor).

5. When the CSEN peripheral is used with chopping enabled (CSEN_CTRL_CHOPEN = ENABLE), IOVDD must be equal to AVDD.

6. The maximum limit on TA may be lower due to device self-heating, which depends on the power dissipation of the specific appli-

cation. TA (max) = TJ (max) - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal

Characteristics table for TJ and THETAJA.

4.1.3 Thermal Characteristics

Table 4.3. Thermal Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Thermal resistance, QFN32

Package

THETAJA_QFN32 4-Layer PCB, Air velocity = 0 m/s — 25.7 — °C/W

4-Layer PCB, Air velocity = 1 m/s — 23.2 — °C/W

4-Layer PCB, Air velocity = 2 m/s — 21.3 — °C/W

Thermal resistance, TQFP48

Package

THE-

TAJA_TQFP48

4-Layer PCB, Air velocity = 0 m/s — 44.1 — °C/W

4-Layer PCB, Air velocity = 1 m/s — 43.5 — °C/W

4-Layer PCB, Air velocity = 2 m/s — 42.3 — °C/W

Thermal resistance, QFN64

Package

THETAJA_QFN64 4-Layer PCB, Air velocity = 0 m/s — 20.9 — °C/W

4-Layer PCB, Air velocity = 1 m/s — 18.2 — °C/W

4-Layer PCB, Air velocity = 2 m/s — 16.4 — °C/W

Thermal resistance, TQFP64

Package

THE-

TAJA_TQFP64

4-Layer PCB, Air velocity = 0 m/s — 37.3 — °C/W

4-Layer PCB, Air velocity = 1 m/s — 35.6 — °C/W

4-Layer PCB, Air velocity = 2 m/s — 33.8 — °C/W

Thermal resistance, QFN80

Package

THETAJA_QFN80 4-Layer PCB, Air velocity = 0 m/s — 20.9 — °C/W

4-Layer PCB, Air velocity = 1 m/s — 18.2 — °C/W

4-Layer PCB, Air velocity = 2 m/s — 16.4 — °C/W

Thermal resistance, TQFP80

Package

THE-

TAJA_TQFP80

4-Layer PCB, Air velocity = 0 m/s — 49.3 — °C/W

4-Layer PCB, Air velocity = 1 m/s — 44.5 — °C/W

4-Layer PCB, Air velocity = 2 m/s — 42.6 — °C/W

EFM32TG11 Family Data Sheet

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4.1.4 DC-DC Converter

Test conditions: L_DCDC=4.7 µH (Murata LQH3NPN4R7MM0L), C_DCDC=4.7 µF (Samsung CL10B475KQ8NQNC), V_DCDC_I=3.3

V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.

Table 4.4. DC-DC Converter

Parameter Symbol Test Condition Min Typ Max Unit

Input voltage range VDCDC_I Bypass mode, IDCDC_LOAD = 50

1.8 — VVREGVDD_

MAX

Low noise (LN) mode, 1.8 V out-

put, IDCDC_LOAD = 100 mA, or

Low power (LP) mode, 1.8 V out-

put, IDCDC_LOAD = 10 mA

2.4 — VVREGVDD_

MAX

Low noise (LN) mode, 1.8 V out-

put, IDCDC_LOAD = 200 mA

2.6 — VVREGVDD_

MAX

Output voltage programma-

ble range1

VDCDC_O 1.8 — VVREGVDD V

Regulation DC accuracy ACCDC Low Noise (LN) mode, 1.8 V tar-

get output

TBD — TBD V

Regulation window4WINREG Low Power (LP) mode,

LPCMPBIASEMxx3 = 0, 1.8 V tar-

get output, IDCDC_LOAD ≤ 75 µA

TBD — TBD V

Low Power (LP) mode,

LPCMPBIASEMxx3 = 3, 1.8 V tar-

get output, IDCDC_LOAD ≤ 10 mA

TBD — TBD V

Steady-state output ripple VR— 3 — mVpp

Output voltage under/over-

shoot

VOV CCM Mode (LNFORCECCM3 =

1), Load changes between 0 mA

and 100 mA

— 25 TBD mV

DCM Mode (LNFORCECCM3 =

0), Load changes between 0 mA

and 10 mA

— 45 TBD mV

Overshoot during LP to LN

CCM/DCM mode transitions com-

pared to DC level in LN mode

— 200 — mV

Undershoot during BYP/LP to LN

CCM (LNFORCECCM3 = 1) mode

transitions compared to DC level

in LN mode

— 40 — mV

Undershoot during BYP/LP to LN

DCM (LNFORCECCM3 = 0) mode

transitions compared to DC level

in LN mode

— 100 — mV

DC line regulation VREG Input changes between

VVREGVDD_MAX and 2.4 V

— 0.1 — %

DC load regulation IREG Load changes between 0 mA and

100 mA in CCM mode

— 0.1 — %

EFM32TG11 Family Data Sheet

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Parameter Symbol Test Condition Min Typ Max Unit

Max load current ILOAD_MAX Low noise (LN) mode, Heavy

Drive2, T ≤ 85 °C

— — 200 mA

Low noise (LN) mode, Heavy

Drive2, T > 85 °C

— — 100 mA

Low noise (LN) mode, Medium

Drive2

— — 100 mA

Low noise (LN) mode, Light

Drive2

— — 50 mA

Low power (LP) mode,

LPCMPBIASEMxx3 = 0

— — 75 µA

Low power (LP) mode,

LPCMPBIASEMxx3 = 3

— — 10 mA

DCDC nominal output ca-

pacitor5

CDCDC 25% tolerance 1 4.7 4.7 µF

DCDC nominal output induc-

tor

LDCDC 20% tolerance 4.7 4.7 4.7 µH

Resistance in Bypass mode RBYP — 1.2 TBD Ω

Note:

1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD.

2. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-

um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.

3. LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the

EMU_DCDCLOEM01CFG register, depending on the energy mode.

4. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits.

5. Output voltage under/over-shoot and regulation are specified with CDCDC 4.7 µF. Different settings for DCDCLNCOMPCTRL

must be used if CDCDC is lower than 4.7 µF. See Application Note AN0948 for details.

EFM32TG11 Family Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 24

4.1.5 Backup Supply Domain

Table 4.5. Backup Supply Domain

Parameter Symbol Test Condition Min Typ Max Unit

Backup supply voltage range VBU_VIN TBD — 3.8 V

PWRRES resistor RPWRRES EMU_BUCTRL_PWRRES =

RES0

TBD 3900 TBD Ω

EMU_BUCTRL_PWRRES =

RES1

TBD 1800 TBD Ω

EMU_BUCTRL_PWRRES =

RES2

TBD 1330 TBD Ω

EMU_BUCTRL_PWRRES =

RES3

TBD 815 TBD Ω

Output impedance between

BU_VIN and BU_VOUT 2

RBU_VOUT EMU_BUCTRL_VOUTRES =

STRONG

TBD 110 TBD Ω

EMU_BUCTRL_VOUTRES =

MED

TBD 775 TBD Ω

EMU_BUCTRL_VOUTRES =

WEAK

TBD 6500 TBD Ω

Supply current IBU_VIN BU_VIN not powering backup do-

main

— 10 TBD nA

BU_VIN powering backup do-

main1

— 450 TBD nA

Note:

1. Additional current required by backup circuitry when backup is active. Includes supply current of backup switches and backup

regulator. Does not include supply current required for backed-up circuitry.

2. BU_VOUT and BU_STAT signals are not available in all package configurations. Check the device pinout for availability.

EFM32TG11 Family Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 25

4.1.6 Current Consumption

4.1.6.1 Current Consumption 3.3 V without DC-DC Converter

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = 3.3 V. T = 25 °C. DCDC is off. Minimum and maxi-

mum values in this table represent the worst conditions across supply voltage and process variation at T = 25 °C.

Table 4.6. Current Consumption 3.3 V without DC-DC Converter

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in EM0

mode with all peripherals dis-

abled

IACTIVE 48 MHz crystal, CPU running

while loop from flash

— 45 — µA/MHz

48 MHz HFRCO, CPU running

while loop from flash

— 44 TBD µA/MHz

48 MHz HFRCO, CPU running

Prime from flash

— 57 — µA/MHz

48 MHz HFRCO, CPU running

CoreMark loop from flash

— 71 — µA/MHz

32 MHz HFRCO, CPU running

while loop from flash

— 45 — µA/MHz

26 MHz HFRCO, CPU running

while loop from flash

— 46 TBD µA/MHz

16 MHz HFRCO, CPU running

while loop from flash

— 50 — µA/MHz

1 MHz HFRCO, CPU running

while loop from flash

— 161 TBD µA/MHz

Current consumption in EM0

mode with all peripherals dis-

abled and voltage scaling

enabled

IACTIVE_VS 19 MHz HFRCO, CPU running

while loop from flash

— 41 — µA/MHz

1 MHz HFRCO, CPU running

while loop from flash

— 145 — µA/MHz

Current consumption in EM1

mode with all peripherals dis-

abled

IEM1 48 MHz crystal — 34 — µA/MHz

48 MHz HFRCO — 33 TBD µA/MHz

32 MHz HFRCO — 34 — µA/MHz

26 MHz HFRCO — 35 TBD µA/MHz

16 MHz HFRCO — 39 — µA/MHz

1 MHz HFRCO — 150 TBD µA/MHz

Current consumption in EM1

mode with all peripherals dis-

abled and voltage scaling

enabled

IEM1_VS 19 MHz HFRCO — 32 — µA/MHz

1 MHz HFRCO — 136 — µA/MHz

Current consumption in EM2

mode, with voltage scaling

enabled

IEM2_VS Full 32 kB RAM retention and

RTCC running from LFXO

— 1.48 — µA

Full 32 kB RAM retention and

RTCC running from LFRCO

— 1.86 — µA

8 kB (1 bank) RAM retention and

RTCC running from LFRCO2

— 1.59 TBD µA

Current consumption in EM3

mode, with voltage scaling

enabled

IEM3_VS Full 32 kB RAM retention and

CRYOTIMER running from ULFR-

— 1.23 TBD µA

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Electrical Specifications

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Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in

EM4H mode, with voltage

scaling enabled

IEM4H_VS 128 byte RAM retention, RTCC

running from LFXO

— 0.82 — µA

128 byte RAM retention, CRYO-

TIMER running from ULFRCO

— 0.45 — µA

128 byte RAM retention, no RTCC — 0.45 TBD µA

Current consumption in

EM4S mode

IEM4S No RAM retention, no RTCC — 0.07 TBD µA

Current consumption of pe-

ripheral power domain 1,

with voltage scaling enabled

IPD1_VS Additional current consumption in

EM2/3 when any peripherals on

power domain 1 are enabled1

— 0.18 — µA

Current consumption of pe-

ripheral power domain 2,

with voltage scaling enabled

IPD2_VS Additional current consumption in

EM2/3 when any peripherals on

power domain 2 are enabled1

— 0.18 — µA

Note:

1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.2.3 EM2 and

EM3 Power Domains for a list of the peripherals in each power domain.

2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1

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4.1.6.2 Current Consumption 3.3 V using DC-DC Converter

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = 1.8 V DC-DC output. T = 25 °C.

Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25 °C.

Table 4.7. Current Consumption 3.3 V using DC-DC Converter

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in EM0

mode with all peripherals dis-

abled, DCDC in Low Noise

DCM mode2

IACTIVE_DCM 48 MHz crystal, CPU running

while loop from flash

— 38 — µA/MHz

48 MHz HFRCO, CPU running

while loop from flash

— 37 — µA/MHz

48 MHz HFRCO, CPU running

Prime from flash

— 45 — µA/MHz

48 MHz HFRCO, CPU running

CoreMark loop from flash

— 53 — µA/MHz

32 MHz HFRCO, CPU running

while loop from flash

— 43 — µA/MHz

26 MHz HFRCO, CPU running

while loop from flash

— 47 — µA/MHz

16 MHz HFRCO, CPU running

while loop from flash

— 61 — µA/MHz

1 MHz HFRCO, CPU running

while loop from flash

— 587 — µA/MHz

Current consumption in EM0

mode with all peripherals dis-

abled, DCDC in Low Noise

CCM mode1

IACTIVE_CCM 48 MHz crystal, CPU running

while loop from flash

— 49 — µA/MHz

48 MHz HFRCO, CPU running

while loop from flash

— 48 — µA/MHz

48 MHz HFRCO, CPU running

Prime from flash

— 55 — µA/MHz

48 MHz HFRCO, CPU running

CoreMark loop from flash

— 63 — µA/MHz

32 MHz HFRCO, CPU running

while loop from flash

— 60 — µA/MHz

26 MHz HFRCO, CPU running

while loop from flash

— 68 — µA/MHz

16 MHz HFRCO, CPU running

while loop from flash

— 96 — µA/MHz

1 MHz HFRCO, CPU running

while loop from flash

— 1157 — µA/MHz

Current consumption in EM0

mode with all peripherals dis-

abled, DCDC in LP mode3

IACTIVE_LPM 32 MHz HFRCO, CPU running

while loop from flash

— 32 — µA/MHz

26 MHz HFRCO, CPU running

while loop from flash

— 33 — µA/MHz

16 MHz HFRCO, CPU running

while loop from flash

— 36 — µA/MHz

1 MHz HFRCO, CPU running

while loop from flash

— 156 — µA/MHz

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Electrical Specifications

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Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in EM0

mode with all peripherals dis-

abled and voltage scaling

enabled, DCDC in Low

Noise CCM mode1

IACTIVE_CCM_VS 19 MHz HFRCO, CPU running

while loop from flash

— 81 — µA/MHz

1 MHz HFRCO, CPU running

while loop from flash

— 1147 — µA/MHz

Current consumption in EM0

mode with all peripherals dis-

abled and voltage scaling

enabled, DCDC in LP mode3

IACTIVE_LPM_VS 19 MHz HFRCO, CPU running

while loop from flash

— 30 — µA/MHz

1 MHz HFRCO, CPU running

while loop from flash

— 144 — µA/MHz

Current consumption in EM1

mode with all peripherals dis-

abled, DCDC in Low Noise

DCM mode2

IEM1_DCM 48 MHz crystal — 31 — µA/MHz

48 MHz HFRCO — 30 — µA/MHz

32 MHz HFRCO — 36 — µA/MHz

26 MHz HFRCO — 41 — µA/MHz

16 MHz HFRCO — 54 — µA/MHz

1 MHz HFRCO — 581 — µA/MHz

Current consumption in EM1

mode with all peripherals dis-

abled, DCDC in Low Power

mode3

IEM1_LPM 32 MHz HFRCO — 25 — µA/MHz

26 MHz HFRCO — 26 — µA/MHz

16 MHz HFRCO — 29 — µA/MHz

1 MHz HFRCO — 153 — µA/MHz

Current consumption in EM1

mode with all peripherals dis-

abled and voltage scaling

enabled, DCDC in Low

Noise DCM mode2

IEM1_DCM_VS 19 MHz HFRCO — 46 — µA/MHz

1 MHz HFRCO — 573 — µA/MHz

Current consumption in EM1

mode with all peripherals dis-

abled and voltage scaling

enabled. DCDC in LP mode3

IEM1_LPM_VS 19 MHz HFRCO — 25 — µA/MHz

1 MHz HFRCO — 140 — µA/MHz

Current consumption in EM2

mode, with voltage scaling

enabled, DCDC in LP mode3

IEM2_VS Full 32 kB RAM retention and

RTCC running from LFXO

— 1.26 — µA

Full 32 kB RAM retention and

RTCC running from LFRCO

— 1.54 — µA

8 kB (1 bank) RAM retention and

RTCC running from LFRCO5

— 1.30 — µA

Current consumption in EM3

mode, with voltage scaling

enabled

IEM3_VS Full 32 kB RAM retention and

CRYOTIMER running from ULFR-

— 0.93 — µA

Current consumption in

EM4H mode, with voltage

scaling enabled

IEM4H_VS 128 byte RAM retention, RTCC

running from LFXO

— 0.78 — µA

128 byte RAM retention, CRYO-

TIMER running from ULFRCO

— 0.50 — µA

128 byte RAM retention, no RTCC — 0.50 — µA

Current consumption in

EM4S mode

IEM4S No RAM retention, no RTCC — 0.06 — µA

EFM32TG11 Family Data Sheet

Electrical Specifications

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Parameter Symbol Test Condition Min Typ Max Unit

Current consumption of pe-

ripheral power domain 1,

with voltage scaling enabled,

DCDC in LP mode3

IPD1_VS Additional current consumption in

EM2/3 when any peripherals on

power domain 1 are enabled4

— 0.18 — µA

Current consumption of pe-

ripheral power domain 2,

with voltage scaling enabled,

DCDC in LP mode3

IPD2_VS Additional current consumption in

EM2/3 when any peripherals on

power domain 2 are enabled4

— 0.18 — µA

Note:

1. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.

2. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.

3. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIM-

SEL=1, ANASW=DVDD.

4. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.2.3 EM2 and

EM3 Power Domains for a list of the peripherals in each power domain.

5. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1

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4.1.6.3 Current Consumption 1.8 V without DC-DC Converter

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = 1.8 V. T = 25 °C. DCDC is off. Minimum and maxi-

mum values in this table represent the worst conditions across supply voltage and process variation at T = 25 °C.

Table 4.8. Current Consumption 1.8 V without DC-DC Converter

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in EM0

mode with all peripherals dis-

abled

IACTIVE 48 MHz crystal, CPU running

while loop from flash

— 45 — µA/MHz

48 MHz HFRCO, CPU running

while loop from flash

— 44 — µA/MHz

48 MHz HFRCO, CPU running

Prime from flash

— 57 — µA/MHz

48 MHz HFRCO, CPU running

CoreMark loop from flash

— 71 — µA/MHz

32 MHz HFRCO, CPU running

while loop from flash

— 45 — µA/MHz

26 MHz HFRCO, CPU running

while loop from flash

— 46 — µA/MHz

16 MHz HFRCO, CPU running

while loop from flash

— 49 — µA/MHz

1 MHz HFRCO, CPU running

while loop from flash

— 158 — µA/MHz

Current consumption in EM0

mode with all peripherals dis-

abled and voltage scaling

enabled

IACTIVE_VS 19 MHz HFRCO, CPU running

while loop from flash

— 41 — µA/MHz

1 MHz HFRCO, CPU running

while loop from flash

— 142 — µA/MHz

Current consumption in EM1

mode with all peripherals dis-

abled

IEM1 48 MHz crystal — 34 — µA/MHz

48 MHz HFRCO — 33 — µA/MHz

32 MHz HFRCO — 34 — µA/MHz

26 MHz HFRCO — 35 — µA/MHz

16 MHz HFRCO — 39 — µA/MHz

1 MHz HFRCO — 147 — µA/MHz

Current consumption in EM1

mode with all peripherals dis-

abled and voltage scaling

enabled

IEM1_VS 19 MHz HFRCO — 32 — µA/MHz

1 MHz HFRCO — 133 — µA/MHz

Current consumption in EM2

mode, with voltage scaling

enabled

IEM2_VS Full 32 kB RAM retention and

RTCC running from LFXO

— 1.39 — µA

Full 32 kB RAM retention and

RTCC running from LFRCO

— 1.63 — µA

8 kB (1 bank) RAM retention and

RTCC running from LFRCO2

— 1.37 — µA

Current consumption in EM3

mode, with voltage scaling

enabled

IEM3_VS Full 32 kB RAM retention and

CRYOTIMER running from ULFR-

— 1.10 — µA

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Electrical Specifications

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Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in

EM4H mode, with voltage

scaling enabled

IEM4H_VS 128 byte RAM retention, RTCC

running from LFXO

— 0.75 — µA

128 byte RAM retention, CRYO-

TIMER running from ULFRCO

— 0.37 — µA

128 byte RAM retention, no RTCC — 0.37 — µA

Current consumption in

EM4S mode

IEM4S No RAM retention, no RTCC — 0.05 — µA

Current consumption of pe-

ripheral power domain 1,

with voltage scaling enabled

IPD1_VS Additional current consumption in

EM2/3 when any peripherals on

power domain 1 are enabled1

— 0.18 — µA

Current consumption of pe-

ripheral power domain 2,

with voltage scaling enabled

IPD2_VS Additional current consumption in

EM2/3 when any peripherals on

power domain 2 are enabled1

— 0.18 — µA

Note:

1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.2.3 EM2 and

EM3 Power Domains for a list of the peripherals in each power domain.

2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1

EFM32TG11 Family Data Sheet

Electrical Specifications

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4.1.7 Wake Up Times

Table 4.9. Wake Up Times

Parameter Symbol Test Condition Min Typ Max Unit

Wake up time from EM1 tEM1_WU — 3 — AHB

Clocks

Wake up from EM2 tEM2_WU Code execution from flash — 10.1 — µs

Code execution from RAM — 3.1 — µs

Wake up from EM3 tEM3_WU Code execution from flash — 10.1 — µs

Code execution from RAM — 3.1 — µs

Wake up from EM4H1tEM4H_WU Executing from flash — 88 — µs

Wake up from EM4S1tEM4S_WU Executing from flash — 282 — µs

Time from release of reset

source to first instruction ex-

ecution

tRESET Soft Pin Reset released — 50 — µs

Any other reset released — 352 — µs

Power mode scaling time tSCALE VSCALE0 to VSCALE2, HFCLK =

19 MHz4 2

— 31.8 — µs

VSCALE2 to VSCALE0, HFCLK =

19 MHz3

— 4.3 — µs

Note:

1. Time from wake up request until first instruction is executed. Wakeup results in device reset.

2. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/µs for approximately 20 µs. During this transition,

peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70 mA

(with a 2.7 µF capacitor).

3. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 µs + 29 HFCLKs.

4. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 µs + 28 HFCLKs.

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4.1.8 Brown Out Detector (BOD)

Table 4.10. Brown Out Detector (BOD)

Parameter Symbol Test Condition Min Typ Max Unit

DVDD BOD threshold VDVDDBOD DVDD rising — — TBD V

DVDD falling (EM0/EM1) TBD — — V

DVDD falling (EM2/EM3) TBD — — V

DVDD BOD hysteresis VDVDDBOD_HYST — 18 — mV

DVDD BOD response time tDVDDBOD_DELAY Supply drops at 0.1V/µs rate — 2.4 — µs

AVDD BOD threshold VAVDDBOD AVDD rising — — TBD V

AVDD falling (EM0/EM1) TBD — — V

AVDD falling (EM2/EM3) TBD — — V

AVDD BOD hysteresis VAVDDBOD_HYST — 20 — mV

AVDD BOD response time tAVDDBOD_DELAY Supply drops at 0.1V/µs rate — 2.4 — µs

EM4 BOD threshold VEM4DBOD AVDD rising — — TBD V

AVDD falling TBD — — V

EM4 BOD hysteresis VEM4BOD_HYST — 25 — mV

EM4 BOD response time tEM4BOD_DELAY Supply drops at 0.1V/µs rate — 300 — µs

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4.1.9 Oscillators

4.1.9.1 Low-Frequency Crystal Oscillator (LFXO)

Table 4.11. Low-Frequency Crystal Oscillator (LFXO)

Parameter Symbol Test Condition Min Typ Max Unit

Crystal frequency fLFXO — 32.768 — kHz

Supported crystal equivalent

series resistance (ESR)

ESRLFXO — — 70 kΩ

Supported range of crystal

load capacitance 1

CLFXO_CL 6 — 18 pF

On-chip tuning cap range 2CLFXO_T On each of LFXTAL_N and

LFXTAL_P pins

8 — 40 pF

On-chip tuning cap step size SSLFXO — 0.25 — pF

Current consumption after

startup 3

ILFXO ESR = 70 kOhm, CL = 7 pF,

GAIN4 = 2, AGC4 = 1

— 273 — nA

Start- up time tLFXO ESR = 70 kOhm, CL = 7 pF,

GAIN4 = 2

— 308 — ms

Note:

1. Total load capacitance as seen by the crystal.

2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the

two caps will be seen in series by the crystal.

3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.

4. In CMU_LFXOCTRL register.

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4.1.9.2 High-Frequency Crystal Oscillator (HFXO)

Table 4.12. High-Frequency Crystal Oscillator (HFXO)

Parameter Symbol Test Condition Min Typ Max Unit

Crystal frequency fHFXO 4 — 48 MHz

Supported crystal equivalent

series resistance (ESR)

ESRHFXO 48 MHz crystal — — 50 Ω

24 MHz crystal — — 150 Ω

4 MHz crystal — — 180 Ω

Supported range of crystal

load capacitance1

CHFXO_CL TBD — TBD pF

Nominal on-chip tuning cap

range2

CHFXO_T On each of HFXTAL_N and

HFXTAL_P pins

8.7 — 51.7 pF

On-chip tuning capacitance

step

SSHFXO — 0.08 — pF

Startup time tHFXO 48 MHz crystal, ESR = 50 Ohm,

CL = 8 pF

— 350 — µs

24 MHz crystal, ESR = 150 Ohm,

CL = 6 pF

— 700 — µs

4 MHz crystal, ESR = 180 Ohm,

CL = 18 pF

— 3 — ms

Current consumption after

startup

IHFXO 48 MHz crystal — 880 — µA

24 MHz crystal — 420 — µA

4 MHz crystal — 80 — µA

Note:

1. Total load capacitance as seen by the crystal.

2. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the

two caps will be seen in series by the crystal.

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4.1.9.3 Low-Frequency RC Oscillator (LFRCO)

Table 4.13. Low-Frequency RC Oscillator (LFRCO)

Parameter Symbol Test Condition Min Typ Max Unit

Oscillation frequency fLFRCO ENVREF2 = 1 TBD 32.768 TBD kHz

ENVREF2 = 1, T > 85 °C TBD 32.768 TBD kHz

ENVREF2 = 0 TBD 32.768 TBD kHz

Startup time tLFRCO — 500 — µs

Current consumption 1ILFRCO ENVREF = 1 in

CMU_LFRCOCTRL

— 370 — nA

ENVREF = 0 in

CMU_LFRCOCTRL

— 520 — nA

Note:

1. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.

2. In CMU_LFRCOCTRL register.

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4.1.9.4 High-Frequency RC Oscillator (HFRCO)

Table 4.14. High-Frequency RC Oscillator (HFRCO)

Parameter Symbol Test Condition Min Typ Max Unit

Frequency accuracy fHFRCO_ACC At production calibrated frequen-

cies, across supply voltage and

temperature

TBD — TBD %

Start-up time tHFRCO fHFRCO ≥ 19 MHz — 300 — ns

4 < fHFRCO < 19 MHz — 1 — µs

fHFRCO ≤ 4 MHz — 2.5 — µs

Current consumption on all

supplies

IHFRCO fHFRCO = 48 MHz — 258 TBD µA

fHFRCO = 38 MHz — 218 TBD µA

fHFRCO = 32 MHz — 182 TBD µA

fHFRCO = 26 MHz — 156 TBD µA

fHFRCO = 19 MHz — 130 TBD µA

fHFRCO = 16 MHz — 112 TBD µA

fHFRCO = 13 MHz — 101 TBD µA

fHFRCO = 7 MHz — 80 TBD µA

fHFRCO = 4 MHz — 29 TBD µA

fHFRCO = 2 MHz — 26 TBD µA

fHFRCO = 1 MHz — 24 TBD µA

fHFRCO = 40 MHz, DPLL enabled — 393 TBD µA

fHFRCO = 32 MHz, DPLL enabled — 313 TBD µA

fHFRCO = 16 MHz, DPLL enabled — 180 TBD µA

fHFRCO = 4 MHz, DPLL enabled — 46 TBD µA

fHFRCO = 1 MHz, DPLL enabled — 33 TBD µA

Coarse trim step size (% of

period)

SSHFRCO_COARS

— 0.8 — %

Fine trim step size (% of pe-

riod)

SSHFRCO_FINE — 0.1 — %

Period jitter PJHFRCO — 0.2 — % RMS

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Parameter Symbol Test Condition Min Typ Max Unit

Frequency limits fHFRCO_BAND FREQRANGE = 0, FINETUNIN-

GEN = 0

TBD — TBD MHz

FREQRANGE = 3, FINETUNIN-

GEN = 0

TBD — TBD MHz

FREQRANGE = 6, FINETUNIN-

GEN = 0

TBD — TBD MHz

FREQRANGE = 7, FINETUNIN-

GEN = 0

TBD — TBD MHz

FREQRANGE = 8, FINETUNIN-

GEN = 0

TBD — TBD MHz

FREQRANGE = 10, FINETUNIN-

GEN = 0

TBD — TBD MHz

FREQRANGE = 11, FINETUNIN-

GEN = 0

TBD — TBD MHz

FREQRANGE = 12, FINETUNIN-

GEN = 0

TBD — TBD MHz

FREQRANGE = 13, FINETUNIN-

GEN = 0

TBD — TBD MHz

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4.1.9.5 Auxiliary High-Frequency RC Oscillator (AUXHFRCO)

Table 4.15. Auxiliary High-Frequency RC Oscillator (AUXHFRCO)

Parameter Symbol Test Condition Min Typ Max Unit

Frequency accuracy fAUXHFRCO_ACC At production calibrated frequen-

cies, across supply voltage and

temperature

TBD — TBD %

Start-up time tAUXHFRCO fAUXHFRCO ≥ 19 MHz — 400 — ns

4 < fAUXHFRCO < 19 MHz — 1.4 — µs

fAUXHFRCO ≤ 4 MHz — 2.5 — µs

Current consumption on all

supplies

IAUXHFRCO fAUXHFRCO = 48 MHz — 238 TBD µA

fAUXHFRCO = 38 MHz — 196 TBD µA

fAUXHFRCO = 32 MHz — 160 TBD µA

fAUXHFRCO = 26 MHz — 137 TBD µA

fAUXHFRCO = 19 MHz — 110 TBD µA

fAUXHFRCO = 16 MHz — 101 TBD µA

fAUXHFRCO = 13 MHz — 78 TBD µA

fAUXHFRCO = 7 MHz — 54 TBD µA

fAUXHFRCO = 4 MHz — 30 TBD µA

fAUXHFRCO = 2 MHz — 27 TBD µA

fAUXHFRCO = 1 MHz — 25 TBD µA

Coarse trim step size (% of

period)

SSAUXHFR-

CO_COARSE

— 0.8 — %

Fine trim step size (% of pe-

riod)

SSAUXHFR-

CO_FINE

— 0.1 — %

Period jitter PJAUXHFRCO — 0.2 — % RMS

4.1.9.6 Ultra-low Frequency RC Oscillator (ULFRCO)

Table 4.16. Ultra-low Frequency RC Oscillator (ULFRCO)

Parameter Symbol Test Condition Min Typ Max Unit

Oscillation frequency fULFRCO TBD 1 TBD kHz

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Electrical Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 40

4.1.10 Flash Memory Characteristics5

Table 4.17. Flash Memory Characteristics5

Parameter Symbol Test Condition Min Typ Max Unit

Flash erase cycles before

failure

ECFLASH 10000 — — cycles

Flash data retention RETFLASH T ≤ 85 °C 10 — — years

T ≤ 125 °C 10 — — years

Word (32-bit) programming

time

tW_PROG Burst write, 128 words, average

time per word

20 26 32 µs

Single word 59 68 83 µs

Page erase time4tPERASE 20 27 35 ms

Mass erase time1tMERASE 20 27 35 ms

Device erase time2 3tDERASE T ≤ 85 °C — 54 70 ms

T ≤ 125 °C — 54 75 ms

Erase current6IERASE Page Erase — — 1.7 mA

Mass or Device Erase — — 2.0 mA

Write current6IWRITE — — 3.5 mA

Supply voltage during flash

erase and write

VFLASH 1.62 — 3.6 V

Note:

1. Mass erase is issued by the CPU and erases all flash.

2. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock

Word (ULW).

3. From setting the DEVICEERASE bit in AAP_CMD to 1 until the ERASEBUSY bit in AAP_STATUS is cleared to 0. Internal setup

and hold times for flash control signals are included.

4. From setting the ERASEPAGE bit in MSC_WRITECMD to 1 until the BUSY bit in MSC_STATUS is cleared to 0. Internal setup

and hold times for flash control signals are included.

5. Flash data retention information is published in the Quarterly Quality and Reliability Report.

6. Measured at 25 °C.

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Electrical Specifications

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4.1.11 General-Purpose I/O (GPIO)

Table 4.18. General-Purpose I/O (GPIO)

Parameter Symbol Test Condition Min Typ Max Unit

Input low voltage VIL GPIO pins — — IOVDD*0.3 V

Input high voltage VIH GPIO pins IOVDD*0.7 — — V

Output high voltage relative

to IOVDD

VOH Sourcing 3 mA, IOVDD ≥ 3 V,

DRIVESTRENGTH1 = WEAK

IOVDD*0.8 — — V

Sourcing 1.2 mA, IOVDD ≥ 1.62

DRIVESTRENGTH1 = WEAK

IOVDD*0.6 — — V

Sourcing 20 mA, IOVDD ≥ 3 V,

DRIVESTRENGTH1 = STRONG

IOVDD*0.8 — — V

Sourcing 8 mA, IOVDD ≥ 1.62 V,

DRIVESTRENGTH1 = STRONG

IOVDD*0.6 — — V

Output low voltage relative to

IOVDD

VOL Sinking 3 mA, IOVDD ≥ 3 V,

DRIVESTRENGTH1 = WEAK

— — IOVDD*0.2 V

Sinking 1.2 mA, IOVDD ≥ 1.62 V,

DRIVESTRENGTH1 = WEAK

— — IOVDD*0.4 V

Sinking 20 mA, IOVDD ≥ 3 V,

DRIVESTRENGTH1 = STRONG

— — IOVDD*0.2 V

Sinking 8 mA, IOVDD ≥ 1.62 V,

DRIVESTRENGTH1 = STRONG

— — IOVDD*0.4 V

Input leakage current IIOLEAK All GPIO except LFXO pins, GPIO

≤ IOVDD, T ≤ 85 °C

— 0.1 TBD nA

LFXO Pins, GPIO ≤ IOVDD, T ≤

85 °C

— 0.1 TBD nA

All GPIO except LFXO pins, GPIO

≤ IOVDD, T > 85 °C

— — TBD nA

LFXO Pins, GPIO ≤ IOVDD, T >

85 °C

— — TBD nA

Input leakage current on

5VTOL pads above IOVDD

I5VTOLLEAK IOVDD < GPIO ≤ IOVDD + 2 V — 3.3 TBD µA

I/O pin pull-up/pull-down re-

sistor

RPUD TBD 40 TBD kΩ

Pulse width of pulses re-

moved by the glitch suppres-

sion filter

tIOGLITCH TBD 25 TBD ns

EFM32TG11 Family Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 42

Parameter Symbol Test Condition Min Typ Max Unit

Output fall time, From 70%

to 30% of VIO

tIOOF CL = 50 pF,

DRIVESTRENGTH1 = STRONG,

SLEWRATE1 = 0x6

— 1.8 — ns

CL = 50 pF,

DRIVESTRENGTH1 = WEAK,

SLEWRATE1 = 0x6

— 4.5 — ns

Output rise time, From 30%

to 70% of VIO

tIOOR CL = 50 pF,

DRIVESTRENGTH1 = STRONG,

SLEWRATE = 0x61

— 2.2 — ns

CL = 50 pF,

DRIVESTRENGTH1 = WEAK,

SLEWRATE1 = 0x6

— 7.4 — ns

Note:

1. In GPIO_Pn_CTRL register.

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Electrical Specifications

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4.1.12 Voltage Monitor (VMON)

Table 4.19. Voltage Monitor (VMON)

Parameter Symbol Test Condition Min Typ Max Unit

Supply current (including

I_SENSE)

IVMON In EM0 or EM1, 1 supply moni-

tored, T ≤ 85 °C

— 6.3 TBD µA

In EM0 or EM1, 4 supplies moni-

tored, T ≤ 85 °C

— 12.5 TBD µA

In EM2, EM3 or EM4, 1 supply

monitored and above threshold

— 62 — nA

In EM2, EM3 or EM4, 1 supply

monitored and below threshold

— 62 — nA

In EM2, EM3 or EM4, 4 supplies

monitored and all above threshold

— 99 — nA

In EM2, EM3 or EM4, 4 supplies

monitored and all below threshold

— 99 — nA

Loading of monitored supply ISENSE In EM0 or EM1 — 2 — µA

In EM2, EM3 or EM4 — 2 — nA

Threshold range VVMON_RANGE 1.62 — 3.4 V

Threshold step size NVMON_STESP Coarse — 200 — mV

Fine — 20 — mV

Response time tVMON_RES Supply drops at 1V/µs rate — 460 — ns

Hysteresis VVMON_HYST — 26 — mV

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4.1.13 Analog to Digital Converter (ADC)

Specified at 1 Msps, ADCCLK = 16 MHz, BIASPROG = 0, GPBIASACC = 0, unless otherwise indicated.

Table 4.20. Analog to Digital Converter (ADC)

Parameter Symbol Test Condition Min Typ Max Unit

Resolution VRESOLUTION 6 — 12 Bits

Input voltage range5VADCIN Single ended — — VFS V

Differential -VFS/2 — VFS/2 V

Input range of external refer-

ence voltage, single ended

and differential

VADCREFIN_P 1 — VAVDD V

Power supply rejection2PSRRADC At DC — 80 — dB

Analog input common mode

rejection ratio

CMRRADC At DC — 80 — dB

Current from all supplies, us-

ing internal reference buffer.

Continous operation. WAR-

MUPMODE4 = KEEPADC-

WARM

IADC_CONTI-

NOUS_LP

1 Msps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 1 3

— 270 TBD µA

250 ksps / 4 MHz ADCCLK, BIA-

SPROG = 6, GPBIASACC = 1 3

— 125 — µA

62.5 ksps / 1 MHz ADCCLK, BIA-

SPROG = 15, GPBIASACC = 1 3

— 80 — µA

Current from all supplies, us-

ing internal reference buffer.

Duty-cycled operation. WAR-

MUPMODE4 = NORMAL

IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 1 3

— 45 — µA

5 ksps / 16 MHz ADCCLK BIA-

SPROG = 0, GPBIASACC = 1 3

— 8 — µA

Current from all supplies, us-

ing internal reference buffer.

Duty-cycled operation.

AWARMUPMODE4 = KEEP-

INSTANDBY or KEEPIN-

SLOWACC

IADC_STAND-

BY_LP

125 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 1 3

— 105 — µA

35 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 1 3

— 70 — µA

Current from all supplies, us-

ing internal reference buffer.

Continous operation. WAR-

MUPMODE4 = KEEPADC-

WARM

IADC_CONTI-

NOUS_HP

1 Msps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 0 3

— 325 — µA

250 ksps / 4 MHz ADCCLK, BIA-

SPROG = 6, GPBIASACC = 0 3

— 175 — µA

62.5 ksps / 1 MHz ADCCLK, BIA-

SPROG = 15, GPBIASACC = 0 3

— 125 — µA

Current from all supplies, us-

ing internal reference buffer.

Duty-cycled operation. WAR-

MUPMODE4 = NORMAL

IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 0 3

— 85 — µA

5 ksps / 16 MHz ADCCLK BIA-

SPROG = 0, GPBIASACC = 0 3

— 16 — µA

Current from all supplies, us-

ing internal reference buffer.

Duty-cycled operation.

AWARMUPMODE4 = KEEP-

INSTANDBY or KEEPIN-

SLOWACC

IADC_STAND-

BY_HP

125 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 0 3

— 160 — µA

35 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 0 3

— 125 — µA

Current from HFPERCLK IADC_CLK HFPERCLK = 16 MHz — 166 — µA

EFM32TG11 Family Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 45

Parameter Symbol Test Condition Min Typ Max Unit

ADC clock frequency fADCCLK — — 16 MHz

Throughput rate fADCRATE — — 1 Msps

Conversion time1tADCCONV 6 bit — 7 — cycles

8 bit — 9 — cycles

12 bit — 13 — cycles

Startup time of reference

generator and ADC core

tADCSTART WARMUPMODE4 = NORMAL — — 5 µs

WARMUPMODE4 = KEEPIN-

STANDBY

— — 2 µs

WARMUPMODE4 = KEEPINSLO-

WACC

— — 1 µs

SNDR at 1Msps and fIN =

10kHz

SNDRADC Internal reference7, differential

measurement

TBD 67 — dB

External reference6, differential

measurement

— 68 — dB

Spurious-free dynamic range

(SFDR)

SFDRADC 1 MSamples/s, 10 kHz full-scale

sine wave

— 75 — dB

Differential non-linearity

(DNL)

DNLADC 12 bit resolution, No missing co-

des

TBD — TBD LSB

Integral non-linearity (INL),

End point method

INLADC 12 bit resolution TBD — TBD LSB

Offset error VADCOFFSETERR TBD 0 TBD LSB

Gain error in ADC VADCGAIN Using internal reference — -0.2 TBD %

Using external reference — -1 — %

Temperature sensor slope VTS_SLOPE — -1.84 — mV/°C

Note:

1. Derived from ADCCLK.

2. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL.

3. In ADCn_BIASPROG register.

4. In ADCn_CNTL register.

5. The absolute voltage allowed at any ADC input is dictated by the power rail supplied to on-chip circuitry, and may be lower than

the effective full scale voltage. All ADC inputs are limited to the ADC supply (AVDD or DVDD depending on

EMU_PWRCTRL_ANASW). Any ADC input routed through the APORT will further be limited by the IOVDD supply to the pin.

6. External reference is 1.25 V applied externally to ADCnEXTREFP, with the selection CONF in the SINGLECTRL_REF or

SCANCTRL_REF register field and VREFP in the SINGLECTRLX_VREFSEL or SCANCTRLX_VREFSEL field. The differential

input range with this configuration is ± 1.25 V.

7. Internal reference option used corresponds to selection 2V5 in the SINGLECTRL_REF or SCANCTRL_REF register field. The

differential input range with this configuration is ± 1.25 V. Typical value is characterized using full-scale sine wave input. Minimum

value is production-tested using sine wave input at 1.5 dB lower than full scale.

EFM32TG11 Family Data Sheet

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silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 46

4.1.14 Analog Comparator (ACMP)

Table 4.21. Analog Comparator (ACMP)

Parameter Symbol Test Condition Min Typ Max Unit

Input voltage range VACMPIN ACMPVDD =

ACMPn_CTRL_PWRSEL 1

— — VACMPVDD V

Supply voltage VACMPVDD BIASPROG4 ≤ 0x10 or FULL-

BIAS4 = 0

1.8 — VVREGVDD_

MAX

0x10 < BIASPROG4 ≤ 0x20 and

FULLBIAS4 = 1

2.1 — VVREGVDD_

MAX

Active current not including

voltage reference2

IACMP BIASPROG4 = 1, FULLBIAS4 = 0 — 50 — nA

BIASPROG4 = 0x10, FULLBIAS4

= 0

— 306 — nA

BIASPROG4 = 0x02, FULLBIAS4

= 1

— 6.5 — µA

BIASPROG4 = 0x20, FULLBIAS4

= 1

— 74 TBD µA

Current consumption of inter-

nal voltage reference2

IACMPREF VLP selected as input using 2.5 V

Reference / 4 (0.625 V)

— 50 — nA

VLP selected as input using VDD — 20 — nA

VBDIV selected as input using

1.25 V reference / 1

— 4.1 — µA

VADIV selected as input using

VDD/1

— 2.4 — µA

EFM32TG11 Family Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 47

Parameter Symbol Test Condition Min Typ Max Unit

Hysteresis (VCM = 1.25 V,

BIASPROG4 = 0x10, FULL-

BIAS4 = 1)

VACMPHYST HYSTSEL5 = HYST0 TBD 0 TBD mV

HYSTSEL5 = HYST1 TBD 18 TBD mV

HYSTSEL5 = HYST2 TBD 33 TBD mV

HYSTSEL5 = HYST3 TBD 46 TBD mV

HYSTSEL5 = HYST4 TBD 57 TBD mV

HYSTSEL5 = HYST5 TBD 68 TBD mV

HYSTSEL5 = HYST6 TBD 79 TBD mV

HYSTSEL5 = HYST7 TBD 90 TBD mV

HYSTSEL5 = HYST8 TBD 0 TBD mV

HYSTSEL5 = HYST9 TBD -18 TBD mV

HYSTSEL5 = HYST10 TBD -33 TBD mV

HYSTSEL5 = HYST11 TBD -45 TBD mV

HYSTSEL5 = HYST12 TBD -57 TBD mV

HYSTSEL5 = HYST13 TBD -67 TBD mV

HYSTSEL5 = HYST14 TBD -78 TBD mV

HYSTSEL5 = HYST15 TBD -88 TBD mV

Comparator delay3tACMPDELAY BIASPROG4 = 1, FULLBIAS4 = 0 — 30 — µs

BIASPROG4 = 0x10, FULLBIAS4

= 0

— 3.7 — µs

BIASPROG4 = 0x02, FULLBIAS4

= 1

— 360 — ns

BIASPROG4 = 0x20, FULLBIAS4

= 1

— 35 — ns

Offset voltage VACMPOFFSET BIASPROG4 =0x10, FULLBIAS4

= 1

TBD — TBD mV

Reference voltage VACMPREF Internal 1.25 V reference TBD 1.25 TBD V

Internal 2.5 V reference TBD 2.5 TBD V

Capacitive sense internal re-

sistance

RCSRES CSRESSEL6 = 0 — infinite — kΩ

CSRESSEL6 = 1 — 15 — kΩ

CSRESSEL6 = 2 — 27 — kΩ

CSRESSEL6 = 3 — 39 — kΩ

CSRESSEL6 = 4 — 51 — kΩ

CSRESSEL6 = 5 — 100 — kΩ

CSRESSEL6 = 6 — 162 — kΩ

CSRESSEL6 = 7 — 235 — kΩ

EFM32TG11 Family Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 48

Parameter Symbol Test Condition Min Typ Max Unit

Note:

1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD.

2. The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference. IACMPTOTAL = IACMP +

IACMPREF.

3. ± 100 mV differential drive.

4. In ACMPn_CTRL register.

5. In ACMPn_HYSTERESIS registers.

6. In ACMPn_INPUTSEL register.

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4.1.15 Digital to Analog Converter (VDAC)

DRIVESTRENGTH = 2 unless otherwise specified. Primary VDAC output.

Table 4.22. Digital to Analog Converter (VDAC)

Parameter Symbol Test Condition Min Typ Max Unit

Output voltage VDACOUT Single-Ended 0 — VVREF V

Differential2-VVREF — VVREF V

Current consumption includ-

ing references (2 channels)1

IDAC 500 ksps, 12-bit, DRIVES-

TRENGTH = 2, REFSEL = 4

— 396 — µA

44.1 ksps, 12-bit, DRIVES-

TRENGTH = 1, REFSEL = 4

— 72 — µA

200 Hz refresh rate, 12-bit Sam-

ple-Off mode in EM2, DRIVES-

TRENGTH = 2, BGRREQTIME =

1, EM2REFENTIME = 9, REFSEL

= 4, SETTLETIME = 0x0A, WAR-

MUPTIME = 0x02

— 2 — µA

Current from HFPERCLK4IDAC_CLK — 5.8 — µA/MHz

Sample rate SRDAC — — 500 ksps

DAC clock frequency fDAC — — 1 MHz

Conversion time tDACCONV fDAC = 1MHz 2 — — µs

Settling time tDACSETTLE 50% fs step settling to 5 LSB — 2.5 — µs

Startup time tDACSTARTUP Enable to 90% fs output, settling

to 10 LSB

— — 12 µs

Output impedance ROUT DRIVESTRENGTH = 2, 0.4 V ≤

VOUT ≤ VOPA - 0.4 V, -8 mA <

IOUT < 8 mA, Full supply range

— 2 — Ω

DRIVESTRENGTH = 0 or 1, 0.4 V

≤ VOUT ≤ VOPA - 0.4 V, -400 µA <

IOUT < 400 µA, Full supply range

— 2 — Ω

DRIVESTRENGTH = 2, 0.1 V ≤

VOUT ≤ VOPA - 0.1 V, -2 mA <

IOUT < 2 mA, Full supply range

— 2 — Ω

DRIVESTRENGTH = 0 or 1, 0.1 V

≤ VOUT ≤ VOPA - 0.1 V, -100 µA <

IOUT < 100 µA, Full supply range

— 2 — Ω

Power supply rejection ratio6PSRR Vout = 50% fs. DC — 65.5 — dB

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Parameter Symbol Test Condition Min Typ Max Unit

Signal to noise and distortion

ratio (1 kHz sine wave),

Noise band limited to 250

kHz

SNDRDAC 500 ksps, single-ended, internal

1.25V reference

— 60.4 — dB

500 ksps, single-ended, internal

2.5V reference

— 61.6 — dB

500 ksps, single-ended, 3.3V

VDD reference

— 64.0 — dB

500 ksps, differential, internal

1.25V reference

— 63.3 — dB

500 ksps, differential, internal

2.5V reference

— 64.4 — dB

500 ksps, differential, 3.3V VDD

reference

— 65.8 — dB

Signal to noise and distortion

ratio (1 kHz sine wave),

Noise band limited to 22 kHz

SNDRDAC_BAND 500 ksps, single-ended, internal

1.25V reference

— 65.3 — dB

500 ksps, single-ended, internal

2.5V reference

— 66.7 — dB

500 ksps, differential, 3.3V VDD

reference

— 68.5 — dB

500 ksps, differential, internal

1.25V reference

— 67.8 — dB

500 ksps, differential, internal

2.5V reference

— 69.0 — dB

500 ksps, single-ended, 3.3V

VDD reference

— 70.0 — dB

Total harmonic distortion THD — 70.2 — dB

Differential non-linearity3DNLDAC TBD — TBD LSB

Intergral non-linearity INLDAC TBD — TBD LSB

Offset error5VOFFSET T = 25 °C TBD — TBD mV

Across operating temperature

range

TBD — TBD mV

Gain error5VGAIN T = 25 °C, Low-noise internal ref-

erence (REFSEL = 1V25LN or

2V5LN)

TBD — TBD %

Across operating temperature

range, Low-noise internal refer-

ence (REFSEL = 1V25LN or

2V5LN)

TBD — TBD %

External load capactiance,

OUTSCALE=0

CLOAD — — 75 pF

EFM32TG11 Family Data Sheet

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silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 51

Parameter Symbol Test Condition Min Typ Max Unit

Note:

1. Supply current specifications are for VDAC circuitry operating with static output only and do not include current required to drive

the load.

2. In differential mode, the output is defined as the difference between two single-ended outputs. Absolute voltage on each output is

limited to the single-ended range.

3. Entire range is monotonic and has no missing codes.

4. Current from HFPERCLK is dependent on HFPERCLK frequency. This current contributes to the total supply current used when

the clock to the DAC module is enabled in the CMU.

5. Gain is calculated by measuring the slope from 10% to 90% of full scale. Offset is calculated by comparing actual VDAC output at

10% of full scale to ideal VDAC output at 10% of full scale with the measured gain.

6. PSRR calculated as 20 * log10(ΔVDD / ΔVOUT), VDAC output at 90% of full scale

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4.1.16 Capacitive Sense (CSEN)

Table 4.23. Capacitive Sense (CSEN)

Parameter Symbol Test Condition Min Typ Max Unit

Single conversion time (1x

accumulation)

tCNV 12-bit SAR Conversions — 20.2 — µs

16-bit SAR Conversions — 26.4 — µs

Delta Modulation Conversion (sin-

gle comparison)

— 1.55 — µs

Maximum external capacitive

load

CEXTMAX CS0CG=7 (Gain = 1x), including

routing parasitics

— 68 — pF

CS0CG=0 (Gain = 10x), including

routing parasitics

— 680 — pF

Maximum external series im-

pedance

REXTMAX — 1 — kΩ

Supply current, EM2 bonded

conversions, WARMUP-

MODE=NORMAL, WAR-

MUPCNT=0

ICSEN_BOND 12-bit SAR conversions, 20 ms

conversion rate, CS0CG=7 (Gain

= 1x), 10 channels bonded (total

capacitance of 330 pF)1

— 326 — nA

Delta Modulation conversions, 20

ms conversion rate, CS0CG=7

(Gain = 1x), 10 channels bonded

(total capacitance of 330 pF)1

— 226 — nA

12-bit SAR conversions, 200 ms

conversion rate, CS0CG=7 (Gain

= 1x), 10 channels bonded (total

capacitance of 330 pF)1

— 33 — nA

Delta Modulation conversions,

200 ms conversion rate,

CS0CG=7 (Gain = 1x), 10 chan-

nels bonded (total capacitance of

330 pF)1

— 25 — nA

Supply current, EM2 scan

conversions, WARMUP-

MODE=NORMAL, WAR-

MUPCNT=0

ICSEN_EM2 12-bit SAR conversions, 20 ms

scan rate, CS0CG=0 (Gain =

10x), 8 samples per scan1

— 690 — nA

Delta Modulation conversions, 20

ms scan rate, 8 comparisons per

sample (DMCR = 1, DMR = 2),

CS0CG=0 (Gain = 10x), 8 sam-

ples per scan1

— 515 — nA

12-bit SAR conversions, 200 ms

scan rate, CS0CG=0 (Gain =

10x), 8 samples per scan1

— 79 — nA

Delta Modulation conversions,

200 ms scan rate, 8 comparisons

per sample (DMCR = 1, DMR =

2), CS0CG=0 (Gain = 10x), 8

samples per scan1

— 57 — nA

EFM32TG11 Family Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 53

Parameter Symbol Test Condition Min Typ Max Unit

Supply current, continuous

conversions, WARMUP-

MODE=KEEPCSENWARM

ICSEN_ACTIVE SAR or Delta Modulation conver-

sions of 33 pF capacitor,

CS0CG=0 (Gain = 10x), always

— 90.5 — µA

HFPERCLK supply current ICSEN_HFPERCLK Current contribution from

HFPERCLK when clock to CSEN

block is enabled.

— 2.25 — µA/MHz

Note:

1. Current is specified with a total external capacitance of 33 pF per channel. Average current is dependent on how long the module

is actively sampling channels within the scan period, and scales with the number of samples acquired. Supply current for a specif-

ic application can be estimated by multiplying the current per sample by the total number of samples per period (total_current =

single_sample_current * (number_of_channels * accumulation)).

EFM32TG11 Family Data Sheet

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4.1.17 Operational Amplifier (OPAMP)

Unless otherwise indicated, specified conditions are: Non-inverting input configuration, VDD = 3.3 V, DRIVESTRENGTH = 2, MAIN-

OUTEN = 1, CLOAD = 75 pF with OUTSCALE = 0, or CLOAD = 37.5 pF with OUTSCALE = 1. Unit gain buffer and 3X-gain connection as

specified in table footnotes8 1.

Table 4.24. Operational Amplifier (OPAMP)

Parameter Symbol Test Condition Min Typ Max Unit

Supply voltage (from AVDD) VOPA HCMDIS = 0, Rail-to-rail input

range

2 — 3.8 V

HCMDIS = 1 1.62 — 3.8 V

Input voltage VIN HCMDIS = 0, Rail-to-rail input

range

VVSS — VOPA V

HCMDIS = 1 VVSS — VOPA-1.2 V

Input impedance RIN 100 — — MΩ

Output voltage VOUT VVSS — VOPA V

Load capacitance2CLOAD OUTSCALE = 0 — — 75 pF

OUTSCALE = 1 — — 37.5 pF

Output impedance ROUT DRIVESTRENGTH = 2 or 3, 0.4 V

≤ VOUT ≤ VOPA - 0.4 V, -8 mA <

IOUT < 8 mA, Buffer connection,

Full supply range

— 0.25 — Ω

DRIVESTRENGTH = 0 or 1, 0.4 V

≤ VOUT ≤ VOPA - 0.4 V, -400 µA <

IOUT < 400 µA, Buffer connection,

Full supply range

— 0.6 — Ω

DRIVESTRENGTH = 2 or 3, 0.1 V

≤ VOUT ≤ VOPA - 0.1 V, -2 mA <

IOUT < 2 mA, Buffer connection,

Full supply range

— 0.4 — Ω

DRIVESTRENGTH = 0 or 1, 0.1 V

≤ VOUT ≤ VOPA - 0.1 V, -100 µA <

IOUT < 100 µA, Buffer connection,

Full supply range

— 1 — Ω

Internal closed-loop gain GCL Buffer connection TBD 1 TBD -

3x Gain connection TBD 2.99 TBD -

16x Gain connection TBD 15.7 TBD -

Active current4IOPA DRIVESTRENGTH = 3, OUT-

SCALE = 0

— 580 — µA

DRIVESTRENGTH = 2, OUT-

SCALE = 0

— 176 — µA

DRIVESTRENGTH = 1, OUT-

SCALE = 0

— 13 — µA

DRIVESTRENGTH = 0, OUT-

SCALE = 0

— 4.7 — µA

EFM32TG11 Family Data Sheet

Electrical Specifications

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Parameter Symbol Test Condition Min Typ Max Unit

Open-loop gain GOL DRIVESTRENGTH = 3 — 135 — dB

DRIVESTRENGTH = 2 — 137 — dB

DRIVESTRENGTH = 1 — 121 — dB

DRIVESTRENGTH = 0 — 109 — dB

Loop unit-gain frequency7UGF DRIVESTRENGTH = 3, Buffer

connection

— 3.38 — MHz

DRIVESTRENGTH = 2, Buffer

connection

— 0.9 — MHz

DRIVESTRENGTH = 1, Buffer

connection

— 132 — kHz

DRIVESTRENGTH = 0, Buffer

connection

— 34 — kHz

DRIVESTRENGTH = 3, 3x Gain

connection

— 2.57 — MHz

DRIVESTRENGTH = 2, 3x Gain

connection

— 0.71 — MHz

DRIVESTRENGTH = 1, 3x Gain

connection

— 113 — kHz

DRIVESTRENGTH = 0, 3x Gain

connection

— 28 — kHz

Phase margin PM DRIVESTRENGTH = 3, Buffer

connection

— 67 — °

DRIVESTRENGTH = 2, Buffer

connection

— 69 — °

DRIVESTRENGTH = 1, Buffer

connection

— 63 — °

DRIVESTRENGTH = 0, Buffer

connection

— 68 — °

Output voltage noise NOUT DRIVESTRENGTH = 3, Buffer

connection, 10 Hz - 10 MHz

— 146 — µVrms

DRIVESTRENGTH = 2, Buffer

connection, 10 Hz - 10 MHz

— 163 — µVrms

DRIVESTRENGTH = 1, Buffer

connection, 10 Hz - 1 MHz

— 170 — µVrms

DRIVESTRENGTH = 0, Buffer

connection, 10 Hz - 1 MHz

— 176 — µVrms

DRIVESTRENGTH = 3, 3x Gain

connection, 10 Hz - 10 MHz

— 313 — µVrms

DRIVESTRENGTH = 2, 3x Gain

connection, 10 Hz - 10 MHz

— 271 — µVrms

DRIVESTRENGTH = 1, 3x Gain

connection, 10 Hz - 1 MHz

— 247 — µVrms

DRIVESTRENGTH = 0, 3x Gain

connection, 10 Hz - 1 MHz

— 245 — µVrms

EFM32TG11 Family Data Sheet

Electrical Specifications

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Parameter Symbol Test Condition Min Typ Max Unit

Slew rate5SR DRIVESTRENGTH = 3,

INCBW=13

— 4.7 — V/µs

DRIVESTRENGTH = 3,

INCBW=0

— 1.5 — V/µs

DRIVESTRENGTH = 2,

INCBW=13

— 1.27 — V/µs

DRIVESTRENGTH = 2,

INCBW=0

— 0.42 — V/µs

DRIVESTRENGTH = 1,

INCBW=13

— 0.17 — V/µs

DRIVESTRENGTH = 1,

INCBW=0

— 0.058 — V/µs

DRIVESTRENGTH = 0,

INCBW=13

— 0.044 — V/µs

DRIVESTRENGTH = 0,

INCBW=0

— 0.015 — V/µs

Startup time6TSTART DRIVESTRENGTH = 2 — — TBD µs

Input offset voltage VOSI DRIVESTRENGTH = 2 or 3, T =

25 °C

TBD — TBD mV

DRIVESTRENGTH = 1 or 0, T =

25 °C

TBD — TBD mV

DRIVESTRENGTH = 2 or 3,

across operating temperature

range

TBD — TBD mV

DRIVESTRENGTH = 1 or 0,

across operating temperature

range

TBD — TBD mV

DC power supply rejection

ratio9

PSRRDC Input referred — 70 — dB

DC common-mode rejection

ratio9

CMRRDC Input referred — 70 — dB

Total harmonic distortion THDOPA DRIVESTRENGTH = 2, 3x Gain

connection, 1 kHz, VOUT = 0.1 V

to VOPA - 0.1 V

— 90 — dB

DRIVESTRENGTH = 0, 3x Gain

connection, 0.1 kHz, VOUT = 0.1 V

to VOPA - 0.1 V

— 90 — dB

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Parameter Symbol Test Condition Min Typ Max Unit

Note:

1. Specified configuration for 3X-Gain configuration is: INCBW = 1, HCMDIS = 1, RESINSEL = VSS, VINPUT = 0.5 V, VOUTPUT = 1.5

V. Nominal voltage gain is 3.

2. If the maximum CLOAD is exceeded, an isolation resistor is required for stability. See AN0038 for more information.

3. When INCBW is set to 1 the OPAMP bandwidth is increased. This is allowed only when the non-inverting close-loop gain is ≥ 3,

or the OPAMP may not be stable.

4. Current into the load resistor is excluded. When the OPAMP is connected with closed-loop gain > 1, there will be extra current to

drive the resistor feedback network. The internal resistor feedback network has total resistance of 143.5 kOhm, which will cause

another ~10 µA current when the OPAMP drives 1.5 V between output and ground.

5. Step between 0.2V and VOPA-0.2V, 10%-90% rising/falling range.

6. From enable to output settled. In sample-and-off mode, RC network after OPAMP will contribute extra delay. Settling error < 1mV.

7. In unit gain connection, UGF is the gain-bandwidth product of the OPAMP. In 3x Gain connection, UGF is the gain-bandwidth

product of the OPAMP and 1/3 attenuation of the feedback network.

8. Specified configuration for Unit gain buffer configuration is: INCBW = 0, HCMDIS = 0, RESINSEL = DISABLE. VINPUT = 0.5 V,

VOUTPUT = 0.5 V.

9. When HCMDIS=1 and input common mode transitions the region from VOPA-1.4V to VOPA-1V, input offset will change. PSRR

and CMRR specifications do not apply to this transition region.

4.1.18 LCD Driver

Table 4.25. LCD Driver

Parameter Symbol Test Condition Min Typ Max Unit

Frame rate fLCDFR TBD — TBD Hz

LCD supply range2VLCDIN 1.8 — 3.8 V

LCD output voltage range VLCD Current source mode, No external

LCD capacitor

2.0 — VLCDIN-0.4 V

Step-down mode with external

LCD capacitor

2.0 — VLCDIN V

Charge pump mode with external

LCD capacitor

2.0 — Min of 3.8

and 1.9 *

VLCDIN

Contrast control step size STEPCONTRAST Current source mode — 64 — mV

Charge pump or Step-down mode — 43 — mV

Contrast control step accura-

cy1

ACCCONTRAST — +/-4 — %

Note:

1. Step size accuracy is measured relative to the typical step size, and typ value represents one standard deviation.

2. VLCDIN is selectable between the AVDD or DVDD supply pins, depending on EMU_PWRCTRL_ANASW.

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4.1.19 Pulse Counter (PCNT)

Table 4.26. Pulse Counter (PCNT)

Parameter Symbol Test Condition Min Typ Max Unit

Input frequency FIN Asynchronous Single and Quad-

rature Modes

— — 20 MHz

Sampled Modes with Debounce

filter set to 0.

— — 8 kHz

4.1.20 Analog Port (APORT)

Table 4.27. Analog Port (APORT)

Parameter Symbol Test Condition Min Typ Max Unit

Supply current2 1IAPORT Operation in EM0/EM1 — 7 — µA

Operation in EM2/EM3 — 915 — nA

Note:

1. Specified current is for continuous APORT operation. In applications where the APORT is not requested continuously (e.g. peri-

odic ACMP requests from LESENSE in EM2), the average current requirements can be estimated by mutiplying the duty cycle of

the requests by the specified continuous current number.

2. Supply current increase that occurs when an analog peripheral requests access to APORT. This current is not included in repor-

ted module currents. Additional peripherals requesting access to APORT do not incur further current.

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4.1.21 I2C

4.1.21.1 I2C Standard-mode (Sm)1

Table 4.28. I2C Standard-mode (Sm)1

Parameter Symbol Test Condition Min Typ Max Unit

SCL clock frequency2fSCL 0 — 100 kHz

SCL clock low time tLOW 4.7 — — µs

SCL clock high time tHIGH 4 — — µs

SDA set-up time tSU_DAT 250 — — ns

SDA hold time3tHD_DAT 100 — 3450 ns

Repeated START condition

set-up time

tSU_STA 4.7 — — µs

(Repeated) START condition

hold time

tHD_STA 4 — — µs

STOP condition set-up time tSU_STO 4 — — µs

Bus free time between a

STOP and START condition

tBUF 4.7 — — µs

Note:

1. For CLHR set to 0 in the I2Cn_CTRL register.

2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual.

3. The maximum SDA hold time (tHD_DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).

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4.1.21.2 I2C Fast-mode (Fm)1

Table 4.29. I2C Fast-mode (Fm)1

Parameter Symbol Test Condition Min Typ Max Unit

SCL clock frequency2fSCL 0 — 400 kHz

SCL clock low time tLOW 1.3 — — µs

SCL clock high time tHIGH 0.6 — — µs

SDA set-up time tSU_DAT 100 — — ns

SDA hold time3tHD_DAT 100 — 900 ns

Repeated START condition

set-up time

tSU_STA 0.6 — — µs

(Repeated) START condition

hold time

tHD_STA 0.6 — — µs

STOP condition set-up time tSU_STO 0.6 — — µs

Bus free time between a

STOP and START condition

tBUF 1.3 — — µs

Note:

1. For CLHR set to 1 in the I2Cn_CTRL register.

2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual.

3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).

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4.1.21.3 I2C Fast-mode Plus (Fm+)1

Table 4.30. I2C Fast-mode Plus (Fm+)1

Parameter Symbol Test Condition Min Typ Max Unit

SCL clock frequency2fSCL 0 — 1000 kHz

SCL clock low time tLOW 0.5 — — µs

SCL clock high time tHIGH 0.26 — — µs

SDA set-up time tSU_DAT 50 — — ns

SDA hold time tHD_DAT 100 — — ns

Repeated START condition

set-up time

tSU_STA 0.26 — — µs

(Repeated) START condition

hold time

tHD_STA 0.26 — — µs

STOP condition set-up time tSU_STO 0.26 — — µs

Bus free time between a

STOP and START condition

tBUF 0.5 — — µs

Note:

1. For CLHR set to 0 or 1 in the I2Cn_CTRL register.

2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual.

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Electrical Specifications

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4.1.22 USART SPI

SPI Master Timing

Table 4.31. SPI Master Timing

Parameter Symbol Test Condition Min Typ Max Unit

SCLK period 1 3 2tSCLK 2 *

tHFPERCLK

— — ns

CS to MOSI 1 3tCS_MO -19.8 — 18.9 ns

SCLK to MOSI 1 3tSCLK_MO -10 — 14.5 ns

MISO setup time 1 3tSU_MI IOVDD = 1.62 V 75 — — ns

IOVDD = 3.0 V 40 — — ns

MISO hold time 1 3tH_MI -10 — — ns

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).

2. tHFPERCLK is one period of the selected HFPERCLK.

3. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).

SCLK

CLKPOL = 0

MOSI

MISO

tCS_MO

tH_MI

tSU_MI

tSCKL_MO

tSCLK

SCLK

CLKPOL = 1

Figure 4.1. SPI Master Timing Diagram

EFM32TG11 Family Data Sheet

Electrical Specifications

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SPI Slave Timing

Table 4.32. SPI Slave Timing

Parameter Symbol Test Condition Min Typ Max Unit

SCLK period 1 3 2tSCLK 6 *

tHFPERCLK

— — ns

SCLK high time1 3 2tSCLK_HI 2.5 *

tHFPERCLK

— — ns

SCLK low time1 3 2tSCLK_LO 2.5 *

tHFPERCLK

— — ns

CS active to MISO 1 3tCS_ACT_MI 20 — 70 ns

CS disable to MISO 1 3tCS_DIS_MI 15 — 150 ns

MOSI setup time 1 3tSU_MO 4 — — ns

MOSI hold time 1 3 2tH_MO 7 — — ns

SCLK to MISO 1 3 2tSCLK_MI 14 + 1.5 *

tHFPERCLK

— 40 + 2.5 *

tHFPERCLK

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).

2. tHFPERCLK is one period of the selected HFPERCLK.

3. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).

SCLK

CLKPOL = 0

MOSI

MISO

tCS_ACT_MI

tSCLK_HI

tSCLK

tSU_MO

tH_MO

tSCLK_MI

tCS_DIS_MI

tSCLK_LO

SCLK

CLKPOL = 1

Figure 4.2. SPI Slave Timing Diagram

4.2 Typical Performance Curves

Typical performance curves indicate typical characterized performance under the stated conditions.

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4.2.1 Supply Current

Figure 4.3. EM0 Active Mode Typical Supply Current vs. Temperature

EFM32TG11 Family Data Sheet

Electrical Specifications

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Figure 4.4. EM1 Sleep Mode Typical Supply Current vs. Temperature

Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.

EFM32TG11 Family Data Sheet

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Figure 4.5. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Temperature

EFM32TG11 Family Data Sheet

Electrical Specifications

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Figure 4.6. EM0 and EM1 Mode Typical Supply Current vs. Supply

Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.

EFM32TG11 Family Data Sheet

Electrical Specifications

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Figure 4.7. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Supply

EFM32TG11 Family Data Sheet

Electrical Specifications

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4.2.2 DC-DC Converter

Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 4.7 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz

Figure 4.8. DC-DC Converter Typical Performance Characteristics

EFM32TG11 Family Data Sheet

Electrical Specifications

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100μs/div 10μs/div

2V/div

offset:1.8V

20mV/div

offset:1.8V

100mA

1mA

ILOAD

60mV/div

offset:1.8V

VSW

DVDD

Load Step Response in LN (CCM) mode

(Heavy Drive)

LN (CCM) and LP mode transition (load: 5mA)

Figure 4.9. DC-DC Converter Transition Waveforms

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5. Pin Definitions

5.1 EFM32TG11B5xx in QFP80 Device Pinout

Figure 5.1. EFM32TG11B5xx in QFP80 Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 5.14 GPIO Functionality Table or 5.15 Alternate Functionality Overview.

Table 5.1. EFM32TG11B5xx in QFP80 Device Pinout

Pin Name Pin(s) Description Pin Name Pin(s) Description

PA0 1 GPIO PA1 2 GPIO

PA2 3 GPIO PA3 4 GPIO

PA4 5 GPIO PA5 6 GPIO

PA6 7 GPIO IOVDD0

Digital IO power supply 0.

EFM32TG11 Family Data Sheet

Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

VSS

Ground PB3 10 GPIO

PB4 11 GPIO PB5 12 GPIO

PB6 13 GPIO PC1 14 GPIO (5V)

PC2 15 GPIO (5V) PC3 16 GPIO (5V)

PC4 17 GPIO PC5 18 GPIO

PB7 19 GPIO PB8 20 GPIO

PA8 21 GPIO PA9 22 GPIO

PA10 23 GPIO PA12 25 GPIO

PA14 26 GPIO RESETn 27

Reset input, active low. To apply an ex-

ternal reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

PB11 28 GPIO PB12 29 GPIO

AVDD 30

34 Analog power supply. PB13 31 GPIO

PB14 32 GPIO PD0 35 GPIO (5V)

PD1 36 GPIO PD3 37 GPIO

PD4 38 GPIO PD5 39 GPIO

PD6 40 GPIO PD7 41 GPIO

PD8 42 GPIO PC6 43 GPIO

PC7 44 GPIO VREGVSS 45 Voltage regulator VSS

VREGSW 46 DCDC regulator switching node VREGVDD 47 Voltage regulator VDD input

DVDD 48 Digital power supply. DECOUPLE 49

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PE4 52 GPIO PE5 53 GPIO

PE6 54 GPIO PE7 55 GPIO

PC8 56 GPIO PC9 57 GPIO

PC10 58 GPIO (5V) PC11 59 GPIO (5V)

PC13 60 GPIO (5V) PC14 61 GPIO (5V)

PC15 62 GPIO (5V) PF0 63 GPIO (5V)

PF1 64 GPIO (5V) PF2 65 GPIO

PF3 66 GPIO PF4 67 GPIO

PF5 68 GPIO PE8 71 GPIO

PE9 72 GPIO PE10 73 GPIO

PE11 74 GPIO BODEN 75

Brown-Out Detector Enable. This pin

may be left disconnected or tied to

AVDD.

EFM32TG11 Family Data Sheet

Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

PE12 76 GPIO PE13 77 GPIO

PE14 78 GPIO PE15 79 GPIO

PA15 80 GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 74

5.2 EFM32TG11B5xx in QFN80 Device Pinout

Figure 5.2. EFM32TG11B5xx in QFN80 Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 5.14 GPIO Functionality Table or 5.15 Alternate Functionality Overview.

Table 5.2. EFM32TG11B5xx in QFN80 Device Pinout

Pin Name Pin(s) Description Pin Name Pin(s) Description

VREGVSS 0

46 Voltage regulator VSS PA0 1 GPIO

PA1 2 GPIO PA2 3 GPIO

PA3 4 GPIO PA4 5 GPIO

PA5 6 GPIO PA6 7 GPIO

IOVDD0

Digital IO power supply 0. PB3 9 GPIO

EFM32TG11 Family Data Sheet

Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

PB4 10 GPIO PB5 11 GPIO

PB6 12 GPIO PC0 13 GPIO (5V)

PC1 14 GPIO (5V) PC2 15 GPIO (5V)

PC3 16 GPIO (5V) PC4 17 GPIO

PC5 18 GPIO PB7 19 GPIO

PB8 20 GPIO PA8 21 GPIO

PA9 22 GPIO PA10 23 GPIO

PA12 24 GPIO PA13 25 GPIO (5V)

PA14 26 GPIO RESETn 27

Reset input, active low. To apply an ex-

ternal reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

PB11 28 GPIO PB12 29 GPIO

AVDD 30

34 Analog power supply. PB13 31 GPIO

PB14 32 GPIO PD0 35 GPIO (5V)

PD1 36 GPIO PD2 37 GPIO (5V)

PD3 38 GPIO PD4 39 GPIO

PD5 40 GPIO PD6 41 GPIO

PD7 42 GPIO PD8 43 GPIO

PC6 44 GPIO PC7 45 GPIO

VREGSW 47 DCDC regulator switching node VREGVDD 48 Voltage regulator VDD input

DVDD 49 Digital power supply. DECOUPLE 50

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PE4 52 GPIO PE5 53 GPIO

PE6 54 GPIO PE7 55 GPIO

PC8 56 GPIO PC9 57 GPIO

PC10 58 GPIO (5V) PC11 59 GPIO (5V)

PC12 60 GPIO (5V) PC13 61 GPIO (5V)

PC14 62 GPIO (5V) PC15 63 GPIO (5V)

PF0 64 GPIO (5V) PF1 65 GPIO (5V)

PF2 66 GPIO PF3 67 GPIO

PF4 68 GPIO PF5 69 GPIO

PE8 71 GPIO PE9 72 GPIO

PE10 73 GPIO PE11 74 GPIO

BODEN 75

Brown-Out Detector Enable. This pin

may be left disconnected or tied to

AVDD.

PE12 76 GPIO

PE13 77 GPIO PE14 78 GPIO

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Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

PE15 79 GPIO PA15 80 GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

EFM32TG11 Family Data Sheet

Pin Definitions

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5.3 EFM32TG11B5xx in QFP64 Device Pinout

Figure 5.3. EFM32TG11B5xx in QFP64 Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 5.14 GPIO Functionality Table or 5.15 Alternate Functionality Overview.

Table 5.3. EFM32TG11B5xx in QFP64 Device Pinout

Pin Name Pin(s) Description Pin Name Pin(s) Description

PA0 1 GPIO PA1 2 GPIO

PA2 3 GPIO PA3 4 GPIO

PA4 5 GPIO PA5 6 GPIO

IOVDD0

Digital IO power supply 0. VSS

Ground

PB3 9 GPIO PB4 10 GPIO

PB5 11 GPIO PB6 12 GPIO

EFM32TG11 Family Data Sheet

Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

PC4 13 GPIO PC5 14 GPIO

PB7 15 GPIO PB8 16 GPIO

PA8 17 GPIO PA12 18 GPIO

PA14 19 GPIO RESETn 20

Reset input, active low. To apply an ex-

ternal reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

PB11 21 GPIO PB12 22 GPIO

AVDD 24

28 Analog power supply. PB13 25 GPIO

PB14 26 GPIO PD0 29 GPIO (5V)

PD1 30 GPIO PD3 31 GPIO

PD4 32 GPIO PD5 33 GPIO

PD6 34 GPIO PD7 35 GPIO

PD8 36 GPIO PC7 37 GPIO

VREGVSS 38 Voltage regulator VSS VREGSW 39 DCDC regulator switching node

VREGVDD 40 Voltage regulator VDD input DVDD 41 Digital power supply.

DECOUPLE 42

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PE4 43 GPIO

PE5 44 GPIO PE6 45 GPIO

PE7 46 GPIO PC12 47 GPIO (5V)

PC13 48 GPIO (5V) PF0 49 GPIO (5V)

PF1 50 GPIO (5V) PF2 51 GPIO

PF3 52 GPIO PF4 53 GPIO

PF5 54 GPIO PE8 57 GPIO

PE9 58 GPIO PE10 59 GPIO

PE11 60 GPIO PE12 61 GPIO

PE13 62 GPIO PE14 63 GPIO

PE15 64 GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

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Pin Definitions

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5.4 EFM32TG11B3xx in QFP64 Device Pinout

Figure 5.4. EFM32TG11B3xx in QFP64 Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 5.14 GPIO Functionality Table or 5.15 Alternate Functionality Overview.

Table 5.4. EFM32TG11B3xx in QFP64 Device Pinout

Pin Name Pin(s) Description Pin Name Pin(s) Description

PA0 1 GPIO PA1 2 GPIO

PA2 3 GPIO PA3 4 GPIO

PA4 5 GPIO PA5 6 GPIO

IOVDD0

Digital IO power supply 0. VSS

Ground

PB3 9 GPIO PB4 10 GPIO

PB5 11 GPIO PB6 12 GPIO

EFM32TG11 Family Data Sheet

Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

PC4 13 GPIO PC5 14 GPIO

PB7 15 GPIO PB8 16 GPIO

PA12 17 GPIO PA13 18 GPIO (5V)

PA14 19 GPIO RESETn 20

Reset input, active low. To apply an ex-

ternal reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

PB11 21 GPIO AVDD 23

27 Analog power supply.

PB13 24 GPIO PB14 25 GPIO

PD0 28 GPIO (5V) PD1 29 GPIO

PD2 30 GPIO (5V) PD3 31 GPIO

PD4 32 GPIO PD5 33 GPIO

PD6 34 GPIO PD7 35 GPIO

PD8 36 GPIO PC6 37 GPIO

PC7 38 GPIO DVDD 39 Digital power supply.

DECOUPLE 40

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PE4 41 GPIO

PE5 42 GPIO PE6 43 GPIO

PE7 44 GPIO PC12 45 GPIO (5V)

PC13 46 GPIO (5V) PC14 47 GPIO (5V)

PC15 48 GPIO (5V) PF0 49 GPIO (5V)

PF1 50 GPIO (5V) PF2 51 GPIO

PF3 52 GPIO PF4 53 GPIO

PF5 54 GPIO PE8 57 GPIO

PE9 58 GPIO PE10 59 GPIO

PE11 60 GPIO PE12 61 GPIO

PE13 62 GPIO PE14 63 GPIO

PE15 64 GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

EFM32TG11 Family Data Sheet

Pin Definitions

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5.5 EFM32TG11B1xx in QFP64 Device Pinout

Figure 5.5. EFM32TG11B1xx in QFP64 Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 5.14 GPIO Functionality Table or 5.15 Alternate Functionality Overview.

Table 5.5. EFM32TG11B1xx in QFP64 Device Pinout

Pin Name Pin(s) Description Pin Name Pin(s) Description

PA0 1 GPIO PA1 2 GPIO

PA2 3 GPIO PA3 4 GPIO

PA4 5 GPIO PA5 6 GPIO

IOVDD0

Digital IO power supply 0. VSS

Ground

PC0 9 GPIO (5V) PC1 10 GPIO (5V)

PC2 11 GPIO (5V) PC3 12 GPIO (5V)

EFM32TG11 Family Data Sheet

Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

PC4 13 GPIO PC5 14 GPIO

PB7 15 GPIO PB8 16 GPIO

PA8 17 GPIO PA9 18 GPIO

PA10 19 GPIO RESETn 20

Reset input, active low. To apply an ex-

ternal reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

PB11 21 GPIO AVDD 23

27 Analog power supply.

PB13 24 GPIO PB14 25 GPIO

PD0 28 GPIO (5V) PD1 29 GPIO

PD2 30 GPIO (5V) PD3 31 GPIO

PD4 32 GPIO PD5 33 GPIO

PD6 34 GPIO PD7 35 GPIO

PD8 36 GPIO PC6 37 GPIO

PC7 38 GPIO DVDD 39 Digital power supply.

DECOUPLE 40

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PC8 41 GPIO

PC9 42 GPIO PC10 43 GPIO (5V)

PC11 44 GPIO (5V) PC12 45 GPIO (5V)

PC13 46 GPIO (5V) PC14 47 GPIO (5V)

PC15 48 GPIO (5V) PF0 49 GPIO (5V)

PF1 50 GPIO (5V) PF2 51 GPIO

PF3 52 GPIO PF4 53 GPIO

PF5 54 GPIO PE8 57 GPIO

PE9 58 GPIO PE10 59 GPIO

PE11 60 GPIO PE12 61 GPIO

PE13 62 GPIO PE14 63 GPIO

PE15 64 GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

EFM32TG11 Family Data Sheet

Pin Definitions

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5.6 EFM32TG11B5xx in QFN64 Device Pinout

Figure 5.6. EFM32TG11B5xx in QFN64 Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 5.14 GPIO Functionality Table or 5.15 Alternate Functionality Overview.

Table 5.6. EFM32TG11B5xx in QFN64 Device Pinout

Pin Name Pin(s) Description Pin Name Pin(s) Description

VREGVSS 0

38 Voltage regulator VSS PA0 1 GPIO

PA1 2 GPIO PA2 3 GPIO

PA3 4 GPIO PA4 5 GPIO

PA5 6 GPIO PA6 7 GPIO

IOVDD0

Digital IO power supply 0. PB3 9 GPIO

EFM32TG11 Family Data Sheet

Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

PB4 10 GPIO PB5 11 GPIO

PB6 12 GPIO PC4 13 GPIO

PC5 14 GPIO PB7 15 GPIO

PB8 16 GPIO PA8 17 GPIO

PA12 18 GPIO PA13 19 GPIO (5V)

PA14 20 GPIO RESETn 21

Reset input, active low. To apply an ex-

ternal reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

PB11 22 GPIO PB12 23 GPIO

AVDD 24

28 Analog power supply. PB13 25 GPIO

PB14 26 GPIO PD0 29 GPIO (5V)

PD1 30 GPIO PD3 31 GPIO

PD4 32 GPIO PD5 33 GPIO

PD6 34 GPIO PD7 35 GPIO

PD8 36 GPIO PC7 37 GPIO

VREGSW 39 DCDC regulator switching node VREGVDD 40 Voltage regulator VDD input

DVDD 41 Digital power supply. DECOUPLE 42

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PE4 43 GPIO PE5 44 GPIO

PE6 45 GPIO PE7 46 GPIO

PC12 47 GPIO (5V) PC13 48 GPIO (5V)

PF0 49 GPIO (5V) PF1 50 GPIO (5V)

PF2 51 GPIO PF3 52 GPIO

PF4 53 GPIO PF5 54 GPIO

PE8 56 GPIO PE9 57 GPIO

PE10 58 GPIO PE11 59 GPIO

PE12 60 GPIO PE13 61 GPIO

PE14 62 GPIO PE15 63 GPIO

PA15 64 GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

EFM32TG11 Family Data Sheet

Pin Definitions

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5.7 EFM32TG11B3xx in QFN64 Device Pinout

Figure 5.7. EFM32TG11B3xx in QFN64 Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 5.14 GPIO Functionality Table or 5.15 Alternate Functionality Overview.

Table 5.7. EFM32TG11B3xx in QFN64 Device Pinout

Pin Name Pin(s) Description Pin Name Pin(s) Description

VREGVSS 0 Voltage regulator VSS PA0 1 GPIO

PA1 2 GPIO PA2 3 GPIO

PA3 4 GPIO PA4 5 GPIO

PA5 6 GPIO PA6 7 GPIO

IOVDD0

Digital IO power supply 0. PB3 9 GPIO

PB4 10 GPIO PB5 11 GPIO

EFM32TG11 Family Data Sheet

Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

PB6 12 GPIO PC4 13 GPIO

PC5 14 GPIO PB7 15 GPIO

PB8 16 GPIO PA12 17 GPIO

PA13 18 GPIO (5V) PA14 19 GPIO

RESETn 20

Reset input, active low. To apply an ex-

ternal reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

PB11 21 GPIO

PB12 22 GPIO AVDD 23

27 Analog power supply.

PB13 24 GPIO PB14 25 GPIO

PD0 28 GPIO (5V) PD1 29 GPIO

PD2 30 GPIO (5V) PD3 31 GPIO

PD4 32 GPIO PD5 33 GPIO

PD6 34 GPIO PD7 35 GPIO

PD8 36 GPIO PC6 37 GPIO

PC7 38 GPIO DVDD 39 Digital power supply.

DECOUPLE 40

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PE4 41 GPIO

PE5 42 GPIO PE6 43 GPIO

PE7 44 GPIO PC12 45 GPIO (5V)

PC13 46 GPIO (5V) PC14 47 GPIO (5V)

PC15 48 GPIO (5V) PF0 49 GPIO (5V)

PF1 50 GPIO (5V) PF2 51 GPIO

PF3 52 GPIO PF4 53 GPIO

PF5 54 GPIO PE8 56 GPIO

PE9 57 GPIO PE10 58 GPIO

PE11 59 GPIO PE12 60 GPIO

PE13 61 GPIO PE14 62 GPIO

PE15 63 GPIO PA15 64 GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

EFM32TG11 Family Data Sheet

Pin Definitions

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5.8 EFM32TG11B1xx in QFN64 Device Pinout

Figure 5.8. EFM32TG11B1xx in QFN64 Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 5.14 GPIO Functionality Table or 5.15 Alternate Functionality Overview.

Table 5.8. EFM32TG11B1xx in QFN64 Device Pinout

Pin Name Pin(s) Description Pin Name Pin(s) Description

VREGVSS 0 Voltage regulator VSS PA0 1 GPIO

PA1 2 GPIO PA2 3 GPIO

PA3 4 GPIO PA4 5 GPIO

PA5 6 GPIO PA6 7 GPIO

IOVDD0

Digital IO power supply 0. PC0 9 GPIO (5V)

PC1 10 GPIO (5V) PC2 11 GPIO (5V)

EFM32TG11 Family Data Sheet

Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

PC3 12 GPIO (5V) PC4 13 GPIO

PC5 14 GPIO PB7 15 GPIO

PB8 16 GPIO PA8 17 GPIO

PA9 18 GPIO PA10 19 GPIO

RESETn 20

Reset input, active low. To apply an ex-

ternal reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

PB11 21 GPIO

PB12 22 GPIO AVDD 23

27 Analog power supply.

PB13 24 GPIO PB14 25 GPIO

PD0 28 GPIO (5V) PD1 29 GPIO

PD2 30 GPIO (5V) PD3 31 GPIO

PD4 32 GPIO PD5 33 GPIO

PD6 34 GPIO PD7 35 GPIO

PD8 36 GPIO PC6 37 GPIO

PC7 38 GPIO DVDD 39 Digital power supply.

DECOUPLE 40

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PC8 41 GPIO

PC9 42 GPIO PC10 43 GPIO (5V)

PC11 44 GPIO (5V) PC12 45 GPIO (5V)

PC13 46 GPIO (5V) PC14 47 GPIO (5V)

PC15 48 GPIO (5V) PF0 49 GPIO (5V)

PF1 50 GPIO (5V) PF2 51 GPIO

PF3 52 GPIO PF4 53 GPIO

PF5 54 GPIO PE8 56 GPIO

PE9 57 GPIO PE10 58 GPIO

PE11 59 GPIO PE12 60 GPIO

PE13 61 GPIO PE14 62 GPIO

PE15 63 GPIO PA15 64 GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

EFM32TG11 Family Data Sheet

Pin Definitions

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5.9 EFM32TG11B5xx in QFP48 Device Pinout

Figure 5.9. EFM32TG11B5xx in QFP48 Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 5.14 GPIO Functionality Table or 5.15 Alternate Functionality Overview.

Table 5.9. EFM32TG11B5xx in QFP48 Device Pinout

Pin Name Pin(s) Description Pin Name Pin(s) Description

PA0 1 GPIO PA1 2 GPIO

PA2 3 GPIO IOVDD0

Digital IO power supply 0.

VSS

Ground PB3 6 GPIO

PB4 7 GPIO PB5 8 GPIO

PB6 9 GPIO PB7 10 GPIO

EFM32TG11 Family Data Sheet

Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

PB8 11 GPIO PA8 12 GPIO

PA12 13 GPIO PA14 14 GPIO

RESETn 15

Reset input, active low. To apply an ex-

ternal reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

PB11 16 GPIO

AVDD 18

22 Analog power supply. PB13 19 GPIO

PB14 20 GPIO PD4 23 GPIO

PD5 24 GPIO PD6 25 GPIO

PD7 26 GPIO PD8 27 GPIO

VREGVSS 28 Voltage regulator VSS VREGSW 29 DCDC regulator switching node

VREGVDD 30 Voltage regulator VDD input DVDD 31 Digital power supply.

DECOUPLE 32

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PE4 33 GPIO

PE5 34 GPIO PE6 35 GPIO

PE7 36 GPIO PF0 37 GPIO (5V)

PF1 38 GPIO (5V) PF2 39 GPIO

PF3 40 GPIO PF4 41 GPIO

PF5 42 GPIO PE10 45 GPIO

PE11 46 GPIO PE12 47 GPIO

PE13 48 GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

EFM32TG11 Family Data Sheet

Pin Definitions

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5.10 EFM32TG11B3xx in QFP48 Device Pinout

Figure 5.10. EFM32TG11B3xx in QFP48 Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 5.14 GPIO Functionality Table or 5.15 Alternate Functionality Overview.

Table 5.10. EFM32TG11B3xx in QFP48 Device Pinout

Pin Name Pin(s) Description Pin Name Pin(s) Description

PA0 1 GPIO PA1 2 GPIO

PA2 3 GPIO IOVDD0

Digital IO power supply 0.

VSS

Ground PB3 6 GPIO

PB4 7 GPIO PB5 8 GPIO

PB6 9 GPIO PC4 10 GPIO

EFM32TG11 Family Data Sheet

Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

PB7 11 GPIO PB8 12 GPIO

PA12 13 GPIO PA13 14 GPIO (5V)

PA14 15 GPIO RESETn 16

Reset input, active low. To apply an ex-

ternal reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

PB11 17 GPIO AVDD 19

23 Analog power supply.

PB13 20 GPIO PB14 21 GPIO

PD4 24 GPIO PD5 25 GPIO

PD6 26 GPIO PD7 27 GPIO

DVDD 28 Digital power supply. DECOUPLE 29

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PE4 30 GPIO PE5 31 GPIO

PE6 32 GPIO PE7 33 GPIO

PC13 34 GPIO (5V) PC14 35 GPIO (5V)

PC15 36 GPIO (5V) PF0 37 GPIO (5V)

PF1 38 GPIO (5V) PF2 39 GPIO

PF3 40 GPIO PF4 41 GPIO

PF5 42 GPIO PE10 45 GPIO

PE11 46 GPIO PE12 47 GPIO

PE13 48 GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

EFM32TG11 Family Data Sheet

Pin Definitions

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5.11 EFM32TG11B1xx in QFP48 Device Pinout

Figure 5.11. EFM32TG11B1xx in QFP48 Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 5.14 GPIO Functionality Table or 5.15 Alternate Functionality Overview.

Table 5.11. EFM32TG11B1xx in QFP48 Device Pinout

Pin Name Pin(s) Description Pin Name Pin(s) Description

PA0 1 GPIO PA1 2 GPIO

PA2 3 GPIO IOVDD0

Digital IO power supply 0.

VSS

Ground PC0 6 GPIO (5V)

PC1 7 GPIO (5V) PC2 8 GPIO (5V)

PC3 9 GPIO (5V) PC4 10 GPIO

EFM32TG11 Family Data Sheet

Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

PB7 11 GPIO PB8 12 GPIO

PA8 13 GPIO PA9 14 GPIO

PA10 15 GPIO RESETn 16

Reset input, active low. To apply an ex-

ternal reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

PB11 17 GPIO AVDD 19

23 Analog power supply.

PB13 20 GPIO PB14 21 GPIO

PD4 24 GPIO PD5 25 GPIO

PD6 26 GPIO PD7 27 GPIO

DVDD 28 Digital power supply. DECOUPLE 29

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PC8 30 GPIO PC9 31 GPIO

PC10 32 GPIO (5V) PC11 33 GPIO (5V)

PC13 34 GPIO (5V) PC14 35 GPIO (5V)

PC15 36 GPIO (5V) PF0 37 GPIO (5V)

PF1 38 GPIO (5V) PF2 39 GPIO

PF3 40 GPIO PF4 41 GPIO

PF5 42 GPIO PE10 45 GPIO

PE11 46 GPIO PE12 47 GPIO

PE13 48 GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

EFM32TG11 Family Data Sheet

Pin Definitions

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5.12 EFM32TG11B5xx in QFN32 Device Pinout

Figure 5.12. EFM32TG11B5xx in QFN32 Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 5.14 GPIO Functionality Table or 5.15 Alternate Functionality Overview.

Table 5.12. EFM32TG11B5xx in QFN32 Device Pinout

Pin Name Pin(s) Description Pin Name Pin(s) Description

VREGVSS 0

19 Voltage regulator VSS PA0 1 GPIO

PA1 2 GPIO PA2 3 GPIO

IOVDD0

Digital IO power supply 0. PC0 5 GPIO (5V)

PB7 6 GPIO PB8 7 GPIO

EFM32TG11 Family Data Sheet

Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

PA14 8 GPIO RESETn 9

Reset input, active low. To apply an ex-

ternal reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

PB11 10 GPIO AVDD 11 Analog power supply.

PB13 12 GPIO PB14 13 GPIO

PD4 15 GPIO PD5 16 GPIO

PD6 17 GPIO PD7 18 GPIO

VREGSW 20 DCDC regulator switching node VREGVDD 21 Voltage regulator VDD input

DVDD 22 Digital power supply. DECOUPLE 23

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PE4 24 GPIO PE5 25 GPIO

PC15 26 GPIO (5V) PF0 27 GPIO (5V)

PF1 28 GPIO (5V) PF2 29 GPIO

PE11 31 GPIO PE12 32 GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

EFM32TG11 Family Data Sheet

Pin Definitions

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5.13 EFM32TG11B1xx in QFN32 Device Pinout

Figure 5.13. EFM32TG11B1xx in QFN32 Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see 5.14 GPIO Functionality Table or 5.15 Alternate Functionality Overview.

Table 5.13. EFM32TG11B1xx in QFN32 Device Pinout

Pin Name Pin(s) Description Pin Name Pin(s) Description

VREGVSS 0 Voltage regulator VSS PA0 1 GPIO

PA1 2 GPIO PA2 3 GPIO

IOVDD0

Digital IO power supply 0. PC0 5 GPIO (5V)

PC1 6 GPIO (5V) PB7 7 GPIO

EFM32TG11 Family Data Sheet

Pin Definitions

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Pin Name Pin(s) Description Pin Name Pin(s) Description

PB8 8 GPIO RESETn 9

Reset input, active low. To apply an ex-

ternal reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

PB11 10 GPIO AVDD 11

15 Analog power supply.

PB13 12 GPIO PB14 13 GPIO

PD4 16 GPIO PD5 17 GPIO

PD6 18 GPIO PD7 19 GPIO

DVDD 20 Digital power supply. DECOUPLE 21

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin.

PC13 22 GPIO (5V) PC14 23 GPIO (5V)

PC15 24 GPIO (5V) PF0 25 GPIO (5V)

PF1 26 GPIO (5V) PF2 27 GPIO

PE10 29 GPIO PE11 30 GPIO

PE12 31 GPIO PE13 32 GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

EFM32TG11 Family Data Sheet

Pin Definitions

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5.14 GPIO Functionality Table

A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of each GPIO

pin, followed by the functionality available on that pin. Refer to 5.15 Alternate Functionality Overview for a list of GPIO locations availa-

ble for each function.

Table 5.14. GPIO Functionality Table

GPIO Name Pin Alternate Functionality / Description

Analog Timers Communication Other

PA0 BUSBY BUSAX

LCD_SEG13

TIM0_CC0 #0 TIM0_CC1

#7 PCNT0_S0IN #4

US1_RX #5 US3_TX #0

LEU0_RX #4 I2C0_SDA

CMU_CLK2 #0 PRS_CH0

#0 PRS_CH3 #3

GPIO_EM4WU0

PA1 BUSAY BUSBX

LCD_SEG14

TIM0_CC0 #7 TIM0_CC1

#0 PCNT0_S1IN #4 US3_RX #0 I2C0_SCL #0 CMU_CLK1 #0 PRS_CH1

PA2 BUSBY BUSAX

LCD_SEG15 TIM0_CC2 #0 US1_RX #6 US3_CLK #0 CMU_CLK0 #0

PA3 BUSAY BUSBX

LCD_SEG16 TIM0_CDTI0 #0 US3_CS #0 U0_TX #2

CMU_CLK2 #1

CMU_CLK2 #4

CMU_CLKI0 #1 LES_AL-

TEX2

PA4 BUSBY BUSAX

LCD_SEG17 TIM0_CDTI1 #0 US3_CTS #0 U0_RX #2 LES_ALTEX3

PA5 BUSAY BUSBX

LCD_SEG18 TIM0_CDTI2 #0 US3_RTS #0 U0_CTS #2 LES_ALTEX4 ACMP1_O

PA6 BUSBY BUSAX

LCD_SEG19 WTIM0_CC0 #1 U0_RTS #2 PRS_CH6 #0 ACMP0_O

#4 GPIO_EM4WU1

PB3

BUSAY BUSBX

LCD_SEG20 /

LCD_COM4

TIM1_CC3 #2

WTIM0_CC0 #6 US2_TX #1 US3_TX #2 ACMP0_O #7

PB4

BUSBY BUSAX

LCD_SEG21 /

LCD_COM5

WTIM0_CC1 #6 US2_RX #1

PB5

BUSAY BUSBX

LCD_SEG22 /

LCD_COM6

WTIM0_CC2 #6

PCNT0_S0IN #6

US0_RTS #4 US2_CLK

PB6

BUSBY BUSAX

LCD_SEG23 /

LCD_COM7

TIM0_CC0 #3

PCNT0_S1IN #6 US0_CTS #4 US2_CS #1

PC0

VDAC0_OUT0ALT /

OPA0_OUTALT #0 BU-

SACMP0Y BUSACMP0X

TIM0_CC1 #3

PCNT0_S0IN #2

CAN0_RX #0 US0_TX #5

US1_TX #0 US1_CS #4

US2_RTS #0 US3_CS #3

I2C0_SDA #4

LES_CH0 PRS_CH2 #0

PC1

VDAC0_OUT0ALT /

OPA0_OUTALT #1 BU-

SACMP0Y BUSACMP0X

TIM0_CC2 #3

WTIM0_CC0 #7

PCNT0_S1IN #2

CAN0_TX #0 US0_RX #5

US1_TX #4 US1_RX #0

US2_CTS #0 US3_RTS

#1 I2C0_SCL #4

LES_CH1 PRS_CH3 #0

PC2

VDAC0_OUT0ALT /

OPA0_OUTALT #2 BU-

SACMP0Y BUSACMP0X

TIM0_CDTI0 #3

WTIM0_CC1 #7 US1_RX #4 US2_TX #0 LES_CH2

PC3

VDAC0_OUT0ALT /

OPA0_OUTALT #3 BU-

SACMP0Y BUSACMP0X

TIM0_CDTI1 #3

WTIM0_CC2 #7 US1_CLK #4 US2_RX #0 LES_CH3

EFM32TG11 Family Data Sheet

Pin Definitions

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GPIO Name Pin Alternate Functionality / Description

Analog Timers Communication Other

PC4

BUSACMP0Y BU-

SACMP0X OPA0_P

LCD_SEG24

TIM0_CC0 #5

TIM0_CDTI2 #3 LE-

TIM0_OUT0 #3

US2_CLK #0 U0_TX #4

I2C1_SDA #0

LES_CH4

GPIO_EM4WU6

PC5

BUSACMP0Y BU-

SACMP0X OPA0_N

LCD_SEG25

TIM0_CC1 #5 LE-

TIM0_OUT1 #3

US2_CS #0 U0_RX #4

I2C1_SCL #0 LES_CH5

PB7 LFXTAL_P TIM0_CDTI0 #4

TIM1_CC0 #3

US0_TX #4 US1_CLK #0

US3_RX #2 U0_CTS #4

PB8 LFXTAL_N TIM0_CDTI1 #4

TIM1_CC1 #3

US0_RX #4 US1_CS #0

U0_RTS #4 CMU_CLKI0 #2

PA8 BU_STAT TIM0_CC0 #6 LE-

TIM0_OUT0 #6 US2_RX #2

PA9 BUSAY BUSBX

LCD_SEG26

TIM0_CC1 #6 LE-

TIM0_OUT1 #6 US2_CLK #2

PA10 BUSBY BUSAX

LCD_SEG27 TIM0_CC2 #6 US2_CS #2

PA12 BU_VOUT WTIM0_CDTI0 #2 US0_CLK #5 US2_RTS

CMU_CLK0 #5 ACMP1_O

PA13 BUSAY BUSBX TIM0_CC2 #7

WTIM0_CDTI1 #2 US0_CS #5 US2_TX #3

PA14 BUSBY BUSAX

LCD_BEXT WTIM0_CDTI2 #2 US1_TX #6 US2_RX #3

US3_RTS #2 ACMP1_O #4

PB11

BUSAY BUSBX

VDAC0_OUT0 /

OPA0_OUT LCD_SEG28

TIM0_CDTI2 #4

TIM1_CC2 #3 LE-

TIM0_OUT0 #1

PCNT0_S1IN #7

US0_CTS #5 US1_CLK

#5 US2_CS #3 I2C1_SDA

CMU_CLK1 #5

CMU_CLKI0 #7

ACMP0_O #3

GPIO_EM4WU7

PB12

BUSBY BUSAX

VDAC0_OUT1 /

OPA1_OUT LCD_SEG29

TIM1_CC3 #3 LE-

TIM0_OUT1 #1

PCNT0_S0IN #7

US2_CTS #1 I2C1_SCL

PB13 BUSAY BUSBX

HFXTAL_P WTIM1_CC0 #0 US0_CLK #4 US1_CTS

#5 LEU0_TX #1

CMU_CLKI0 #3

PRS_CH7 #0

PB14 BUSBY BUSAX

HFXTAL_N WTIM1_CC1 #0 US0_CS #4 US1_RTS #5

LEU0_RX #1 PRS_CH6 #1

PD0

VDAC0_OUT0ALT /

OPA0_OUTALT #4

OPA2_OUTALT BU-

SADC0Y BUSADC0X

WTIM1_CC2 #0 CAN0_RX #2 US1_TX #1

PD1

VDAC0_OUT1ALT /

OPA1_OUTALT #4 BU-

SADC0Y BUSADC0X

OPA3_OUT

TIM0_CC0 #2

WTIM1_CC3 #0 CAN0_TX #2 US1_RX #1

PD2 BUSADC0Y BUSADC0X TIM0_CC1 #2

WTIM1_CC0 #1 US1_CLK #1

PD3 BUSADC0Y BUSADC0X

OPA2_N LCD_SEG30

TIM0_CC2 #2

WTIM1_CC1 #1 US1_CS #1

PD4 BUSADC0Y BUSADC0X

OPA2_P LCD_SEG31

WTIM0_CDTI0 #4

WTIM1_CC2 #1

US1_CTS #1 US3_CLK

#2 LEU0_TX #0

I2C1_SDA #3

CMU_CLKI0 #0

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 101

GPIO Name Pin Alternate Functionality / Description

Analog Timers Communication Other

PD5 BUSADC0Y BUSADC0X

OPA2_OUT

WTIM0_CDTI1 #4

WTIM1_CC3 #1

US1_RTS #1 U0_CTS #5

LEU0_RX #0 I2C1_SCL

PD6

BUSADC0Y BUSADC0X

ADC0_EXTP

VDAC0_EXT OPA1_P

TIM1_CC0 #4

WTIM0_CDTI2 #4

WTIM1_CC0 #2 LE-

TIM0_OUT0 #0

PCNT0_S0IN #3

US0_RTS #5 US1_RX #2

US2_CTS #5 US3_CTS

#2 U0_RTS #5 I2C0_SDA

CMU_CLK2 #2 LES_AL-

TEX0 PRS_CH5 #2

ACMP0_O #2

PD7 BUSADC0Y BUSADC0X

ADC0_EXTN OPA1_N

TIM1_CC1 #4

WTIM1_CC1 #2 LE-

TIM0_OUT1 #0

PCNT0_S1IN #3

US1_TX #2 US3_CLK #1

U0_TX #6 I2C0_SCL #1

CMU_CLK0 #2 LES_AL-

TEX1 ACMP1_O #2

PD8 BU_VIN WTIM1_CC2 #2 US2_RTS #5 CMU_CLK1 #1

PC6

BUSACMP0Y BU-

SACMP0X OPA3_P

LCD_SEG32

WTIM1_CC3 #2 US0_RTS #2 US1_CTS

#3 I2C0_SDA #2 LES_CH6

PC7

BUSACMP0Y BU-

SACMP0X OPA3_N

LCD_SEG33

WTIM1_CC0 #3 US0_CTS #2 US1_RTS

#3 I2C0_SCL #2 LES_CH7

PE4 BUSDY BUSCX

LCD_COM0

WTIM0_CC0 #0

WTIM1_CC1 #4

US0_CS #1 US1_CS #5

US3_CS #1 U0_RX #6

I2C0_SDA #7

PE5 BUSCY BUSDX

LCD_COM1

WTIM0_CC1 #0

WTIM1_CC2 #4

US0_CLK #1 US1_CLK

#6 US3_CTS #1

I2C0_SCL #7

PE6 BUSDY BUSCX

LCD_COM2

WTIM0_CC2 #0

WTIM1_CC3 #4 US0_RX #1 US3_TX #1 PRS_CH6 #2

PE7 BUSCY BUSDX

LCD_COM3 WTIM1_CC0 #5 US0_TX #1 US3_RX #1 PRS_CH7 #2

PC8 BUSACMP1Y BU-

SACMP1X LCD_SEG34 US0_CS #2 LES_CH8 PRS_CH4 #0

PC9 BUSACMP1Y BU-

SACMP1X LCD_SEG35 US0_CLK #2 LES_CH9 PRS_CH5 #0

GPIO_EM4WU2

PC10 BUSACMP1Y BU-

SACMP1X US0_RX #2 LES_CH10

PC11 BUSACMP1Y BU-

SACMP1X US0_TX #2 I2C1_SDA #4 LES_CH11

PC12

VDAC0_OUT1ALT /

OPA1_OUTALT #0 BU-

SACMP1Y BUSACMP1X

TIM1_CC3 #0

US0_RTS #3 US1_CTS

#4 US2_CTS #4 U0_RTS

CMU_CLK0 #1

LES_CH12

PC13

VDAC0_OUT1ALT /

OPA1_OUTALT #1 BU-

SACMP1Y BUSACMP1X

TIM0_CDTI0 #1

TIM1_CC0 #0 TIM1_CC2

#4 PCNT0_S0IN #0

US0_CTS #3 US1_RTS

#4 US2_RTS #4 U0_CTS

LES_CH13

PC14

VDAC0_OUT1ALT /

OPA1_OUTALT #2 BU-

SACMP1Y BUSACMP1X

TIM0_CDTI1 #1

TIM1_CC1 #0 TIM1_CC3

#4 LETIM0_OUT0 #5

PCNT0_S1IN #0

US0_CS #3 US1_CS #3

US2_RTS #3 US3_CS #2

U0_TX #3 LEU0_TX #5

LES_CH14 PRS_CH0 #2

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 102

GPIO Name Pin Alternate Functionality / Description

Analog Timers Communication Other

PC15

VDAC0_OUT1ALT /

OPA1_OUTALT #3 BU-

SACMP1Y BUSACMP1X

TIM0_CDTI2 #1

TIM1_CC2 #0

WTIM0_CC0 #4 LE-

TIM0_OUT1 #5

US0_CLK #3 US1_CLK

#3 US3_RTS #3 U0_RX

#3 LEU0_RX #5

LES_CH15 PRS_CH1 #2

PF0 BUSDY BUSCX

TIM0_CC0 #4

WTIM0_CC1 #4 LE-

TIM0_OUT0 #2

CAN0_RX #1 US1_CLK

#2 US2_TX #5 LEU0_TX

#3 I2C0_SDA #5

DBG_SWCLKTCK

BOOT_TX

PF1 BUSCY BUSDX

TIM0_CC1 #4

WTIM0_CC2 #4 LE-

TIM0_OUT1 #2

US1_CS #2 US2_RX #5

U0_TX #5 LEU0_RX #3

I2C0_SCL #5

PRS_CH4 #2

DBG_SWDIOTMS

GPIO_EM4WU3

BOOT_RX

PF2 BUSDY BUSCX

LCD_SEG0

TIM0_CC2 #4 TIM1_CC0

CAN0_TX #1 US1_TX #5

US2_CLK #5 U0_RX #5

LEU0_TX #4 I2C1_SCL

CMU_CLK0 #4 PRS_CH0

#3 ACMP1_O #0

DBG_TDO

GPIO_EM4WU4

PF3 BUSCY BUSDX

LCD_SEG1

TIM0_CDTI0 #2

TIM1_CC1 #5 US1_CTS #2 CMU_CLK1 #4 PRS_CH0

PF4 BUSDY BUSCX

LCD_SEG2

TIM0_CDTI1 #2

TIM1_CC2 #5 US1_RTS #2 PRS_CH1 #1

PF5 BUSCY BUSDX

LCD_SEG3

TIM0_CDTI2 #2

TIM1_CC3 #6 US2_CS #5 PRS_CH2 #1 DBG_TDI

PE8 BUSDY BUSCX

LCD_SEG4 PRS_CH3 #1

PE9 BUSCY BUSDX

LCD_SEG5

PE10 BUSDY BUSCX

LCD_SEG6

TIM1_CC0 #1

WTIM0_CDTI0 #0 US0_TX #0 PRS_CH2 #2

GPIO_EM4WU9

PE11 BUSCY BUSDX

LCD_SEG7

TIM1_CC1 #1

WTIM0_CDTI1 #0 US0_RX #0 LES_ALTEX5 PRS_CH3

PE12 BUSDY BUSCX

LCD_SEG8

TIM1_CC2 #1

WTIM0_CDTI2 #0 LE-

TIM0_OUT0 #4

US0_RX #3 US0_CLK #0

I2C0_SDA #6

CMU_CLK1 #2

CMU_CLKI0 #6 LES_AL-

TEX6 PRS_CH1 #3

PE13 BUSCY BUSDX

LCD_SEG9

TIM1_CC3 #1 LE-

TIM0_OUT1 #4

US0_TX #3 US0_CS #0

I2C0_SCL #6

LES_ALTEX7 PRS_CH2

#3 ACMP0_O #0

GPIO_EM4WU5

PE14 BUSDY BUSCX

LCD_SEG10

US0_CTS #0 LEU0_TX

PE15 BUSCY BUSDX

LCD_SEG11

US0_RTS #0 LEU0_RX

PA15 BUSAY BUSBX

LCD_SEG12 US2_CLK #3

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 103

5.15 Alternate Functionality Overview

A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alter-

nate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings and the associated GPIO

pin. Refer to 5.14 GPIO Functionality Table for a list of functions available on each GPIO pin.

Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout

is shown in the column corresponding to LOCATION 0.

Table 5.15. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

ACMP0_O

0: PE13

2: PD6

3: PB11

4: PA6

7: PB3

Analog comparator ACMP0, digital output.

ACMP1_O

0: PF2

2: PD7

3: PA12

4: PA14

7: PA5

Analog comparator ACMP1, digital output.

ADC0_EXTN

0: PD7

Analog to digital converter ADC0 external reference input negative pin.

ADC0_EXTP

0: PD6

Analog to digital converter ADC0 external reference input positive pin.

BOOT_RX

0: PF1

Bootloader RX.

BOOT_TX

0: PF0

Bootloader TX.

BU_STAT

0: PA8

Backup Power Domain status, whether or not the system is in backup mode.

BU_VIN

0: PD8

Battery input for Backup Power Domain.

BU_VOUT

0: PA12

Power output for Backup Power Domain.

CAN0_RX

0: PC0

1: PF0

2: PD0 CAN0 RX.

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 104

Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

CAN0_TX

0: PC1

1: PF2

2: PD1 CAN0 TX.

CMU_CLK0

0: PA2

1: PC12

2: PD7

4: PF2

5: PA12 Clock Management Unit, clock output number 0.

CMU_CLK1

0: PA1

1: PD8

2: PE12

4: PF3

5: PB11 Clock Management Unit, clock output number 1.

CMU_CLK2

0: PA0

1: PA3

2: PD6

4: PA3

Clock Management Unit, clock output number 2.

CMU_CLKI0

0: PD4

1: PA3

2: PB8

3: PB13

6: PE12

7: PB11

Clock Management Unit, clock input number 0.

DBG_SWCLKTCK

0: PF0 Debug-interface Serial Wire clock input and JTAG Test Clock.

Note that this function is enabled to the pin out of reset, and has a built-in pull down.

DBG_SWDIOTMS

0: PF1 Debug-interface Serial Wire data input / output and JTAG Test Mode Select.

Note that this function is enabled to the pin out of reset, and has a built-in pull up.

DBG_TDI

0: PF5 Debug-interface JTAG Test Data In.

Note that this function becomes available after the first valid JTAG command is re-

ceived, and has a built-in pull up when JTAG is active.

DBG_TDO

0: PF2 Debug-interface JTAG Test Data Out.

Note that this function becomes available after the first valid JTAG command is re-

ceived.

GPIO_EM4WU0

0: PA0

Pin can be used to wake the system up from EM4

GPIO_EM4WU1

0: PA6

Pin can be used to wake the system up from EM4

GPIO_EM4WU2

0: PC9

Pin can be used to wake the system up from EM4

GPIO_EM4WU3

0: PF1

Pin can be used to wake the system up from EM4

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 105

Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

GPIO_EM4WU4

0: PF2

Pin can be used to wake the system up from EM4

GPIO_EM4WU5

0: PE13

Pin can be used to wake the system up from EM4

GPIO_EM4WU6

0: PC4

Pin can be used to wake the system up from EM4

GPIO_EM4WU7

0: PB11

Pin can be used to wake the system up from EM4

GPIO_EM4WU9

0: PE10

Pin can be used to wake the system up from EM4

HFXTAL_N

0: PB14

High Frequency Crystal negative pin. Also used as external optional clock input pin.

HFXTAL_P

0: PB13

High Frequency Crystal positive pin.

I2C0_SCL

0: PA1

1: PD7

2: PC7

4: PC1

5: PF1

6: PE13

7: PE5

I2C0 Serial Clock Line input / output.

I2C0_SDA

0: PA0

1: PD6

2: PC6

4: PC0

5: PF0

6: PE12

7: PE4

I2C0 Serial Data input / output.

I2C1_SCL

0: PC5

1: PB12

3: PD5

4: PF2

I2C1 Serial Clock Line input / output.

I2C1_SDA

0: PC4

1: PB11

3: PD4

4: PC11

I2C1 Serial Data input / output.

LCD_BEXT

0: PA14 LCD external supply bypass in step down or charge pump mode. If using the LCD in

step-down or charge pump mode, a 1 uF (minimum) capacitor between this pin and

VSS is required.

To reduce supply ripple, a larger capcitor of approximately 1000 times the total LCD

segment capacitance may be used.

If using the LCD with the internal supply source, this pin may be left unconnected or

used as a GPIO.

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 106

Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

LCD_COM0

0: PE4

LCD driver common line number 0.

LCD_COM1

0: PE5

LCD driver common line number 1.

LCD_COM2

0: PE6

LCD driver common line number 2.

LCD_COM3

0: PE7

LCD driver common line number 3.

LCD_SEG0

0: PF2

LCD segment line 0.

LCD_SEG1

0: PF3

LCD segment line 1.

LCD_SEG2

0: PF4

LCD segment line 2.

LCD_SEG3

0: PF5

LCD segment line 3.

LCD_SEG4

0: PE8

LCD segment line 4.

LCD_SEG5

0: PE9

LCD segment line 5.

LCD_SEG6

0: PE10

LCD segment line 6.

LCD_SEG7

0: PE11

LCD segment line 7.

LCD_SEG8

0: PE12

LCD segment line 8.

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 107

Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

LCD_SEG9

0: PE13

LCD segment line 9.

LCD_SEG10

0: PE14

LCD segment line 10.

LCD_SEG11

0: PE15

LCD segment line 11.

LCD_SEG12

0: PA15

LCD segment line 12.

LCD_SEG13

0: PA0

LCD segment line 13.

LCD_SEG14

0: PA1

LCD segment line 14.

LCD_SEG15

0: PA2

LCD segment line 15.

LCD_SEG16

0: PA3

LCD segment line 16.

LCD_SEG17

0: PA4

LCD segment line 17.

LCD_SEG18

0: PA5

LCD segment line 18.

LCD_SEG19

0: PA6

LCD segment line 19.

LCD_SEG20 /

LCD_COM4

0: PB3

LCD segment line 20. This pin may also be used as LCD COM line 4

LCD_SEG21 /

LCD_COM5

0: PB4

LCD segment line 21. This pin may also be used as LCD COM line 5

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 108

Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

LCD_SEG22 /

LCD_COM6

0: PB5

LCD segment line 22. This pin may also be used as LCD COM line 6

LCD_SEG23 /

LCD_COM7

0: PB6

LCD segment line 23. This pin may also be used as LCD COM line 7

LCD_SEG24

0: PC4

LCD segment line 24.

LCD_SEG25

0: PC5

LCD segment line 25.

LCD_SEG26

0: PA9

LCD segment line 26.

LCD_SEG27

0: PA10

LCD segment line 27.

LCD_SEG28

0: PB11

LCD segment line 28.

LCD_SEG29

0: PB12

LCD segment line 29.

LCD_SEG30

0: PD3

LCD segment line 30.

LCD_SEG31

0: PD4

LCD segment line 31.

LCD_SEG32

0: PC6

LCD segment line 32.

LCD_SEG33

0: PC7

LCD segment line 33.

LCD_SEG34

0: PC8

LCD segment line 34.

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 109

Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

LCD_SEG35

0: PC9

LCD segment line 35.

LES_ALTEX0

0: PD6

LESENSE alternate excite output 0.

LES_ALTEX1

0: PD7

LESENSE alternate excite output 1.

LES_ALTEX2

0: PA3

LESENSE alternate excite output 2.

LES_ALTEX3

0: PA4

LESENSE alternate excite output 3.

LES_ALTEX4

0: PA5

LESENSE alternate excite output 4.

LES_ALTEX5

0: PE11

LESENSE alternate excite output 5.

LES_ALTEX6

0: PE12

LESENSE alternate excite output 6.

LES_ALTEX7

0: PE13

LESENSE alternate excite output 7.

LES_CH0

0: PC0

LESENSE channel 0.

LES_CH1

0: PC1

LESENSE channel 1.

LES_CH2

0: PC2

LESENSE channel 2.

LES_CH3

0: PC3

LESENSE channel 3.

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 110

Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

LES_CH4

0: PC4

LESENSE channel 4.

LES_CH5

0: PC5

LESENSE channel 5.

LES_CH6

0: PC6

LESENSE channel 6.

LES_CH7

0: PC7

LESENSE channel 7.

LES_CH8

0: PC8

LESENSE channel 8.

LES_CH9

0: PC9

LESENSE channel 9.

LES_CH10

0: PC10

LESENSE channel 10.

LES_CH11

0: PC11

LESENSE channel 11.

LES_CH12

0: PC12

LESENSE channel 12.

LES_CH13

0: PC13

LESENSE channel 13.

LES_CH14

0: PC14

LESENSE channel 14.

LES_CH15

0: PC15

LESENSE channel 15.

LETIM0_OUT0

0: PD6

1: PB11

2: PF0

3: PC4

4: PE12

5: PC14

6: PA8 Low Energy Timer LETIM0, output channel 0.

EFM32TG11 Family Data Sheet

Pin Definitions

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Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

LETIM0_OUT1

0: PD7

1: PB12

2: PF1

3: PC5

4: PE13

5: PC15

6: PA9 Low Energy Timer LETIM0, output channel 1.

LEU0_RX

0: PD5

1: PB14

2: PE15

3: PF1

4: PA0

5: PC15 LEUART0 Receive input.

LEU0_TX

0: PD4

1: PB13

2: PE14

3: PF0

4: PF2

5: PC14 LEUART0 Transmit output. Also used as receive input in half duplex communication.

LFXTAL_N

0: PB8

Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional ex-

ternal clock input pin.

LFXTAL_P

0: PB7

Low Frequency Crystal (typically 32.768 kHz) positive pin.

OPA0_N

0: PC5

Operational Amplifier 0 external negative input.

OPA0_P

0: PC4

Operational Amplifier 0 external positive input.

OPA1_N

0: PD7

Operational Amplifier 1 external negative input.

OPA1_P

0: PD6

Operational Amplifier 1 external positive input.

OPA2_N

0: PD3

Operational Amplifier 2 external negative input.

OPA2_OUT

0: PD5

Operational Amplifier 2 output.

OPA2_OUTALT

0: PD0

Operational Amplifier 2 alternative output.

OPA2_P

0: PD4

Operational Amplifier 2 external positive input.

EFM32TG11 Family Data Sheet

Pin Definitions

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Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

OPA3_N

0: PC7

Operational Amplifier 3 external negative input.

OPA3_OUT

0: PD1

Operational Amplifier 3 output.

OPA3_P

0: PC6

Operational Amplifier 3 external positive input.

PCNT0_S0IN

0: PC13

2: PC0

3: PD6

4: PA0

6: PB5

7: PB12

Pulse Counter PCNT0 input number 0.

PCNT0_S1IN

0: PC14

2: PC1

3: PD7

4: PA1

6: PB6

7: PB11

Pulse Counter PCNT0 input number 1.

PRS_CH0

0: PA0

1: PF3

2: PC14

3: PF2

Peripheral Reflex System PRS, channel 0.

PRS_CH1

0: PA1

1: PF4

2: PC15

3: PE12

Peripheral Reflex System PRS, channel 1.

PRS_CH2

0: PC0

1: PF5

2: PE10

3: PE13

Peripheral Reflex System PRS, channel 2.

PRS_CH3

0: PC1

1: PE8

2: PE11

3: PA0

Peripheral Reflex System PRS, channel 3.

PRS_CH4

0: PC8

2: PF1 Peripheral Reflex System PRS, channel 4.

PRS_CH5

0: PC9

2: PD6 Peripheral Reflex System PRS, channel 5.

PRS_CH6

0: PA6

1: PB14

2: PE6 Peripheral Reflex System PRS, channel 6.

PRS_CH7

0: PB13

2: PE7 Peripheral Reflex System PRS, channel 7.

EFM32TG11 Family Data Sheet

Pin Definitions

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Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

TIM0_CC0

0: PA0

2: PD1

3: PB6

4: PF0

5: PC4

6: PA8

7: PA1

Timer 0 Capture Compare input / output channel 0.

TIM0_CC1

0: PA1

2: PD2

3: PC0

4: PF1

5: PC5

6: PA9

7: PA0

Timer 0 Capture Compare input / output channel 1.

TIM0_CC2

0: PA2

2: PD3

3: PC1

4: PF2

6: PA10

7: PA13

Timer 0 Capture Compare input / output channel 2.

TIM0_CDTI0

0: PA3

1: PC13

2: PF3

3: PC2

4: PB7

Timer 0 Complimentary Dead Time Insertion channel 0.

TIM0_CDTI1

0: PA4

1: PC14

2: PF4

3: PC3

4: PB8

Timer 0 Complimentary Dead Time Insertion channel 1.

TIM0_CDTI2

0: PA5

1: PC15

2: PF5

3: PC4

4: PB11

Timer 0 Complimentary Dead Time Insertion channel 2.

TIM1_CC0

0: PC13

1: PE10

3: PB7

4: PD6

5: PF2 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1

0: PC14

1: PE11

3: PB8

4: PD7

5: PF3 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2

0: PC15

1: PE12

3: PB11

4: PC13

5: PF4 Timer 1 Capture Compare input / output channel 2.

TIM1_CC3

0: PC12

1: PE13

2: PB3

3: PB12

4: PC14

6: PF5 Timer 1 Capture Compare input / output channel 3.

U0_CTS 2: PA5

3: PC13

4: PB7

5: PD5 UART0 Clear To Send hardware flow control input.

U0_RTS 2: PA6

3: PC12

4: PB8

5: PD6 UART0 Request To Send hardware flow control output.

U0_RX 2: PA4

3: PC15

4: PC5

5: PF2

6: PE4 UART0 Receive input.

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 114

Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

U0_TX 2: PA3

3: PC14

4: PC4

5: PF1

6: PD7 UART0 Transmit output. Also used as receive input in half duplex communication.

US0_CLK

0: PE12

1: PE5

2: PC9

3: PC15

4: PB13

5: PA12 USART0 clock input / output.

US0_CS

0: PE13

1: PE4

2: PC8

3: PC14

4: PB14

5: PA13 USART0 chip select input / output.

US0_CTS

0: PE14

2: PC7

3: PC13

4: PB6

5: PB11 USART0 Clear To Send hardware flow control input.

US0_RTS

0: PE15

2: PC6

3: PC12

4: PB5

5: PD6 USART0 Request To Send hardware flow control output.

US0_RX

0: PE11

1: PE6

2: PC10

3: PE12

4: PB8

5: PC1 USART0 Asynchronous Receive.

USART0 Synchronous mode Master Input / Slave Output (MISO).

US0_TX

0: PE10

1: PE7

2: PC11

3: PE13

4: PB7

5: PC0

USART0 Asynchronous Transmit. Also used as receive input in half duplex communica-

tion.

USART0 Synchronous mode Master Output / Slave Input (MOSI).

US1_CLK

0: PB7

1: PD2

2: PF0

3: PC15

4: PC3

5: PB11

6: PE5 USART1 clock input / output.

US1_CS

0: PB8

1: PD3

2: PF1

3: PC14

4: PC0

5: PE4 USART1 chip select input / output.

US1_CTS 1: PD4

2: PF3

3: PC6

4: PC12

5: PB13 USART1 Clear To Send hardware flow control input.

US1_RTS 1: PD5

2: PF4

3: PC7

4: PC13

5: PB14 USART1 Request To Send hardware flow control output.

US1_RX

0: PC1

1: PD1

2: PD6

4: PC2

5: PA0

6: PA2

USART1 Asynchronous Receive.

USART1 Synchronous mode Master Input / Slave Output (MISO).

US1_TX

0: PC0

1: PD0

2: PD7

4: PC1

5: PF2

6: PA14

USART1 Asynchronous Transmit. Also used as receive input in half duplex communica-

tion.

USART1 Synchronous mode Master Output / Slave Input (MOSI).

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 115

Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

US2_CLK

0: PC4

1: PB5

2: PA9

3: PA15

5: PF2 USART2 clock input / output.

US2_CS

0: PC5

1: PB6

2: PA10

3: PB11

5: PF5 USART2 chip select input / output.

US2_CTS

0: PC1

1: PB12

4: PC12

5: PD6 USART2 Clear To Send hardware flow control input.

US2_RTS

0: PC0

2: PA12

3: PC14

4: PC13

5: PD8 USART2 Request To Send hardware flow control output.

US2_RX

0: PC3

1: PB4

2: PA8

3: PA14

5: PF1 USART2 Asynchronous Receive.

USART2 Synchronous mode Master Input / Slave Output (MISO).

US2_TX

0: PC2

1: PB3

3: PA13

5: PF0

USART2 Asynchronous Transmit. Also used as receive input in half duplex communica-

tion.

USART2 Synchronous mode Master Output / Slave Input (MOSI).

US3_CLK

0: PA2

1: PD7

2: PD4 USART3 clock input / output.

US3_CS

0: PA3

1: PE4

2: PC14

3: PC0

USART3 chip select input / output.

US3_CTS

0: PA4

1: PE5

2: PD6 USART3 Clear To Send hardware flow control input.

US3_RTS

0: PA5

1: PC1

2: PA14

3: PC15

USART3 Request To Send hardware flow control output.

US3_RX

0: PA1

1: PE7

2: PB7

USART3 Asynchronous Receive.

USART3 Synchronous mode Master Input / Slave Output (MISO).

US3_TX

0: PA0

1: PE6

2: PB3

USART3 Asynchronous Transmit. Also used as receive input in half duplex communica-

tion.

USART3 Synchronous mode Master Output / Slave Input (MOSI).

VDAC0_EXT

0: PD6

Digital to analog converter VDAC0 external reference input pin.

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 116

Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

VDAC0_OUT0 /

OPA0_OUT

0: PB11

Digital to Analog Converter DAC0 output channel number 0.

VDAC0_OUT0ALT

/ OPA0_OUTALT

0: PC0

1: PC1

2: PC2

3: PC3

4: PD0

Digital to Analog Converter DAC0 alternative output for channel 0.

VDAC0_OUT1 /

OPA1_OUT

0: PB12

Digital to Analog Converter DAC0 output channel number 1.

VDAC0_OUT1ALT

/ OPA1_OUTALT

0: PC12

1: PC13

2: PC14

3: PC15

4: PD1

Digital to Analog Converter DAC0 alternative output for channel 1.

WTIM0_CC0

0: PE4

1: PA6

4: PC15

6: PB3

7: PC1

Wide timer 0 Capture Compare input / output channel 0.

WTIM0_CC1

0: PE5 4: PF0

6: PB4

7: PC2

Wide timer 0 Capture Compare input / output channel 1.

WTIM0_CC2

0: PE6 4: PF1

6: PB5

7: PC3

Wide timer 0 Capture Compare input / output channel 2.

WTIM0_CDTI0

0: PE10

2: PA12

4: PD4

Wide timer 0 Complimentary Dead Time Insertion channel 0.

WTIM0_CDTI1

0: PE11

2: PA13

4: PD5

Wide timer 0 Complimentary Dead Time Insertion channel 1.

WTIM0_CDTI2

0: PE12

2: PA14

4: PD6

Wide timer 0 Complimentary Dead Time Insertion channel 2.

WTIM1_CC0

0: PB13

1: PD2

2: PD6

3: PC7

5: PE7 Wide timer 1 Capture Compare input / output channel 0.

WTIM1_CC1

0: PB14

1: PD3

2: PD7

4: PE4

Wide timer 1 Capture Compare input / output channel 1.

WTIM1_CC2

0: PD0

1: PD4

2: PD8

4: PE5

Wide timer 1 Capture Compare input / output channel 2.

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 117

Alternate LOCATION

Functionality 0 - 3 4 - 7 Description

WTIM1_CC3

0: PD1

1: PD5

2: PC6

4: PE6

Wide timer 1 Capture Compare input / output channel 3.

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 118

5.16 Analog Port (APORT) Client Maps

The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,

DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal rout-

ing. Figure 5.14 APORT Connection Diagram on page 119 shows the APORT routing for this device family (note that available features

may vary by part number). A complete description of APORT functionality can be found in the Reference Manual.

PA1

PA2

PA3

PA4

PA5

PA6

PB3

PB4

PB5

PB6

PB12

PB13

PB14

PA15

PA0

PB11

PA14

PA13

PA10

PA9

PE7

PE6

PD6

PD3

PD2

PD1

PD0

OPA1_P

ADC1X

ADC1Y

ACMP0X

ACMP0Y

ACMP1X

ACMP1Y

POS

NEG

ACMP0

POS

NEG

ACMP1

POS

NEG

ADC0

EXTP

EXTN

POS

NEG

OPA0

OPA0_P

OPA0_N

OUT0

OUT0ALT

OUT1

OUT2

OUT3

OUT4

OUT

POS

NEG

OPA1

OUT

OPA1_P

OPA1_N

OUT1

OUT1ALT

OUT1

OUT2

OUT3

OUT4

POS

NEG

OPA2

OPA2_P

OPA2_N

OUT2

OUT2ALT

OUT1

OUT2

OUT3

OUT4

OUT

nX, nY APORTnX, APORTnY

AX, BY, … BUSAX, BUSBY, ...

ADC0X,

ADC0Y

BUSADC0X,

BUSADC0Y

ACMP0X,

ACMP1Y, …

BUSACMP0X,

BUSACMP1Y, ...

CEXT

CSEN

CEXT_SENSE

POS

NEG

OPA3

OUT

OPA3_P

OPA3_N

OUT3

OUT3ALT

OUT1

OUT2

OUT3

OUT4

PE15

PE14

PE13

PE12

PE11

PE10

PE9

PE8

PF5

PF4

PF3

PF2

PF1

PF0

VDAC0_OUT0ALT

OPA2_ALT

ALT0OUT

OPA3_OUT

OUT3

OPA2_N

PD4

OPA2_P

PD5

OUT2

ADC_EXTP

ALT0OUT

PD7

PC6

PC7

OPA2_N

PE5

PE4

PC15

OPA1_ALT

PC14

PC13

PC12

PC11

PC13

PC12

PC11

PC0

OPA0_ALT

PC1

OPA0_ALT

PC2

OPA0_ALT

PC3

OPA0_ALT

PC4

PC5

OPA0_P

OPA0_N

OPA1_N

ADC_EXTN

OPA1_OUT

OUT1

OPA0_OUT

OUT0

NEXT0

NEXT2

NEXT1

NEXT3

NEXT2

NEXT1

NEXT0

NEXT1

NEXT0

NEXT1

NEXT0

NEXT1

NEXT0

NEXT1

NEXT0

Figure 5.14. APORT Connection Diagram

Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the

peripheral's port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins.

In general, enumerations for the pin selection field in an analog peripheral's register can be determined by finding the desired pin con-

nection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 119

PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared

bus used by this connection is indicated in the Bus column.

Table 5.16. ACMP0 Bus and Pin Mapping

Port

Bus

CH31

CH30

CH29

CH28

CH27

CH26

CH25

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

APORT0X

BUSACMP0X

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

APORT0Y

BUSACMP0Y

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

APORT1X

BUSAX

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT1Y

BUSAY

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2X

BUSBX

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2Y

BUSBY

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT3X

BUSCX

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

APORT3Y

BUSCY

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4X

BUSDX

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4Y

BUSDY

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 120

Table 5.17. ACMP1 Bus and Pin Mapping

Port

Bus

CH31

CH30

CH29

CH28

CH27

CH26

CH25

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

APORT0X

BUSACMP1X

PC15

PC14

PC13

PC12

PC11

PC10

PC9

PC8

APORT0Y

BUSACMP1Y

PC15

PC14

PC13

PC12

PC11

PC10

PC9

PC8

APORT1X

BUSAX

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT1Y

BUSAY

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2X

BUSBX

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2Y

BUSBY

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT3X

BUSCX

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

APORT3Y

BUSCY

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4X

BUSDX

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4Y

BUSDY

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 121

Table 5.18. ADC0 Bus and Pin Mapping

Port

Bus

CH31

CH30

CH29

CH28

CH27

CH26

CH25

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

APORT0X

BUSADC0X

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

APORT0Y

BUSADC0Y

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

APORT1X

BUSAX

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT1Y

BUSAY

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2X

BUSBX

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2Y

BUSBY

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT3X

BUSCX

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

APORT3Y

BUSCY

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4X

BUSDX

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4Y

BUSDY

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 122

Table 5.19. CSEN Bus and Pin Mapping

Port

Bus

CH31

CH30

CH29

CH28

CH27

CH26

CH25

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

CEXT

APORT1X

BUSAX

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT1Y

BUSAY

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT3X

BUSCX

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

APORT3Y

BUSCY

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

CEXT_SENSE

APORT2X

BUSBX

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2Y

BUSBY

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT4X

BUSDX

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4Y

BUSDY

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 123

Table 5.20. VDAC0 / OPA Bus and Pin Mapping

Port

Bus

CH31

CH30

CH29

CH28

CH27

CH26

CH25

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

OPA0_N

APORT1Y

BUSAY

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2Y

BUSBY

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT3Y

BUSCY

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4Y

BUSDY

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

OPA0_P

APORT1X

BUSAX

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT2X

BUSBX

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT3X

BUSCX

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

APORT4X

BUSDX

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 124

Port

Bus

CH31

CH30

CH29

CH28

CH27

CH26

CH25

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

OPA1_N

APORT1Y

BUSAY

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2Y

BUSBY

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT3Y

BUSCY

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4Y

BUSDY

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

OPA1_P

APORT1X

BUSAX

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT2X

BUSBX

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT3X

BUSCX

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

APORT4X

BUSDX

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

OPA2_N

APORT1Y

BUSAY

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2Y

BUSBY

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT3Y

BUSCY

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4Y

BUSDY

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 125

Port

Bus

CH31

CH30

CH29

CH28

CH27

CH26

CH25

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

OPA2_OUT

APORT1Y

BUSAY

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2Y

BUSBY

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT3Y

BUSCY

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4Y

BUSDY

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

OPA2_P

APORT1X

BUSAX

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT2X

BUSBX

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT3X

BUSCX

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

APORT4X

BUSDX

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

OPA3_N

APORT1Y

BUSAY

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2Y

BUSBY

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT3Y

BUSCY

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4Y

BUSDY

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 126

Port

Bus

CH31

CH30

CH29

CH28

CH27

CH26

CH25

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

OPA3_OUT

APORT1Y

BUSAY

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2Y

BUSBY

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT3Y

BUSCY

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4Y

BUSDY

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

OPA3_P

APORT1X

BUSAX

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT2X

BUSBX

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT3X

BUSCX

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

APORT4X

BUSDX

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

VDAC0_OUT0 / OPA0_OUT

APORT1Y

BUSAY

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2Y

BUSBY

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT3Y

BUSCY

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4Y

BUSDY

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 127

Port

Bus

CH31

CH30

CH29

CH28

CH27

CH26

CH25

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

VDAC0_OUT1 / OPA1_OUT

APORT1Y

BUSAY

PB13

PB11

PB5

PB3

PA15

PA13

PA9

PA5

PA3

PA1

APORT2Y

BUSBY

PB14

PB12

PB6

PB4

PA14

PA10

PA6

PA4

PA2

PA0

APORT3Y

BUSCY

PF5

PF3

PF1

PE15

PE13

PE11

PE9

PE7

PE5

APORT4Y

BUSDY

PF4

PF2

PF0

PE14

PE12

PE10

PE8

PE6

PE4

EFM32TG11 Family Data Sheet

Pin Definitions

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 128

6. TQFP80 Package Specifications

6.1 TQFP80 Package Dimensions

Figure 6.1. TQFP80 Package Drawing

EFM32TG11 Family Data Sheet

TQFP80 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 129

Table 6.1. TQFP80 Package Dimensions

Dimension Min Typ Max

A — — 1.20

A1 0.05 — 0.15

A2 0.95 1.00 1.05

b 0.17 0.20 0.27

c 0.09 — 0.20

D 14.00 BSC

D1 12.00 BSC

e 0.50 BSC

E 14.00 BSC

E1 12.00 BSC

L 0.45 0.60 0.75

L1 1.00 REF

θ 0 3.5 7

aaa 0.20

bbb 0.20

ccc 0.08

ddd 0.08

eee 0.05

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This package outline conforms to JEDEC MS-026, variant ADD.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.

EFM32TG11 Family Data Sheet

TQFP80 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 130

6.2 TQFP80 PCB Land Pattern

Figure 6.2. TQFP80 PCB Land Pattern Drawing

EFM32TG11 Family Data Sheet

TQFP80 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 131

Table 6.2. TQFP80 PCB Land Pattern Dimensions

Dimension Min Max

C1 13.30 13.40

C2 13.30 13.40

E 0.50 BSC

X 0.20 0.30

Y 1.40 1.50

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

5. The stencil thickness should be 0.125 mm (5 mils).

6. The ratio of stencil aperture to land pad size can be 1:1 for all pads.

7. A No-Clean, Type-3 solder paste is recommended.

8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

6.3 TQFP80 Package Marking

PPPPPPPPPP

TTTTTT

YYWW

EFM32

Figure 6.3. TQFP80 Package Marking

The package marking consists of:

• PPPPPPPPPP – The part number designation.

• TTTTTT – A trace or manufacturing code. The first letter is the device revision.

• YY – The last 2 digits of the assembly year.

• WW – The 2-digit workweek when the device was assembled.

EFM32TG11 Family Data Sheet

TQFP80 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 132

7. QFN80 Package Specifications

7.1 QFN80 Package Dimensions

Figure 7.1. QFN80 Package Drawing

EFM32TG11 Family Data Sheet

QFN80 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 133

Table 7.1. QFN80 Package Dimensions

Dimension Min Typ Max

A 0.70 0.75 0.80

A1 0.00 — 0.05

b 0.20 0.25 0.30

A3 0.203 REF

D 9.00 BSC

e 0.40 BSC

E 9.00 BSC

D2 7.10 7.20 7.30

E2 7.10 7.20 7.30

L 0.35 0.40 0.45

aaa 0.10

bbb 0.10

ccc 0.10

ddd 0.05

eee 0.08

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

EFM32TG11 Family Data Sheet

QFN80 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 134

7.2 QFN80 PCB Land Pattern

Figure 7.2. QFN80 PCB Land Pattern Drawing

EFM32TG11 Family Data Sheet

QFN80 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 135

Table 7.2. QFN80 PCB Land Pattern Dimensions

Dimension Typ

C1 8.90

C2 8.90

E 0.40

X1 0.20

Y1 0.85

X2 7.30

Y2 7.30

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-

cation Allowance of 0.05mm.

4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

6. The stencil thickness should be 0.125 mm (5 mils).

7. The ratio of stencil aperture to land pad size can be 1:1 for all pads.

8. A 3x3 array of 1.45 mm square openings on a 2.00 mm pitch can be used for the center ground pad.

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

EFM32TG11 Family Data Sheet

QFN80 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 136

7.3 QFN80 Package Marking

PPPPPPPPPP

TTTTTT

YYWW

EFM32

Figure 7.3. QFN80 Package Marking

The package marking consists of:

• PPPPPPPPPP – The part number designation.

• TTTTTT – A trace or manufacturing code. The first letter is the device revision.

• YY – The last 2 digits of the assembly year.

• WW – The 2-digit workweek when the device was assembled.

EFM32TG11 Family Data Sheet

QFN80 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 137

8. TQFP64 Package Specifications

8.1 TQFP64 Package Dimensions

Figure 8.1. TQFP64 Package Drawing

EFM32TG11 Family Data Sheet

TQFP64 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 138

Table 8.1. TQFP64 Package Dimensions

Dimension Min Typ Max

A — 1.15 1.20

A1 0.05 — 0.15

A2 0.95 1.00 1.05

b 0.17 0.22 0.27

b1 0.17 0.20 0.23

c 0.09 — 0.20

c1 0.09 — 0.16

D 12.00 BSC

D1 10.00 BSC

e 0.50 BSC

E 12.00 BSC

E1 10.00 BSC

L 0.45 0.60 0.75

L1 1.00 REF

R1 0.08 — —

R2 0.08 — 0.20

S 0.20 — —

θ 0 3.5 7

ϴ1 0 — 0.10

ϴ2 11 12 13

ϴ3 11 12 13

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

EFM32TG11 Family Data Sheet

TQFP64 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 139

8.2 TQFP64 PCB Land Pattern

Figure 8.2. TQFP64 PCB Land Pattern Drawing

EFM32TG11 Family Data Sheet

TQFP64 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 140

Table 8.2. TQFP64 PCB Land Pattern Dimensions

Dimension Min Max

C1 11.30 11.40

C2 11.30 11.40

E 0.50 BSC

X 0.20 0.30

Y 1.40 1.50

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

5. The stencil thickness should be 0.125 mm (5 mils).

6. The ratio of stencil aperture to land pad size can be 1:1 for all pads.

7. A No-Clean, Type-3 solder paste is recommended.

8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

8.3 TQFP64 Package Marking

PPPPPPPPPP

TTTTTT

YYWW

EFM32

Figure 8.3. TQFP64 Package Marking

The package marking consists of:

• PPPPPPPPPP – The part number designation.

• TTTTTT – A trace or manufacturing code. The first letter is the device revision.

• YY – The last 2 digits of the assembly year.

• WW – The 2-digit workweek when the device was assembled.

EFM32TG11 Family Data Sheet

TQFP64 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 141

9. QFN64 Package Specifications

9.1 QFN64 Package Dimensions

Figure 9.1. QFN64 Package Drawing

EFM32TG11 Family Data Sheet

QFN64 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 142

Table 9.1. QFN64 Package Dimensions

Dimension Min Typ Max

A 0.70 0.75 0.80

A1 0.00 — 0.05

b 0.20 0.25 0.30

A3 0.203 REF

D 9.00 BSC

e 0.50 BSC

E 9.00 BSC

D2 7.10 7.20 7.30

E2 7.10 7.20 7.30

L 0.40 0.45 0.50

L1 0.00 — 0.10

aaa 0.10

bbb 0.10

ccc 0.10

ddd 0.05

eee 0.08

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

EFM32TG11 Family Data Sheet

QFN64 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 143

9.2 QFN64 PCB Land Pattern

Figure 9.2. QFN64 PCB Land Pattern Drawing

EFM32TG11 Family Data Sheet

QFN64 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 144

Table 9.2. QFN64 PCB Land Pattern Dimensions

Dimension Typ

C1 8.90

C2 8.90

E 0.50

X1 0.30

Y1 0.85

X2 7.30

Y2 7.30

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-

cation Allowance of 0.05mm.

4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

6. The stencil thickness should be 0.125 mm (5 mils).

7. The ratio of stencil aperture to land pad size can be 1:1 for all pads.

8. A 3x3 array of 1.45 mm square openings on a 2.00 mm pitch can be used for the center ground pad.

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

EFM32TG11 Family Data Sheet

QFN64 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 145

9.3 QFN64 Package Marking

PPPPPPPPPP

TTTTTT

YYWW

EFM32

Figure 9.3. QFN64 Package Marking

The package marking consists of:

• PPPPPPPPPP – The part number designation.

• TTTTTT – A trace or manufacturing code. The first letter is the device revision.

• YY – The last 2 digits of the assembly year.

• WW – The 2-digit workweek when the device was assembled.

EFM32TG11 Family Data Sheet

QFN64 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 146

10. TQFP48 Package Specifications

10.1 TQFP48 Package Dimensions

Figure 10.1. TQFP48 Package Drawing

EFM32TG11 Family Data Sheet

TQFP48 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 147

Table 10.1. TQFP48 Package Dimensions

Dimension Min Typ Max

A 7.00 BSC

A1 3.50 BSC

B 7.00 BSC

B1 3.50 BSC

C 1.00 — 1.20

D 0.17 — 0.27

E 0.95 — 1.05

F 0.17 — 0.23

G 0.50 BSC

H 0.05 — 0.15

J 0.09 — 0.20

K 0.50 — 0.70

L 0 — 7

M 12 REF

N 0.09 — 0.16

P 0.25 BSC

R 0.150 — 0.250

S 9.00 BSC

S1 4.50 BSC

V 9.00 BSC

V1 4.50 BSC

W 0.20 BSC

AA 1.00 BSC

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

EFM32TG11 Family Data Sheet

TQFP48 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 148

10.2 TQFP48 PCB Land Pattern

Figure 10.2. TQFP48 PCB Land Pattern Drawing

Table 10.2. TQFP48 PCB Land Pattern Dimensions

Dimension Typ

C1 8.50

C2 8.50

E 0.50

X 0.30

Y 1.60

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

5. The stencil thickness should be 0.125 mm (5 mils).

6. The ratio of stencil aperture to land pad size can be 1:1 for all pads.

7. A No-Clean, Type-3 solder paste is recommended.

8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.

EFM32TG11 Family Data Sheet

TQFP48 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 149

10.3 TQFP48 Package Marking

PPPPPPPPPP

TTTTTT

YYWW

EFM32

Figure 10.3. TQFP48 Package Marking

The package marking consists of:

• PPPPPPPPPP – The part number designation.

• TTTTTT – A trace or manufacturing code. The first letter is the device revision.

• YY – The last 2 digits of the assembly year.

• WW – The 2-digit workweek when the device was assembled.

EFM32TG11 Family Data Sheet

TQFP48 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 150

11. QFN32 Package Specifications

11.1 QFN32 Package Dimensions

Figure 11.1. QFN32 Package Drawing

EFM32TG11 Family Data Sheet

QFN32 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 151

Table 11.1. QFN32 Package Dimensions

Dimension Min Typ Max

A 0.70 0.75 0.80

A1 0.00 — 0.05

A3 0.203 REF

b 0.20 0.25 0.30

D 5.0 BSC

D2/E2 3.60 3.70 3.80

E 5.0 BSC

e 0.50 BSC

L 0.35 0.40 0.45

aaa 0.10

bbb 0.10

ccc 0.10

ddd 0.05

eee 0.08

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

EFM32TG11 Family Data Sheet

QFN32 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 152

11.2 QFN32 PCB Land Pattern

Figure 11.2. QFN32 PCB Land Pattern Drawing

EFM32TG11 Family Data Sheet

QFN32 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 153

Table 11.2. QFN32 PCB Land Pattern Dimensions

Dimension Typ

C1 5.00

C2 5.00

E 0.50

X1 0.30

Y1 0.80

X2 3.80

Y2 3.80

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

5. The stencil thickness should be 0.125 mm (5 mils).

6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.

7. A 2x2 array of 0.9 mm square openings on a 1.2 mm pitch should be used for the center ground pad.

8. A No-Clean, Type-3 solder paste is recommended.

9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

EFM32TG11 Family Data Sheet

QFN32 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 154

11.3 QFN32 Package Marking

PPPPPPPPPP

TTTTTT

YYWW

EFM32

Figure 11.3. QFN32 Package Marking

The package marking consists of:

• PPPPPPPPPP – The part number designation.

• TTTTTT – A trace or manufacturing code. The first letter is the device revision.

• YY – The last 2 digits of the assembly year.

• WW – The 2-digit workweek when the device was assembled.

EFM32TG11 Family Data Sheet

QFN32 Package Specifications

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 155

12. Revision History

Revision 0.5

February, 2018

•4.1 Electrical Characteristics updated with latest characterization data and production test limits.

• Added 4.1.3 Thermal Characteristics.

• Added 4.2 Typical Performance Curves section.

• Corrected OPA / VDAC output connections in Figure 5.14 APORT Connection Diagram on page 119.

Revision 0.1

May 1st, 2017

Initial release.

EFM32TG11 Family Data Sheet

Revision History

silabs.com | Building a more connected world. Preliminary Rev. 0.5 | 156

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Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or

intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes

without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included

information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted

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