KM68512ALT-5L - Samsung Electronics

KM68512A Family CMOS SRAM

Revision 4.0

January 1997

Document Title

64Kx8 bit Low Power CMOS Static RAM

Revision History

Revision No.

0.0

0.1

1.0

2.0

3.0

4.0

Remark

Design target

Preliminary

Final

History

Initial draft

Revision

Finalize

Revision

- Add 45ns part with 30pf test load.

Revision

- Change Data Sheet format :

One data sheets for industrial and commercial product

Revision

- Change Data Sheet format

- Remove 45ns part from commercial product and 100ns part

from industrial product

- Remove low power part form TSOP package

Draft Data

Novemer 28, 1993

May 13, 1994

December 1, 1994

August 12, 1995

April 15, 1996

January 9, 1998

The attached data, sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

KM68512A Family CMOS SRAM

Revision 4.0

January 1997

64Kx8 bit Low Power CMOS Static RAM

GENERAL DESCRIPTION

The KM68512A families are fabricated by SAMSUNG′s

advanced CMOS process technology. The families support

various operating temperature ranges and have various

package types for user flexibility of system design. The

families also support low data retention voltage for battery

back-up operation with low data retention current.

FEATURES

• Process Technology: Poly Load

• Organization: 64Kx8

• Power Supply Voltage: 4.5~5.5V

• Low Data Retention Voltage: 2V(Min)

• Three state output and TTL Compatible

• Package Type: 32-SOP-525, 32-TSOP1-0820F

PIN DESCRIPTION

Name Function

CS1, CS2Chip Select Inputs

OE Output Enable Input

WE Write Enable Input

A0~A15 Address Inputs

I/O1~I/O8Data Inputs/Outputs

Vcc Power

Vss Ground

N.C No Connection

PRODUCT FAMILY

Product Family Operating Temperature VCC Range Speed Power Dissipation PKG Type

Standby

(ISB1, Max) Operating

(ICC2, Max)

KM68512AL Commercial (0~70°C)

4.5 to 5.5V

55/70ns 100µA

70mA 32-SOP

32-TSOP1-F

KM68512AL-L 20µA

KM68512ALI Industrial (-40~85°C) 70ns 100µA

KM68512ALI-L 50µA

FUNCTIONAL BLOCK DIAGRAM

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

A11

A13

CS2

A15

A14

A12

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

32-TSOP

Type1 - Forward

N.C

A14

A12

I/O1

I/O2

I/O3

VSS

VCC

A15

CS2

A13

A11

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

32-SOP

N.C

VCC

Precharge circuit.

Memory array

512 rows

128×8 columns

I/O Circuit

Column select

Clk gen.

Row

select

A0 A1 A2 A8 A9 A11A10

A12

A14

CS1

CS2

I/O1 Data

cont

Data

cont

I/O8

A13

A15

Control

Logic

KM68512A Family CMOS SRAM

Revision 4.0

January 1997

PRODUCT LIST

Commercial Temperature Products(0~70°C) Industrial Temperature Products(-40~85°C)

Part Name Function Part Name Function

KM68512ALG-5

KM68512ALG-5L

KM68512ALG-7

KM68512ALG-7L

KM68512ALT-5L

KM68512ALT-7L

32-SOP, 55ns, L-pwr

32-SOP, 55ns, LL-pwr

32-SOP, 70ns, L-pwr

32-SOP, 70ns, LL-pwr

32-TSOP1-F, 55ns, LL-pwr

32-TSOP1-F, 70ns, LL-pwr

KM68512ALGI-7

KM68512ALGI-7L

KM68512ALTI-7L

32-SOP, 70ns, L-pwr

32-SOP, 70ns, LL-pwr

32-TSOP1-F, 70ns, LL-pwr

FUNCTIONAL DESCRIPTION

1. X means don′t care.(Must be low or high state)

CS1CS2OE WE I/O Pin Mode Power

HX1) X1) X1) High-Z Deselected Standby

X1) LX1) X1) High-Z Deselected Standby

LHHH High-Z Output Disabled Active

LHLHDout Read Active

LHX1) LDin Write Active

ABSOLUTE MAXIMUM RATINGS1)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.5 to 7.0 V-

Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V-

Power Dissipation PD1.0 W-

Storage temperature TSTG -65 to 150 °C-

Operating Temperature TA0 to 70 °CKM68512A

-40 to 85 °CKM68512AI

Soldering temperature and time TSOLDER 260°C, 10sec(Lead Only) - -

KM68512A Family CMOS SRAM

Revision 4.0

January 1997

RECOMMENDED DC OPERATING CONDITIONS1)

Note

1. Commercial Product : TA=0 to 70°C, unless otherwise specified

Industrial Product : TA=-40 to 85°C, unless otherwise specified

2. Overshoot : VCC+3.0V in case of pulse width≤30ns

3. Undershoot : -3.0V in case of pulse width≤30ns

4. Overshoot and undershoot are sampled, not 100% tested

Item Symbol Min Typ Max Unit

Supply voltage Vcc 4.5 5.0 5.5 V

Ground Vss 0 0 0 V

Input high voltage VIH 2.2 -Vcc+0.5V2) V

Input low voltage VIL -0.53) -0.8 V

CAPACITANCE1)(f=1MHz, TA=25°C)

1. Capacitance is sampled, not 100% tested

Item Symbol Test Condition Min Max Unit

Input capacitance CIN VIN=0V -6pF

Input/Output capacitance CIO VIO=0V -8pF

DC AND OPERATING CHARACTERISTICS

Item Symbol Test Conditions Min Typ Max Unit

Input leakage current ILI VIN=Vss to Vcc -1 -1µA

Output leakage current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 -1µA

Operating power supply current ICC IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL -715 mA

Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA

CS1≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or VIN≥Vcc -0.2V - - 10 mA

ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL - - 70 mA

Output low voltage VOL IOL=2.1mA - - 0.4 V

Output high voltage VOH IOH=-1.0mA 2.4 - - V

Standby Current(TTL) ISB CS1=VIH, CS2=VIL, Other inputs =VIH or VIL - - 3mA

Standby

Current

(CMOS)

KM68512AL/L-L

ISB1 CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V

Other inputs =0 ~ Vcc

Low Power

Low Low Power -

-2

1100

20 µA

KM68512ALI/LI-L Low Power

Low Low Power -

-2

1100

50 µA

KM68512A Family CMOS SRAM

Revision 4.0

January 1997

AC CHARACTERISTICS (Vcc=4.5~5.5V, KM68512A Family:TA=0 to 70°C, KM68512AI Family:TA=-40 to 85°C)

Parameter List Symbol

Speed Bins

Units

55ns 70ns

Min Max Min Max

Read

Read cycle time tRC 55 -70 -ns

Address access time tAA -55 -70 ns

Chip select to output tCO1, tCO2 -55 -70 ns

Output enable to valid output tOE -25 -35 ns

Chip select to low-Z output tLZ 10 -10 -ns

Output enable to low-Z output tOLZ 5-5-ns

Chip disable to high-Z output tHZ 020 025 ns

Output disable to high-Z output tOHZ 020 025 ns

Output hold from address change tOH 10 -10 -ns

Write

Write cycle time tWC 55 -70 -ns

Chip select to end of write tCW 45 -60 -ns

Address set-up time tAS 0-0-ns

Address valid to end of write tAW 45 -60 -ns

Write pulse width tWP 40 -50 -ns

Write recovery time tWR 0-0-ns

Write to output high-Z tWHZ 020 025 ns

Data to write time overlap tDW 25 -30 -ns

Data hold from write time tDH 0-0-ns

End write to output low-Z tOW 5-5-ns

CL1)

1. Including scope and jig capacitance

AC OPERATING CONDITIONS

TEST CONDITIONS( Test Load and Input/Output Reference)

Input pulse level : 0.8 to 2.4V

Input rising and falling time : 5ns

Input and output reference voltage :1.5V

Output load(see right) : CL=100pF+1TTL

DATA RETENTION CHARACTERISTICS

1. CS1≥Vcc-0.2V, CS2≥Vcc-0.2V( CS1 controlled) or CS2≤0.2V(CS2 controlled).

Item Symbol Test Condition Min Typ Max Unit

Vcc for data retention VDR CS11)≥Vcc-0.2V 2.0 -5.5 V

Data retention current IDR

KM68512AL/L-L Vcc=3.0V CS1≥Vcc-0.2V

CS2≥Vcc-0.2V or CS2≤0.2V

L-Ver

LL-Ver -

-1

0.5 50

10 µA

KM68512ALI/LI-L L-Ver

LL-Ver -

-50

Data retention set-up time tSDR See data retention waveform 0- - ms

Recovery time tRDR 5- -

KM68512A Family CMOS SRAM

Revision 4.0

January 1997

Address

Data Out Previous Data Valid Data Valid

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH)

tAA

tRC

tOH

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Data Valid

High-Z

CS1

Address

Data out

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

CS2

tOH

tAA

tOLZ

tLZ tOHZ

tHZ(1,2)

tRC

tCO2tOE

tCO1

KM68512A Family CMOS SRAM

Revision 4.0

January 1997

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

CS1

tCW(2) tWR(4)

TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)

Address

CS1

tWC

tWR(4)

tAS(3)

CS2tCW(2)

tWP(1)

tDW tDH

tOW

tWHZ

Data Undefined

Data Valid

Data in

Data out

tDW tDH

Data Valid

Data in

Data out High-Z High-Z

CS2

tWC

tAW

tAS(3)

tCW(2)

tWP(1)

tAW

KM68512A Family CMOS SRAM

Revision 4.0

January 1997

DATA RETENTION WAVE FORM

CS1 controlled

VCC

4.5V

2.2V

VDR

CS1

GND

Data Retention Mode

CS1≥VCC - 0.2V

tSDR tRDR

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

Address

CS1

tAW

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,

CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,

tWP is measured from the begining of write to the end of write.

2. tCW is measured from the CS1 going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2)

applied in case a write ends as CS2 going to low.

CS2

tCW(2)

Data in Data Valid

Data out High-Z High-Z

tCW(2) tWR(4)

tWP(1)

tDW tDH

tAS(3)

tWC

CS2 controlled

VCC

4.5V

0.4V

VDR

CS2

GND

Data Retention Mode

tSDR tRDR

CS2≤0.2V

KM68512A Family CMOS SRAM

Revision 4.0

January 1997

PACKAGE DIMENSIONS

32 PIN SMALL OUTLINE PACKAGE (525mil)

Units: millimeter(Inch)

0~8°

#32

20.47±0.20

0.806±0.008

MAX

20.87

0.822 MAX

2.74±0.20

0.108±0.008

3.00

0.118

MIN

0.002

0.05

0.004 MAX

0.10 MAX

0.71

( )

0.028

13.34

0.525

11.43±0.20

0.450±0.008

0.80±0.20

0.031±0.008

+0.10

0.20 -0.05

+0.004

0.008

-0.002

14.12±0.30

0.556±0.012

#17

#16

1.27

0.050

+0.100

0.41 -0.050

+0.004

0.016 -0.002

32-THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

#32

1.00±0.10

0.039±0.004

MAX

8.40

0.331

0.10 MAX

0.004 MAX

0.50

( )

0.020

18.40±0.10

0.724±0.004

0.45 ~0.75

0.018 ~0.030

20.00±0.20

0.787±0.008

#17

+0.10

0.15 -0.05

+0.004

0.006

-0.002

0~8°

+0.10

0.20 -0.05

+0.004

0.008

-0.002

0.50

0.0197

0.25

( )

0.010

MIN

0.05

0.002

MAX

1.20

0.047

8.00

0.315

TYP

0.25

0.010

#16