Peripheral Data Controller (PDC) - Atmel Corporation

Features

•Compatible with an Embedded ARM7TDMI™Processor

•Generates Transfers to/from Serial Peripheral such as USART and SPI

•Supports Up to Eight USARTs/Four SPIs – Parametrizable on Request

•One ARM Cycle Needed for a Transfer from Memory to Peripheral

•Two ARM Cycles Needed for a Transfer from Peripheral to Memory

•Fully Scan Testable up to 98% Fault Coverage

•Can be Directly Connected to the Atmel Implementation of the AMBA™Bridge

•Not Fully Compatible with AMBA: Retract Response not Supported

Description

The Peripheral Data Controller (PDC) transfers data between on-chip peripherals

such as the USART and SPI and the on- and off-chip memories. This transfer is

achieved via the AMBA Bridge using a simple arbitration mechanism between the

AMBA System Bus (ASB) and the PDC to control Bridge access. This avoids proces-

sor intervention, and removes the processor interrupt handling overhead. This

significantly reduces the number of clock cycles required for a data transfer and, as a

result, improves the performance of the microcontroller and makes it more power-

efficient.

The PDC channels are implemented in pairs, each pair dedicated to a particular

peripheral. One PDC channel in the pair is dedicated to the receiving channel and one

to the transmitting channel of each USART and SPI.

The user interface of a PDC channel is integrated in the memory space of each

peripheral. It contains a 32-bit memory pointer register and a 16-bit transfer count reg-

ister. The peripheral triggers PDC transfers using transmit and receive signals. When

the programmed data is transferred, an end of transfer interrupt is generated by the

corresponding peripheral.

32-bit

Embedded ASIC

Macrocell

Peripheral Data

Controller

(PDC)

Rev. 1363D–CASIC–04/02

2Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Figure 1. PDC Symbol

Table 1. PDC Pin Description

Name Definition Type

Active

Level Comments

Chip-wide

nreset_r System Reset Input Low Resets all counters and signals–clocked on

rising edge of clock

nreset_f System Reset Input Low Resets all counters and signals–clocked on

falling edge of clock

clock System Clock Input – System clock

nclock System Clock Input – Inverted system clock

AMBA System Bus (ASB)

agnt Grant Signal Input High Arbiter grants the bus to the PDC when this

input is set to 1

bwait Bus Wait Input High 1 cycle wait is required

bridge_sel Bridge Select Input High From address decoder of system bus

areq Request Signal Output High Bus request sent to the Arbiter

oe_master_address Output Enable Output High Output address enable–this signal indicates

that master_add[31:0], blok, bprot[1:0],

bsize[1:0] and bwrite signals are currently

valid with PDC granted on the bus

master_add[31:0] Address System Bus Output – Address bus generated by master

blok Bus Locked Output High Indicates that the ongoing instruction must

not be interrupted

bprot[1:0] Bus Protection Output – Protection information

nreset_r

PDC

nreset_f

clock

agnt

bwait

bridge_sel

periph_write

periph_stb

periph_add[13:0]

p_d_in[31:0]

periph_clocks[(per_n1-1):0]

periph_rx_rdy[(per_n1-1):0]

periph_tx_rdy[(per_n1-1):0]

p_sel_periph[(per_n1-1):0]

spi_size[(2*spi_n2):0]

scan_test_mode

test_si[(1+per_n1):1]

test_se

areq

oe_master_address

master_add[31:0]

bprot[1:0]

blok

p_d_out[31:0]

memory_write

btran[1:0]

bwrite

bsize[1:0]

pdc_add[20:0]

pdc_sel

pdc_size[1:0]

pdc_write

periph_rx_end[(per_n1-1):0]

periph_tx_end[(per_n1-1):0]

test_so[(1+per_n1):1]

AMBA

System

Bus (ASB)

AMBA

Peripheral

Bus (APB)

Test

Scan

Peripherals

Test Scan

Peripherals

Bridge

AMBA

Peripheral

Bus (APB)

AMBA

System

Bus (ASB)

Memory

Management

Unit/EBI

1 per_n: Number of peripherals 2 spi_n: Number of SPI blocks

nclock

Peripheral Data Controller (PDC)

1363D–CASIC–04/02

bsize[1:0] Size of Transfer Output –Bus size

btran[1:0] Type of Transfer Output –Bus transfer

bwrite Bus Write Output High The PDC transfers data from the peripheral

to internal memory

AMBA Peripheral Bus (APB)

periph_write Peripheral Write Enable Input High From host (Bridge)

periph_stb Peripheral Strobe Input High From host (Bridge)

periph_add[13:0] Peripheral Address Bus Input –From host (Bridge)

p_d_in[31:0] Peripheral Data Bus Input –From host (Bridge)–user interface data bus

p_d_out[31:0] Peripheral Data Bus output Output –User interface data bus

Peripherals

periph_clocks

[per_n-1:0]

Peripheral System Clocks

(USART/SPI)

Input –Per_n values range from 1 to 12. Maximum

number of SPIs is 4. Zero possible.

Maximum number of USARTs is 8. Zero

possible.

LSBs are reserved for USARTs. Remaining

upper bits reserved for SPIs.

periph_rx_rdy

[(per_n-1):0]

Peripheral Receiver Ready Input High Once a character has been received by

peripheral, one of these bits is set to 1.

LSBs are reserved for USARTs. Remaining

upper bits are reserved for SPIs

periph_tx_rdy

[(per_n-1):0]

Peripheral Transmitter Ready Input High Once the holding transmit register is

available, one of these bits is set to 1

spi_size[(2*spi_n):0] SPI Transfer Sizes Input –The spi_n is the number of SPIs connected to

the PDC. The MSB is reserved and must be

tied to 0

This value changes the memory pointer

2 bits are reserved for each SPI, for example,

SPI1=SPI_SIZE[1:0], SPI2=SPI_SIZE[3:2].

Each field indicates the size of the transfer

(byte, half-word, word).

p_sel_periph

[(per_n-1):0]

Peripheral selects Input High From host (Bridge)–also input of each

peripheral connected

periph_rx_end

[(per_n-1):0]

Peripheral receive end Output High End of receive transfer (each bit corresponds

to a peripheral)–the associated buffer for the

channel is full

periph_tx_end

[(per_n-1):0]

Peripheral Transmit End Output High End of transmit transfer (each bit

corresponds to a peripheral)–the associated

buffer for the channel is full

Bridge Interface

pdc_add[20:0] PDC Address Bus Output –Used by the Bridge to access the peripherals

pdc_sel PDC Select Output High Used by the Bridge to access the peripherals

Table 1. PDC Pin Description (Continued)

Name Definition Type

Active

Level Comments

4Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Scan Test

Configuration

The fault coverage is maximum if all non-scan inputs can be controlled and all non-scan

outputs can be observed. In order to achieve this, the ATPG vectors must be generated

on the entire circuit (top-level) which includes the PDC, or all PDC I/Os must have a top

level access and ATPG vectors must be applied to these pins.

Configuration The PDC has a standard Atmel Bridge interface that enables the user to configure and

control the data transfers for each channel.

The size of the transfer is configured in an internal 16-bit transfer counter register, and it

is possible, at any moment, to read the number of transfers left for each channel.

The base memory address is configured in a 32-bit memory pointer, by defining the

location of the first access point in the memory. It is possible, at any moment, to read the

location in memory of the next transfer.

The PDC does not have a dedicated status register—the status for each channel is

located in the peripheral. The PDC sends status flags (periph_end) to the peripheral,

which latches the flag in its status register.

System Bus Interface The PDC interfaces with the AMBA System Bus (ASB) and generates all the control sig-

nals for interfacing with a Memory Management Unit or EBI for memory read and write.

pdc_size[1:0] PDC Size of Transfer Output –Multiplex the spi_size inputs–used by the

Bridge to determine the size of the transfer

between memories and the SPI

pdc_write PDC Write Output High Used by the Bridge to access the peripherals

Memory Interface

memory_write Memory Write from Peripheral Output High Used by Memory Management Unit or EBI to

select data coming from masters or

peripherals (Bridge)

Test Scan

scan_test_mode Clock Selection for Test

Purposes

Input High Tied to 1 during scan test–tied to 0 when in

function mode

test_se Scan Test Enable Input High

/low

Scan shift/scan capture

test_si [(1+per_n):1] Scan Test Input Input –Entry of scan chain

test_so [(1+per_n):1] Scan Test Output Output –Ouput of scan chain

Table 1. PDC Pin Description (Continued)

Name Definition Type

Active

Level Comments

Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Memory Pointers Each peripheral is connected to the PDC by a receive data channel and a transmit data

channel. Each channel has an internal 32-bit memory pointer. Each memory pointer

points to a location in the system bus memory space (on-chip memory or external bus

interface memory)

Depending on the type of transfer (byte, half-word or word) the memory pointer is incre-

mented by 1, 2 or 4 respectively for SPI transfers.

USART-associated memory pointers only increment by 1.

If a memory pointer is reprogrammed while the PDC is in operation, the transfer

addresses are changed, and the PDC performs transfers using the new address.

Transfer Counters There is one internal 16-bit transfer counter for each channel. Each counter is used to

count the size of the block already transferred by its associated channel. These

counters are decremented after each data transfer. When the counter reaches zero, the

transfer is complete and the PDC stops transferring data and disables the trigger.

If the counter is reprogrammed while the PDC is operating then the number of transfers

is changed, and the PDC counts transfers from the new value.

Data Transfers The peripheral triggers PDC transfers using transmit (periph_tx_rdy) and receive

(periph_rx_rdy) signals.

When the peripheral receives an external character, it sends a Receive Ready signal to

the PDC, which then requests access to the system bus (ASB) from the Bus Arbiter.

When access is granted, the PDC starts a read of the peripheral Receive Holding Regis-

ter, via the dedicated pdc_add, pdc_sel, pdc_write and pdc_size signals to the Bridge.

Next, the PDC triggers a write in the memory by setting the ASB control signals and, at

the same time, the Bridge provides the data that is to be written to the memory.

After each transfer, the relevant PDC memory pointer is incremented, and the numbers

of transfers left is decremented. When the memory block size is reached, a signal is

sent to the peripheral and the transfer stops.

The same procedure is followed, in reverse, for transmit transfers.

These timing exchanges are shown in Figures 4, 5, 6, 7, and 8.

6Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Figure 2. Example of PDC Connection with Bridge and SPI

Note: Range: From 0 to 3

ba[31:0]

bwrite

bwdata[31:0]

master_add[31:0]

bsize[1:0]

bwrite

blok

bprot[1:0]

btran[1:0]

pdc_sel

pdc_size[1:0]

pdc_add[20:0]

pdc_write

periph_rx_rdy[i]

periph_tx_rdy[i]

periph_rx_end[i]

periph_tx_end[i]

spi_size[((2*i)+1):(2*i)]

spi_size[1:0]

spi_tx_end

spi_rx_end

spi_tx_rdy

spi_rx_rdy

pdc_data[31:0]

add_master[20:0]

write_master

data_from_master[31:0]

pdc_sel

pdc_size[1:0]

pdc_add[20:0]

pdc_write

periph_stb

periph_add[13:0]

periph_write

p_sel_spi[i](1)

data_from_periph[31:0]

data_to_periph[31:0]

p_stb_rising

SPI

(spi[i](1))

Data from

Memories

PDC

BRIDGE

Master Signals Manager

p_sel_periph[i]

periph_write

periph_add[13:0]

periph_stb

p_d_in[31:0]

p_d_out[31:0]

p_d_in[31:0]

p_d_out[31:0]

p_write

p_sel_spi

p_stb_rising

periph_add[13:0]

periph_stb

MUX

ba_from_masters[31:0]

bsize[1:0]

bwrite_from_masters

blok_from_masters

bprot_from_masters[1:0]

btran_from_masters[1:0]

data_to_master[31:0] bwdata_from_masters[31:0]

Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Figure 3. oe_master_address Signal for Atmel AMBA Bus

This output is generated to simplify the multiplexing of the control signals generated by

the PDC. It indicates that the PDC is “really granted”on the bus (ASB) and that its con-

trol signals must be sent to the slaves.

Thus, oe_master_address is asserted when the PDC is granted via agnt and there is no

transfer being done by another master, i.e. bwait_in is inactive. oe_master_address is

de-asserted when the core has finished its last transfer, i.e. bwait_in is inactive.

agnt

clock

bwait_in

tOVMABE

oe_master_address

8Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Figure 4. ASB to APB Transfer with Zero Wait States Memory Followed by an APB Access Made by Another Master

clock

areq (PDC)

agnt (PDC)

bridge_sel

agnt (other master)

bwait

bwrite (PDC)

master_add[31:0]

PDC status

bwrite (ASB)

ba[31:0] (ASB)

memory_write

pdc_size[1:0]

pdc_write

pdc_add[20:0]

Data from Memories

(pdc_data[31:0] on Bridge)

pdc_sel

bwdata[31:0]

(data_from_master[31:0] on bridge)

periph_stb

pstb_rising

periph_add[13:0]

periph_write

p_d_in[31:0]

done donewaitwait

Memory

Address

TransferNOT GRANTED NOT GRANTED

Peripheral Address

PDC Data

PDC

Data Data from Master

14'h0000 Peripheral Address Address from Master 14'h0000

bwrite from Master

Previous Data PDC Data Data from Master

done

bwrite from Master

Memory

Address ba from Master

Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Figure 5. APB to ASB Transfer with Zero Wait States Memory Followed by an APB Access Made by Another Master

clock

areq (PDC)

agnt (PDC)

bridge_sel

agnt (other master)

bwait

bwrite

ba[31:0]

PDC status

bwrite (ASB)

ba[31:0] (ASB)

memory_write

pdc_size[1:0]

pdc_write

pdc_add[20:0]

pdc_sel

brdata[31:0]

periph_stb

pstb_rising

periph_add[13:0]

periph_write

data_to_master[31:0]

(output of the bridge)

done donewait

Memory Address

TransferNOT GRANTED NOT GRANTED

Peripheral Address

Data from Bridge

14'h0000 Peripheral Address Address from Master 14'h0000

bwrite from Master

Previous Data Data for PDC Transfer Data for Master

done done

Locked Idle Cycle

bwrite from Master

Memory Address ba from Master

Data from Memories

14'h0000

10 Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Figure 6. APB to ASB Transfer with Zero Wait States Following:

1. Series of APB Accesses Made by Another Master,

2. Memory With One Wait State Made by Another Master

clock

areq (PDC)

agnt (PDC)

bridge_sel

agnt (other master)

bwait

bwrite

ba[31:0]

PDC status

bwrite (ASB)

ba[31:0] (ASB)

memory_write

pdc_size[1:0]

pdc_write

pdc_add[20:0]

pdc_sel

brdata[31:0]

periph_stb

pstb_rising

periph_add[13:0]

periph_write

data_to_master[31:0]

(output of the bridge)

done

Memory Address

TransferNOT GRANTED NOT GRANTED

Data from Bridge

Peripheral Address14'h0000

bwrite from Master

done done

Locked Idle Cycle

bwrite from Master

Data from Memories

wait done wait wait done

bwrite from Master

Memory Addressba from Master

ba from Master ba from Master

Peripheral Address

Data from Bridge

Address from Master Address from Master 14'h0000

bwrite from Master

Data for Master Data for PDC TransferData for Master

Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Figure 7. ASB to APB Transfer with Three Wait States Memory

clock

areq (PDC)

agnt (PDC)

bridge_sel

agnt (other master)

bwait

bwrite

ba[31:0]

PDC status

bwrite (ASB)

ba [31:0] (ASB)

memory_write

pdc_size[1:0]

pdc_write

pdc_add[20:0]

done

Memory Address

TransferNOT GRANTED NOT GRANTED

wait

bwrite from Master

Memory Address ba from Master

Peripheral Address

pdc_sel

bwdata[31:0]

(data_from_master[31:0]

on bridge)

periph_stb

pstb_rising

periph_add[13:0]

periph_write

p_d_in[31:0]

(pwdata[31:0])

Address from MasterPeripheral Address14'h0000

done wait wait wait wait done

PDC Data

Data from Master

PDC

Data

bwrite from Master

Previous Data Data from MasterPDC Data

Data from Memories

(pdc_data[31:0] on bridge)

12 Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Figure 8. APB to ASB Transfer with Three Wait States Memory

clock

areq (PDC)

agnt (PDC)

bridge_sel

agnt (other master)

bwait

bwrite

ba[31:0]

PDC status

bwrite (ASB)

ba[31:0] (ASB)

memory_write

pdc_size[1:0]

pdc_write

pdc_add[20:0]

pdc_sel

brdata[31:0]

periph_stb

pstb_rising

periph_add[13:0]

periph_write

data_to_master[31:0]

(output of the bridge)

Memory Address

Transfer

NOT GRANTED NOT

GRANTED

bwrite from Master

Data from Memories

done wait wait done

Memory Addressba from Master

Peripheral Address

14'h0000 Peripheral Address 14'h0000

Data for PDC Transfer

Previous Data

wait done wait wait wait

Locked Idle Cycle

Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Software Interface

Four registers make up the peripheral memory map for each of the peripherals.

USART User Interface

SPI User Interface

Table 2. USART Memory Map

Offset Register Name Access Reset State

0x30 Receive Pointer Register US_RPR Read/Write 0

0x34 Receive Counter Register US_RCR Read/Write 0

0x38 Transmit Pointer Register US_TPR Read/Write 0

0x3C Transmit Counter Register US_TCR Read/Write 0

Table 3. SPI Memory Map

Offset Register Name Access Reset State

0x20 Receive Pointer Register SP_RPR Read/Write 0

0x24 Receive Counter Register SP_RCR Read/Write 0

0x28 Transmit Pointer Register SP_TPR Read/Write 0

0x2C Transmit Counter Register SP_TCR Read/Write 0

14 Peripheral Data Controller (PDC)

1363D–CASIC–04/02

USART/SPI Receive Pointer Register

Access Type: Read/Write

•RXPTR: Receive Pointer Register

RXPTR must be loaded with the address of the receive buffer.

USART/SPI Receive Counter Register

Access Type: Read/Write

•RXCTR: Receive Counter Register

RXCTR must be loaded with the size of the receive buffer.

0 = Stop peripheral data transfer to the receiver

1 - 65535 = Start peripheral data transfer if corresponding periph_px_rdy is active

31 30 29 28 27 26 25 24

RXPTR

23 22 21 20 19 18 17 16

RXPTR

15 14 13 12 11 10 9 8

RXPTR

76543210

RXPTR

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

RXCTR

76543210

RXCTR

Peripheral Data Controller (PDC)

1363D–CASIC–04/02

USART/SPI Transmit Pointer Register

Access Type: Read/Write

•TXPTR: Transmit Counter Register

TXCTR must be loaded with the address of the transmit buffer.

USART/SPI Transmit Counter Register

Access Type: Read/Write

•TXCTR: Transmit Counter Register

TXCTR must be loaded with the size of the transmit buffer.

0 = Stop peripheral data transfer to the transmitter

1- 65535 = Start peripheral data transfer if corresponding periph_tx_rdy is active

31 30 29 28 27 26 25 24

TXTPR

23 22 21 20 19 18 17 16

TXTPR

15 14 13 12 11 10 9 8

TXTPR

76543210

TXTPR

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

TXCTR

76543210

TXCTR

16 Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Timing Diagrams

Figure 9. Peripheral Bus Interface

periph_clock[i]

periph_stb

periph_write

p_d_in[31:0]

p_d_out[31:0]

p_sel_periph[i]

SU_STB

HOLD_STB

HOLD_A

SU_A

SU_DIN

HOLD_DIN

SU_WRITE

HOLD_WRITE

VALID_OUT

HOLD_OUT

SU_PSEL

HOLD_PSEL

periph_add[13:0]

Table 4. Peripheral Bus Interface Parameters

Parameter Description

tSU_STB periph_stb setup to rising periph_clocks [i]

tHOLD_STB periph_stb hold after rising periph_clocks [i]

tSU_A periph_add setup to rising periph_clocks [i]

tHOLD_A periph_add hold after rising periph_clocks [i]

tSU_DIN p_d_in setup to rising periph_clocks [i]

tHOLD_DIN p_d_in hold after rising periph_clocks [i]

tSU_WRITE periph_write setup to rising periph_clocks [i]

tHOLD_WRITE periph_write hold after rising periph_clocks [i]

tSU_PSEL p_sel_periph setup to rising periph_clocks [i]

tHOLD_PSEL p_sel_periph hold after rising periph_clocks [i]

tVALID_OUT p_d_out valid after falling periph_clocks[i]

tHOLD_OUT p_d_out hold after falling p_sel_periph[i]

Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Figure 10. Advanced System Bus Dedicated Signals

clock

areq

bsize[1:0]

bprot[1:0]

btran[1:0]

VALID_AREQ

HOLD_AREQ

master_add[31:0]

HOLD_BA

VALID_BA

HOLD_BPROT

VALID_BPROT

HOLD_BSIZE

VALID_BSIZE

HOLD_BTRAN

VALID_BTRAN

HOLD_BWRITE

VALID_BWRITE

HOLD_BLOK

VALID_BLOK

Memory Address

bwrite

blok

18 Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Specific Signals Interfacing with Bridge and EBI

Figure 11. Read APB

clock

agnt

pdc_sel

bwait

memory_write

(to memory

management

units)

pdc_add[20:0]

tINVALID_RPDC_SEL

tVALID_RPDC_SEL

pdc_size[1:0]

pdc_write

tVALID_PDC_WRITE tHOLD_PDC_WRITE

tVALID_PDC_SIZE tHOLD_PDC_SIZE

tVALID_PDC_ADD tHOLD_PDC_ADD

tVALID_MW tHOLD_MW

Peripheral Data Controller (PDC)

1363D–CASIC–04/02

Figure 12. Write APB

clock

agnt

pdc_sel

bwait

memory_write

(to memory

management

units)

pdc_add[20:0]

tHOLD_WPDC_SEL

tVALID_WPDC_SEL

pdc_size[1:0]

pdc_write

tVALID_PDC_WRITE tHOLD_PDC_WRITE

tVALID_PDC_SIZE tHOLD_PDC_SIZE

tVALID_PDC_ADD tHOLD_PDC_ADD

tVALID_MW tHOLD_MW

Printed on recycled paper.

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