AHA3431 StarLite - Advanced Hardware Architectures, Inc.

PS3431-0500

2365 NE Ho p kin s Co urt

Pullman, WA 99163-5601

tel: 509.334.1000

fax: 509.334.9000

e-mail: sales@aha . com

www.aha.com

advancedhardwarearchitectures

Product Specification

AHA3431 StarLiteTM

40 MBytes/sec Simultaneous

Compressor/Decompressor IC, 3.3V

Advanced Hardware Architectures, Inc.
PS3431-0500 i
Table of Contents
0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
0 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1 Data Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2 DMA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3 Pad Word Handling in Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4 DMA Request Signals and Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.1 FIFO Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2 Request During an End-of-Record. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.3 Request Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6 Odd Byte Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6.1 Compression Input and Pad Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6.2 Compression Output and Pad Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6.3 Decompression Input, Pad Bytes and Error Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6.4 Decompression Output and Pad Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7 Video Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
7.1 Video Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
7.2 Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
8 Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
9 Compression Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
10 Decompression Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
11 Prearming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
12 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
13 Duplex Printing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4
14 Blank Bands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
15 Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
16 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1 System Configuration 0, Address 0x00 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2 System Configuration 1, Address 0x01 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3 Input FIFO Thresholds, Address 0x02 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4 Output FIFO Thresholds, Address 0x03 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5 Compression Ports Status, Address 0x04 - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
6 Decompression Ports Status, Address 0x05 - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7 Port Control, Address 0x06 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
8 Interrupt Status/Control 1, Address 0x07 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
9 Interrupt Mask 1, Address 0x09 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
10 Version, Address 0x0A - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
11 Decompression Record Length, Address 0x0C, 0x0D, 0x0E, 0x0F - Read/Write. . . . . . . . . . . . . . . . . . . .22
12 Compression Record Length, Address 0x10, 0x11, 0x12, 0x13 - Read/Write . . . . . . . . . . . . . . . . . . . . . .22
13 Compression Control, Address 0x14 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
14 Compression Reserved, Address 0x15 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
15 Compression Line Length, Address 0x16, 0x17 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
16 Decompression Control, Address 0x18 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
17 Decompression Reserved, Address 0x1A - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Advanced Hardware Arc h itectur es, Inc.
ii PS3431-0500
18 Decompression Line Length, Address 0x1C, 0x1D - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
19 Compression Record Count, Address 0x20, 0x21 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
20 Interrupt Status/Control 2, Address 0x27 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
21 Interrupt Mask 2, Address 0x29 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
22 Decompression Record Count, Address 0x2C, 0x2D - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
23 Compression Byte Count, Address 0x30, 0x31, 0x32, 0x33 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . .2 6
24 Compression Control Prearm, Address 0x34 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
25 Pattern, Address 0x35 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
26 Decompression Control Prearm, Address 0x38 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
27 Decompression Reserved, Address 0x3A - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2 Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3 Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
0 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
0 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
1 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
0 AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
0 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
0 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
2 Part Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
0 Related Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2
Appendix A:Additional Timing Diagrams for DMA Mode Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Appendix B:Recommended Power Decoupling Capacitor Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Advanced Hardware Architectures, Inc.
PS3431-0500 iii
Figures
Figure 1: Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3: Microprocessor Port Read (PROCMODE[1:0]=“01”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4: Microprocessor Port Write (PROCMODE[1:0]=“11”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5: Microprocessor Port Read (PROCMODE[1:0]=“11”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100. . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100. . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 8: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=100 . . . . . . . . .7
Figure 9: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=100. . . . . . . . .8
Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=100 . . . . . . . .8
Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DS C=100 . . . . . . . .8
Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO). . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 14: Timing Diagram, Video Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 15: Timing Diagram, Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 16: Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 17: Data Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 4
Figure 18: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-7; ERC=0 . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 19: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-7; ERC=1 . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 20: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0. . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 21: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1. . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 22: Output Enable Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 23: Video Input Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 6
Figure 24: Video Output Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 25: Microprocessor Interface Timing (PROCMODE[1]=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 26: Microprocessor Interface Timing (PROCMODE[1]=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 27: Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 28: Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 29: Power On Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure A1: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000...............................................43
Figure A2: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000...............................................43
Figure A3: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=000 ...............43
Figure A4: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=000...............44
Figure A5: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=000..............44
Figure A6: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=000..............4 4
Figure A7: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=010...............................................45
Figure A8: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=010...............................................45
Figure A9: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=010 ...............45
Figure A10:DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=010...............46
Figure A11:DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=010..............46
Figure A12:DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=010..............46
Figure A13:DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011...............................................47
Figure A14:DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011 ...............................................47
Figure A15:DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=011...............47
Figure A16:DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=011...............48
Figure A17:DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=011..............48
Figure A18:DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=011..............48
Figure A19:DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111...............................................49
Figure A20:DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111...............................................49

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iv PS3431-0500
Tables
Table 1: Data Bus and FIFO Sizes Supported by AHA3431 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 2: AHA3431 Connection to Host Microprocessors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Table 3: Microprocessor Port Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 4: Internal Strobe Conditions for DMA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 5: Internal Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 6: Data Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 7: Request vs. EOR Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 6
Table 8: Output Enable Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 9: Video Input Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 10: Video Output Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 11: Microprocessor Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 12: Interrupt Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 13: Clock Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 14: Power On Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

PS3431-0500 Page 1 of 50

Advanced Hardware Architectures, Inc.

1.0 INTRODUCTION

AHA3431 is a lossless compression

coprocessor IC for hardcopy systems on many

standard platforms. The device is targeted for high

throughput and high resolution hardcopy systems.

The AHA3431 is functionally backward compatible

to the AHA3411.

Enhancements to this product over the

AHA3411 include improved I/O timings, higher

operati ng frequency and data rate, and l ower power .

Blank band generation in real time and

prearming registers between records enable

advanced banding techniques. Bands may be in raw

uncompressed, compressed or blank format in the

frame buffer. The device processes all three formats

and outputs the raster data to the printer engine.

Appropri ate registers are prearmed when swit ching

from one type to the next. Separate byte ordering

between the Compressor and the Decompressor

with bit order control into the compressor allow full

reversal of the image data for duplex printing

support. A system may use multiple record counters

and End-of-Transfer interrupts to easily handle

pages partitioned into smaller records or bands.

This docume nt contains f unctional descr iption,

system configurations, register descriptions,

electrical characteristics and ordering information.

It is inten ded for system designers c onsi derin g a

compression coprocessor in their embedded

applications. Software simulation and an analysis of

the algorithm for p r inter and copier image s of

various complexity are also available for

evaluation. A comprehensive Designer’s Guide

complements this document to assist with the

system design. Section 11.0 contains a list of related

technical publications.

1.1 CONVENTIONS, NOTATIONS AND

DEFINITIONS

–Active low signals h ave an “N” appended to the

end of the signal name. For example, CSN and

RDYN.

–A “bar” over a signal name indicates an inverse of

the signal. For example, SD indicates an inverse

of SD. This terminology is used only in logic

equations.

–“Signal assertion” means the output signal is

logically true.

–Hex values are represented with a prefix of “0x”,

such as Register “0x00”. Binary values do not

contain a prefix, for example, DSC=000.

–A range of signal names or register bits is denoted

by a set of colons between the numbers. Most

signif icant bi t i s a lway s shown fir st , followed by

least significant bit. For example, VOD[7:0]

indicates signal names VOD7 through VOD0.

–A logical “AND” function of two signals is

expressed w i th an “&” between variables.

–Mega Bytes per second is referred to as MBytes/

sec or MB/sec.

–In refe rencing microproc essors, an x, xx or xxx is

used as suffix to indicate more than one

process or. For exampl e, Motor ola 68xxx

processor family includes various 68000

processors from Motorola.

–Reserved bits in reg isters are referred as “res”.

–REQN or ACKN refer to either CI, DI, CO or DO

Request or Acknowledge signals, as applicable.

1.2 FEATURES

PERFORMANCE:

•40 MBytes /s ec maxi mum sus ta ine d compressi on

and decompression rate

•160 MBytes/se c burst data rat e over a 32- bit dat a

bus

•40 MBytes/sec synchronous 8-bit video in and

video out ports

•Maximum clock speeds up to 40 MHz

•Simultane ous compress ion and deco mpressi on at

full bandwidth

•Average 15 to 1 compression ratio for 1200 dpi

bitmap image data

•Advanced banding support: blank bands,

prearming

FLEXIBILITY:

•Big Endian or Little Endian; 32 or 16-bit bus

width and data bit/byte reordering for duplex

printing support

•Programmable Record Length, Record Count and

Scan Length Registers may be prearmed

•Scan line length up to 2K bytes

•Interfaces directly with various MIPS, Motorola

68xxx and Cold FIRE, and Intel i960 embedded

processors

•Pass-through mode passes raw data through

compression and decompression engines

•Counter checks errors in decompression

SYSTEM INTERFACE:

•Single chi p comp ressi on/dec ompress ion sol ution

– no external SRAM required

•Four 16 × 32-bit FIFOs with programmable

threshold counters facilitate burst mode transfers

OTHERS:

•Low power modes

•Software emulation program available

•128 pin quad flat package

•3.3V operation

•Test pin tris tates outputs

•Firmware, Register, Pinout and Functional

compatible with 5V, AHA3411

Page 2 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

Figure 1: Functional Block Diagram

1.3 FUNCTIONAL OVERVIEW

The copr ocesso r device has t hree exter nal h igh

speed synchronous data ports capable of

transf erri ng once ever y cloc k cycl e. Thes e are a 32-

bit bidirectional data port, an 8-bit V ideo Input Data

(VID) port and a Video Output Data (VOD) port.

The 32-bit port is capable of transferring up to 4

bytes per clock. The VID and VOD are capable of

up to one byte per clock.

The devic e accepts unc ompressed data through

the 8-bit VID port or the 32 -bit d ata po rt into its

Compression In FIFO (CI FIFO). The 32-bit data

port may be configured for 16-bit transfers.

Compressed data is available through the 32-bit

data port via the Compressed Output FIFO (CO

FIFO). The sustained data rate through the

compression engine is one byte per clock.

Decompression data may be simultaneously

processed by the device. Decompression data is

accepted through the 32-bit data port, buffered in

the Decompression Inpu t FIF O (DI FIFO) and

decompressed. The output data is made available on

the 32-bi t data port via the Dec ompression Ou tput

FIFO (DO FIFO) or the 8-bit Video Output port.

The decompr ession engin e is cap able of process ing

an uncompressed byte every clock.

The four FIFOs are organized as 16×32 each.

For data transfers through the three ports, the

“effective” FIFO sizes dif fer according to their data

bus widths. The table below shows the size of the

data port and the “effective” FIFO size fo r the

various configurations supported by the device.

Table 1: Data Bus and FIFO Sizes Supported by AHA3431

(From Scanner)

VIREQN

VID[7:0]

VIACKN

D[31:0]

DRIVEN

TEST

CLK

RSTN

PROCMODE[1:0]

PD[7:0]

PA[5:0]

CSN

DIR

RDYN

INTRN

VOACKN

VOD[7:0]

VOREQN

VOEORN

VOEOTN

(To Printer)

COEORN

DOREQN

COREQN

DIREQN

CIREQN

DOACKN

COACKN

DIACKN

CIACKN

VID

PORT

DATA

PORT

FIFO

16x32

FIFO

16x32

CLOCK

DATA PORT CONTR O L

COMPRESSOR

DECOMPRESSOR

MICROP ROCESSO R INT ERFACE

FIFO

16x32

FIFO

16x32

VOD

PORT

AHA3431

StarLiteTM

8 8

888

32 32

COEOTN

OPERATION DATA BUS WIDTH PORT EFFECTIVE FIFO SIZE

Compres sion Data In 8 Video In 16 x 8

Com pression Data In/Out 32 Data Port 16 x 32

Com pression Data In/Out 16 Data Port 16 x 16

Decompression Data In/Out 32 Data Port 16 x 32

Decompression Data In/Out 16 Data Port 16 x 16

Decompressed Data Out 8 Video Out 16 x 8

PS3431-0500 Page 3 of 50

Advanced Hardware Architectures, Inc.

Table 2: AHA3431 Connection to Host Microproce ss ors

Movement of data for compression or

decompression is performed using synchronous

DMA over the 32-bit data port. The Video ports

support synchronous DMA mode transfers. The

DMA strobe cond itions ar e configur able for t he 32-

bit data port depending upon the system processor

and the available DMA controller.

Data transfer for compressio n or

decompression is synchronous over the three data

ports functioning as DMA masters. To initiate a

transfer into or out of the Video ports, the device

asserts VxREQN, the external device responds with

VxACKN and begins to transfer data o ver t he VID

or VOD busses on each succeeding rising edge of

the clock until VxREQN is deasserted. The 32-bit

port relies on the FIFO Threshold settings to

determine the transfer.

The sections below describe the various

configurations, programming and other special

conside rations in developi ng a compression system

using AHA3431.

2.0 SYSTEM CONFIGURATION

This section provides information on

connecting AHA3431 to various microprocessors.

2.1 MICROPROCESSOR INTERFACE

The devi ce i s cap abl e of interf aci ng directl y to

various processors for embedded application. T able

2 and Table 3 show how AHA3431 should be

connected to various host microprocessors.

All register accesses to AHA3431 are

performed on the 8-bit PD bus. The PD bus is the

lowest byte of the 32-bit microprocessor bus.

During reads of the internal registers, the upper 24

bits are not driven. System designers should

terminate these lines with Pullup resis tors.

AHA3431 provides four modes of operation for

the microprocessor port. Both active high and active

low writ e enabl e si gnals are al lowed a s well as two

modes for c hip se lect. T he mode of oper atio n is set

by the PROCMODE[1:0] pins. The

PROCMODE[1] signal select s whe n CSN must be

active and also ho w long an access last s.

When PROCMODE[1] is high, CSN

determines the length of the ac cess. CSN must be at

least 5 clocks in length. On a read, valid data is

driven ont o PD[7:0] during th e 5th clock . If CSN is

longer than 5 clocks, then valid data continues to b e

driven out onto PD[7:0]. When CSN goes inactive

(high), PD[7:0] goes tristate (asynchronously) and

RDYN is driven high asynchronously . CSN must be

high for at least two clocks. RDYN is always driven

(it is not tristated when P ROCMODE[1] is high). The

mode is typical of processors such as the Motorola

68xxx.

When PROCMODE[1] is low, accesses are

fixed at 5 cl ocks, PD[7: 0] is onl y driven dur ing the

fifth cloc k, and RDYN is drive n high for the first 4

clocks and low during the fifth clock. RDYN is

tristated at all other times. Write data must be driven

the clock afte r CSN is sampled low. Accesses may

be back to back with no delays in between. This

mode is typical of RISC processors such as the i960.

PROCMODE[0] dete rmin es th e pol arit y of t he

DIR pin. If PROCMODE[0] is high, then the DIR

pin is an active low write enable. If PROCMODE[0]

is low, then the DIR pin is an active hi gh write

enable. Figure 2 through Figure 5 illustrate the

detailed timing diagrams for the microprocessor

interface.

For additional notes on interfacing to various

microprocessors, refer to AHA A pplication No te

(ANDC16), Designer’s Guide for StarLiteTM Family

Products. AHA Applications Engineering is

availa ble to support with othe r processors not in the

Designer’s Guide.

PIN NAM E i960 Cx i960Kx IDT3 08 1 Motorola

MCFS102(ColdFIRE)

PA A LAD Latched Address Latched Address

CSN CS CS System Dependent Decoded Chip Select

DIR W/R W/R WR R/W

PD D LAD A/D A/D[7:0]

SD WAIT READY System Dependent System Dependent

RDYN No Connect READY ACK TA

DRIVEN DEN System Dependent System Dependent System Dependent

CLOCK PCLK No Connect SYSCLK BCLOCK

Page 4 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

Table 3: Microprocessor Port Configuration

Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”)

Figure 3: Microprocessor Port Read (PROCMODE[1:0]=“01”)

PROCMODE[1:0] DIR CYCLE LENGTH EXAMPLE PROCESSOR

00 Active high write fixed i960

01 Active lo w write fixed

10 Active high write variable

11 Active low write variable 68xxx, MIPS R3000

CLOCK

PA[5:0]

CSN

DIR

PD[7:0]

RDYN

D0 D1

CLOCK

PA[5:0]

CSN

DIR

PD[7:0]

RDYN

PS3431-0500 Page 5 of 50

Advanced Hardware Architectures, Inc.

Figure 4: Microprocessor Port W rit e (P RO CM OD E [1 :0] =“11”)

Figure 5: Microprocessor Port Read (PROCMODE[1:0]= “11”)

CLOCK

PA[5:0]

CSN

DIR

PD[7:0]

RDYN

CLOCK

PA[5:0]

CSN

DIR

PD[7:0]

RDYN

Page 6 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

3.0 FUNCTIONAL DESCRIPTION

This section describes the various data ports,

special handling, data formats and clocking

structure.

3.1 DATA PORTS

AHA3431 contains two data input ports, CI and

DI, and two data output ports, CO and DO on the

same 32-bit data bus, D[31:0]. Data transfers are

controlled by external DMA control. The logical

conditions under which data is written to the input

FIFOs or re ad from th e output FIFOs are set by t he

DSC (Data Strobe Condition) field of the System

Configuration 1 register.

A strobe condition defines under what logical

conditions the input FIFOs are written or the output

FIFOs read. CIACKN, COACKN, DIACKN,

DOACKN, and SD pins combine to strobe data in a

manner similar to DMA controllers. The DMA

Mode sub-sect ion des cr ibes th e var ious da ta st robe

options.

3.2 DMA MODE

On the ris ing edge o f CLOCK when the st robe

condition is met, the port with the active

acknowledge either strobes data into or out of the

chip. No more than one port may assert

acknowledge at any one time. Table 4 shows the

various conditions that may be programmed into

Figure 6 through Figure 11 illustrate the DMA

mode timings for singl e, fou r word and ei ght word

burst transfers for DSC=100 selection. For other

DSC settings, please refer to Appendix A. Note that

the only di ffere nce between odd and even val ues of

DSC is the polarity of SD. Waveforms are only

shown for polarities of SD corresponding to specific

systems.

Table 4: Internal Strobe Conditions for DMA Mode

DSC[2:0] LOGIC EQUATION SYSTEM CONFIGURATION

000 i960Cx with i nt er nal DMA cont roller. SD is co nnec te d to

WAITN.

001 No speci fic system

010 General purpose DMA controlle r

011 i960Kx with external, bus master type DMA controller.

SD is connected to RDYN.

100 No speci fic system

101 No speci fic system

110 No specific system

111 N o specific system

ACKN()& ACKNdelayed

()& SD)(

ACKN()& ACKNdelayed

()& SD()

ACKN()& SD()

ACKNdelayed

()& SDdelayed

()

ACKNdelayed

()& SDdelayed

()

ACKN()& ACKNdelayed

()

ACKN()& ACKNdelayed

()

ACKNdelayed ACKN delayed 1 clock=

SDdelayed SD delayed 1 clock=

PS3431-0500 Page 7 of 50

Advanced Hardware Architectures, Inc.

Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100

Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100

Figure 8: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition

of DSC=100

CLOCK

ACKN

DRIVEN

DD0 D1

CLOCK

ACKN

DRIVEN

DD1D0

CLOCK

ACKN

DRIVEN

DD0 D2D1 D3

Page 8 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

Figure 9: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition

of DSC=100

Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait St ate, Strobe Condition

of DSC=100

Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition

of DSC=100

CLOCK

ACKN

DRIVEN

DD1D0 D2 D3

CLOCK

ACKN

DRIVEN

DD0 D2D1 D3 D4 D5 D6 D7

CLOCK

ACKN

DRIVEN

DD0 D2D1 D3 D4 D5 D6 D7

PS3431-0500 Page 9 of 50

Advanced Hardware Architectures, Inc.

3.3 PAD WORD HANDLING IN

BURST MODE

The S tarLite compression algorithm appends

a 15 bit End-of-Record codeword to terminate a

compression record. If a word containing an End-

of-Recor d comes out during a bur st read, the words

following the End-of-Record are invalid (pad)

words. This prevents a burst read from crossing

record boundaries. The first word of the next burst

read is the first word of the next record. Any pad

words not previously removed must be deleted.

Two methods are availa ble to delete pad words.

During decompression pad words may be deleted

by using the Decompression Pause on Record

Boundaries bit (DPOR), in the Decompression

Control register. After the part is paused, the DI

FIFO must be reset by asserting the DIRST bit in the

Port Control register. Decompressor must also be

reset by asserting D DR bit in D ecompression

Control register. The COEOTN signal is asserted

when an End-of- R eco rd i s pre sent on the outp ut of

the CO FIFO and the compression record counter

has decremente d t o z er o, t hus indi cat in g t he end of

a tra nsfer compris ed of one or more compressed

records.

Another method to remove pad words during

compression is to read the Compressed Byte Count

subtract this from the system’s received word count.

This difference is the number of pad words that

must be removed from the end of the compressed

record.

The COEORN signal is asserted when an End-

of-Recor d is present on the output of th e CO FIFO.

COEORN is deasserted after the transfer. In some

systems COEORN can b e used to generat e a DMA-

done condition if conditioned with the

acknowledge.

3.4 DMA REQUEST SIGNALS

AND STATUS

AHA3431 requests data using request pins

(CIREQN, DIREQN, COREQN, DOREQN). The

requests are controlled by programmable FIFO

thresholds. Both input and output FIFOs have

programmable empty and full thresholds set in the

Input FI FO Thr eshol d and Ou tput FIFO Thr es hold

registers. By requesting only when a FIFO can

sustain a cert ain burst size, the bus is used m ore

efficiently.

Operation of these request signals should not be

confused with the request signals on the video ports.

CIREQN or DIREQN active indicates space

available in the particular input FIFO, and

COREQN or DOREQN active indicates data is

available in the particular output FIFO. These

request signals inactive does not prevent data

transfers. Th e data transfers are controlled solely

with the particular acknowledge signal being active.

The input requests, CIREQN and DIREQN,

opera te under the fol lowing priori tize d ru les, li sted

in order of highest to lowest:

1) If the FIFO res et in th e Port Control

2) If a FIFO overflow interrupt is active, the

request is inactive.

3) If the FIFO is at or below the empty

threshold, the reques t remains acti ve.

4) If the FIFO is at or above the full threshold,

the request stays inactive .

The output requests, COREQN and DOREQN,

opera te under the fol lowing priori tize d ru les, li sted

in order of highest to lowest:

1) If the FIFO res et in th e Port Control

2) If the out put FIFO un derflow interrupt is

active, the request is inactive.

3) If an EOR is present in the output FIFO, the

request goes active.

4) If the output FIFO is at or above the full

threshold, the reques t goes acti ve.

5) If an EOR is read (strobed) out of the FIFO,

the request goes inactive during the same

clock as the strobe (if ERC=0), oth erwise it

goes inactive on the next clock.

6) If the output FIFO is at or below t he empty

threshold, the reques t goes in act iv e.

3.4.1 FIFO THRESHOLDS

For maxi mum efficiency, the F IFO thre sholds

should be set in such a way that the compressor

seldom runs out of data from the CI FIFO or

completely fills the output FIFO. The FIFOs are 16

words deep.

For example, in a system with fixed 8-word

bursts, good values for the thresholds are:

IET=3, IFT=4, OFT=D, OET=C

Setting the input full threshold to one higher

than the input empty threshold simply guarantees

that the request deasserts as soon as possible. The

latency between a word being strobed in and the

request changing due to a FIFO threshold condition

is 3 clocks. This should be kept in mind when

programming threshold values. Refer to Section 4.0

of AHA Application Note (ANDC16), Designer’s

Guid e for StarLiteTM Family Products for a more

thorough discussion of FIFO thresholds. The

following figure shows an example of an input

FIFO crossing its full thresho ld.

Page 10 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO)

Note: CIREQN deasserted when threshold counter exceeds IFT=4, but additional words are reading as long as

ACKN is asserted.

Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010

3.4.2 REQUEST DURING AN END-OF-RECORD

The request deasserts at an EOR in one of two

ways. If ERC bit in System Configura tion 1 is zero,

the reque st dea sserts as ynch ronously d uring the

clock where the EOR is strobed out of the FIFO.

This leads to a long output delay for REQN, but may

be necessary in some systems. For DSC values of 4

or 5, the reque st deasse rts the first cloc k after the

acknowledge pulse for the EOR. If ERC is set to

one, then the request deasserts synchronously the

clock after the EOR is strobed out. The minimum

low time on the requ est in this case is one cloc k.

The request delay varies between the different

strobe conditions. See Section 8.0 AC Electrical

Specifications for further details.

3.4.3 REQ UE ST STATUS BITS

An external microprocessor ca n also rea d the

value of each request using the CIREQ and COREQ

bits in the Compr ession Port S tatus register and the

DIREQ and DOREQ bits in the Decompression

Port Status register. Please note the request status

bits are active high while the pins are active low.

CLOCK

CIACKN

CIREQN

Threshold

12345

678

12345678

Counter

EOR-2

CLOCK

ACKN

REQN

EOR-1 EOR

(ERC=0)

EORN

REQN

(ERC=1)

PS3431-0500 Page 11 of 50

Advanced Hardware Architectures, Inc.

3.5 DATA FORMAT

The width of the D bus is selected with the

WIDE bit in System Configur at ion 0. If WIDE=1,

then D is a 32-bit bus. If WIDE=0, D is a 16-bit bus.

If the bus is configured to be 16-bits wide

(WIDE=0) , al l dat a tr ansfers occu r on D[15:0] and

the upper 16 bits of the bus, D[31:16], should be

terminated with Pullup resisto rs. If WIDE=0, the

FIFO is sixteen words deep.

Since the compression algorithm is byte

oriented, it is necessary for AHA3431 to know the

ordering of the bytes within the word. The COMP

and DECOMP BIG bits in System Configuration 0

select between big endian and little endian byte

ordering for the compression and decompression

channel . Litt le end ian stores the first byte in the

lower eight bits of a word (D[7:0]). Big endian

stores the firs t by te in the up per m ost ei ght b it s of a

word (D[ 31 : 2 4] for WI D E= 1 , D[15:8 ] for WID E= 0 )

for the decompression engine or compression

engine.

REVERSE BYTE in the System Confi guration

0 register allows the bit order into the compression

engine to be swapped. This control is useful for

reversing a page of data for duplex printing

applications and has no significant impact on

compressi on ratio perfo rmanc e.

3.6 ODD BYTE HANDLING

All data transfers to or from either the

compression or decompression engines are

perfor med on the D bu s on wo rd bounda ries . Since

no provision is made for single byte transfers,

occasionally words will contain pad bytes.

Following is a descr ipt io n of when t hes e pad byt es

are necessary for each of the data interfaces.

3.6.1 COMPRESSIO N INPUT AND PAD BYTES

Uncompressed data input into AHA3431 is

treated as records. The length of these records is

fixed by the value in the Record Length or RLEN

uncompressed byte s in ea ch record. If the valu e in

RLEN is not an integer multiple of n umber of bytes

per word as selected by WIDE, the final word in the

transfer of the record contains pad bytes. The

compression engine simply discards these pad bytes

and has no effect on either the dictionary or the

output data stream. The next record must begin on a

word boundary.

The minimum value for RLEN is 4 bytes.

3.6.2 COMPRESSIO N OUTPUT AND

PAD BYTES

If a record ends on a byte other than the last byte

in a word, the final word contains 1, 2 or 3 pad bytes.

The pad byt es have a val ue of 0x00. Th is appli es to

the 32-bit data port only.

3.6.3 DECOMPRESSIO N INPUT, P AD BY TES

AND ERROR CHECKING

This port re cognizes the end of a recor d by the

appearan ce of a speci al End-o f-Record sequen ce in

the data stream. Once this is seen, the remaining

bytes in the current word are treated as pad bytes

and discarded. The word following the end of the

record is the beginning of the next record.

When operating in decompression mode, the

Decompression Record Len gth (DRLEN) register

can be used to provide error checking. The expected

length of the decompressed record is programmed

into the DRLEN register. The decompressor then

counts down from the value in DRLEN to zero.

A DERR interrupt is is sued if an E OR is not

read out of the decompressor when the counter

expires or if an EOR occurs before the counter

expires (i.e., when the record lengths do not match).

If the DERR interrupt is masked, use of the DRLEN

When operating in pass -through mode, there is

no End-of-Record codeword for the decompressor

to see. In pass-through mode, the user must set the

record length in the DRLEN register.

3.6.4 DECOMPRESSIO N OUTPUT AND

PAD BYTES

When the decompressor detects an End-of-

Record codeword, it will add enough pad bytes of

value 0x00 to complete the current word as defined

by the WIDE bit in the System Configuration 0

other than the last byte in a word, the final word

contains 1, 2 or 3 pad bytes. This applies to the 32-

bit data port only, not the VOD port. The VOD port

never outputs pad bytes since it is 8-bits wide.

Page 12 of 50 PS3431-0500

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Figure 14: Timing Diagram, Video Input

3.7 VIDEO INTERFACES

3.7.1 V IDEO INPUT

The video input port is enabled by the VDIE bit

in the System Configuration 1 register . The port uses

VIREQN to indicate that the port can accept another

byte. The value on VID[7:0] is written into

AHA3431 each clock th at VI RE QN and VIACKN

are both low.

The video input port asserts VIREQN whenever

there is room in the CI FIFO. The values in IET and

IFT are a ll ignor ed. The compre ssion inpu t FIFO is

16 bytes deep in this mode. The video input port can

transfer up to one byte per clock (33 MB/sec). The

DMA interface cannot access the compression input

FIFO when VDIE is set.

3.7.2 VIDEO OUTPUT

The video outpu t port is ena bled by the VDOE

bit in the System Conf ig urat ion 1 r egi st er. The port

uses VOREQN to indicate that the byte on

VOD[7:0] is valid. An 8-bit word is read each clock

when both VOREQN and VOACKN are sampled

low on a rising edge of CLOCK. Pad bytes at an end

of recor d are discarded by the video output port and

do not appear on VOD[7:0]. When the byte on

VOD[7:0] is the last byte in a record, the VOEORN

signal goes low. To use VOEORN as an End-of-

Record indicator, it should be conditioned with

VOREQN and VOACKN. Unlike a DMA tr ansfer,

there are no pad bytes after an End-of-Record.

VOEOTN operates similar to VOEORN. It

flags the end of an output transfer of one or more

decompres sed r eco rds. VOEOTN is asser te d when

the End-of -Re cor d is at t he out put of t he DO FIFO

and the decompression record count has

decremented to zero.

The port requests whenever a valid byte is

present on t he output. The va lues in OET a nd OFT

are all ignored. The decompression output FIFO is

16 bytes deep in this mode. The video output port

can output up to one byte per clock. The DMA

interface cannot access the decompression output

FIFO when VDOE is set.

Figure 15: Timing Diagram, Video Output

CLOCK

VIREQN

VIACKN

VID[7:0] 0 3

don’t

care 1 2 don’t care 4 5 don’t

care

CLOCK

VOREQN

VOACKN

VOD[7:0] 0 31 2 4 5

VOEORN,

VOEOTN

PS3431-0500 Page 13 of 50

Advanced Hardware Architectures, Inc.

3.8 ALGORITHM

AHA3431 compress ion is an efficient

implementation of an algorithm optimized for

bitonal images. For some comparison data refer to

the AHA Application Note ( AN DC13), Compr ession

Performance: StarLiteTM: ENCODEB2 on

Bitonal Images. A software emulation of the

algorithm is available for evaluation.

3.9 COMPRESSION ENGINE

The compression engine supports either

compression or pass-through processes. The

compression engine is enabled with the CO M P bit in

the Compr ession Contr ol register . When the engine is

enabled, it takes data from the CI FI F O as it becomes

available. This data is either compressed by the engine

or passed through unaltered. This pass-through mode

is selected with the CPASS bit in the Compression

Control register . The CPASS bit may only be changed

when COM P is set to ‘0’. The contents of the

dictionary are preserved when COMP is changed.

However , when CPA S S is changed, the contents are

lost. Consequently, the device cannot be changed from

pass-through mode to compression mode or vice versa

without losing the contents of the dictionary.

The compress or can be instructed to halt at the

end of a record or an end of multiple-record transfer.

If the CPOR bit is set, the com pressor stops taki ng

data out of the CI FIFO immediately after the last

byte of a record, and the COMP bit is cleared. If the

CPOT bit is set the compressor halts at the end of the

multiple-record transfer. The CEMP bit indicates

the compressor has emptied all data. Compression is

restarted by setting the COMP bit.

The compressi on engi ne t akes data from the

compression input FIFO at a maxi mum r ate of 33

MBytes/sec. Two conditions cause t he data rat e to

drop below the maxi mum. The first is caused by the

compression input FIFO running empty of data to be

compress ed. The seco nd condition i s ca used b y the

output FIFO fi ll ing. When thi s occurs, the engi ne

halts and waits for the FIFO. While halted, the engine

goes into a low power standby mode. Refe r to the

table in Se cti on 7.1 for the exte nt of power savi ngs.

The compression byte counter counts the number

of bytes output from the CO data port. The counter is

valid to read after a compression end of transfer

interrupt (CEOT), or pausing after End-of-Record.

3.10 DECOMPRESSION ENGINE

The decompression engine is enabled with the

DCOMP bit in the Deco mpr ession Contr ol register .

When the engine is enabled , it takes data fro m the

DI FIFO a s it be comes a vailable. This d ata is either

decompressed by the engine or passed through

unaltered. Pass-through mode is selected with the

DPASS bit. DPASS may only be changed when

DCOMP is set to zero an d DEMP is set to one. The

contents of the dictionary are preserved when

DCOMP is changed. However, when DPASS is

changed, the contents are lost. Consequently,

AHA3431 cannot be changed from pass-through

mode to decompression mode or vice versa wi thout

losing the contents of the dictionary.

The decompressor can be instructed to halt at

the end of a record or an end of multiple-record

transfer. If the DPOR bit is set, the decompressor

stops taking data out of the DI FIFO immediately

after the last byte of a record, and the DCOMP bit is

cleared. If DPOT bit is set the decompressor halts at

the end of the multiple-record transfer. The DEMP

bit indicates the decompressor has emptied of all

data. Decompression is restarted by setting the

DCOMP bit. If DPOR or DPOT is set and data from

a second record enters the FIFO immediately after

the first record, bytes from the second record will

have entered the decompressor prior to decoding the

EOR. An im plication of th is is that bytes f rom the

second r eco rd will remai n in t he deco mpres sor an d

prevent DEMP from setting after all of the data from

the first r ecord has le ft the d ecompressor. This

differs from operation of the compression engine. In

either mode, a DEOR interrupt is generated when

the las t byte of a decompressed record is read out of

the chip, and DEOT when the last byte of a transfer

is read out of th e chip .

The decompressor takes data from the

decompres sio n input FIFO at the maximum clock

rate. AHA3431 can maintain this data rate as long as

the decompression input FIFO is not empty or the

decompression output FIFO is not full.

Caveat: Changing the mode for the decompressor

between reco rds or multipl e-record t ransfers must be

done with the data of the following record or tr ansfer

held off until the DEOR status bit is true for the current

record and the Decompression Control registers have

been reprogrammed . This reprogramming can occur

automatic ally wi th prearming.

3.11 PREARMING

Prearming i s the ability to wri te certa in regist ers

that apply to t he next record whi le the device is

processing the c urrent rec ord. Prea rming occurs

automatic ally at the end of a record. I f a prearmable

record, at the end of the record the part takes its program

from the regist er valu e last written. Com pression

Control and Decompressio n Control register s each

have separate cor responding pr earm registe rs.

Page 14 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

The lower 3 bytes of both the Compression

Record Length and the Decompression Length

regist ers are prear mable. They may be changed an d

the new value s loaded in to the respective cou nter at

the next End-of-Record. If the most significant byte

is written in either of the Record Length registers,

the count er is immedia tely reloade d with the new 4

byte value in the part icular register.

3.12 INTERRUPTS

Nine conditions are reported in the Interrupt

Status/Control 1 and Status/Control 2 registers as

individual bits. All interrupts are maskable by

setti ng the corres ponding bits in the Inter rupt Mask

the corresponding bit in the Interrupt S tatus/Control

pin (INTRN). The INTRN pin is active whenever

any unmasked interrupt bit is set to a one.

An End-of-Record inte rrupt is posted when a

word containing an end-of-record is strobed out of

the compression or decompression output FIFO

(CEOR and DEOR respectively). A DEOR

interr upt is als o reported if an end- of-reco rd is read

from the video output port. A compression or

decompres sion end of transfer interr upt will als o be

posted if this is the last record o f a transfer.

End-of- Transfer interrupts are pos ted w hen a n

EOR occurs that caus es the c ounter to decrement to

zero. These are CEOT and DEOT , and they apply to

both the compression and decompression engines

respectively.

Four FIFO error conditions are also reported.

Overflowing the input FIFOs generates a CIOF or

DIOF interrupt. An overflow can only be cleared by

resetting the re spective FIFO via the Port Control

Underflo wing the out put FIFOs (readi ng when

they are not ready) generates a COUF or DOUF.

Underflow interrupts are cleared by writing a one to

COUF or DOUF. In the event of an underflow, the

respect ive FIFO mus t be reset. Note that in systems

using fi xed leng th bursts which rearbi trate du ring a

burst, the CO FIFO may request another burst when

the record actually finishes near the end of the

current burst. In thi s scen ario a second burst takes

place ca using a FIFO underflow . As long as a pause

on End-of-Record is used, data is not corrupted. The

FIFO simply must be reset.

3.13 DUPLEX PRINTING

Duplex Printing is the ability to print on both

sides of the page. AHA3431 supports this with

separate endian control for the Compressor and

Decompressor, and bit order control at the input to

the comp ressor . Bit order control allows revers al of

the data bits within each byte of data. For example,

reverse order means bit-7 is swapped with bit- 0, bit-

6 is swappe d with bi t-1, et c.... Duri ng compres sion

operation of the back side of the page the data words

are sent to the AHA3431 device in reverse order.

The byte order is swapped if necessary by the

COMP BIG bit in the System Configuration 0

with the REVERSE BYTE bit in this same register.

During decompression of this reversed page the

DECOMP BIG bit in this register must be

programmed to the same value used when this p age

of data was compressed. Use of this feature has

virtually no effect on the compression ratio when

compared to compressing in forward order.

3.14 BLANK BANDS

Setting DBLANK in the Decompression

Control regist er causes the nex t record outpu t from

the Decompressor to be comprised of a repeating 8-

bit patte rn def ine d by the Pattern register.

DBLANK automatically clears at the end of the

next re cord. This command bit may be prearmed by

writing to the Decompression Control Prearm

regist er . When progr amming the device to generate

blank record s the syst em must no t send da ta to be

decompressed until the device has reached the end

of record for the blank record.

3.15 LOW POWER MODE

The AHA3431 is a data-driven system. When

no data transfers are taking place, only the clock and

on-chip RAMs includ ing the FIFOs re qui re power.

To reduce power consumption to its absolute

minimum, the user can stop the clock when it is

high. With the system clock stopped and at a high

level, the current consumption is due to leakage.

Control and Status registers are preserved in this

mod e. Reinitia lization of Control registers a r e not

necessary when switching from Low Power to

Normal operating mode.

3.16 TEST M ODE

In order t o facil i tate board level testing, the

AHA3431 provides the ability to tristate all outputs.

When the TEST0 pi n is high, all out puts of the chip

are tristated. When TEST0 is low , the chip returns to

normal operation.

PS3431-0500 Page 15 of 50

Advanced Hardware Architectures, Inc.

4.0 REGISTER DESCRIPTIONS

The microprocessor configures, controls and monitors IC operation through the use of the registers

defined in this sect ion. The bit s labeled “res” are re served and must b e s et t o zer o when writ ing t o regis ters

unless otherwise noted.

A summar y of registers is list ed bel ow.

Table 5: Internal Registers

ADDRESS R/W DESCRIPTION FUNCTION DEFAULT

AFTER

RSTN PREARM

0x00 R/W System Configuration 0 Big Endian vs. Little Endian,

32-b it vs. 16-bit, Reverse Byte Undefined No

0x01 R/W System Configuration 1 Data Strobe Condition, EOR

Request Control, VDO Port

Enable, VDI Port Enable 0x00 No

0x02 R/W I nput FIFO Thresholds Input FIFOs Empty

Threshold, Full Threshold Undefined No

0x03 R/W Output FIFO Thresholds Output FIFOs Empty

Threshold, Full Threshold Undefined No

0x04 R Compression Ports Status FIFO Status, Request Status,

EOR Statu s Undefined No

0x05 R Decompression Ports Status FIFO Status, Request Status,

EOR Statu s Undefined No

0x06 R/W Port Control Reset Individual FIFOs 0x0F No

0x07 R/W Interrupt Status/Control 1 EOR, Overflow, Underflow 0x00 No

0x09 R/W I nterrupt Mask 1 Interrupt Mask bits 0xFF No

0x0A R Version Die Version Number 0x31 No

0x0C R/W Decompressio n Record

Length 0 Bytes Remaining, Byte 0 0xFF Yes

0x0D R/W Decompression Record

Length 1 Bytes Remaining, Byte 1 0xFF Yes

0x0E R/W Deco mpression Record

Length 2 Bytes Remaining, Byte 2 0xFF Yes

0x0F R/W Decompressio n Record

Length 3 Bytes Remaining, Byte 3 0xFF No

0x10 R/W Compression Record Length 0 Length of Uncompressed Data

in Bytes, Byte 0 Undefined Yes

0x11 R/W Compression Record Length 1 " " , Byte 1 Undefined Yes

0x12 R/W Compression Record Length 2 " " , Byte 2 Undefined Yes

0x13 R/W Compression Record Length 3 " " , Byte 3 Undefined No

0x14 R/W Compression Control

Pause on Record Boundaries,

Enable Compression,

Compression Engine Empty

S t at us, Comp re ssi on

Dictionary Reset, Select Pass -

Through Mode

0x04 Yes

0x15 R/W Compression Reserved Reserved 0x00 No

0x16 R/W Compression Line Length 0 Line Length Register Lower

8bits Undefined No

0x17 R/W Compression Line Length 1 Line Length Register Upper

3bits Undefined No

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0x18 R/W Decompression Control

Pause on Record Boundaries,

Enable Decompression

Engine, Decompression

Engine Empty Status,

Dictionary Reset, Enable

Pass-Through Mode

0x04 Yes

0x1A R/W D ecompression Reserved 1 Reserved 0x00 No

0x1C R/W Decompression Line Length 0 Line Length Register Lower

8bits Undefined No

0x1D R/W D ecompression Line Length 1 Line Length Register Upper

3bits Undefined No

0x20 R/W Compression Record Count 0 Compressor number of

records in a tran sfer 0xFF No

0x21 R/W Compression Record Count 1 Compressor number of

records in a tran sfer 0xFF No

0x27 R/W Interrupt Status/Control 2 Compression EOT Interrupt,

Decompres sio n EOT Inter rupt 0x00 No

0x29 R/W I nterrupt Mask 2 Interrupt Mask bits for CEOT ,

DEOT 0xFF No

0x2C R/W Decompression Record Count 0 Decompressor number of

records in a tran sfer 0xFF No

0x2D R/W D ecompression Record Count 1 Decompressor number of

records in a tran sfer 0xFF No

0x30 R Compression Byte Count 0 Compressed byte count,

byte 0 0x00 No

0x31 R Compression Byte Count 1 Compressed byte count,

byte 1 0x00 No

0x32 R Compression Byte Count 2 Compressed byte count,

byte 2 0x00 No

0x33 R Compression Byte Count 3 Compressed byte count,

byte 3 0x00 No

0x34 R/W Compression Control Prearm Pre arm R egister for

Compression Control 0x00 No

0x35 R/W Pattern 8-bit patte rn for blank rec ord

generation Undefined No

0x38 R/W Decompression Control Prearm Pre arm R egister for

Decompression Control 0x00 No

0x3A R/W D ecompression Reserved 2 Reserved 0x00 No

0x3F Reserved Reserved 0x0F No

ADDRESS R/W DESCRIPTION FUNCTION DEFAULT

AFTER

RSTN PREARM

PS3431-0500 Page 17 of 50

Advanced Hardware Architectures, Inc.

4.1 SYSTEM CONFIGURATION 0, ADDRESS 0x00 - READ/WRITE

After re set, its contents are undefi ned. It must be writt en before an y input or output dat a movement may

be performed.

COMP BIG-Selects between little or big endian byte order for the compressor. See table.

DECOMP BIG-Selects between little or big endian byte order for the decompressor. See table.

REVERSE BYTE- When thi s bit is one the by te data e nte ri ng t he compress or is reversed . Bit 0 i s s w appe d

with bit7, bit1 is swapped with bit6, bit2 is swapped with bit5, etc. . .

res - Bits must always be written with zeros.

WIDE - Selects between 32 and 16-bit D buses.

4.2 SYSTEM CONFIGURATION 1, ADDRESS 0x01 - READ/WRITE

This register is cleared by reset.

DSC[2:0] - Data Str obe Cond it ion. Control t he conditio n used to str obe data into an d out of the dat a ports

on the D bus . T a ble 4 shows the p rogramming for t he strobe cond ition for va rious DMA modes.

res - Bits must always be written with zeros.

ERC - EOR Request Control. Determines when COREQN and DOREQN deassert at an End-of-

Record. If ERC=0, then the req uest deasser ts asynchronou sly during the clock when an EOR is

strobed out. If ERC=1, then the request deasserts synchronously the clock after an EOR is

strobed out. See Figure 18 through Figure 21.

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x00 res WIDE res REVERSE

BYTE DECOMP

BIG COMP

BIG

COMP BIG or

DECOMP BIG WIDE DESCRIPTION

Little Endian data order 16-bit words

D[15:8] D[7:0]

Byte 1 Byte 0

Little Endian data order 32-bit words

D[31:24] D[23:16] D[15:8] D[7:0]

Byte 3 Byte 2 Byte 1 Byte 0

Big Endian data order 16-bit words

D[15:8] D[7:0]

Byte 0 Byte 1

Big Endian data order 32-bit words

D[31:24] D[23:16] D[15:8] D[7:0]

Byte 0 Byte 1 Byte 2 Byte 3

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x01 res VDIE VDOE ERC res DSC[2:0]

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VDOE - VDO Port Enable. When this bit is set, the data from the decompression output FIFO goes to

the VDO port. When the bit is clear, the decompressed data is read by DMA on the D bus.

VDIE - VDI Port E nable . When this bit is set, the VD I port handshakes data and writes it into the

compressi on input FIFO. When th e bit is clea r , the compressi on input FIFO is wri tten by DMA

from the D bus.

4.3 INPUT FIFO THRESHOLDS, ADDRESS 0x02 - READ/WRITE

After re set, its contents are undefi ned. It must be writt en before an y input or output dat a movement may

be performed.

IET[3:0] - Empty threshold for input FIFOs. If the number of words in the input FIFO (CI or DI) is less

than or equal to this number, the reque st for that channel is asserted.

IFT[3:0 ] - Full thre shold for input FIFOs. If the number of words in the in put FIFO (C I or D I) is great er

than or equal to this n umber, the re ques t for the channel is dea sserted.

4.4 OUTPUT FIFO THRESHOLDS, ADDRESS 0x03 - READ/WRITE

After re set, its contents are undefi ned. It must be writt en before an y input or output dat a movement may

be performed.

OET [3:0] - Empty threshol d for output FIFO s. If the number of words in the output FI FO (CO or DO) is

less tha n or equal to this number , t he request fo r the channel is deas serted (exce pt in the case of

an End-of-Record).

OFT[3:0] - Full threshold for output FIFOs. If the number of words in the output FIFO (CO or DO) is

greater than or equ al to this number, the request for that channel is asse rted.

4.5 COMPRESSION PORTS STATUS, ADDRESS 0x04 - READ ONLY

This is a read onl y regist er. W riti ng to this re giste r has no ef fect . After re set, its content s are undef ined.

CIFT - Compr es si on input FIFO full thresh old . This sig nal is active when the CI FIFO is g rea te r than

or equal to the programmed FIFO full threshold. After reset and the Input FIFO Threshold

CIREQ - Compression input request signal state. Reports the current state for the CIREQN pin. Notice

that this bit is active high while the pin is active low. Therefore, the value of this bit is always

the inverse of the value of the signal. After reset this bit contains a zero.

COET - Compressi on output FIFO empty th reshold. This bit is acti ve when the CO FIFO is l ess than or

equal to the programmed FIFO empty threshold. After reset and the Output FIFO Threshold

COREQ - Compression output request signal state . Reports the current state for the COREQN pin. Notice

that this bit is active high while the pin is active low. Therefore, the value of this bit is always

the inverse of the value of the signal. After reset this bit contains a zero.

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x02 IFT[3:0] IET[3:0]

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x03 OFT[3:0] OET[3:0]

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x04 COEMP CIEMP res CEOR COREQ COET CIREQ CIFT

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Advanced Hardware Architectures, Inc.

CEOR - Compressi on output en d of recor d. This bit is activ e when the out put FIFO cont ains the end-of-

record code. After reset this bit contains a zero.

res - Bits must always be written with zeros.

CIEMP - Compression input empty. This bit is active when the CI FIFO is empty. After reset this bit

contains a one.

COEMP - Compression output empty. This bit is active when the CO FIFO is empty. After reset this bit

contains a one.

4.6 DECOMPRESSION PORTS STATUS, ADDRESS 0x05 - READ ONLY

This is a read onl y regist er. W riti ng to this re giste r has no ef fect . After re set, its content s are undef ined.

DIFT - D ecompression i nput FIFO ful l threshold. This signal is activ e when the DI FIFO is at or above

the progr ammed FI FO full threshold. After r eset and the Input FIFO Threshold register has

been written, this bit contains a zero.

DIREQ - Decompression input requ est signal state. Repor ts the current state for the DIREQN pin. Notice

that this bit is active high while the pin is active low. Therefore, the value of this bit is always

the inverse of the value of the signal. After reset this bit contains a zero.

DOET - Decompression output FIFO empty threshold. This bit is active when the DO FIFO is at or

below the programmed FIFO empty threshold. After reset and the Output FIFO Threshold

DOREQ - Decompression output request signal state. Reports the current state for the DOREQN pin.

Notice that this bit is active high while the pin is active low. Therefore, the value of this bit is

always the inverse of the value of the signal. After reset this bit contains a zero.

DEOR - Decompression outp ut end of recor d. This bit is active when th e output FIFO contai ns the End-

of-Record code. After reset this bit contains a zero.

res - Bits must always be written with zeros.

DIEMP - Decompression input empty. This bit is active when the DI FIFO is empty. After reset this bit

contains a one.

DOEMP - Decompression output empty. This bit is active when the DO FIFO is empty. After reset this bit

contains a one.

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x05 DOEMP DIEMP res DEOR DOREQ DOET DIREQ DIFT

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4.7 PORT CONTROL, ADDRESS 0x06 - READ/WRITE

This register is initialized to 0x0F after reset.

CIRST - Compression input reset. Setting this bit to a one resets the CI FIFO and clears state machines

on the compression input port. The reset condition remains active until the microprocessor

writes a zero t o this bit.

CORST - Compression output reset. Setting this bit to a one resets the CO FIFO and clears state machines

on the compression output port. The reset condition remains active until the microprocessor

writes a zero t o this bit.

DIRST - Decompression input reset. Setting this bit to a one resets the DI FIFO and clears the state

machines in the decompression input port. The reset condition remains active until the

microprocessor writes a zero to this bit.

DORST - Decompression output reset. Setting this bit to a one resets the DO FIFO and clears the state

machines in the decompression output port. The reset condition remains active until the

microprocessor writes a zero to this bit.

res - Bits must always be written with zeros.

4.8 INTERRUPT STATUS/CONTROL 1, ADDRESS 0x07 - READ/WRITE

This register is initialized to 0x00 after reset.

CEOR- Compression End-of-Record interrupt. This bit is set when an End-of-Record codeword is

strobed out of the compression output port. The microprocessor must write a one to this bit to

clear this interrupt.

DEOR - Decompression End-of-Record interrupt. This bit is set when the last byte of a record is strobed

out of the decompression DMA or video output port. The microprocessor must write a one to

this bit to clear this interrupt.

DERR - Decompression Error. This bit is set if an EOR leaves the decompressor before DRLEN has

counted down to zero or if DRLEN counts to zero and the last byte is not an EOR. DERR is

only active in decompression mode (DPASS=0). The microprocessor must write a one to this

bit to clear this interrupt.

res - Bits must always be written with zeros.

CIOF - Compressi on Input FIFO Ove rf low. This int er rup t i s generate d when a wri te to a n al re ady full

CI FIFO is performed. Dat a writ te n in thi s con dit io n is los t. The only means of rec over y fr om

this error is to re set th e FIFO with the CIRST bit. R esetting the FIFO causes this interrupt to

clear. CIREQN is inactive while the interrupt is set.

DIOF - Decompression Input FIFO Overflow. This interrupt is generated when a write to an already

full DI FI FO is performed. Dat a written in thi s condition is lost. The on ly means of recovery

from this error is to reset the FIFO with the DIRST bit. Resetting the FIFO causes this interrupt

to clear. DIREQN is inactive while the interrupt is set.

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x06 res DORST DIRST CORST CIRST

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x07 DOUF COUF DIOF CIOF res DERR DEOR CEOR

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Advanced Hardware Architectures, Inc.

COUF - Compression Output FIFO underflow. This interrupt is generated when a read from an empty

CO FIFO is performed. Once this interrupt is set, the CO FIFO must be reset with the CORST

bit. The micropr ocessor mus t write a one to thi s bit t o clear t his inte rrupt. COREQN is inactiv e

while the interrupt is set.

DOUF - Decompression Output FIFO underflow . Th is interrupt is generated when a read from an empty

DO FIFO is performed. Once this interrupt is set, the DO FIFO must be reset with the DORST

bit. The micropro cessor mus t write a one to this bit to clear thi s in terrupt. DOREQN i s inact ive

while the interrupt is set.

4.9 INTERRUPT MASK 1, ADDRESS 0x09 - READ/WRITE

This registe r is initial i zed to 0xF F after res et.

CEORM - Compressi on End-of-Record I nterrupt Mas k. When set to a one, prevent s Compression End- of-

Record from causing INTRN to go active.

DEORM - Decompression End-of-Record Interrupt Mask. When set to a one, prevents Decompression

End-of-Record from causing INTRN to go active.

DERRM - Decompr ess ion Erro r Mask. When set to a one, prevents a dec ompre ssi on er ro r (DERR) fro m

causing INTRN to go active.

res - Bits must always be written with zeros.

CIOFM - Compression Input FIFO Overflow Mask. When set to a one, prevents a compression input

FIFO overflow (CIOF) from causing INTRN to go active.

DIOFM - Decompression Input FIFO Overflow Mask. When set to a one, prevents a decompression

input FIFO overflow (DIOF) from causing INTRN to go active.

COUFM - Compression Output FIFO Underflow Mask. When set to a one, prevents a compr ession output

FIFO underflow (COUF) from causing INTRN to go active.

DOUFM - Decompression Output FIFO Underflow Mask. When set to a one, prevents a decompression

output FIFO underflow (DOUF) from causing INTRN to go active.

4.10 VERSION, ADDRESS 0x0A - READ ONLY

VERSION[7:0] - Contains version number of the die. The AHA3431 returns the version number 0x31.

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x09 DOUFM COUFM DIOFM CIOFM res DERRM DEORM CEORM

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x0A VERSION[7:0]

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4.11 DECOMPRESSION RECORD LENGTH, ADDRESS 0x0C, 0x0D, 0x0E, 0x0F -

READ/WRITE

These registers are initialized to 0xFF after reset.

DRLEN[31:0]-Decompression Record Length. Contains the number of bytes in a decompressed record.

These registers provide different functions depending on whether the decompressor is in pass-

through or decompression mode. In decompress mode, the data itself contains EOR

information and DRLEN is only used for error checking. DRLEN is decremented each time a

byte leaves the decompressor.

In decompression mode, a DERR interrupt is issued if an EOR is not read out of the

decompressor when the counter expires or if an EOR occurs before the counter expires (i.e.,

when the record lengths do not match). If the DERR interrupt is masked, use of the DRLEN

In pass-through mode, DRLEN determines the size of records read out of the decompressor.

The counter is decremented for each byte read into the decompressor.

In either mode, the counter reloads when it reaches zero or when DRLEN[31:24] is written.

Reading DRLEN returns the number of bytes left in the count. The lower three bytes of this

when the part is not programme d to pause on End -of-Record. The upp er byte is not prea rmable

since writing to this byte triggers an immediate reload to the counter.

4.12 COMPRESSION RECORD LENGTH, ADDRESS 0x10, 0x11, 0x12, 0x13 - READ/

WRITE

These reg isters are undefin ed after reset.

RLEN[31:0]-Record Length. Length of an uncompressed record in bytes. Writing these addresses sets a

regist er cont aini ng the l ength of a reco rd. Readi ng thes e addre sses re tu rns a co unter i ndica ting

the number of bytes remaining in the current record. The counter is decremented each time a

byte leaves the CI FIFO. The counter automatically reloads from the register at the end of a

record. The counter is also reloaded when RLEN[31:24] is written. The record length register

is also valid during pass-through operation. The lower three bytes of this register may be

prearmed s ince the cou nter is aut omatical ly reloade d at the end of a record when t he part is no t

programmed t o pause on End-of -Record. The upp er byte is not prearmable si nce writing to t his

byte triggers an immediate reload to the counter.

The minimum value for RLEN is 4.

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x0C DRLEN[7:0]

0x0D DRLEN[15:8]

0x0E DRLEN[23:16]

0x0F DRLEN[31:24]

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x10 RLEN[7:0]

0x11 RLEN[15:8]

0x12 RLEN[23:16]

0x13 RLEN[31:24]

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Advanced Hardware Architectures, Inc.

4.13 COMPRESSION CONTROL, ADDRESS 0x14 - READ/WRITE

This register is initialized to 0x04 after reset.

CPOR - Compression Pause on record boundaries. When this bit is set to one, the compressor stops

taking data from the input FIFO once a record boundary is found. A record boundary is

indicated by the RLEN register decrementing to zero. Upon finding the record boundary,

COMP is cleared. This bit may only be changed when COMP is set to zero. After system reset,

this bit is cleared.

COMP - Compression. Setting this bit to a one enables the data compression engine (or pass-through

mode if CPASS is set) to take data from the compression input FIFO. If this bit is cleared,

compression stop s. The bit is au tomatically clear ed at the end of a record if CPOR is set or at

the end of a transfer if CPOT is set. The compression can be restarted without loss of data by

setting COMP. A fter reset, this bit is c leared.

CEMP - Compression engine empty. This bit is set to a one when no data is present inside the

comp ressor. Writing to this bit has no effect. After system reset, this bi t is set.

CDR - Compression Dictionary Reset. Setting this bit immediately resets the compressor including the

compression dictionary. The reset condition remains active until the microprocessor writes a

zero to this bit.

CPASS - Compression pass-through mode. While this bit is set, data is passed directly through the

compression engine without any effect on either the dictionary or the data itself. This bit may

only be changed when compression is disabled (COMP=0) and the compression engine is

empty o f d ata (CEMP= 0). The pass-t hro ugh operat ion is star te d by setting COMP. To stop the

pass-t hrough operat ion, COMP should be cleared (t o pause opera tion) and then CPASS may be

cleared.

CPOT - Compression Pause on Transfer boundaries. When this bit is set the compressor stops taking

data from the input FIFO once the end of transfer is reached indicated by the Record Counter

decrementing to zero. Upon finding the End of Transfer boundary the COMP bit is cleared.

CPOT can only be set when COMP is cleared.

res - Bits must always be written with zeros.

CPREARM -Pre arm Enabl e. When this bit is s et, Compression Control Prearm reg ister is loaded i nto the

Compression Control register when the next end of record leaves the compressor.

4.14 COMPRESSION RESERVED, ADDRESS 0x15 - READ/WRITE

This register is used for production testing. Must be written with zero if at all. Resets to zero.

res - Bits must always be written with zeros.

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x14 CPREARM res CPOT CPASS CDR CEMP COMP CPOR

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x15 res

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4.15 COMPRESSION LINE LENGTH, ADDRESS 0x16, 0x17 - READ/WRITE

This register contains information necessary for the compression operation. It must be set prior to any

compressi on operat ion. It shou ld only be change d when COMP is cle ared and CEMP i s set. Af ter chan ging

compression line length, the compressor should be reset using CDR. These registers are undefined after reset.

res - Bits must always be written with zeros.

LINE[10:0]-Line length. The number of bytes in the scan line is programmed here. Minimum value is 16.

4.16 DECOMPRESSION CONTROL, ADDRESS 0x18 - READ/WRITE

This register is initialized to 0x04 after reset. This register can be prearmed.

DPOR - Decompr ession Pause on record boundaries. When th is bit is set to one, the decompr essor stops

taking data from the input FIFO once a record boundary is found. Upon finding the record

boundary, DCOMP is cleared . This bit may only be change d when DCOMP is set to zero. After

system reset or DDR, this bit is cleared.

DCOMP - Decompression. Setting this bit to a one enables the decompression engine (or pass-through

mode if DPASS is set) to take data from the decompression input FIFO. If this bit is cleared,

decompression stops. The bit is automatically cleared at the end of a record if DPOR is set.

Decompress ion can be r est ar ted withou t l oss of data by s et ti ng DCOMP. After sys tem r eset or

DDR, this bit is cleared.

DEMP - D ecompression engi ne empty. This bit is set whe n the decompressi on engine is clear ed of data.

Writing to this bit has no effect. After syste m reset, this bit is set.

DDR - Decompression Dictionary Reset. Setting this bit immediately resets the decompressor

including the decompression dictionary. The reset condition remains active until the

microprocessor writes a zero to this bit.

DPASS - Decompression pass-through mode. While this bit is set, data is passed directly through the

decompression engine without any effect on the data. This bit may only be changed when

decompression is disabled (DCOMP=0) and the decompression engine is empty of data

(DEMP=1). The pass-th rough operat ion is sta rted by sett ing DCOMP. To stop t he pass-thr ough

operation, DCOMP should be cleared (to pause operation) and then DPASS may be cleared.

DPOT - Decompression Pause on Transfer Boundaries. When this bit is set the decompressor stops

taking data from the input FIFO once a decompression end of transfer boundary is found

indicated by the Decompression Record Counter decrementing to zero.

DBLANK -Decompression Blank record. The data in the next record output from the decompressor is a

repeating byte pattern using the 8-bit data defined in the PATTERN register. DBLANK

automatically clears at the end of the record when the Decompression Record Count

decrements to zero. When using DBLANK to generate a blank record the device must not

contain data to be deco mpressed an d the system must not send data t o be decompresse d for any

future records until the part has reached the End-of-Record for the blank record.

DPREARM -Prearm Enable . When this bit is set , Decompression Control Prear m register is loaded in to the

Decompression Control register when the next end of record leaves the decompressor.

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x16 LINE[7:0]

0x17 res LINE[10:8]

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x18 DPREARM DBLANK DPOT DPASS DDR DEMP DCOMP DPOR

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Advanced Hardware Architectures, Inc.

4.17 DECOMPRESSION RESERVED, ADDRESS 0x1A - READ/WRITE

This regi ster is used for produ ction testing only. Must be w ritten with zer o if at a ll. In itialized to 0x00

afte r res et .

4.18 DECOMPRESSION LINE LENGTH, ADDRESS 0x1C, 0x1D - READ/WRITE

This register contains information necessary for the decompression operation. It must be set prior to any

decompres sion ope rati on. It sho uld only be ch anged bet ween rec ords when DCOMP is clear ed and DEMP

is set. These registers are und efine d after reset.

res - Bits must always be written with zeros.

LINE[10:0]-Line length. The number of bytes in the scan line is programmed here. Minimum value is 16.

For scan line lengths larger than the maximum allowed, set to 16.

4.19 COMPRESSION RECORD COUNT, ADDRESS 0x20, 0x21 - READ/WRITE

These registers are initialized to 0xFFFF after reset.

RC[15:0] - Record Count is the number of records in the current transfer. This counter is decremented as

the last by te of a record is comp ressed.

4.20 INTERRUPT STATUS/CONTROL 2, ADDRESS 0x27 - READ/WRITE

This register is initialized to 0x00 after reset.

CEOT - Compression End-of-Transfer Interrupt. This bit is set when an end of transfer condition is

reached indicated by the compression Record Counter counting down to zero. The

micropr ocessor must wr ite a one to this b it to clear this in terrupt.

DEOT - Decompression End-of-T ransfer Interrupt . This bit is set wh en a decompres sion end of tr ansfer

condition is reached indicated by the Decompression Record Counter counting down to zero.

The m icroprocessor must writ e a one to thi s bit to clear this inter rupt.

res - Bits must always be written with zeros.

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x1A res

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x1C LINE[7:0]

0x1D res LINE[10:8]

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x20 RC[7:0]

0x21 RC[15:8]

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x27 res DEOT CEOT

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4.21 INTERRUPT MASK 2, ADDRESS 0x29 - READ/WRITE

This registe r is initial i zed to 0xF F after res et.

CEOTM - Compress ion End-of-Transfer I nterr upt Ma sk. When set to a one, prevents Compression End-

of-Transfer from causing INTRN to go active.

DEOTM - Decompression End-of-Transfer Interrupt Mask. When set to a one, prevents Decompression

End-of-Transfer from causing INTRN to go active.

res - Bits must always be written with zeros.

4.22 DECOMPRESSION RECORD COUNT, ADDRESS 0x2C, 0x2D - READ/W RITE

These registers are initialized to 0xFFFF after reset.

DRC[15:0] -Decompression Record Count is the number of records in the current transfer. Expiration of

this coun ter causes a CE OT interrupt to be po sted.

4.23 COMPRESSION BYTE COUNT, ADDRESS 0x30, 0x31, 0x32, 0x33 - READ/WRITE

BCNT[31:0]-Compressed Byte Count is the number of bytes output from the CO FIFO, rounded up to a

word boundary defined by WIDE, for the current record. Systems may use this data to remove

pad words from the compressed data stream. The count gets reset at the beginning of each

record and when CORST is active.

4.24 COMPRESSION CONTROL PREARM, ADDRESS 0x34 - READ/WRITE

This register is initialized to 0x00 after reset.

res - Bits must always be written with zeros.

See Compression Control register for bit descriptions. This register is the prearm register for the

Compress ion Control reg ister.

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x29 res DEOTM CEOTM

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x2C DRC[7:0]

0x2D DRC[15:8]

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x30 BCNT[7:0]

0x31 BCNT[15:8]

0x32 BCNT[23:16]

0x33 BCNT[31:24]

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x34 NCPREARM res NCPOT NCPASS NCDR res NCOMP NCPOR

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4.25 PATTERN, ADDRESS 0x35 - READ/WRITE

This registe r is und efined after reset.

PATTERN[7:0]-Pattern is the 8-bit data use d to generate bla nk bands or record s. If DBLANK is set, the part

outputs this register value repeatedly for the entire record (or band).

4.26 DECOMPRESSION CONTROL PREARM, ADDRESS 0x38 - READ/WRITE

This register initializes to 0x00 after reset.

res - Bits must always be written with zeros.

4.27 DECOMPRESSION RESERVED, ADDRESS 0x3A - READ/WRITE

This regi ster is used for produ ction testing only. Must be w ritten with zer o if at a ll. In itialized to 0x00

afte r res et .

See Decompression Control register for bit descriptions. This register is the prearm register for the

Decompressi on Control register.

5.0 SIGNAL DESCRIPTIONS

This section contains descriptions for all the pins. Each signal has a type code associated with it. The

type codes are described in the following table.

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x35 PATTERN[7:0]

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x38 NDPREARM NDBLANK NDPOT NDPASS NDDR res NDCOMP NDPOR

Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0x3A res

TYPE CODE DESCRIPTION

IInput only pin

OOutput only pin

I/O Input/Output pin

SSynchronous signal

AAsynchronous signal

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5.1 MICROPROCESSOR INTERFACE

MICROPROCESSOR INTERFACE

SIGNAL TYPE DESCRIPTION

PD[7:0] I/O

SProcessor Data. Data for all microprocessor reads and writes of

registe rs wit hi n AHA3431 are per for med on t hi s b us. This bu s may

be tied to the Data bus, D[31:0], provided microprocessor accesses

do not occur at the same time as DMA accesses.

PA[5:0] I

SProcessor Address Bus. Used to address internal registers within

AHA3431.

CSN I

SChip Select. Selects AHA3431 as the source or destination of the

current microproce ssor bu s cycle. CSN n eeds only b e active for one

clock cycle to start a microprocessor access.

DIR I

SDirection. This signal indicates whether the access to the register

specified by the P A bus is a read or a write. The polarity of this signal

is programmed with the PROCMODE0 pin.

RDYN O

A,S Ready. Indicates valid dat a is on the data bus duri ng rea d operation

and completion of write operation. Its operation depends on

PROCMODE[1:0] settings.

INTRN O

SInterrupt. The compression and decompression processes generate

interrupts that are reported with this signal. INTRN is low whenever

any non-masked bits are set in the Interrupt Status/Control register.

PROCMODE[1:0] I

SMicroprocessor Port Configuration Mode. Selects the polarity of the

DIR pin and operation of the CSN pin. Refer to Section 2.1

Microprocessor Interface for details. (Figure 2 through Figure 5)

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5.2 DATA INTERFACE

DATA INTERFACE

SIGNAL TYPE DESCRIPTION

D[31:0] I/O

SData for all channels is transmitted on this bus. The ACKN is used to

distinguish between the four channels. Data being written to AHA3431 is

latched on the rising edge of CLOCK when the strobe condition is met.

Data setup and hold times are relative to CLOCK. If the bus is configured

to 16-bit transfers (WIDE=0), data is carried on D[15:0]. In this case,

D[31:16] should be terminated with pullup resistors.

DRIVEN I

ADrive En able. Active low output driver enable. This input must be low in

order to drive data onto D[31:0] in accordance with the current strobe

condition.

SD I

SStrobe Delay. Active high. Allows insertion of wait states for DMA

access to the FIFOs. The strobe condition, as programmed in the DSC

field of System Configuration 1, enables this signal and selects its

polarity.

CIREQN O

SCompression Input Data Request, active low. This signal, when active,

indicates the ability of the CI FIFO to accept data.

CIACKN I

SCompression Input Data Acknowledge. Active low. This signal, when

active, indicates the data on D is for the compression input FIFO. Data on

D is latched on the rising edge of CLOCK when the strobe condition is

met.

COREQN O

A,S Compression Output Data Request, active l ow. When thi s sign al is

active, i t indicates the abili ty of the CO FIFO to transmit da ta.

COACKN I

SCompression Output Data Acknowledge. Active low. The definition of

COACKN varies with the data strobe condition in System

Configuration 1. See Table 4.

COEORN O

SCompression Output End-of-Record, active low. COEORN is active

when the wo rd curren tl y on the out put of th e CO FI FO contains an End-

of-Record.

COEOTN O

SCompression Output End-of-Transfer, active low. COEOTN is active

when the wor d current ly on the out put of the CO FIFO contai ns the End-

of-Transfer.

DIREQN O

SDecompression Input Data Request, active low. When this signal is

active, it indicates the ability of the DI port to accept data.

DIACKN I

SDecompression Input Data Acknowledge. Active low decompression

data in put. Whe n this si gnal is ac tive, it indicate s the d ata on D is f or the

decompression input port. Data on D is latched on the rising edge of

CLOCK when the strobe condition is met.

DOREQN O

A, S Decompression Output Data Request, active low. When this signal is

active, it indicates the a bility of the DO port to tran smit data.

DOACKN I

SDecompression Output Data Acknowledge. The definition of DOACKN

varies with the data strobe condition in System Configuration 1. See

Table 4.

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5.3 VIDEO INTERFACE

5.4 SYSTEM CONTROL

VIDEO INTERFACE

SIGNAL TYPE DESCRIPTION

VIREQN O

SVideo Input Request. Active low output indicating that the VDI port is

ready to accept another byte on VID[7:0].

VIACKN I

SVideo Input Acknowledge. Active low input indicating that VID[7:0] is

being driven with a valid byte.

VID[7:0] I

SVideo Input Data. The value on this input bus is written into AHA3431

when both VIREQN and VIACKN are active.

VOREQN O

SVideo Output Request. Active low output indicating that the byte on

VOD[7:0] is valid.

VOACKN I

SV ideo Output Acknowledge. Active low input indicating that the external

system is ready to read VOD[7:0].

VOD[7:0] O

SVideo Output Data. The value on this output bus is read when both

VOREQN and VOACKN are low.

VOEORN O

SVideo Output End of Record is active low indicating the byte on

VOD[7:0] contains the last byte in a record.

VOEOTN O

SVideo Output End of Tr ansfer is active low indicating the byte on

VOD[7:0] contains the last byte in a multi-record transfer.

SYSTEM CONTROL

SIGNAL TYPE DESCRIPTION

CLOCK I System Clock. This signal is connected to the clock of the

microprocessor. The In tel i960Cx cal ls this pin P CLK.

RSTN I

APower on Reset. Act ive low reset sig nal. AHA3431 must be rese t before

any DMA or microprocessor activity is attempted. RSTN should be a

minimum of 10 CLOCK periods.

TEST0 I

ABoard Te st mode. When TEST is high, all outputs are tristated. When

TEST is low, the chip performs normally.

TEST1 I

AUsed for production tests. This input should always be tied low.

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6.0 PINOUT

PIN SIGNAL PIN SIGNAL PIN SIGNAL

1 VID[4] 44 VSS 87 VOD[7]

2 VID[3] 45 VSS 88 COEORN

3 VID[2] 46 VDD 89 VDD

4 VID[1] 47 CLOCK 90 VSS

5 VID[0] 48 VSS 91 VOACKN

6 INTRN 49 VDD 92 TEST0

7 VSS 50 VDD 93 PA[0]

8 VDD 51 VSS 94 PA[1]

9 DRIVEN 52 VDD 95 PA[2]

10 SD 53 D[15] 96 PA[3]

11 DOACKN 54 D[16] 97 VDD

12 COACKN 55 D[17] 98 PA[5]

13 DIACKN 56 D[18] 99 VSS

14 CIACKN 57 D[19] 100 PA[4]

15 VSS 58 D[20] 101 COEOTN

16 VDD 59 D[21] 102 VOEOTN

17 DOREQN 60 D[22] 103 PROCMODE[1]

18 COREQN 61 D[23] 104 PROCMODE[0]

19 DIREQN 62 D[24] 105 CSN

20 CIREQN 63 VSS 106 VDD

21 VIREQN 64 VDD 107 VSS

22 D[0] 65 D[25] 108 DIR

23 VSS 66 D[26] 109 RSTN

24 VSS 67 D[27] 110 PD[7]

25 VDD 68 D[28] 111 PD[6]

26 VDD 69 D[29] 112 PD[5]

27 D[1] 70 D[30] 113 VDD

28 D[2] 71 VDD 114 VSS

29 D[3] 72 VDD 115 PD[4]

30 D[4] 73 VSS 116 PD[3]

31 D[5] 74 VSS 117 PD[2]

32 D[6] 75 D[31] 118 PD[1]

33 D[7] 76 VOREQN 119 PD[0]

34 D[8] 77 VOEORN 120 VDD

35 D[9] 78 VOD[0] 121 VSS

36 D[10] 79 VOD[1] 122 RDYN

37 D[11] 80 VOD[2] 123 VIACKN

38 VSS 81 VDD 124 VID[7]

39 VDD 82 VSS 125 VID[6]

40 D[12] 83 VOD[3] 126 VID[5]

41 D[13] 84 VOD[4] 127 VDD

42 D[14] 85 VOD[5] 128 VSS

43 TEST1 86 VOD[6]

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Figure 16: Pinout

AHA3431 StarLiteTM

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

PA[3]

PA[2]

PA[1]

PA[0]

TEST0

VOACKN

VSS

VDD

COEORN

VOD[7]

VOD[6]

VOD[5]

VOD[4]

VOD[3]

VSS

VDD

VOD[2]

VOD[1]

VOD[0]

VOEORN

VOREQN

D[31]

VSS

VDD

D[30]

D[29]

D[28]

D[27]

D[26]

D[25]

VDD

VSS

D[24]

D[23]

D[22]

D[21]

D[20]

D[19]

D[18]

D[17]

D[16]

D[15]

VDD

VSS

VDD

VSS

CLOCK

VDD

VSS

TEST1

D[14]

D[13]

D[12]

VDD

VSS

D[11]

D[10]

D[9]

D[8]

D[7]

VID[4]

VID[3]

VID[2]

VID[1]

VID[0]

INTRN

VSS

VDD

DRIVEN

DOACKN

COACKN

DIACKN

CIACKN

VSS

VDD

DOREQN

COREQN

DIREQN

CIREQN

VIREQN

D[0]

VSS

VDD

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

VDD

PA[5]

VSS

PA[4]

COEOTN

VOEOTN

PROCMODE[1]

PROCMODE[0]

CSN

VDD

VSS

DIR

RSTN

PD[7]

PD[6]

PD[5]

VDD

VSS

PD[4]

PD[3]

PD[2]

PD[1]

PD[0]

VDD

VSS

RDYN

VIACKN

VID[7]

VID[6]

VID[5]

VDD

VSS

PS3431-0500 Page 33 of 50

Advanced Hardware Architectures, Inc.

7.0 DC ELECTRICAL SPECIFICATIONS

7.1 OPERATING CONDITIONS

Notes:

1) Dynamic current; typical operating conditi ons ( 3.3V)

2) Static current (cl ock high )

3) Timings referenced to this load

4) ILOAD=0 mA

7.2 ABSOLUTE MAXIMUM ST RESS RATINGS

OPERATING CONDITIONS

SYMBOL PARAMETER MIN MAX UNITS NOTES

Vdd Supply voltage 3.0 3.6 V

Idd Supply current (active) 160 mA 4

Idd Supply current (typical) 120 mA 1, 4

Idd Supply current (static) 1 mA 2, 4

Ta Ambient temperat ure 0 70 °C

Vil Input low voltage Vss-0.3 0.8 V

Vih Input high voltage 2.0 Vdd+0.3 V

Iil Input leakage current -10 10 µA

Vol Output low voltage (Iol=-4mA) 0.4 V

Voh Output high voltage (Ioh=4mA) 2.4 V

Iol Output low current 4 mA

Ioh Output high current -4 mA

Ioz Output leakage current during trista te -1 0 10 µA

Cin Input capacitance 10 pF

Cout Output capacitance 7 pF

Cio Input/Output capacitance 10 pF

Comax Maximum capacitance load for all

signals (including self loading) 50 pF 3

ABSOLUTE MAXIMUM STRESS RATINGS

SYMBOL PARAMETER MIN MAX UNITS NOTES

Tstg Storage temperature -50 150 °C

Vdd Supply voltage -0.5 4.5 V

Vin Input voltage Vss-0.5 Vdd+0.5 V

Page 34 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

8.0 AC ELECTRICAL SPECIFICATIONS

Notes:

1) Production test condition is 50 pF.

2) All timings are referenced to 1.4 volts.

Figure 17: Data Interface Timing

Table 6: Data Port Timing Requirements

Figure 18: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-7; ERC=0

NUMBER PARAMETER MIN MAX UNITS

1 CIACKN, DIACKN, COACKN, DOACKN and SD se tup time 7 ns

2 CIACKN, DIACKN, COACKN, DOACKN and SD hold time 2 ns

3 D-bus input setup time 7 ns

4 D-bus input hold time 2 ns

5 REQN delay (non-EOR case) 12 ns

6 REQN hold (non-EOR case) 2 ns

7 D-bus, COEORN, COEOTN output delay 12 ns

8 D-bus, COEORN, COEOTN output hold 2 ns

CLOCK

REQN

D, COEORN,

COEOTN

ACKN,

Valid 0

Valid

Va lid 1

1 2

3 4

CLOCK

ACKN

REQN

EOR-1 EOR

PS3431-0500 Page 35 of 50

Advanced Hardware Architectures, Inc.

Figure 19: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-7; ERC=1

Figure 20: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0

Figure 21: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1

CLOCK

ACKN

REQN

EOR-1 EOR

CLOCK

ACKN

REQN

EOR-1 EOR

CLOCK

ACKN

REQN

EOR-1 EOR

Page 36 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

Table 7: Request vs. EOR Timing

Figure 22: Output Enable Timing

Tab le 8: Output Enable Timing Requirements

Figure 23: Video Input Port Timing

Table 9: Video Input Port Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 ACKN, SD to REQN ERC=0 12 ns

2 CLOCK to REQN ERC=0 12 ns

3 CLOCK to REQN DSC=0-3, 6, 7; ERC=1 12 ns

4 CLOCK to REQN DSC=4, 5; ERC=0 12 ns

5 CLOCK to REQN DSC=4, 5; ERC=1 12 ns

NUMBER PARAMETER MIN MAX UNITS

1 DRIVEN to D valid 12 ns

2 DRIVEN to D tristate 6 ns

3 ACKN to D valid 12 ns

4 ACKN to D tristate 6 ns

5 CLOCK to D tristate (DSC=100, 101) 8 ns

NUMBER PARAMETER MIN MAX UNITS

1 VIR EQN d elay 12 ns

2 VIREQN hold 2 ns

3 VIACKN setup 7 ns

4 VIACKN hold 1 ns

5VID setup 7 ns

6 VID hold 1 ns

CLOCK

ACKN

DRIVEN

1 3 4 5

CLOCK

VIACKN

VID[7:0]

VIREQN

PS3431-0500 Page 37 of 50

Advanced Hardware Architectures, Inc.

Figure 24: Video Output Port Timing

Table 10: Video Output Port Timing Requirements

Figure 25: Microprocessor Interface Timing (PROCMODE[1]=0)

NUMBER PARAMETER MIN MAX UNITS

1 VOREQN delay 12 ns

2 VOREQN hold 2 ns

3 VOACKN setup 7 ns

4 VOACKN hold 1 ns

5 VOD delay 12 ns

6 VOD hold 2 ns

7 VOEORN, VOEOTN hold 2 ns

8 VOEORN, VOEOTN delay 12 ns

CLOCK

VOACKN

VOD[7:0]

VOREQN

1 2

VOEORN,

7 8

VOEOTN

CLOCK

CSN

RDYN

DIR

READ

212

3 4

910

12 13

Valid tristate

Valid

tristate

910

Valid

DIR

WRITE

234512

Page 38 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

Figure 26: Microprocessor Interface Timing (PROCMODE[1]=1)

Table 11: Microprocessor Interface Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 PA setup time 7 ns

2 PA hold time 1 ns

3 CSN setup time 7 ns

4 CSN hold time 2 ns

6 CSN to valid RDYN 12 ns

7 RDYN valid delay 12 ns

8 RDYN drive disable 8 ns

9 DIR setup time 7 ns

10 DIR hold time 2 ns

12 PD valid dela y 12 ns

13 PD drive disable 8 ns

14 PD setup time 7 ns

15 PD hold time 1 ns

16 CSN high to PD tristate 8 ns

17 CSN high to RDYN high 12 ns

CLOCK

CSN

RDYN

DIR

READ

DIR

WRITE

123 5N4

Valid

14 15

tristate

PS3431-0500 Page 39 of 50

Advanced Hardware Architectures, Inc.

Figure 27: Interrupt Timing

Table 12: Interrupt Timing Requirements

Figure 28: Clock Timing

Table 13: Clock Timing Requirements

Figure 29: Power On Reset Timing

Table 14: Power On Reset Timing Requirements

Notes:

1) RSTN signal can be asynchronous to the CLOCK signal. It is internally synchronized to the rising edge of

CLOCK.

NUMBER PARAMETER MIN MAX UNITS

1 INTRN delay time 12 ns

2 INTRN hold time 2 ns

NUMBER PARAMETER MIN MAX UNITS

1 CLOCK rise time 4 ns

2 CLOCK fall time 4 ns

3 CLOCK high time 10 ns

4 CLOCK low time 10 ns

5 CLOCK period 25 ns

NUMBER PARAMETER MIN MAX UNITS

1 RSTN low pulsewidth 10 clocks

2 RSTN setup to CLOCK rise 10 ns

3 RSTN hold time 2 ns

CLOCK

INTRN

1 2

CLK

2.0V

1.4V

0.8V

CLOCK

RSTN

Page 40 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

9.0 PACKAGE SPECIFICATIONS

JEDEC outline is MO-1 08

DETAIL A

A2 A

(LCA)

29 30 31 32

(LCB)

125

126

127

128

100

E1 E

PS3431-0500 Page 41 of 50

Advanced Hardware Architectures, Inc.

10.0 ORDERING INFORMATION

10.1 AVAILABLE PARTS

10.2 PART NUMBERING

Device Number:

3431

Revision Letter:

Packa ge Material Codes:

P Plastic

Package Type Codes:

Q Quad Flat Pack

Test Specifications:

C Commercial 0°C to +70°C

PLASTIC QUAD FLAT PACK PACKAGE DIMENSIONS

SYMBOL

NUMBER OF PIN AND SPECIFICATION DIMENSION

128

MIN NOM MAX

(LCA) 32

(LCB) 32

A 3.7 4.07

A1 0.25 0.33

A2 3.2 3.37 3.6

D 30.95 31.2 31.45

D1 27.99 28 28.12

E 30.95 31.2 31.45

E1 27.99 28 28.12

L 0.73 0.88 1.03

P0.8

B 0.3 0.35 0.4

PART NUMBER DESCRIPTION

AHA3431A-040 PQC 40 MBytes/sec Simultaneous Lossless Data Compression/

Decompression Coprocessor IC

AHA 3431 A- 040 P Q C

Manufacturer Device

Number Revision

Level Speed

Designation Package

Material Package

Type Test

Specification

Page 42 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

11.0 RELATED TECHNICAL PUBLICATIONS

DOCUMENT # DESCRIPTION

PS3411 AH A Product Specification – AHA3411 StarLiteTM 16 MBytes/sec Simultaneous

Compressor/Decompressor IC

ABDC18 AHA Application Brief – AHA3410C, AHA3411 and AHA3431 Device Differences

ANDC12 AHA Application Note – AHA3410C StarLiteTM Designer’s Guide

ANDC13 AHA Application Note – Compression Performance on Bitonal Images

ANDC14 AHA Application Note – StarLiteTM Evaluation Software

ANDC15 AHA Application Note – ENCODEB2 Compression Algorithm Description

ANDC16 AHA Application Not e – Designer’s Gu ide for S tarLi teTM Fami ly Product s: AHA341 1,

AHA3422 and AHA3431

ANDC17 AHA Application Note – StarLiteTM Compression on Continuous Tone Images

GLGEN1 General Glossary of Terms

STARSW StarLiteTM Evaluation Software (WindowsTM)

PS3431-0500 Page 43 of 50

Advanced Hardware Architectures, Inc.

APPENDIX A: ADDITIONAL TIMING DIAGRAMS FOR DMA MODE TRANSFERS

Figure A1: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000

Figure A2: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000

Figure A3: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition

of DSC=000

CLOCK

ACKN

DRIVEN

DD0 D1

CLOCK

ACKN

DRIVEN

DD1D0

CLOCK

ACKN

DRIVEN

DD0 D2D1 D3

Page 44 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

Figure A4: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition

of DSC=000

Figure A5: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition

of DSC=000

Figure A6: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition

of DSC=000

CLOCK

ACKN

DRIVEN

DD1D0 D2 D3

CLOCK

ACKN

DRIVEN

DD0 D2D1 D3 D4 D5 D6 D7

CLOCK

ACKN

DRIVEN

DD0 D2D1 D3 D4 D5 D6 D7

PS3431-0500 Page 45 of 50

Advanced Hardware Architectures, Inc.

Figure A7: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=010

Figure A8: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=010

Figure A9: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition

of DSC=010

CLOCK

ACKN

DRIVEN

DD0 D1

CLOCK

ACKN

DRIVEN

DD1D0

CLOCK

ACKN

DRIVEN

DD0 D2D1 D3

CLOCK

ACKN

DRIVEN

DD0 D2D1 D3

Page 46 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

Figure A10: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition

of DSC=010

Figure A11: DMA Mode Timing for Eight Word Burst Wr ite, Zero Wait State, Strobe Condition

of DSC=010

Figure A12: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition

of DSC=010

CLOCK

ACKN

DRIVEN

DD1D0 D2 D3

CLOCK

ACKN

DRIVEN

DD0 D2D1 D3 D4 D5 D6 D7

CLOCK

ACKN

DRIVEN

DD2D1 D3 D4 D5 D6 D7D0

PS3431-0500 Page 47 of 50

Advanced Hardware Architectures, Inc.

Figure A13: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011

Figure A14: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011

Figure A15: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition

of DSC=011

CLOCK

ACKN

DRIVEN

DD0 D1

CLOCK

ACKN

DRIVEN

DD1D0

CLOCK

ACKN

DRIVEN

DD0 D2D1 D3

Page 48 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

Figure A16: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition

of DSC=011

Figure A17: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition

of DSC=011

Figure A18: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition

of DSC=011

CLOCK

ACKN

DRIVEN

DD1D0 D2 D3

CLOCK

ACKN

DRIVEN

DD0 D2D1 D3 D4 D5 D6 D7

CLOCK

ACKN

DRIVEN

DD2D1 D3 D4 D5 D6 D7D0

PS3431-0500 Page 49 of 50

Advanced Hardware Architectures, Inc.

Figure A19: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111

Figure A20: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111

CLOCK

ACKN

DRIVEN

DD0 D1 D2

CLOCK

ACKN

DRIVEN

DD1D0 D2

Page 50 of 50 PS3431-0500

Advanced Hardware Arc h itectur es, Inc.

APPENDIX B: RECOMMENDED POWER DECOUPLING CAPACITOR

PLACEMENT

GUIDELINES FOR LOW NOISE OPERATION:

1) Use of dedicated power and ground planes within a multilayer printed circuit board is highly

recommended for high speed designs.

2) Use (8) 0.047uF ceramic leadless chip capacitors placed as shown.

3) Minimize VDD trace distance from IC to capacitor VDD pad.

4) Minimize VDD trace from capacitor VDD pad to power plane via.

5) Minimize VSS trace from IC to ground plane via.

AHA3431 StarLiteTM

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

RECOMMENDED POWER DECOUPLING CAPACITOR PLACEMENT