HM628128A Series
131,072-word ×8-bit High Speed CMOS Static RAM
Rev. X
January 1995
The Hitachi HM628128A is a CMOS static RAM
organized 128 kword ×8 bit. It realizes higher
density, higher performance and low power
consumption by employing 0.8 µm Hi-CMOS
process technology.
It offers low power standby power dissipation;
therefore, it is suitable for battery back-up systems.
The device, packaged in a 525-mil SOP (460-mil
body SOP) or a 600-mil plastic DIP, or a 8 ×20
mm TSOP with thickness of 1.2 mm, is available
for high density mounting. TSOP package is
suitable for cards, and reverse type TSOP is also
provided.
Features
• High speed
— Fast access time: 55/70/85/100 ns (max)
• Low power
— Active: 75 mW (typ)
— Standby: 10 µW (typ)
• Single 5 V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
Three state output
• Directly TTL compatible
All inputs and outputs
• Capability of battery back up operation
2 chip selection for battery back up
ADE-XXX-XXX
Ordering Information
Access
Type No. time Package
HM628128ALP–5 55 ns 600-mil 32-pin
HM628128ALP–7 70 ns plastic DIP
HM628128ALP–8 85 ns (DP-32)
HM628128ALP–10 100 ns
HM628128ALP–5L 55 ns
HM628128ALP–7L 70 ns
HM628128ALP–8L 85 ns
HM628128ALP–10L 100 ns
HM628128ALP–5SL 55 ns
HM628128ALP–7SL 70 ns
HM628128ALP–8SL 85 ns
HM628128ALP–10SL 100 ns
HM628128ALFP–5 55 ns 525-mil 32-pin
HM628128ALFP–7 70 ns plastic SOP
HM628128ALFP–8 85 ns (FP-32D)
HM628128ALFP–10 100 ns
HM628128ALFP–5L 55 ns
HM628128ALFP–7L 70 ns
HM628128ALFP–8L 85 ns
HM628128ALFP–10L 100 ns
HM628128ALFP–5SL 55 ns
HM628128ALFP–7SL 70 ns
HM628128ALFP–8SL 85 ns
HM628128ALFP–10SL100 ns
Access
Type No. time Package
HM628128ALT–5 55 ns 8 mm ×20 mm
HM628128ALT–7 70 ns 32-pin TSOP
HM628128ALT–8 85 ns (normal type)
HM628128ALT–10 100 ns (TFP-32D)
HM628128ALT–5L 55 ns
HM628128ALT–7L 70 ns
HM628128ALT–8L 85 ns
HM628128ALT–10L 100 ns
HM628128ALT-5SL 55 ns
HM628128ALT-7SL 70 ns
HM628128ALT-8SL 85 ns
HM628128ALT-10SL 100 ns
HM628128ALR–5 55 ns 8 mm ×20 mm
HM628128ALR–7 70 ns 32-pin TSOP
HM628128ALR–8 85 ns (reverse type)
HM628128ALR–10 100 ns (TFP-32DR)
HM628128ALR–5L 55 ns
HM628128ALR–7L 70 ns
HM628128ALR–8L 85 ns
HM628128ALR–10L 100 ns
HM628128ALR-5SL 55 ns
HM628128ALR-7SL 70 ns
HM628128ALR-8SL 85 ns
HM628128ALR-10SL 100 ns
2
HM628128A Series
Pin Arrangement
3
HM628128A Series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
CC
(Top View)
HM628128ALP/ALFP Series
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A4
A5
A6
A7
A12
A14
A16
NC
V
A15
CS2
WE
A13
A8
A9
A11
SS
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
I/O3
I/O4
I/O5
I/O6
I/O7
CS1
A10
OE
CC
(Top View)
HM628128ALT Series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CS2
A15
V
NC
A16
A14
A12
A7
A6
A5
A4
SS
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
V
I/O2
I/O1
I/O0
A0
A1
A2
A3
CC
(Top View)
HM628128ALR Series
Pin Description
Pin name Function
A0 – A16 Address
I/O0 – I/O7 Input/output
CS1 Chip select 1
CS2 Chip select 2
WE Write enable
Pin name Function
OE Output enable
NC No connection
VCC Power supply
VSS Ground
Block Diagram
Function Table
CS1 CS2 OE WE Mode VCC current I/O pin Ref. cycle
H X X X Standby ISB, ISB1 High-Z —
X L X X Standby ISB, ISB1 High-Z —
L H H H Output disable ICC High-Z —
L H L H Read ICC Dout Read cycle
L H H L Write ICC Din Write cycle (1)
L H L L Write ICC Din Write cycle (2)
Note: X: H or L
4
HM628128A Series
•
•
•
•
•
•
•
•
•
•
•
I/O0
I/O7
CS2
WE
OE
A8 A9 A11 A0 A2
V
V
CC
SS
Row
Decoder Memory Matrix
512 x 2,048
Column I/O
Column Decoder
Input
Data
Control
Timing Pulse Generator
Read/Write Control
A1 A3
A13
A15
A6
A7
A12
A14
A16
A5
A4
CS1
A10
(MSB)
(LSB)
(LSB) (MSB)
Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply voltage relative to VSS VCC –0.5 to +7.0 V
Voltage on any pin relative to VSS*1 VT–0.5 *2 to VCC + 0.3*3 V
Power dissipation PT1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature under bias Tbias –10 to +85 °C
Note: 1. With respect to VSS
2. –3.0 V for pulse half-width ≤30 ns
3. Maximum voltage is 7.0V.
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
VSS 000V
Input voltage VIH 2.2 — VCC + 0.3 V
(HM628128A-7/8/10) VIL –0.3 *1 — 0.8 V
Input voltage VIH 2.4 — VCC + 0.3 V
(HM628128A-5) VIL –0.3 *1 — 0.8 V
Note: 1. –3.0 V for pulse half-width ≤30 ns
5
HM628128A Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
Parameter Symbol Min Typ*1 Max Unit Test conditions
Input leakage current |ILI| — — 1.0 µA Vin = VSS to VCC
Output leakage current |ILO| — — 1.0 µA CS1 = VIH or CS2 = VIL or
OE = VIH or WE = VIL,
VI/O = VSS to VCC
Operating power supply ICC —1530mACS1 = VIL, CS2 = VIH,
current: DC Others = VIH/VIL
II/O = 0 mA
Operating power supply ICC1 — 45 70 mA Min cycle, duty = 100%,
current (HM628128 CS1 = VIL, CS2 = VIH,
A-7/8/10) Others = VIH/VIL
ICC1 —5080mA
I
I/O = 0 mA
(HM628128
A-5)
ICC2 — 15 25 mA Cycle time = 1 µs, duty = 100%,
II/O = 0 mA, CS1 ≤0.2 V,
CS2 ≥VCC – 0.2 V
VIH ≥VCC – 0.2 V, VIL ≤0.2 V
Standby power supply ISB — 1 2 mA (1) CS1 = VIH, CS2 = VIH or
current: DC (2) CS2 = VIL
Standby power supply ISB1 — 2 100 µA 0 V ≤Vin ≤VCC ,
current (1): DC (L version) (1) CS1 ≥VCC – 0.2 V,
ISB1 —2 50µA CS2 ≥VCC – 0.2 V or
(L-L/L-SL (2) 0 V ≤CS2 ≤0.2 V
version)
Output voltage VOL — — 0.4 V IOL = 2.1 mA
VOH 2.4 — — V IOH = –1.0 mA
Note: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading.
Capacitance (Ta = 25°C, f = 1.0 MHz)*1
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance Cin — — 8 pF Vin = 0 V
Input/output capacitance CI/O — — 10 pF VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
6
HM628128A Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
• Input pulse levels: 0.8 V to 2.4 V (HM628128A-7/8/10)
0 V to 3 V (HM628128A-5)
• Input rise and fall times: 5 ns
• Input and output timing reference levels: 1.5 V
• Output load: 1 TTL Gate and CL (100 pF) (HM628128A-7/8/10)
1 TTL Gate and CL (30 pF) (HM628128A-5) (Including scope & jig)
Read Cycle
HM628128A
-5 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Read cycle time tRC 55 — 70 — 85 — 100 — ns
Address access time tAA — 55 — 70 — 85 — 100 ns
Chip selection to tCO1 — 55 — 70 — 85 — 100 ns
output valid tCO2 — 55 — 70 — 85 — 100 ns
Output enable to tOE — 30 — 35 — 45 — 50 ns
output valid
Chip selection to tLZ1 5 — 10 — 10 — 10 — ns 2, 3
output in low-Z tLZ2 5 — 10 — 10 — 10 — ns 2, 3
Output enable to tOLZ 5 — 5 — 5 — 5 — ns 2, 3
output in low-Z
Chip deselection to tHZ1 0 20 0 25 0 30 0 35 ns 1, 2, 3
output in high-Z tHZ2 0 20 0 25 0 30 0 35 ns 1, 2, 3
Output disable to tOHZ 0 20 0 25 0 30 0 35 ns 1, 2, 3
output in high-Z
Output hold from tOH 5 — 10 — 10 — 10 — ns
address change
7
HM628128A Series
Read Timing Waveform *4
Notes: 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given
device and from device to device.
3. This parameter is sampled and not 100% tested.
4. WE is high for read cycle.
8
HM628128A Series
t
t
t
t
t
t
RC
AA
CO1
LZ1
OE
OLZ
tHZ2
tOHZ
Data Valid
Address
CS1
OE
Dout
tOH
CS2
Address Valid
tCO2
tLZ2
High Impedance
tHZ1
Write Cycle
HM628128A
-5 -7 -8 -10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Write cycle time tWC 55 — 70 — 85 — 100 — ns
Chip selection to tCW 50 — 60 — 75 — 80 — ns
end of write
Address setup time tAS 0—0—0—0—ns
Address valid to tAW 50 — 60 — 75 — 80 — ns
end of write
Write pulse width tWP 40 — 50 — 55 — 60 — ns
Write recovery time tWR 0—0—0—0—ns
Write to output in tWHZ 0 20 0 25 0 30 0 35 ns 10
high-Z
Data to write time tDW 25 — 30 — 35 — 40 — ns
overlap
Data hold from tDH 0—0—0—0—ns
write time
Output active from tOW 5—5—5—5—ns10
end of write
9
HM628128A Series
Write Timing Waveform (1) (
OE
Clock)
10
HM628128A Series
Address
CS1
WE
Dout
Din
tWC
tCW
tWR
tWP
tOHZ
tDW tDH
*5
*1
*6 *4
Address Valid
tAW
CS2
tAS
High Impedance
Data Valid
OE
*3
*2
Write Timing Waveform (2) (
OE
low Fixed)
Notes: 1. A write occurs during the overlap of a low CS1, a high CS2, and a low WE. A write begins at the
latest transition among CS1 going low, CS2 going high, and WE going low. A write ends at the
earliest transition among CS1 going high, CS2 going low, and WE going high. tWP is measured
from the beginning of write to the end of write.
2. tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
5. During this period, I/O pins are in the output state; therefore, the input signals of the opposite
phase to the outputs must not be applied.
6. If the CS1 goes low simultaneously with WE going low or after the WE going low, the outputs
remain in a high impedance state.
7. Dout is the same phase of the latest written data in this write cycle.
8. Dout is the read data of next address.
9. If CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the
input signals of opposite phase to the outputs must not be applied to them.
10.This parameter is sampled and not 100% tested.
11.In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
11
HM628128A Series
Address
CS1
WE
Dout
Din
tWC
tCW tWR
tAW
tWP
tAS
tWHZ tOW
tOH
tDW tDH *9
*7 *8
*5
*1 *11
*6
*4
Address Valid
Data Valid
CS2
*2
*3
High Impedance
data bus contention.
tWP ≥tDW min + tWHZ max
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit Test conditions*4
VCC for data retention VDR 2.0 — — V CS1 ≥VCC – 0.2 V,
CS2 ≥VCC – 0.2 V or
0 V ≤CS2 ≤0.2 V
Vin>0 V
Data retention current ICCDR —1 50
*1 µA VCC = 3.0 V, Vin ≥0 V
(L version) CS1 ≥VCC – 0.2V
ICCDR —1 30
*2 µA CS2 ≥VCC – 0.2 V or
(L-L version) 0 V ≤CS2 ≤0.2 V
ICCDR —1 15
*3 µA
(L-SL
version)
Chip deselect to tCDR 0 — — ns See retention waveform
data retention time
Operation recovery time tR5——ms
Low VCC Data Retention Timing Waveform (1) (
CS1
Controlled)
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
12
HM628128A Series
CC
V
4.5 V
2.2 V
0 V
CS1
tCDR tR
CS1 V – 0.2 V
CC
DR1
V
Data retention mode
>
CC
V
4.5 V
0 V
CS2
CDR tR
0 V CS2 0.2 V
DR2
V
Data retention mode
0.4 V
t
<<
Notes: 1. 20 µA max at Ta = 0 to 40˚C (L-version).
2. 6 µA max at Ta = 0 to 40˚C (L-L-version).
3. 3 µA max at Ta = 0 to 40˚C (L-SL-version).
4. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state.
If CS1 controls data retention mode, CS2 must be CS2 ≥VCC – 0.2 V or 0 V ≤CS2 ≤0.2 V. The
other input levels (address, WE, OE, I/O) can be in the high impedance state.
13
HM628128A Series
