TS8388BCFB/Q - Atmel Corporation

Product Specification

MAIN FEATURES

! 8-bit resolution.

! ADC gain adjust.

! 1.5 GHz full power input bandwidth.

! 1 Gsps (min) sampling rate.

! SINAD = 44.3 dB (7.2 Effective Bits) SFDR = 58 dBc

@ FS = 1 Gsps, F IN = 20 MHz :

! SINAD = 42.9 dB (7.0 Effective Bits) SFDR = 52 dBc

@ FS = 1 Gsps, F IN = 500 MHz :

! SINAD = 40.3dB (6.8 Effective Bit s) SFDR = 50 dBc

@ FS = 1 Gs ps, FIN = 1000 MHz (-3 dB FS)

! 2-tone IMD : -52dBc (489 MHz, 490 MHz) @ 1GSPS.

! DNL = 0.3 LSB INL = 0.7 LSB.

! Low Bit Error Rate (10-13 ) @ 1 Gsps

! Very low input capacitance : 3 pF

! 500 mVpp differential or singl e-ended anal og inputs.

! Differential or single-ended 50Ω ECL compatible clock inputs.

! ECL or LVDS/HSTL output compatibil ity.

! Data ready output with asynchronous reset.

! Gray or Binary sel ectable output data ; NRZ output mode.

! Power consumption : 3.4 W @ Tj = 70°C typical

! Radiation t ol erance oriented design (150 Krad (Si) measured).

APPLICATIONS

! Digital Sampling Oscilloscopes.

! Satellite receiver.

! Electronic countermeasures / Electronic warfare.

! Direct RF down–conversion.

SCREENING

! Atmel-Grenoble st andard screening level

! Mil-PRF-38535, QML level Q for package version, DSCC 5962-0050401QYC

! Temperature range: up to -55°C < Tc ; Tj < +125°C

DESCRIPTION

The TS8388BF is a monolithic 8–bit analog–to–digital converter, designed for

digitizing wide bandwidth analog signals at very high sampling rates of up to 1

Gsps.

The TS8388BF is using an innovative architecture, including an on chip Sample

and Hold (S/H), and is fabricated with an advanced high speed bipolar process.

The on–chip S/H has a 1.5 GHz full power input bandwidth, providing excell ent

dynamic perf orm ance in unders am pling appl ications (High IF digitizing).

F Suffix : CQFP 68

Ceramic Quad Flat Pack

ADC 8-bit 1 Gsps

TS8388BF

1/ Die form : JTS8388B

2/ Evaluation board :

TSEV8388BF

3/ Demultiplexer :

TS81102G0 : companion device available

January 2002

2TS8388BF

Product Specification

TABLE OF CONTENTS

1. SIMPLIFIED BLOCK DIAGRAM....................................................................................................................................3

2. FUNCTIONAL DESCRIPTION ........................................................................................................................................3

3. SPECIFICATIONS..............................................................................................................................................................4

3.1. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW).................................................................................................................4

3.2. RECOMMENDED CONDITIONS OF USE..........................................................................................................................................4

3.3. ELECTRICAL OPERATING CHARACTERISTICS..............................................................................................................................5

3.4. TIMING DIAGRAMS ...........................................................................................................................................................................9

3.5. EXPLANATION OF TEST LEVELS...................................................................................................................................................10

3.6. FUNCTIONS DESCRIPTION............................................................................................................................................................10

3.7. DIGITAL OUTPUT CODING.............................................................................................................................................................10

4. PACKAGE DESCRIPTION. ............................................................................................................................................11

4.1. TS8388BF PIN DESCRIPTION.........................................................................................................................................................11

4.2. TS8388BF PINOUT..........................................................................................................................................................................12

4.3. OUTLINE DIMENSIONS – 68 PINS CQFP.......................................................................................................................................13

4.4. THERMAL CHARACTERISTICS ......................................................................................................................................................14

5. TYPICAL CHARACTERIZATION RESULTS.............................................................................................................15

5.1. STATIC LINEARITY – FS = 50 MSPS / FIN = 10 MHZ......................................................................................................................15

5.2. EFFEC TIVE NUMBER OF BITS VER SUS PO WER SU PPLI ES VA R IA T ION....................................................................................16

5.3. TYPICAL FFT RESULTS..................................................................................................................................................................17

5.4. SPURIOUS FREE DYNAMIC RANGE VER SU S INPUT AMPLITUDE..............................................................................................18

5.5. DYNAMIC PERFO R MANC E VERSUS ANALOG INPUT FR EQ U EN CY...........................................................................................19

5.6. EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY................................................................................20

5.7. SFDR VER SUS SAM PLING FR EQ U ENCY......................................................................................................................................20

5.8. TS8388BF ADC PERF OR MANCES VER SUS JUN C TION TEMPER ATURE....................................................................................21

5.9. TYPICAL FULL POWER INPUT BANDWIDTH.................................................................................................................................22

5.10. ADC STEP RESPONSE...............................................................................................................................................................23

6. DEFINITION OF TERM S................................................................................................................................................24

7. TS8388BF MAIN FEATURES..........................................................................................................................................26

7.1. TIMING IN FO R MATIO N S.................................................................................................................................................................26

7.2. PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND..........................................................................27

7.3. ANALOG INPUTS (VIN) (VINB)........................................................................................................................................................27

7.4. CLOCK INPUTS (CLK) (CLKB).........................................................................................................................................................28

7.5. NOISE IMMUNITY INFORMATIONS................................................................................................................................................30

7.6. DIGITAL OUTPUTS..........................................................................................................................................................................30

7.7. OUT OF RANGE BIT ..............................................................................................................................................................................32

7.8. GRAY OR BIN ARY OU TPU T DATA FORMAT SELECT...................................................................................................................33

7.9. DIODE PIN 49 ..................................................................................................................................................................................33

7.10. ADC GAIN CONTROL PIN 60......................................................................................................................................................34

8. EQUIVALENT INPUT / OUTPUT SCHEMATICS ......................................................................................................35

8.1. EQUIVALENT AN AL O G INPU T CIRCUIT AN D ESD PROTECTIONS..............................................................................................35

8.2. EQUI VALENT AN AL OG CLOC K IN PUT CIRC UIT AN D ESD PROTEC TIO NS.................................................................................35

8.3. EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS ................................................................................36

ADC GAIN ADJUST EQUI VALENT INPUT CIR C U ITS AND ESD PROTECT IO N S........................................................................................36

8.5. GORB EQ U I VALENT IN PUT SCHEMATIC AND ESD PROTECTION S............................................................................................37

DRR B EQUIVAL EN T INPUT SC HEMATIC AND ESD PROTECTION S.........................................................................................................37

9. TSEV8388BF : DEVICE EVALUATION BOARD ........................................................................................................38

10. ORDERING INFORMATION ........................................................................................................ .............................39

PACKAGE DEVICE .......................................................................................................................................................................................39

10.2. EVALU ATION BO AR D.................................................................................................................................................................39

Product Specification

TS8388BF

1. SIMPLIFIED B LOCK DIAGRAM

2. FUNCTIONAL D ESCRIPTION

The TS8388BF is an 8 bit 1GSPS ADC based on an advanced high speed bipolar technology feat uri ng a cutoff f requency of 25 GHz.

The TS8388BF includes a front-end master/sl ave Track and Hol d st age (S/ H), followed by an analog encodi ng st age and interpolati on circuitry.

Successive banks of latches are regenerating the analog residues into logical data before entering an error correction circuitry and a

resynchronization stage followed by 75 Ω differential output buffers.

The TS8388BF works in fully differential mode from analog inputs up to digital outputs.

The TS8388BF features a full power input bandwidth of 1.5 GHz.

Control pin GORB is provided to select either Gray or Binary data output format.

Gain control pin is provided in order to adjust the ADC gain.

A Data Ready output asynch ronous reset (DRRB) is available on TS8388BF.

The TS8388BF uses only vertical isolated NPN transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation

tolerance (no performance drift measured at 150kRad total dose).

VIN,VINB

CL K, CLKB

G=2 T/H G=1 T/H G=1

CLOCK

BUFFER

RESISTOR

CHAIN

ANALOG

ENCODING

BLOCK

INTERPOLATION

STAGES

REGENERATION

LATCH ES

ERROR CO RR ECTIO N &

DECODE LOGIC

OUTPU T LA TC HE S &

BUFFERS

GAIN

DRRB DR,DRB GORB DATA,DATAB OR,ORB

MASTER/ SLAVE TRACK & HOLD

4TS8388BF

Product Specification

3. SPECIFICATIONS

3.1. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW)

Parameter Symbol Comments Value Unit

Positive supply voltage VCC GND to 6 V

Digital negative supply

voltage DVEE GND to -5.7 V

Digital posi tive supply

voltage VPLUSD GND-0.3 to 2.8 V

Negative suppl y vol tage VEE GND to -6 V

Maximum difference

between negative supply

voltages

DVEE to VEE 0.3 V

Analog input voltages VIN or VINB -1 to +1 V

Maximum difference

between VIN and VINB

VIN - VINB -2 to +2 V

Digital i nput vol t age VDGORB -0.3 to VCC +0.3 V

Digital i nput vol t age VDDRRB VEE -0.3 to +0.9 V

Digital output voltage Vo VPLUSD-3 to VPLUSD -0.5 V

Clock input voltage VCLK or VCLKB -3 to +1.5 V

Maximum difference

between VCLK and VCLKB

VCLK - VCLKB -2 to +2 V

Maximum juncti on

temperature Tj+135 oC

Storage temperature Tstg -65 t o +150 oC

Lead temperature

(soldering 10s ) Tleads +300 oC

Notes : Absolute maximum ratings are li miting values (ref e renced to GND=0V), to be applied individually, while other parameters are within

specified operating conditions. Long exposure to maximum rating may affect devic e reliabil it y.

The use of a thermal heat sink is mandatory (see Thermal characteristics).

3.2. RECOMMENDED CONDITIONS OF USE

Parameter Symbol Comments Min. Typ. Max. Unit

Positive supply voltage VCC 4.75 +5 5.25 V

Positive digital supply voltage V PLUSD ECL output compatibility GND V

VPLUSD LVDS output compatibility +1.4 +2.4 +2.6 V

Negative suppl y vol tages VEE, DVEE -5.25 -5.0 -4.75 V

Different i al analog i nput voltage

(Full Scale) VIN, VINB

VIN -VINB

50 Ω differential or single-ended ±113

450

±125

500

±137

550

mVpp

Clock input power level PCLK PCLKB 50 Ω single–ended clock i nput 3 4 10 dBm

Operating tem perature range TJCommerc i al grade: “C”

Industri al grade: “V”

Military grade: “M”

0° < Tc ; Tj < 90°

-40 < Tc; Tj < 110°

-55 < Tc ; Tj < +125

Product Specification

TS8388BF

3.3. ELECTRICAL OPERATING CHARACTERISTICS

VEE = DVEE = -5 V ; VCC = +5 V ; VIN -VINB = 500 mVpp Full Scale differenti al input ;

Digital outputs 75 or 50 Ω differentially terminated ;

Tj (typical) = 70°C. Full Temperature Range : up to –55°C<Tc; Tj<+125°C.

Parameter Symb Test

level Min Typ Max Unit

POWER REQUIREMENTS

Positive supply voltage Analog

Digital (ECL)

Digital (LVDS)

VCC

VPLUSD

1, 2, 6

4.7

1.4

2.4

5.3

2.6

Positive supply current Analog

Digital

ICC

IPLUSD

1, 2

385

395

115

120

445

145

Negative suppl y vol t age VEE 1, 2, 6 -5.3 -5 -4.7 V

Negative suppl y current Analog

Digital

AIEE

DIEE

1, 2

165

170

135

145

200

180

Nominal power dissi pati on PD 1, 2

63.4

3.6 4.1

4.3 W

Power supply rejec t ion ratio (note 2) PSRR 4 0.5 2 mV/V

RESOLUTION 8bits

ANALOG I NPUTS

Full Scale Input Voltage range (differential mode)

( 0 Volt common mode voltage ) VIN

VINB

4 -125

-125 125

125 mV

Full Scale Input Voltage range (single–ended input opt i on )

(see Application

Notes)

VIN

VINB

4 -250 0250 mV

Analog input capacitanc e CIN 433.5pF

Input bias current IIN 41020µA

Input Resistance RIN 40.51 MΩ

Full Power input Bandwidth FPBW 4 1.3 1.5 GHz

Small Signal input B andwidth (10 % full scale) SSBW 4 1.5 1.7 GHz

CLOCK INPUTS

Logic compatibility for clock inputs (note 10 )

(see Application Notes) ECL or specified clock input

power level in dBm

ECL Clock inputs voltages (VCLK or VCLKB) : 4

• Logic “0” volt age VIL -1.5 V

• Logic “1” volt age VIH -1.1 V

• Logic “0” current IIL 550µA

• Logic “1” current IIH 550µA

Clock input power level int o 50 Ω ter min a tion DBm into 50 Ω

Clock input power level 4 -2 4 10 dBm

Clock input c apaci t a nce CCLK 433.5pF

6TS8388BF

Product Specification

Parameter Symb Test

level Min Typ Max Unit

DIGITAL OUTPUTS (notes 1,6)

Single ended or diff erential input mode, 50 % clock duty cycl e (CLK, CLKB), B i nary out put data f ormat,

Tj (ty pical ) = 70 °C.

Logic compatibil ity f or digit al outputs

( Depending on the value of VPLUSD )

(see Application Notes)

ECL or LVDS

Different i a l output voltage swings ( assuming VPLUSD = 0V) :

75 Ω open transmission l i nes ( ECL levels )

75 Ω differentiall y terminated

50 Ω differentiall y terminated

41.50

0.70

0.54

1.620

0.825

0.660

Output levels ( assum i ng VPLUSD = 0V)

75 Ω open transmission l i nes (note 6) 4

• Logic “0” volt age VOL -1.62 -1.54 V

• Logic “1” volt age VOH -0.88 -0.8 V

Output levels ( assum i ng VPLUSD = 0V)

75 Ω d ifferentially terminated (note 6) 4

• Logic “0” volt age VOL -1.41 -1.34 V

• Logic “1” volt age VOH -1.07 -1 V

Output levels ( assum i ng VPLUSD = 0V)

50 Ω differentiall y terminated (note 6)

• Logic “0” volt age VOL 1, 2

-1.40

-1.32

-1.25

• Logic “1” volt age VOH 1, 2

-1.16

-1.25

-1.10

Different i al Output Swing DOS 4 270 300 mV

Output level drift with t emperat ure 4 1.6 mV/°C

DC ACCURACY

Single ended or diff erential input mode, 50 % clock duty cycl e (CLK, CLKB), B i nary output data format,

Tj (ty pical ) = 70 °C.

Differential non linearity (notes 2,3) DNL- 1, 2

6-0.5

-0.6 -0.25

-0.35 LSB

LSB

DNL+ 1, 2

60.3

0.4 0.6

0.7 LSB

LSB

Integral non linearity (notes 2,3) INL- 1, 2

6-1.0

-1.2 0.7

0.9 LSB

LSB

INL+ 1, 2

0.7

0.9 1.0

1.2 LSB

LSB

No missing codes (note 3) Guaranteed over specified temperature range

Gain error 1, 2

-10

-11 -2

-2 10

11 % FS

% FS

Input offset volt age 1, 2

6-26

-30 -5

-5 26

30 mV

Gain error drift

Offset error drift 4

100

125

150

ppm/°C

Product Specification

TS8388BF

Parameter Symb Test

level Min Typ Max Unit

TRANSIENT PERFORMANCE

Bit Error Rate (notes 2, 4)

FS = 1 Gsps Fin = 62.5 MH z BER 4 1E-12 Error/

sample

ADC sett ling time (note 2)

VIn -VinB = 400 mVpp TS 4 0.5 1 ns

Overvoltage recovery time (note 2) TOR 4 0.5 1 ns

AC PERFORM ANCE

Single ended or diff erenti al i nput and clock mode, 50 % clock duty c ycl e (CLK, CLKB), Binary output data format,

Tj. = 70°C, unless otherwise specified.

Signal to Noise and Dist ortion ratio (note 2) SINAD

FS = 1 Gsps Fin = 20 MHz 4 42 44 dB

FS = 1 Gsps Fin = 500 MHz 4 41 43 dB

FS = 1 Gsps Fin = 1000 MHz (-1dB Fs) 4 38 40 dB

FS = 50 Msps Fin = 25 MHz 1, 2, 6 40 44 dB

Effecti ve Num ber Of bits ENOB

FS = 1 Gsps Fin = 20 MHz 4 7. 0 7.2 Bits

FS = 1 Gsps Fin = 500 MHz 4 6. 6 6.8 Bits

FS = 1 Gsps Fin = 1000 MHz (-1dBFs) 4 6.2 6.4 Bits

FS = 50 Msps Fin = 25 MHz 1, 2, 6 7.0 7.2 Bi ts

Signal to Noise Ratio (note 2) SNR

FS = 1 Gsps Fin = 20 MHz 4 42 45 dB

FS = 1 Gsps Fin = 500 MHz 4 41 44 dB

FS = 1 Gsps Fin = 1000 MHz (-1dBFs) 4 41 44 dB

FS = 50 Msps Fin = 25 MHz 1, 2, 6 44 45 dB

Total Harmonic Distortion (note 2) THD

FS = 1 Gsps Fin = 20 MHz 4 50 54 dB

FS = 1 Gsps Fin = 500 MHz 4 46 50 dB

FS = 1 Gsps Fin = 1000 MHz (-1dBFs) 4 42 46 dB

FS = 50 Msps Fin = 25 MHz 1, 2, 6 46 51 dB

Spurious Free Dynamic Range (note 2) SFDR

FS = 1 Gsps Fin = 20 MHz 4 52 57 dBc

FS = 1 Gsps Fin = 500 MHz 4 47 52 dBc

FS = 1 Gsps Fin = 1000 MHz (-1dBFs) 4 42 47 dBc

FS = 1 Gsps Fin = 1000 MHz (-3dBFs) 4 45 50 dBc

FS = 50 Msps Fin = 25 MHz 1, 2, 6 40 54 dBc

Two-tone inter-modul ation distortion (note 2) IMD 4

FIN1 = 489 MHz @ FS = 1 Gsps - 47 - 52 dBc

FIN2 = 490 MHz @ FS = 1 Gsps

8TS8388BF

Product Specification

Parameter Symb Test

level Min Typ Max Unit

SWITCHING PERFORMANCE AND CHA RACTERISTICS – See Timing Diagrams Figure 1, Figure 2

Maximum clock frequency (Note 14) FS11.4Gsps

Minimum clock frequency (Note 15) FS410 50Msps

Minimum Clock pulse width (high) TC1 4 0.280 0.500 50 ns

Minimum Clock pulse width (l ow) TC2 4 0.350 0.500 50 ns

Aperture delay (Note 2) TA 4 100 +250 400 ps

Aperture uncertainty (Notes 2, 5) Jitter 4 0.4 0.6 ps (rms )

Data output delay (Notes 2, 10, 11, 12) TOD 4 1150 1360 1660 ps

Output rise/fall time for DATA (20 % – 80 %)

(note 11)TR/TF 4 250 350 550 ps

Output rise/fal l time for DA TA READY

(20 % – 80 % ) (note 11)

TR/TF 4 250 350 550 ps

Data ready output delay (Notes 2,10, 11, 12) TDR 4 1110 1320 1620 ps

Data ready reset delay TRDR 4 720 1000 ps

Data to data ready – clock low pulse width

(See timing diagram, notes 9, 13, 14)

TOD-

TDR 4 0 40 80 ps

Data to data ready output del ay (50% duty cycle)

(See timing diagram, notes 2, 15) @ 1Gsps

TD1 4 420 460 500 ps

Data pipeline del ay TPD 4 4 clock

cycles

Note 1 : Different i al output buffers are i nternally loaded by 75

Ω

resistors. Buff er bi as current = 11 mA.

Note 2 : See definiti on of terms

Note 3 : Histogram test i ng based on sampling of a 10 MHz sinewave at 50 MSPS.

Note 4 : Output error amplit ude <

4 LSB around worst code.

Note 5 : Maximum jitter value obtained for single–ended clock i nput on the JTS8388B die (chi p on board) : 200 fs.

(500 fs expected on TS8388BG)

Note 6 : Digital output back termination options depicted in Application Notes figures 3,4,5 .

Note 7 : With a typical value of TD = 465 ps, at 1 Gsps, the timing safety margin for the data storing using the ECLinPS 10E452 output

registers from Motorola is of

315 ps, equally shared before and after the rising edge of the Data Ready signals (DR, DRB).

Note 8 : The clock inputs may be indifferently entered in differential or single–ended, using ECL levels or 4 dBm typical power level into the

Ω

termination resistor of the inphase clock input.

(4 dBm into 50

Ω

clock input correspond to 10 dBm power level for the clock generat or.)

Note 9 : At 1GSPS, 50/50 clock duty cyc l e, TC2 = 500 ps (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate.

Note 10 : Specified loadi ng conditions for digital outputs :

- 50

Ω

or 75

Ω

controlled impedance traces properly 50 / 75

Ω

terminated, or unterminated 75

Ω

controlled impedance traces.

- Controlled impedanc e trac es far end loaded by 1 standard ECLinPS regi ster f rom Motorola.( e.g. : 10E452 ) ( Typical input parasitic

capacitanc e of 1.5 pF including package and ESD protections. )

Note 11 : Termination load parasitic capacit ance derating values :

- 50

Ω

or 75

Ω

controlled impedance traces properly 50 / 75

Ω

terminated : 60 ps / pF or 75 ps per additionnal ECLinPS load.

- Unterminated ( source terminat ed ) 75

Ω

controlled impedance lines : 100 ps / pF or 150 ps per additionnal ECLinPS terminati on

load.

Note 12 :apply proper 50 / 75

Ω

impedance traces propagation time derating values : 6 ps / mm (155 ps/inch) for TSEV8388BF Evaluation

Board.

Note 13 : Values for TOD and TDR track each other over temperature, ( 1 % variation for TOD - TDR per 100 oC. temperature variation ).

Therefore TOD - TDR variation over temperature is negligible. Moreover, the internal ( onchip ) and package skews between each

Data TODs and TDR effect can be considered as negligible.Consequently, minimum values for TOD and TDR are never more than

100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes about TOD - TDR variation

over temperature in sect i on 7).

Note 14 : Min value guarantees performance. Max value guarantees functionality.

Note 15 : Min value guarantees functionali ty . M ax value guarant ees perf ormanc e.

Product Specification

TS8388BF

3.4. TIMING DIAGRAMS

TC1 TC2

TA= 250 ps

N+1

XN+2

XN+3

Figure 1 : TS8388BF TIMING DIAGRAM ( 1 GSPS CLOCK RATE )

Data Ready Reset , Clock held at LOW level

DIGITAL

OUTPUTS

(VIN, VINB )

Data Ready

(DR, DRB)

(CLK, CLKB)

1. N+5

TD1=TC1+TDR-TOD

= TC1-40 ps = 460 ps

DATA

N-4 DATA

N-3 DATA N

DATA

-1

DATA

N-2

TC=1000 ps

N+4

TOD = 1360 ps

1360 ps

DRRB 1ns (min)

TDR = 1320 ps

TPD: 4.0 Clock periods

1000 ps

TRDR = 720 ps

N-1

TD2 = TC2+TOD-TDR

= TC2+40ps = 540 ps

TDR = 1320 ps

DATA

N-5 DATA

N+1

TC1 TC2

TA= 250ps

X3.

N+1

XN+2

XN+3

Figure 2 : TS8388BF TIMING DIAGRAM ( 1 GSPS CLOCK RATE )

Data Ready Reset , Clock held at HIGH level

DIGITAL

OUTPUTS

(VIN, VINB )

Data Ready

(DR, DRB)

(CLK, CLKB)

2. N+5

TD1=TC1+TDR-TOD

= TC1-40 ps = 460 ps

DATA

N-4 DATA

N-3 DATA N

DATA

N-1

DATA

N-2

TC = 1000 ps

N+4

TOD = 1360 ps

1360 ps

DRRB 1ns (min)

TDR = 1320 ps

TPD: 4.0 Clock periods

1000 ps

TRDR = 720ps

N-1

TD2 = TC 2+TOD-TDR

= TC2+40ps = 540 ps

TDR = 1120 ps

DATA

N-5 DATA

N+1

10 TS8388BF

Product Specification

3.5. EXPLANATION OF TEST LEVELS

1 100% production test ed at +25°C (1) (for “C” Temperature range (2) ).

2 100 % production tested at +25°C (1), and sample tested at specified temperatures (for “V” and “M” Temperature ranges (2) ).

3 Sample test ed onl y at specif i e d temperatures

4 Parameter is guaranteed by des i g n and characteri zation testing (thermal steady-st ate conditions at specified temperature).

5 Parameter is a typical val ue only

6 100 % production tested over specified temperature range (for “B/Q” Temperature range (2) ).

Only MIN and MAX values are guaranteed (typical values are issui ng f rom characterization res ul ts ).

(1) Unless otherwise specifi ed, all tests are pulsed test s : t herefore Tj = Tc = Ta,

where Tj ,Tc and Ta are junction, case and ambient temperature respectively.

(2) Refer to ORDERING INFORMATION chapter.

3.6. FUNCTIONS DESCRIPTION

Name Function

VCC Positive power supply

VEE Analog negative power supply

VPLUSD Digital positi ve power supply

GND Ground

VIN, VINB Differential analog inputs

CLK, CLKB Differential clock input s

<D0:D7>

<D0B:D7B> Differential output data port

DR ; DRB Different ial data ready outputs

OR ; ORB Out of range outputs

GAIN ADC gain adjust

GORB Gray or Binary di gi tal output select

DIOD/DRRB Die junction temp. measurement/

asynchronous data ready reset

3.7. DIGITAL OUTPUT CODING

NRZ (Non Return to Zero) mode, ideal coding : does not include gain, offset, and linearit y voltage errors.

Differential

analog input Vo l tage level Digital output Out of

Range

Binary

GORB = VCC or floating Gray

GORB = GND

> +251 mV > Positive full scal e + 1/2 LSB 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1

+251 mV

+249 mV Positive full scale + 1/2 LSB

Positi ve full scal e – 1/2 LSB 11111111

11111110 10000000

10000001 0

+126 mV

+124 mV Positi ve 1/2 scale + 1/2 LSB

Positive1/2 scale – 1/2 LSB 11000000

10111111 10100000

11100000 0

+1 mV

-1 mV Bipolar zero + 1/2 LSB

Bipolar zero - 1/ 2 LSB 10000000

01111111 11000000

01000000 0

-124 mV

-126 mV Negati ve 1/ 2 scale + 1/2 LSB

Negative 1/2 scale - 1/2 LSB 01000000

00111111 01100000

00100000 0

-249 mV

-251 mV Negati ve f ul l sc al e + 1/2 LSB

Negative full sc al e - 1/2 LSB 00000001

00000000 00000001

00000000 0

< -251 mV < Negative full scale - 1/2 LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

VPLUSD = +0 V (ECL)

VPLUSD = +2 .4V (LVDS)

VIN

VINB

CLK

CLKB

D0 →

→ →

→ D7

D0B →

→→

→ D7B

VEE=-5V

VCC = +5 V

TS8388BF

ORB

GND

GORB

GAIN

DVEE=-5V

DIOD/

DRRB

DRB

Product Specification

TS8388BF

4. PACKAGE DESCRIPTION.

4.1. TS8388BF PIN DESCRIPTION

Symbol Pin number Function

GND 5, 13, 27, 28, 34, 35, 36, 41, 42,

43, 50, 51, 52, 53, 58, 59 Ground pins.

To be connected to external ground plane.

VPLUSD 1, 2, 16, 17, 18, 68 Digital positive supply. (0V for ECL compatibil ity, +2.4V fo r LVDS

compatibility). (note 2)

VCC 26, 29, 32, 33, 46, 47, 61 +5 V positive supply.

VEE 30, 31, 44, 45, 48 -5 V analog negative supply.

DVEE 8, 9, 10 -5 V digital negative supply.

VIN 54(1), 55 In phase (+) analog input signal of the Sample and Hold

different i al preampl ifi er.

VINB 56, 57(1) Inverted phase (-) of analog input si gnal (V IN).

CLK 37(1), 38 In phase (+) ECL clock input signal. The analog input is sampled

and held on the rising edge of the CLK signal.

CLKB 39, 40(1) Inverted phase (-) of ECL clock input signal (CLK).

D0, D1, D2, D3, D4, D5, D6,

D7 23, 21, 19, 14, 6, 3, 66, 64 In phase (+) digital outputs.

B0 is the LSB. B7 is the MSB.

D0B, D1B, D2B, D3B, D4B,

D5B, D6B, D7B 24, 22, 20, 15, 7, 4, 67, 65 Inverted phase (-) Digital outputs.

B0B is the inverted LSB. B7B is the inverted MSB.

OR 62 In phase (+) Out of Range Bit.

Out of Range is high on the leading edge of code 0 and code 256.

ORB 63 Inverted phas e (+) of Out of Range Bit (OR).

DR 11 In phase (+) output of Data Ready Signal.

DRB 12 Inverted phas e (-) output of Dat a Ready Signal (DR).

GORB 25 Gray or Binary sel ect out put format control pin.

– Binary output format if GORB is floati ng or VCC.

– Gray output format if GORB is connected at ground (0 V).

GAIN 60 ADC gain adjust pin.

DIOD/DRRB 49 This pin has a double function (can be left open or grounded if not

used) :

DIOD : die junction temperature m onitori ng pi n.

DRRB : asynchronous data ready reset function

Note 1 : Following pin numbers 37 (CLK), 40 (CLKB), 54 (VIN) and 57 (V INB) have to be c onnected to GND through a 50

Ω

resistor as close

as possible to the package.(50

Ω

termination preferred opti on).

Note 2 : The common mode level of the output buffers is 1.2V below the positive digital supply.

For ECL compatibility the positive digital supply must be set at 0V (ground ).

For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.

If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive digital

supply level i n the same proportion i n order to spare power dissipat i on.

12 TS8388BF

Product Specification

4.2. TS8388BF PINOUT

TS8388BF

VPLUSD

PLUSD

D2B

D1B

D0B

D3B

DRB

D4B

D5B

D6B

D7B

ORB

TOP VIEW :

Product Specification

TS8388BF

4.3. OUTLINE DIMENSIONS – 6 8 PINS CQFP

1.13 3 – 1. 147

78 – 29.13

.950 ± .006

24.13 ± 0.152

0.8 BCS

20.32 BS C

0.05 0 BCS

1.27 BSC

.950 ± .006

24.13 ± 0.152

1.13 3 – 1. 147

28.78 – 29.13

.023 ± .002

0.58 ± 0.05

Pin No 1 index

Ø .005 Z X Y

CQFP 68

68 pins Ceramic Quad Flat Pack – Top view

.135 Max

3.43 Max .004

.005 – .010

0.13 – 0.25

0o – 8o

.027 – .037

0.70 – 0.95

.018 – .035

0.46 – 0.88

.075 ± .008

1.9 ± 0.20

14 TS8388BF

Product Specification

4.4. THERMAL CHARACTERISTICS

Although the power dissipation is low for this performance, the use of a heat sink is mandatory.

You will find here below some advise on this topics.

4.4.1. THERMAL RESISTANCE FROM JUNCTION TO AMBIENT : RTHJA

The following table lists the converter t hermal performance parameters, with or without heatsink.

For the following measurements, a 50 x 50 x 16 mm heatsink has been used. (see drawing in part 4. 4.3. )

4.4.2. THERM AL RESISTANCE FROM JUNCTION TO CASE : RTHJC

Typical val ue for Rt hjc is given to 4. 75 oC/W.

4.4.3. CQFP68

BOARD ASSEMBLY WITH A 50 X 50 X 16 MM EXTERNAL HEATSINK

Air flo w Es tima ted Tar

eted

(m/s) W ithout heatsink With heatsink

050 10

0,5 40 8,9

135 7,9

1,5 32 7,3

230 6,8

2,5 28 6,5

326 6,2

424 5,8

523,5 5,6

Heatsink glued to backside of

package or screwed and

pressed with thermal grease

a therm al resistance

(

oC / W

)

CQFP68 on board

012345

Air flow (m/s)

Rthja (deg/W)

Without heat sink

With heats i nk

24.13

28.96

15.0

1.3

50.0

1.4

2.5

16.0

Printed circuit

Interface : Af-filled epoxy or thermal

conductive

rease – 10 0

m max .

Aluminum

heatsink

Product Specification

TS8388BF

5. TYPICAL CHARACTERIZATION RESU LTS

5.1. STATIC LINEARITY – FS = 50 MSPS / FIN = 10 MHZ

5.1.1. INTEGRAL NON LINEARITY

5.1.2. DIFFERENTIAL NON LINEARITY

LSB

INL = +/- 0.7 LSB

code

Signal Frequency = 10MHzClock Frequency = 50Msps

Positive peak : 0.78 LSB Negative peak : -0. 73 LSB

LSB

DNL = +/- 0.4 LSB

code

Signal Frequency = 10MHzClock Frequency = 50Msps

Positive peak : 0.3 LSB Negati ve peak : -0. 39 LSB

16 TS8388BF

Product Specification

5.2. EFFECTIVE NUMBER OF BITS VERSUS POWER SUPPLIES VARIATION

-7 -6,5 -6 -5,5 -5 -4,5 -4

Effective numbe r of bits = f

(

VEEA

)

; Fs = 500 MSPS ; Fin = 100 MH z

VEEA (V)

ENOB (bits)

33,544,555,566,57

Effective number of bits = f

(

VCC

)

; Fs = 500 MSPS ; Fin = 100 MHz

VCC (V)

ENOB (bits)

-6 -5,5 -5 -4,5 -4 -3,5 -3

Effective number of bits = f

(

VEED

)

; Fs = 500 MSPS ; Fin = 100 MHz

VEED (V)

ENOB (bits)

Product Specification

TS8388BF

5.3. TYPICAL FFT RESULTS

5.3.1 FS = 1 GSPS, F IN=20 MHZ

5.3.2. FS = 1 GSPS, FIN = 495 MHZ

5.3.3. FS = 1 GSPS, FIN = 995 MHZ ( -3DB FULL SCALE INPUT)

Single Ende d or

differential

Fs =1 GSPS

Fin = 20 MHz

Eff. Bi ts =7.2

SINAD = 44.3 dB

SNR = 44.7dB

THD = -54dBc

SFDR = -57 dBc

H3H2

clock duty cycle = 50 %

Binary output coding

H11 H12

Single Ende d or

differential

Fs =1 GSPS

Fin=495MHz

Eff. Bi ts =6.8

SINAD =43 dB

SNR = 44.1 dB

THD = -50 dBc

SFDR= -52 dBc

clock duty cycle = 50 %

H11

H14

H12

Binary output coding

Single Ende d or

differential

Fs =1 GSPS

Fin=995 MHz

Eff. Bi ts =6.6

SINAD =40.8 dB

SNR = 44 dB

THD = -48 dBc

SFDR= -50 dBc

clock duty cycle = 50 %

Binary output coding

H10

18 TS8388BF

Product Specification

5.4. SPURIOUS FREE DYNAMIC RANGE VERSUS INPUT AMPLITUDE

5.4.1. SAMPLING FREQUENCY FS=1 GSPS ; INPUT FREQUENCY FIN=995 M HZ ; GRAY OR BINARY OUTPUT CODING

Fs = 1 GSPS Fin = 995 MHz Full Scale

ENOB

6.4

SINAD

40 dB

SNR

44dB

THD

46 dBc

SFDR

47 dBc

Full Scale

magnitude (code)

SFDR = -47 dBc

-3dB Full Scale

Fs = 1 GSPS Fin = 995 MHz (-3 dB Full Scale)

ENOB = 6.6 SINAD = 40.8 dB SNR = 44dB SFDR = -50dBc

magnitude (code)

THD = -48dBc

SFDR = -50 dBc

Product Specification

TS8388BF

5.5. DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY

Fs=1 Gsps, Fin = 0 up to 1600 MHz, Full Scale input (FS), FS -3 dB

Clock duty cyc l e 50 / 50, Binary/Gray output codi ng, f ully diff erential or single-ended analog and clock inputs

0 200 400 600 800 1000 1200 1400 1600 1800

Input frequenc

(

MHz

)

ENOB (dB)

-3 dB FS

0 200 400 600 800 1000 1200 1400 1600 1800

Input frequency (MH z)

SNR (dB)

-3 dB FS

-60

-55

-50

-45

-40

-35

-30

-25

-20

0 200 400 600 800 1000 1200 1400 1600 1800

Input frequency (MH z)

SFDR (dBc)

-3 dB FS

20 TS8388BF

Product Specification

5.6. EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY

Analog Input Frequency : Fin = 495 MHz and Nyquist conditions ( Fi n = Fs / 2 )

Clock duty cycle 50 / 50 , Binary output coding

5.7. SFDR VERSUS SAMPLING FREQUENCY

Analog Input Frequency : Fin = 495 MHz and Nyquist conditions ( Fin = Fs / 2 )

Clock duty cycle 50 / 50 , Binary output coding

0 200 400 600 800 1000 1200 1400 1600

Sampling frequency (Ms ps)

ENOB (dB)

Fin= FS/2

Fin=500 MHz

-60

-55

-50

-45

-40

-35

-30

-25

-20

0 200 400 600 800 1000 1200 1400 1600

Sampling frequency (Ms ps)

SFDR (dBc)

Fin= FS/2

Fin=500 MHz

Product Specification

TS8388BF

5.8. TS8388BF ADC PERFORMANCES VERSUS JUNCTION TEMPERATURE

-40 -20 0 20 40 60 80 100 120 140 160

Effective numb er o f bits versus junction tem perature

Fs = 1 GSPS ; Fin = 500 MHz ; Duty c yc le = 50%

Temperature

(

)

ENOB (bits)

-60 -40 -20 0 20 40 60 80 100 120

Signal to noise ratio versus junction temperature

Fs = 1 GSPS ; Fin = 507 MHz ; Differential clock, Single-ended analog input (Vin=-1dBF s)

Temperature

(

)

SNR (dB)

-60 -40 -20 0 20 40 60 80 100 120

Total harmonic distorsion versus junction temperature

Fs = 1 GSPS ; Fin = 507 MHz ; Differential clock, Single-ended analog input (Vin=-1dBFs)

Temperature ( oC)

THD (dB)

22 TS8388BF

Product Specification

5.9. TYPICAL FULL POWER INPUT BANDWIDTH

1.5 GHz at -3 dB (-2dBm full power input)

-40 -20 0 20 40 60 80 100 120 140 160

Power consumption versus junction temperature

Fs = 1 G SPS ; Fin = 500 MHz ; Duty cycle = 50%

Tem perature (

oC)

Power consumption (W

)

-6

-5

-4

-3

-2

-1

0100 300 500 700 900 1100 1300 1500 1700

Frequency (MHz)

Magnitude (dB)

Product Specification

TS8388BF

5.10. ADC STEP RESPONSE

Test pulse input characteristics : 20% to 80% input full scale and rise time ~ 200ps.

Note : This step response was obtained with the TSEV8388B chip on board (device in die form).

5.10.1. TEST PULSE DIGITIZED WITH 20 GHZ DSO

5.10.2. SAME TEST PULSE DIGITIZED WITH TS8388BF AD C

N.B. : ripples are due to the test setup (they are present on bot h measurements )

50 mV/div

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.00time (ns)

Vpp ~ 260 mV

Tr ~ 240 ps

50 mV/div

500 ps/div

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.00

200

150

100

ADC code

time (ns)

Tr ~ 280 ps

50 codes/div (Vpp ~260 mV)

500 ps/div

ADC calculated rise time : between 150 and 200

24 TS8388BF

Product Specification

6. DEFINITION OF TERMS

(BER) Bi t Error Rate Probability to exceed a specified error threshold for a sample. An error code is a code that differs

by more than +/- 4 LSB from the correct code.

(BW) Full power i nput

bandwidth A nalog input f requency at which the fundamental component in the di gitally rec onstructed output

has fallen by 3 Db with respect to its low frequency value (determ ined by FFT analysis) for input

at Full Scale.

(SINAD) S i gnal to noise and

distortion ratio Ratio expressed in Db of the RMS signal amplitude, set to 1Db below Full Scale, to the RMS

sum of all other spectral c omponents, including the harmonics except DC.

(SNR) Signal to noise ratio Ratio expressed in Db of the RMS signal amplitude, set to 1Db below Full Scale, to the RMS

sum of all other spectral c omponents excludi ng the five first harmonics.

(THD) Total harmonic

distorsion Rat io expressed i n dBc of the RMS sum of the first five harmonic com ponents, to the RMS value

of the measured fundamental spectral component.

(SFDR) Spurious free dynamic

range Ratio expressed in Db of the RMS signal amplitude, set at 1Db below Full Scale, to the RMS

value of the next highest spectral component (peak spurious spect ral component). SFDR is t he

key parameter for selecting a converter to be used in a frequency domain application ( Radar

systems, digital receiver, network analyzer ….). It may be reported in dBc (i.e., degrades as

signal l evels is lowered), or in Dbfs (i.e. always related back to converter full scale).

(ENOB) Effective Number Of Bits Where A is the actual input amplitude and V

is the full scale range of the ADC under test

(DNL) Differential non

linearity The Differential Non Linearity for an output code i is the difference between the measured step

size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum

value of all DNL (i). DNL error specification of less than 1 LSB guarantees that there are no

missing output c odes and that the transfer function is monotonic.

(INL) Integral non lineari ty The Integral Non Linearity for an output code i is the difference between the measured input

voltage at which the transition occurs and the ideal value of this transition.

INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|.

(DG) Differential gain The peak gain variation (in percent) at five different DC levels for an AC signal of 20% Full

Scale peak to peak amplitude. FIN = 5 MHz . (TB C)

(DP) Diff erential phase Peak Phase variat ion (in degrees) at five different DC levels for an A C signal of 20% Full Sc ale

peak to peak amplitude. FIN = 5 MHz. (TBC)

(TA) Apert ure del ay Delay between the risi ng edge of the differenti al clock inputs (CLK,CLKB) (zero crossi ng point),

and the time at which (VIN,VINB) is sam p l e d.

(JITTER) Aperture uncertainty Sam ple to sample variation in aperture delay. The voltage error due to jitter depends on t he slew

rate of the signal at the sampling point.

(TS) Settling tim e Time delay to achieve 0.2 % accuracy at the converter output when a 80% Full Scale step

function is appli ed to the differential anal og input.

(ORT) Overvoltage recov ery

time Time to recover 0.2 % accuracy at the output, after a 150 % full scale step applied on the input is

reduced to midscal e.

(TOD) Digital data

Output delay Delay from the falling edge of the differential clock inputs (CLK,CLKB) (zero crossing point) to

the next point of change in the differenti al out put data (zero crossing) with specified load.

(TD1) Time delay from Data to

Data Ready Time delay from Data transition to Data ready.

(TD2) Time delay from Data

Ready to Data General expression is TD1 = TC1 + TDR – TOD wi th TC = TC1 + TC2 = 1 encoding clock

period.

(TC) Encoding clock period TC1 = Minimum clock pulse width (high) TC = TC1 + TC2

TC2 = Minimum clock pulse width (low)

(TPD) Pipel i ne Del ay Number of clock cycles between the sampling edge of an input data and the associated output

data being made available, (not taking in account the TOD). For the TS8388BF the TPD is 4

clock periods.

(TRDR) Dat a Ready reset delay Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB)

and the reset to digital zero trans iti on of the Data Ready output si gnal (DR).

(TR) Rise time Time delay for the output DATA signals to rize from 20% to 80% of delta between low level and

SINAD - 1.76 + 20 log (A/V/2)

ENOB = 

6.02

Product Specification

TS8388BF

high level.

(TF) Fall time Time delay for the output DATA signals to fall from 80% to 20% of delta between low level and

high level.

(PSRR) Power supply

rejection ratio Ratio of input offset variation to a change in power supply voltage.

(NRZ) Non return to zero W hen the input signal is larger than the upper bound of the ADC input range, the output code is

identical to the maximum code and the Out of Range bit is set to logic one. When the input

signal is smaller than the lower bound of the ADC input range, the output code is identical to the

minimum code, and the Out of range bit is set to logic one. (It is assumed that the input signal

amplitude rem ains within the absolute maximum ratings).

(IMD) InterModul ati on Distortion The two tones intermodulation distortion ( IMD ) rejection is the ratio of either input tone to the

worst third order int erm odulati on products . The input tones levels are at – 7Db Full Scale.

(NPR) Noise Power Ratio The NPR is measured to characterize the ADC performance in response to broad bandwidth

signals. When using a notch-filtered broadband white-noise generator as the input to the ADC

under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the

average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output

sample test.

26 TS8388BF

Product Specification

7. TS8388BF MAIN FEAT U RES

7.1. TIMING INFORMATIONS

7.1.1. TIMING VALUE FOR TS8388BF

Timing values as defined in 3.3 are advanced data, issuing f rom elect ric simulations and first characterizations results fitt ed with m easurements.

Timing values are given at CQFP68 package inputs/ outputs , taki ng i nto account pack age internal cont rol l ed impedance t races propagation

delays, gullwing pin model, and specified termination loads.

Propagation delays i n 50/75 ohms impedance traces are NOT taken into account for TOD and TDR.

Apply proper derati ng val ues corresponding to termination topology.

The min/max timing values are valid over the full temperature range in the following conditions :

Note 1 : Specified Termination Load (Differential output Data and Data Ready) :

50 ohms resistor in paralle l with 1 standard ECLinPS register from Motorola, (e.g : 10E452)

(Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package and ESD protecti ons)

If addressi ng an output Dmux, take care if some Digit al outputs do not have the same terminat i on load and apply corres pondi ng derating val ue

given below.

Note 2 : Output Termination Load derating values f or TOD and TDR :

~ 35 ps/pF or 50 ps per additional ECLinPS load.

Note 3 :Propagation tim e delay derati ng val ues have also to be appl i ed for TOD and TDR :

~ 6 ps/mm (155 ps/inch) for TSEV8388B Evaluation Board.

Apply proper time delay derating value if a different dielectric layer is used.

7.1.2. PROP AGATION TIME CONSIDERATIONS

TOD and TDR Timing values are given from pin to pin and DO NOT include the additional propagation times between device pins and

input/out put t erminat i on loads. For the TSEV8388B Evaluation Board, the propagat ion time delay is 6ps/mm (155ps/inch) corresponding to 3.4

(@10GHz) dielect ric const ant of the RO4003 used for the Board.

If a different dielect ri c layer is used (f or instance Teflon), please use appropriate propagation time values .

TD does NOT depend on propagation times because it is a differential data.

(TD is the time difference between Data Ready output delay and di gital Data output delay)

TD is also the most straightforward data to measure, again because i t is differenti al :

TD can be measured directly onto termination loads, with matched Oscilloscopes probes.

7.1.3. TOD - TDR VARIATION OVER TEMPERATURE

Values for TOD and TDR track each other over temperature (1 perc ent variation for TOD - TDR per 100 degrees Celsius temperature variation).

Therefore TOD - TDR variation over temperature is negligi bl e. Moreover, t he i nternal (onchip) and package skews between each Data TODs

and TDR effect can be considered as negligi bl e.

Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR m aximum values.

In other terms :

If TOD is at 1150 ps, TDR will not be at 1620 ps ( maximum time delay for TDR ).

If TOD is at 1660 ps, TDR will not be at 1110 ps ( minimum time delay for TDR ) However, external TOD - TDR values may be dictated by total

digital datas skews between every TODs (each digital data) and TDR :

MCM Board , bonding wires and output lines lengths differences, and output termination impedance mismatches.

The external (on board) skew effect has NOT been taken into account for the specification of the minimum and maximum values for TOD-TDR.

7.1.4. PRINCIPLE OF OPERATION

The Analog input is sampled on the rising edge of external clock input (CLK,CLKB ) after TA (aperture delay) of typically 250ps .

The digitized data is avai l abl e after 4 clock periods l atency (pipeline delay (TPD)), on clock ris i ng edge, after 1360 ps typical propagation delay

TOD.

The Data Ready different i al output signal frequency (DR,DRB) is half the external clock frequenc y, t hat i s it switc hes at t he s ame rate as the

digital outputs.

The Data Ready output signal (DR, DRB) switches on external clock falling edge after a propagation delay TDR of typically 1320 ps.

A Master Asynchronous Reset input command DRRB ( ECL compatible single-ended input ) is availabl e for initi a l i zing the diff erent ial Data

Ready output signal ( DR,DRB ) .This feature is mandat ory in certain appl ic ations using interleaved ADCs or using a single ADC with

demultipl exed output s. Actually, without Data Ready signal initializat i on, it is impossibl e to store the output digit al datas i n a defined order.

Product Specification

TS8388BF

7.2. PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND

7.2.1. DATA READY OUTPUT SIGNAL RESET

The Data Ready signal is reset on falling edge of DRRB input command, on ECL logical low level (-1.8V). DRRB may also be tied to VEE = - 5V

for Data Ready out put signal Master Reset . S o long DRRB remains at logical low level, (or tied to VEE = - 5V), the Data Ready output remains

at logical zero and is independant of th e external free running enc odi ng clock.

The Data Ready output signal (DR, DRB) is reset to logic al zero after TRDR= 920 ps typical.

TRDR is measured between the -1.3V point of the falling edge of DRRB input command and the zero crossing point of the differential Data

Ready output signal (DR,DRB).

The Data Ready Reset command may be a pulse of 1 ns minimum time width.

7.2.2. DATA READY OUTPUT SIGNAL RESTART

The Data Ready output signal rest arts on DRRB command rising edge, ECL logical hi gh levels (-0. 8V ).

DRRB may also be Grounded, or is allowed to float, for norm al free running Data Ready output signal.

The Data Ready signal restart s equence depends on the logical level of the external encoding clock, at DRRB rising edge instant :

1) The DRRB rising edge occurs when external encoding cl ock input (CLK,CLKB) is LOW :

The Data Ready output first rising edge occurs after half a clock period on the clock falling edge, after a delay time TDR = 1320 ps already

defined hereabove.

2) The DRRB rising edge occurs when external encoding cl ock input (CLK,CLKB) is HIGH :

The Data Ready output first rising edge occurs after one clock period on the clock falling edge, and a delay TDR = 1320ps.

Consequently, as the analog input is sampled on clock risi ng edge, the fi rst digitized data corresponding to the first acquisition ( N ) after Data

Ready signal rest art ( ri si ng edge ) is always strobed by the third rising edge of the data ready signal.

The time delay (TD1) is specified between the last point of a change in the differenti al output dat a (zero cross i ng point) to the rising or falling

edge of the differenti al Data Ready si gnal (DR,DRB) (zero crossing point).

Note 1 : For normal initializat i on of Data Ready output signal , t he external encoding clock signal frequency and level must be controlled.

It is reminded that the minimum encoding clock sampling rate for the ADC is 10 MSPS and consequently the clock cannot be stopped.

Note 2 : One single pin is used for both DRRB input command and die junction temperature monitori ng.

Pin denomination will be DRRB/DIOD.( On former version denomination was DIOD. )

Temperature monitori ng and Data Ready control by DRRB is not possible simultaneously.

7.3. ANALOG INPUTS (VIN) (VINB)

The analog input Full Scale range is 0.5 Volts peak to peak (Vpp), or -2 dBm into the 50 ohms termination resistor.

In differenti al mode input configurat i on, t hat means 0.25 Volt on each input, or +/- 125 mV around zero volt. The input common m ode is

GROUND.

The typical input capacitanc e is 3 pF for TS8388B in CQFP package.

The input capacitance is mainly due to the package.

Differential inputs voltage span

-125

125

[mV]

-250 mV250 mV

VIN

500mV

Full Scale

analog input

VINB

(VIN,VINB) = +/- 250 mV = 500 mV diff

0 Volt

Differential versus single ended analog input operation

The TS8388BF can operate at full speed in either differential or single ended configuration.

This is explained by the fact the ADC uses a high input impedance differenti al preampl ifi er st age, (prec eedi ng the Sample and hold stage),

which has been designed in order to be entered either in differential m ode or single–ended mode.

28 TS8388BF

Product Specification

This is true so long as the out of phase analog input pin VINB is 50 ohms terminated very closely to one of the neighboring shield ground pins

(52, 53, 58, 59) which constitut e the local ground reference for the inphase analog input pin (VIN).

Thus the differential analog input preamplifier will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as

common mode effects.

In typical singl e–ended conf i guration, enter on the (VIN) input pin, with the inverted phase input pin (VINB) grounded through the 50 ohms

terminat i on resist or.

In single–ended input configuration, the in-phase input amplitude is 0.5 Volt peak to peak,centered on 0V. (or -2 dBm into 50 ohms.)

The inverted phase input is at ground potenti al through the 50 ohms terminati on resist or.

However, dynam ic performances can be somewhat improved by entering either anal og or clock inputs i n different i al mode.

Typical Single ended analog input configuration

VIN or VINB VIN or VINB double pad (pins 54, 55 or 56, 57)

50 Ω

(external)

50 Ω rev erse termi nat i on

1MΩ3 pF

-250

250

[mV]

500 mV

Full Scale

analog input

VINB

VIN

VINB = 0V

VIN = +/- 250 mV ⇔ 500 mV diff

7.4. CLOCK INPUTS (CLK) (CLKB)

The TS8388BF can be clocked at full speed without noticeable performance degradat i on i n either different i al or singl e ended configuration.

This is explained by the fact the ADC uses a differential pream pl ifi er stage for the clock buffer, which has been designed in order to be entered

either in diff erential or singl e–ended mode.

Recommended sinewave generator c haracteristics are typically -120 dBc/ Hz phase noise floor spectral density, @ 1 KHz from carrier ,

assuming a singl e tone 4 dBm input for the clock signal.

7.4.1. SINGLE ENDED CLOCK INPUT (GROUND COMMON MODE)

Although the clock inputs were intended t o be driven differentially with nominal -0.8V / -1.8V ECL levels, the TS8388BF clock buffer can manage

a single–ended sinewave clock signal centered around 0 Volt. This is the most conveni ent clock input configuration as it does not require the

use of a power splitter.

No performance degradation ( e.g. : due to timing jitter) is observed in this particular single–ended configuration up to 1.2GSPS Nyquist

conditi ons ( Fin = 600 MHz ).

This is true so long as the inverted phase clock input pin is 50 ohms terminated very closely to one of the neighbouring shield ground pin, which

constitutes the local Ground reference for the inphase clock input.

Thus the TS8388BF differential clock input buffer will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as

common mode effects.

Moreover, a very low phase noise sinewave generator must be used for enhanced jitter perform ance.

The typical inphase clock input amplitude is 1 Volt peak to peak, centered on 0 Volt (ground) common mode.

This corresponds to a typical clock input power level of 4 dBm into the 50 ohms termination resistor.

Do not exceed 10 dBm to avoid saturation of the preamplifier i nput t ransi st ors.

The inverted phase clock i nput is grounded through t he 50 ohms terminat i on resistor.

Product Specification

TS8388BF

Single ended Clock input (Ground common mode)

VCLK common mode = 0 Volt

VCLKB=0 Volt

4 dBm typical clock input power level

(into 50 ohms terminati on resistor)

[V]

VCLK

VCLKB = ( 0 V )

-0.5V

+0.5V CLK or CLKB

50 Ω

(external)

50 Ω rev erse termi nat i on

1MΩ0.4 pF

CLK or CLKB double pad (pins 37, 38 or 39, 40)

Note 1 : Do not exceed 10 dBm into the 50 ohms termination resistor for single clock i nput pow er lev el.

7.4.2. DIFFERENTIAL ECL CLOCK INPUT

The clock inputs can be driven differenti al l y with nominal -0.8V / -1.8V ECL levels.

In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, fol lowed by a power splitter (hybrid j unction) in order

to obtain 180 degrees out of phase sinewave signals. Biasing tees can be used for offseti ng the common mode voltage to ECL levels.

Note : As the biasing tees propagation times are not matchi ng, a tunable delay line is required in order to ensure the signals t o be 180 degrees

out of phase especiall y at fast clock rates in the GSPS range.

Differential Clock inputs (ECL Levels)

-0.8V

[mV]

-1.8V

VCLKB

VCLK

Common mode = -1.3 V

CLK or CLKB

50 Ω reverse termination

1MΩ0.4 pF

-2V

50 Ω

(external)

CLK or CLKB double pad (pins 37, 38 or 39, 40)

7.4.3. SINGLE ENDED ECL CLOCK INPUT

In single–ended c onfiguration enter on CLK ( resp. CLKB ) pin , with the inverted phase Clock input pin CLKB (respectively CLK) connected to -

1.3V through the 50 ohms termination res istor.

The inphase input amplitude is 1 Volt peak to peak, centered on -1.3 Volt common mode.

Single ended Clock input (ECL):

VCLK common mode = -1.3 Volt.

VCLKB = -1.3 Volt

-0.8V

[V]

-1.8V

VCLK

VCLKB = -1.3 V

30 TS8388BF

Product Specification

7.5. NOISE IMMUNITY INFORMATIONS

Circuit nois e immunity performance begins at design level.

Efforts have been m ade on the design in order to make the device as insensitive as possible to chip environment perturbations resulting from

the circuit it self or induced by external c i rcuitry.

(Cascode st ages isol ation, in t ernal damping resi stors, clamps, internal (onchi p) decoupl i ng capaci tors.)

Furthermore, the fully diff erential operation from analog input up to the digital outputs provides enhanc ed nois e immunit y by common mode

noise rejection.

Common mode noise voltage induced on the differential analog and clock inputs will be canceled out by these balanced differential amplif i ers.

Moreover, proper active signals shielding has been provided on the chip to reduce the amount of coupled noise on the active inputs :

The analog inputs and clock inputs of the TS8388BF device have been surrounded by ground pins, which must be directl y connected to the

external ground plane.

7.6. DIGITAL OUTPUTS

The TS8388BF differential output buffers are internall y 75 ohms loaded. The 75 ohms resistors are connected to the digit al ground pins through

a -0.8v level shift di ode (see Figures 3,4, 5 on next page).

The TS8388BF output buffers are designed for driving 75 ohms (default) or 50 ohms properly terminated impedance lines or coaxial cabl es.

An 11 mA bias current flowing alternatel y i nto one of the 75 ohms resistors when switching ensures a 0. 825 V voltage drop across the resistor

(unterm i nated outputs).

The VPLUSD positive suppl y voltage al l ows the adjustment of the output comm on mode level from -1.2V (VPLUS D=0V for ECL output

compatibil ity) t o +1.2V (VPLUSD=2.4V for LVDS output compatibi l ity).

Therefore, the single ended output voltages vary approximately between -0.8V and -1. 625V, ( outputs unterm i nated ), around -1.2V common

mode voltage.

Three possible line driving and back-termination scenarios are proposed (assuming VPLUSD=0V) :

1 ) 75 Ohms impedance transmission lines, 75 ohms different i al l y termi nated (Fig. 3) :

Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading to +/- 0.41V =0.825 V in differential, around -1.21 V

(respect i vel y +1.21V) common mode for VPLUSD=0V (respectively 2.4V).

2 ) 50 ohms impedance transmission li nes, 50 ohms different i al l y termi nation (Fi g. 4) :

Each output voltage vari es between -1.02V and -1.35V (respectively +1.38V and +1.05V), leading to +/- 0.33V=660 mV in different i al, around -

1.18V (respectivel y +1. 21V) common mode for VPLUSD=0V (respect i vel y 2.4V ).

3 ) 75 ohms impedance open transmission lines (Fig. 5) :

Each output voltage vari es between -1.6 V and -0.8 V (respecti vel y +0. 8V and +1.6V), which are true ECL levels, l eadi ng to +/- 0.8V=1.6V in

different i al, around -1. 2V (respect i vel y +1. 2V) c ommon mode for VPLUSD=0V (respectively 2.4V).

Therefore, it is possibl e to drive di rect l y high input impedance st ori ng registers, without t e rminat i ng the 75 ohms transmiss i o n lines.

In time domain, that means that the incident wave will reflect at the 75 ohms transmission line output and travel back to the generator ( i.e. the

75 ohms data output buffer ). As the buffer output impedance is 75 ohms, no back reflecti on will occur.

Note : This is no longer true if a 50 ohms transmission line is used, as the latter is not matching the buffer 75 ohms output impedance.

Each differential output termi nation l ength must be kept identical .

It is recommended to decouple the midpoint of the different i al term i nation with a 10 nF capacitor to avoid common mode perturbation in case of

slight mismatc h i n the differenti a l output line lengths.

Too large mismatches ( keep < a few mm ) in the differential line lengths will lead to switching currents flowing into the decoupling capacitor

leading to switchi ng ground noise.

The differential output volt age l evels ( 75 or 50 ohms termination ) are not ECL standard voltage l evels, however it is possi b l e to dri ve standard

logic ECL circuitry like the ECLinPS logic line from MOTOROLA.

At sampling rates exceeding 800MSPS, i t may be difficul t t o trigger the HP16500 or any other Acquisition System with digital outputs.

It becomes necess ary to regenerate digital data and Data Ready by means of external amplifiers, in order to be able to test the TS8388BF at its

optimum performance conditions.

Product Specification

TS8388BF

7.6.1. DIFFE RENTI AL OUTPUT LOADING CONFIGURATIONS (LEVELS FOR ECL COMPATIBILITY)

11 mA

DVEE

VPLUSD = 0V

75 Ω75 Ω

75 Ω

impedance 10 nF

75 Ω

Out -1V / -1.41V

OutB -1.41V / -1V

Different ial output :

± 0.41V = 0.825V

Common mode level : -1.2V

(-1.2V below VPLUSD level)

Figure 3 : DIFFERENTIAL OUTPUT : 75 Ω TERMINATED

-0.8V

11 mA

DVEE

VPLUSD = 0V

75 Ω75 Ω

50 Ω

impedance 10 nF

50 Ω

Out -1.02V / -1.3 5V

OutB -1.35V / -1.02V

Different ial output :

± 0.33V = 0.660V

Common mode level : -1.2V

(-1.2V below VPLUSD level)

Figure 4 : DIFFERENTIAL OUTPUT : 50 Ω TERMINATED

-0.8V

11 mA

DVEE

VPLUSD = 0V

75 Ω75 Ω

75 Ω

impedance

Out -0.8V / -1.6 V

OutB -1.6V / -0.8V

Different ial output :

± 0.8V = 1.6V

Common mode level : -1.2V

(-1.2V below VPLUSD level)

Figure 5 : DIFFERENTIAL OUTPUT : OPEN LOADED

-0.8V

32 TS8388BF

Product Specification

7.6.1. DIFFE RENTI AL OUTPUT LOADING CONFIGURATIONS (LEVELS FOR LVDS COMPATIBILITY)

7.7. OUT OF RANGE BIT

An Out of Range (OR,ORB) bit is provided that goes to logical high state when the input exceeds the positive full scale or falls bel ow the

negative full sc al e.

When the analog input exceeds the positive ful l scal e, the digital output datas remai n at high logical st ate, with (OR,ORB) at logical one.

When the analog input falls below the negative full scal e, the digital outputs rem ai n at logic al low state, with (OR,ORB) at logic al one agai n.

11 mA

DVEE

VPLUSD = 2.4V

75 Ω75 Ω

75 Ω

impedance 10 nF

75 Ω

Out 1.4V / 0.99V

OutB 0.99V / 1.4V

Different i al out put :

± 0.41V = 0.825V

Common mode level : -1.2V

(-1.2V below VPLUSD level )

Figure 6 : DIFFERENTIAL OUTPUT : 75 Ω TERMINATED

1.6V

11 mA

DVEE

VPLUSD = 2.4V

75 Ω75 Ω

50 Ω

impedance 10 nF

50 Ω

Out 1.38V / 1.05V

OutB 1.05V / 1.38V

Different i al out put :

± 0.33V = 0.660V

Common mode level : -1.2V

(-1.2V below VPLUSD level )

Figure 7 : DIFFERENTIAL OUTPUT : 50 Ω TERMINATED

1.6V

11 mA

DVEE

VPLUSD = 2.4V

75 Ω75 Ω

75 Ω

impedance

Out 1.6V / 0.8V

OutB 0.8V / 1.6V

Different i al out put :

± 0.8V = 1.6V

Common mode level : -1.2V

(-1.2V below VPLUSD level )

Figure 8 : DIFFERENTIAL OUTPUT : OPEN LOADED

1.6V

Product Specification

TS8388BF

7.8. GRAY OR BINARY OUTPUT DATA FORMAT SELECT

The TS8388BF internal regeneration l atches indecis i on (for inputs very cl ose to latches threshold) may produce errors in the logic encoding

circuitry and l eadi ng to large ampli tude out put errors.

This is due to the fact that the latches are regenerating the internal analog resi dues i nt o logical states with a finite voltage gain value (Av) withi n

a given positive amount of time ∆(t ) :

Av= exp(∆(t)/τ) , with τ the positive feedback regeneration time constant.

The TS8388BF has been designed for reducing the probability of occurrenc e of such errors to approximately 10-13 (targeted for the TS8388BF

at 1GSPS).

A standard technique for reduc i ng the amplitude of such errors down to +/-1 LSB consists to output the digit al datas in Gray code format.

Though the TS8388BF has been designed for featuring a Bit Error Rate of 10-13 with a binary output form at, it is possibl e for t he user t o select

between the Binary or Gray output dat a format, in order to reduc e the amplitude of s uch errors when occu rri ng, by st ori ng Gray output codes.

Digital Da tas format sele c tio n :

BINARY output format if GORB is floating or VCC.

GRAY output format if GORB is connected to ground (0V).

7.9. DIODE PIN 49

One single pin is used for both DRRB input command and die junction monitori ng. The pin denomination is DRRB/ DIOD. Temperat ure

monitori ng and Data Ready c ontrol by DRRB is not poss i bl e simult aneously.

(See section 7.2 for Data Ready Res et input command).

The operating die junction temperature must be kept below145C, therefore an adequate cooling system has to be set up.

The diode mounted transistor measured Vbe value versus junction temperature is given below.

600

640

680

720

760

800

840

880

920

960

1000

-55 -35 -15 5 25 45 65 85 105 125

Junct i on temperature (deg.C)

VBE (mV)

34 TS8388BF

Product Specification

7.10. ADC GAIN CONTROL PIN 60

The ADC gain is adjustable by the means of the pin 60 (input impedance is 1MΩ in parallel with 2pF)

The gain adjust transfer function is gi ven bel ow :

For more information, please refer to the document "DEMUX and ADCs APPLICATION NOTES".

0,80

0,85

0,90

0,95

1,00

1,05

1,10

1,15

1,20

-500 -400 -300 -200 -100 0 100 200 300 400 500

Vgain (com m and voltage) (mV)

ADC Gain

Product Specification

TS8388BF

8. EQUIVALENT INPUT / OUTPUT SCHEMATICS

8.1. EQUIV ALENT ANALOG INPUT CIRCUIT AND ESD PROTECTIONS

8.2. EQUIV ALENT ANALOG CLOCK INPUT CIRCUIT AND ESD PROTECTIONS

GND=0V

VCC=+5V VCLAMP= +2.4V

+1.65V

-1.55V

VEE VEE

VCC

GND

VIN VINB

VEE=-5V

Pad

capacitance

340fF

Pad

capacitance

340fF

-0.8V

-5.8V

5.8V

0.8V

200 Ω200 Ω

50 Ω50 Ω

Note : the ESD protection equival ent capac itance is 150 fF.

E21VE21V

-0.8V

-5.8V

VCC=+5V +0.8V

GND=0V

VEE

VEE=-5V

CLK

VCC

VEE

CLKB

Pad

capacitance

340fF

Pad

capacitance

340fF

-5.8V

-5.8V -5.8V

-5.8V

5.8V5.8V

0.8V 0.8V

150 Ω150 Ω

380 µA 380 µA

Note : the ESD protection equival ent capac itance is 150 fF.

36 TS8388BF

Product Specification

8.3. EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS

8.4. ADC GAIN ADJUST EQUIVALENT INPUT CIRCUITS AND ESD PROTECTIONS

VPLUSD=0V to 2.4V

DVEE=-5V VEE=-5VVEE=-5V

VEE VEE

OUT OUTB

-5.8V -5.8V

5.8V 5.8V

0.8V

0.8V 0.8V

0.8V

I=11mA

75 Ω75 Ω

-3.7V

Pad

capacitance

180 fF

Pad

capacitance

180 fF

Note : the ESD protection equival ent capac itance is 150 fF.

VEE VEE=-5V

VCC=+5V

+1.6V

Pad

capacitance

180 fF

-0.8 V

-5.8 V

0.8V

5.8V

1 kΩ

2 pF

GND

500 µA500

NP1032C2

Note : the ESD protection equival ent capac itance is 150 fF.

+0.8 V

GND

Product Specification

TS8388BF

8.5. GORB EQUIV ALENT INPUT SCHEMATIC AND ESD PROTECTIONS

GORB: gray or binary select input; floating or tied to VCC -> binary

8.6. DRRB EQUIV ALENT INPUT SCHEMATIC AND ESD PROTECTIONS

VCC=+5V

VEE=-5V GND=0V

-0.8V

-5.8V

5.8V

5 kΩ

1 kΩ1 kΩ

1 kΩ

250

A 250

Pad

capacitance

180fF

GORB

VEE

Note : the ESD protection equival ent capac itance is 150 fF.

VEE=-5V

VEE

VCC=+5V

GND=0V

-1.3V

-2.6V

10 kΩ

200 Ω

DRRB

5.8 V

Pad

capacitance

180 fF

Actual protection range: 6.6V above VEE,

In fact stress above GND are clipped by

the CB diode used for Tj monitoring

0.8 V

NP1032C2

Note : the ESD protection equival ent capac itance is 150 fF.

VEE

38 TS8388BF

Product Specification

9. TSEV8388BF : DEVICE EVALUATION BOARD

For complete specification, see separate TSEV8388BF document.

GENERAL DESCRIPTION

The TSEV8388BF Evaluation Board (EB) is a board which has been designed in order to facilitate the evaluati on and the characteri zat i on of the

TS8388BF device up to its 1.5 GHz full power bandwidth at up to 1 Gsps in the military temperature range.

The high speed of the TS8388BF requires careful attention t o circ uit design and layout to achieve optimal performance.

This four metal layer board with internal ground pl ane has the adequate functi ons i n order to allow a quick and simple evaluati on of t he

TS8388BF ADC performances over the temperature range.

The TSEV8388BF Evaluation Board is very straightforward as it only impl em ents the TS8388BF ADC, SMA connectors for input / output

access es and a 2.54 mm pitch connector compati bl e with HP16500C high frequenc y probes.

The board also implements a de–embedding fixture in order to fac ili tate the evaluation of the high frequency insertion loss of the i nput mic rost ri p

lines, and a die junction temperature measurem ent s ett i ng.

The board is constituted by a sandwich of two dielectri c l ayers, featuring low insertion loss and enhanced thermal characteristics for operation in

the high frequency domai n and extended temperat ure range.

The board dimensions are 130 mm x 130 mm.

The board set comes fully assembled and tested, with the TS8388BF in CQFP68 package installed.

Product Specification

TS8388BF

10. ORDERING INFORMATION

10.1. PACKAGE DEVICE

10.2. EVALUATION BOARD

The evaluation board is delivered with an ADC and includes the heat sink.

Manufacturer prefix

Device or family

Temperature range :

Package :

M : -55 < Tc ; Tj < 125°C

V : -40 < Tc ; Tj < 110°C

C : 0 < Tc ; Tj < 90°CF : CQFP68 gullwing

TS 8388B M F B/Q

Screening level :

___ : standard

B/Q : Mil-PRF-38535, QML level Q

TS (X) EV 8388B F ZA2

ZA2 : w ith MC100EL16

digital recei vers

_: Without receivers

Prototype board

Evaluation board pref i x CQFP68 package

40 TS8388BF

Product Specification

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