SCG102A
Synchronous Clock
Generators
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630- 851-4722
Fax: 630- 851- 5040
www.conwin.com
Bulletin SG076
Page 1 of 8
Revision 00
Date 11 APR 07
Issued By ENG
Applications
•SONET / SDH / ATM
•DWDM / FDM
•DSL-PON Interconnects
•FEC (Forward Error Correction)
Features
•3.3V High Precision PLL
•Accepts 1 of 4 Selectable, Pre-determined Input Frequencies
•77.76 MHz to 170 MHz Output Frequencies Available.
•Jitter Generation OC-192 Compliant
•1.0” x 0.80” x 0.285”, Surface Mount
Data Sheet #: SG076 Page 2 of 8 Rev: 00 Date: 4/11/07
© Copyright 2007 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
The SCG102A provides high precision phase lock loop
frequency translation for the telecommunication applications.
The SCG102A product generates LVPECL outputs from an
intrinsically low jitter, voltage controlled crystal oscillator.
SCG102A is well suited for use in line cards, service
termination cards and similar functions to provide reliable
ref erence, phase lock ed, synchronization for TDM, PDH, SONET
and SDH network equipment . The SCG102A provides a jitter
filtered, wander f ollo wing output signal sychronized to a superior
Stratum or peer input reference signal.
The SCG102A includes a lock detect alarm output. The PLL
control voltage is brought out through a 470 kΩ restistor and can
be used to determine when the pull range limits are reached.The
Functional Block Diagram
Figure 1
Frequency
Divider Loop
Filter PECL
VCXO
Frequency
Divider
OUT
(Pin 9)
COut
(Pin 10)
CLKIN
(Pin 1)
Select A
(Pin 12)
Select B
(Pin 13)
LD
(Pin 3)
Enable/Disable
(Pin 8)
Monitor
(Pin 4)
Microprocessor
470 kΩ
10 kΩ
10 kΩ
LVPECL outputs may be put into the tri-state high impedance
condition for external testing purposes by asserting a high signal
to the Enable/Disable pin.
The SCG102A is a 3.3 Volt component that will typically dr a w
75mA. The SCG102A is designed to be used in applications that
require temperature rating of -40°C - 85° C. The SCG102A
package typical dimensions are 1.0” x 0.80” x 0.285” (See fig. 2
for maximum dimensions). Parts are assembled using high
temperature solder to withstand surface mount reflow process.
The SCG102A locks to an y one of four pred-determined input
frequencies selected using the SELECT (A&B) lines (See Table
4). The output may be any single frequency from 77.76 MHz to
170 MHZ.
Absolute Maximum Rating
Table 1
Symbol Parameter Minimum Nominal Maximum Units Notes
Vcc Power Supply Voltage -0.3 5.5 Volts
VIInput Voltage -0.3 Vcc Volts
Ts Storage Temperature -55 125 °C
General Description
Data Sheet #: SG076 Page 3 of 8 Rev: 00 Date: 4/11/07
© Copyright 2007 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Specifications
Table 2
Symbol Parameter Minimum Nominal Maximum Units Notes
fIN Available Input Frequencies CMOS 8 k 100 M Hz
PECL 1 M 100 M Hz
fOUT Output Frequencies(LVPECL) 77.76 M 170 M Hz
Vcc Supply Voltage 3.135 3.3 3.465 Volts
ICC Supply Current 75 100 mA
CLKIN Input Logic A = CMOS CMOS 1
D = PECL PECL
CLKOUT Output Logic F = Comp. PECL PECL
VOH 2.275 V
VOL 1.68 V
TR/TFRise/Fall Time 0.5 1 ns
SYM Output Symmetry 45 55 %
BW Bandwidth 20 Hz
JGEN Jitter Generation RMS 0.5 1 ps
(12 kHz - 20 MHz)
JTRAN Jitter Tr ansfer 0.1 dB 2
APR Input Frequency Tracking ±50 ppm
TOP Operating Temperature F = -40 85 °C
C =0 70 °C
NOTES: 1.0: Only HCMOS and LVHCMOS is suppor ted for input frequencies < 1MHz
2.0: GR-253-CORE, Sec. 5.6.2.1.2
Pin Description
Table 3
Pin # Connection Description
1 CLKIN Input Frequency - The SCG102A AC couples the input , this means that the unit is
capable of handling HCMOS, LVCMOS, PECL, LVPECL input signals.
2 GND Ground
3 Lock Detector Logic “1” indicates that the unit is locked to the input reference
Logic “0” indicates that the reference is lost or out of lock range
4 VCXO Monitor Control voltage level for the PECL oscillator (Between 0.3V and 3.0V when locked)
5 ---- Missing
6 NC No connection
7 GND Ground
8 Enable/Disable Logic “0” (or no connect) = Output Enabled
Logic “1” = Output Disabled (Tri-Stated)
9 Out Output
10 COut Complementar y Output
11 NC No connection
12 Select A Input Frequency Select Control Pin. See Table 4.
13 Select B Input Frequency Select Control Pin. See Table 4.
14 NC No connection
15 GND Ground
16 VCC Power supply voltage (3.3 Vdc ± 5%)
Data Sheet #: SG076 Page 4 of 8 Rev: 00 Date: 4/11/07
© Copyright 2007 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Input Frequency Selection
Table 4
Output Load and Power Supply Filtering Recommendations
Figure 2
50Ω50Ω
V
T
-2 V
DC
(F
OUT
)
****
It is highly recommended
that either a linear regulator
or bypass capacitors be
used. Typical values would
be 10 uF, 0.1 uF, 100 pF.
Frequency
Divider Loop
Filter PECL
VCXO
Frequency
Divider
OUT
(Pin 9)
COut
(Pin 10)
CLKIN
(Pin 1)
Select A
(Pin 12)
Select B
(Pin 13)
LD
(Pin 3)
Enable/Disable
(Pin 8)
Monitor
(Pin 4)
Microprocessor
470 kΩ
10 kΩ
10 kΩ
Input Freq SEL A SEL B
f100
f201
f310
f411
Data Sheet #: SG076 Page 5 of 8 Rev: 00 Date: 4/11/07
© Copyright 2007 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Ordering Information
Table 5
10 MHz A
10 kHz B
8 kHz C
16 kHz D
64 kHz E
1.024 MHz F
1.048 MHz G
1.544 MHz H
2.048 MHz J
4.096 MHz K
8.192 MHz L
13.00 MHz M
16.384 MHz N
19.44 MHz P
20.48 MHz R
26.00 MHz T
27.00 MHz W
38.88 MHz X
44.736 MHz Y
53.10468 MHz Z
51.84 MHz 0
61.44 MHz 1
77.76 MHz 2
82.944 MHz 3
112.00 MHz 4
139.264 MHz 5
155.52 MHz 6
166.6286 MHz 7
114.0 MHz 8
125.0 MHz 9
SCG102A- D F F - A 1 P 6
Supply Voltage
D = 3.3 VDC ± 5%
Output Type
F = Comp. PECL
Temperature Range
C = 0°C to 70°C
F = -40°C to 85°C
Output Frequency (2 to 9)
See char t above. If a custom frequency
is desired, enter S followed by the
frequency. Contact a sales
representative for the availabilty of
custom frequencies.
Input Frequency (A to 9)
See char t above.
If more than one frequency is desired,
enter S and list all desired frequencies.
Contact a sales representative for the
availabilty of custom frequencies.
Number of Input Frequencies
1 = 1 Input Frequency
2 = 2 Input Frequencies
3 = 3 Input Frequencies
4 = 4 Input Frequencies
Input Logic
A = CMOS
D = PECL
Sample Part Number Examples:
SCG-102A- DFF-A1C2
SCG-102A- DFF-A4S2, S = 8 kHz, 16.384 MHz, 19.44 MHz, 38.88 MHz
SCG-102A-DFF-D1ZS, S = Custom Frequency
For any model, the reference inputs and output frequency must have a common frequency of 2.667Hz (8kHz/3)
Ex 1: A Model with reference inputs of 8kHz, 16kHz, 32kHz and 64kHz with a Output frequency of 155.52MHz is valid due to the
common frequency of 2.667kHz. Contact CW regarding models that do not have a input/output common frequency of 2.667kHz.
Data Sheet #: SG076 Page 6 of 8 Rev: 00 Date: 4/11/07
© Copyright 2007 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Package Dimensions
Figure 3
.800
[
20.32mm
]
1.000 [25.40mm]
.740 [18.80mm]
.100 [2.54mm]
PIN 1
.285 [7.24mm]
MAX.
Recommended Footprint Dimensions
Figure 4
Solder Profile
Figure 5
0
50
100
150
200
250
300
0 50 100 150 200 250 300 350
Time (sec)
Temp (°C)
221°C
Reflow Zone
30/90 sec
(Min/Max)
Peak Temp.
245°-255°C for 15 sec Typ.
Soaking Zone
60-90 sec Typ.
(2 min Max)
Ramp Slope not
to exceed
±3°C/sec
Data Sheet #: SG076 Page 7 of 8 Rev: 00 Date: 4/11/07
© Copyright 2007 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630- 851- 4722
Fax: 630- 851- 5040
www.conwin.com
Revision Revision Date Note
00 4/11/07 Final Release
