This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev 13 / Apr. 2001 Hynix Semiconductor
HY62V8100B Series
128Kx8bit CMOS SRAM
Document Title
128K x8 bit 3.3V Low Power CMOS slow SRAM
Revision History
Revision No History Draft Date Remark
10 Initial Revision History Insert Jul.14.2000 Final
11 Change the Notch Location of sTSOP Sep.04.2000 Final
- Left-Top => Left-Center
12 Marking Information Add Dec.04.2000 Final
Revised
- AC Test Condition Add : 5pF Test Load
13 Changed Logo Apr.30.2001 Final
- HYUNDAI -> hynix
- Marking Information Change
HY62V8100B Series
Rev 13 / Apr. 2001
2
DESCRIPTION
The HY62V8100B is a high speed, low power and
1M bit CMOS SRAM organized as 131,072 words
by 8bit. The HY62V8100B uses high performance
CMOS process technology and designed for high
speed low power circuit technology. It is
particulary well suited for used in high density low
power system application. This device has a data
retention mode that guarantees data to remain
valid at a minimum power supply voltage of 2.0V.
FEATURES
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Battery backup(LL-part)
-. 2.0V(min) data retention
• Standard pin configuration
-. 32 SOP - 525mil
-. 32 TSOP-I - 8X20(Standard and Reversed)
-. 32 sTSOP-I - 8X13.4
(Standard and Reversed)
Product Voltage
Speed Operation Standby Current(uA)
Temperature
No. (V) (ns) Current/Icc(mA)
LL (°C)
HY62V8100B 3.0~3.6
70/85/100 5 10 0~70
HY62V8100B-E
3.0~3.6
70/85/100 5 15 -25~85(E)
HY62V8100B-I 3.0~3.6
70/85/100 5 15 -40~85(I)
Note 1. Blank : Commercial, E : Extended, I : Industrial
2. Current value is max.
PIN CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
/WE
A13
A8
A9
A11
/OE
A10
/CS1
I/O8
I/O7
I/O6
I/O5
I/O4
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
CS2
SOP TSOP-I sTSOP-I
(Standard) (Standard)
PIN DESCRIPTION BLOCK DIAGRAM
Pin Name Pin Function
/CS1 Chip Select 1
CS2 Chip Select 2
/WE Write Enable
/OE Output Enable
A0 ~ A16 Address Inputs
I/O1 ~ I/O8 Data Inputs / Outputs
Vcc Power(3.0V~3.6V)
Vss Ground
MEMORY ARRAY
128K x 8
ROW
DECODER
WRITE DRIVER
DATA I/O
BUFFER
I/O1
I/O8
COLUMN
DECODER
ADD INPUT
BUFFER
A0
A16
COLUMN
DECODER
/CS1
CS2
/OE
/WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A1
A2
A3
A11
A9
A8
A13
/WE
CS2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
/CS1
A11
A9
A8
A13
/WE
CS2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
/
OE
A10
/CS1
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
HY62V8100B Series
Rev 13 / Apr. 2001
2
ORDERING INFORMATION
Part No. Speed Power
Temp.
Package
HY62V8100BLLG 70/85/100 LL-part SOP
HY62V8100BLLT1 70/85/100 LL-part TSOP-I(Standard)
HY62V8100BLLR1 70/85/100 LL-part TSOP-I(Reversed)
HY62V8100BLLST 70/85/100 LL-part smaller TSOP-I(Standard)
HY62V8100BLLSR 70/85/100 LL-part smaller TSOP-I(Reversed)
HY62V8100BLLG-E 70/85/100 LL-part E SOP
HY62V8100BLLT1-E 70/85/100 LL-part E TSOP-I(Standard)
HY62V8100BLLR1-E 70/85/100 LL-part E TSOP-I(Reversed)
HY62V8100BLLST-E 70/85/100 LL-part E smaller TSOP-I(Standard)
HY62V8100BLLSR-E 70/85/100 LL-part E smaller TSOP-I(Reversed)
HY62V8100BLLG-I 70/85/100 LL-part I SOP
HY62V8100BLLT1-I 70/85/100 LL-part I TSOP-I(Standard)
HY62V8100BLLR1-I 70/85/100 LL-part I TSOP-I(Reversed)
HY62V8100BLLST-I 70/85/100 LL-part I smaller TSOP-I(Standard)
HY62V8100BLLSR-I 70/85/100 LL-part I smaller TSOP-I(Reversed)
Note 1. Blank : Commercial, E : Extended, I : Industrial
ABSOLUTE MAXIMUM RATING (1)
Symbol Parameter Rating Unit Remark
Vcc, VIN, VOUT
Power Supply, Input/Output Voltage -0.3 to 4.6 V
TA Operating Temperature 0 to 70 °C HY62V8100B
-25 to 85 °C HY62V8100B-E
-40 to 85 °C HY62V8100B-I
TSTG Storage Temperature -65 to 125 °C
PD Power Dissipation 1.0 W
IOUT Data Output Current 50 mA
TSOLDER Lead Soldering Temperature & Time 260 • 10 °C•sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1
CS2
/WE
/OE
Mode I/O Power
H X X X Deselected High-Z Standby
X L X X Deselected High-Z Standby
L H H H Output Disabled High-Z Active
L H H L Read Data Out Active
L H L X Write Data In Active
Note :
1. H=VIH, L=VIL, X=don't care( VIH or VIL )
HY62V8100B Series
Rev 13 / Apr. 2001
3
RECOMMENDED DC OPERATING CONDITION
Symbol Parameter Min. Typ. Max. Unit
Vcc Supply Voltage 3.0 3.3 3.6 V
Vss Ground 0 0 0 V
VIH Input High Voltage 2.2 - Vcc+0.3
V
VIL Input Low Voltage -0.3(1) - 0.6 V
Note :
1. VIL = -1.5V for pulse width less than 30ns and not 100% tested
DC ELECTRICAL CHARACTERISTICS
Vcc = 3.0V~3.6V, TA = 0°C to 70°C / -25°C to 85°C (E) / -40¡É to 85¡É(I), unless otherwise specified
Symbol
Parameter Test Condition Min.
Typ.
Max.
Unit
ILI Input Leakage Current Vss < VIN < Vcc -1 - 1 uA
ILO Output Leakage Current Vss <VOUT < Vcc,
/CS1 = VIH or CS2 = VIL
or /OE = VIH or /WE = VIL
-1 - 1 uA
Icc Operating Power Supply
Current /CS1 = VIL, CS2 = VIH,
VIN = VIH or VIL, II/O = 0mA - 5 mA
ICC1 Average Operating Current /CS1 = VIL, CS2 = VIH,
VIN = VIH or VIL
Cycle Time = Min, 100% duty,
IIO = 0mA
- 35 mA
ISB TTL Standby Current
(TTL Input) /CS1 = VIH or CS2 = VIL ,
VIN = VIH or VIL - - 0.5 mA
ISB1 Standby HY62V8100B /CS1 > Vcc - 0.2V or CS2 < 0.2V,
- 0.5 10 uA
Current HY62V8100B-E
VIN > Vcc - 0.2V or - 0.5 15 uA
(CMOS Input) HY62V8100B-I VIN < Vss + 0.2V - 0.5 15 uA
VOL Output Low Voltage IOL = 2.1mA - - 0.4 V
VOH Output High Voltage IOH = -1mA 2.2 - - V
Note : Typical values are at Vcc = 3.3V, TA = 25°C
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol Parameter Condition
Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VI/O = 0V 8 pF
Note : These parameters are sampled and not 100% tested
HY62V8100B Series
Rev 13 / Apr. 2001
4
AC CHARACTERISTICS
Vcc = 3.0V~3.6V, TA = 0°C to 70°C / -25°C to 85°C (E) / -25¡É to 85¡É(I), unless otherwise specified
-70 -85 -10
Min. Max.
Min. Max.
Min Max.
1 tRC Read Cycle Time 70 - 85 - 100 - ns
2 tAA Address Access Time - 70 - 85 - 100 ns
3 tACS Chip Select Access Time - 70 - 85 - 100 ns
4 tOE Output Enable to Output Valid - 40 - 45 - 50 ns
5 tCLZ Chip Select to Output in Low Z 10 - 10 - 10 - ns
6 tOLZ Output Enable to Output in Low Z 5 - 5 - 5 - ns
7 tCHZ Chip Deselection to Output in High Z 0 30 0 30 0 30 ns
8 tOHZ Out Disable to Output in High Z 0 30 0 30 0 30 ns
9 tOH Output Hold from Address Change 10 - 10 - 15 - ns
10
tWC Write Cycle Time 70 - 85 - 100 - ns
11
tCW Chip Selection to End of Write 60 - 70 - 80 - ns
12
tAW Address Valid to End of Write 60 - 70 - 80 - ns
13
tAS Address Set-up Time 0 - 0 - 0 - ns
14
tWP Write Pulse Width 50 - 55 - 75 - ns
15
tWR Write Recovery Time 0 - 0 - 0 - ns
16
tWHZ Write to Output in High Z 0 25 0 30 0 35 ns
17
tDW Data to Write Time Overlap 30 - 40 - 45 - ns
18
tDH Data Hold from Write Time 0 - 0 - 0 - ns
19
tOW Output Active from End of Write 5 - 5 - 10 - ns
AC TEST CONDITIONS
TA = 0°C to 70°C / -25°C to 85°C (E) / -25¡É to 85¡É(I), unless otherwise specified
Parameter Value
Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Time 5ns
Input and Output Timing Reference Level 1.5V
Output Load tCLZ,tOLZ,tCHZ,tOHZ,tWHZ CL = 5pF + 1TTL Load
Others CL = 100pF + 1TTL Load
AC TEST LOADS
CL(1)
TTL
Note : 1 Including jig and scope capacitance
READ CYCLE
WRITE CYCLE
Symbol
Parameter
#
Unit
HY62V8100B Series
Rev 13 / Apr. 2001
5
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
READ CYCLE 2(Note 1,2,4)
tRC
tAA
Data ValidPrevious Data
tOH tOH
ADDR
Data
Out
READ CYCLE 3(Note 1,2,4)
/CS1
tACS
Data Valid
tCLZ(3)
tCHZ
(3)
Data
Out
CS2
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS1 and a high CS2.
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active
Data Valid
High-Z
ADDR
Data
Out
tRC
/CS1
CS2
/OE
tAA
tACS
tOE
tCLZ(3)
tOLZ(3)
tOH
tCHZ(3)
tOHZ(3)
HY62V8100B Series
Rev 13 / Apr. 2001
6
WRITE CYCLE 1(1,4,5,8) (/WE Controlled)
WRITE CYCLE 2 (Note 1,4,5,8) (/CS1, CS2 Controlled)
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1 and a high CS2.
2. tWR is measured from the earlier of /CS1 or /WE going high or CS2 going low to the end of
write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the the /CS1 low transition and CS2 high transition occur simultaneously with the /WE low transition
or after the /WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active
Data Valid
ADDR
Data
Out
/CS1
CS2
/
WE
tWC
tCW
tWR
(2)
tAW
tWP
Data In
High-Z
tAS
tWHZ
(3,7)
tDW tDH
tOW
(5)
(6)
Data Valid
ADDR
Data
Out
/CS1
CS2
/WE
tWC
tCWtWR(2)
tAW
tWP
Data In
tDWtDH
High-Z
High-Z
tAS
HY62V8100B Series
Rev 13 / Apr. 2001
7
DATA RETENTION ELECTRIC CHARACTERISTIC
TA=0°C to 70°C / -25°C to 85°C (E) / -25¡É to 85¡É(I)
Sym Parameter Test Condition Min Typ
Max
Unit
VDR Vcc for Data Retention /CS1>Vcc-0.2V or CS2<0.2V,
VIN > Vcc-0.2V or VIN < Vss+0.2V 2.0 - - V
ICCDR Data HY62V8100B Vcc=3.0V, - 0.5 10 uA
Retention HY62V8100B-E
/CS1>Vcc - 0.2V or CS2<0.2V, - 0.5 15 uA
Current HY62V8100B-I VIN > Vcc-0.2V or VIN > Vss+0.2V - 0.5 15 uA
tCDR Chip Deselect to Data
Retention Time See Data Retention Timing
Diagram 0 - - ns
tR Operating Recovery Time tRC(2)
- - ns
Notes:
1. Typical values are under the condition of TA = 25°C.
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM 1
CS1
VDR
CS1>VCC-0.2V
tCDR tR
VSS
VCC
3.0V
2.2V
DATA RETENTION MODE
DATA RETENTION TIMING DIAGRAM 2
0.4V
VDR
tCDR tR
VSS
VCC
CS2
3.0V
DATA RETENTION MODE
CS2<0.2V
HY62V8100B Series
Rev 13 / Apr. 2001
8
PACKAGE INFORMATION
32pin 525mil Small Outline Package(G)
UNIT : INCH(mm)
0.444(11.278)
0.438(11.125)
0.564(14.326)
0.546(13.868)
0.810(20.574)
0.804(20.422)
0.109(2.769)
0.099(2.515)
0.011(0.279)
0.004(0.102)
0.020(0.508)
0.014(0.356)
0.050(1.27)BSC
0.0125(0.318)
0.0061(0.155)
0.0425(1.080)
0.0235(0.597)
0 deg
8 deg
HY62V8100B Series
Rev 13 / Apr. 2001
9
32pin 8x20mm Thin Small Outline Package Standard(T1)
UNIT : INCH(mm)
0.319(8.103)
0.311(7.900)
0.728(18.491)
0.720(18.288)
0.792(20.117)
0.784(19.914)
0.025(0.64)
0.021(0.54)
0.008(0.21)
0.004(0.10) 0.020(0.50)
BSC 0.011(0.27)
0.041(1.05)
0.037(0.95)
0.006(0.15)
0.002(0.05)
#1
#32
#16
#17
0.007(0.17)
32pin 8x20mm Thin Small Outline Package Reversed(R1)
UNIT : INCH(mm)
0.319(8.103)
0.311(7.900)
0.728(18.491)
0.720(18.288)
0.792(20.117)
0.784(19.914)
0.025(0.64)
0.021(0.54)
0.008(0.21)
0.004(0.1) 0.020(0.50)
BSC 0.007(0.17)
0.041(1.05)
0.037(0.95)
0.006(0.15)
0.002(0.05)
#16
#17
#1
#32
0.011(0.27)
HY62V8100B Series
Rev 13 / Apr. 2001
10
32pin 8x13.4mm Samller Thin Small Outline Package Standard(ST)
UNIT : INCH(mm)
0.319(8.1)
0.311(7.9)
0.468(11.9)
0.460(11.7)
0.536(13.6)
0.520(13.2)
0.024(0.6)
0.016(0.4)
0.008(0.2)
0.004(0.1) 0.020(0.50)
0.007(0.17)
0.041(1.05)
0.037(0.95)
0.008(0.20)
0.002(0.05)
#1
#32
#16
#17
0.011(0.27)
32pin 8x13.4mm Smaller Thin Small Outline Package Reversed(SR)
UNIT : INCH(mm)
0.319(8.1)
0.311(7.9)
0.468(11.9)
0.460(11.7)
0.536(13.6)
0.520(13.2)
0.024(0.6)
0.016(0.4)
0.008(0.2)
0.004(0.1) 0.020(0.50)
0.007(0.17)
0.041(1.05)
0.037(0.95)
0.008(0.20)
0.002(0.05)
#16
#17
#1
#32
0.011(0.27)
HY62V8100B Series
Rev 13 / Apr. 2001
11
MARKING INFORMATION
hynixKORE A
HY6 2 V8100B
y y w w pc c G-sst
SOP
hynixKORE A
HY6 2 V8100B
y y w w pc c T1-sst
TSOP-I
Package Marking Example
Index
•hynix :hynix Logo
•KOREA / KOR : Origin Country
•HY62V8100B : Part Name
•yy : Year ( ex : 00 = year 2000, 01 = year 2001 )
•ww : Work Week ( ex : 12 = ww12 )
•p: Process Code
•cc : Power Consumption
-L: Low Power
-LL : Low Low Power
•G / T1 / ST : Package Type
-G: SOP
-T1 : TSOP-I
-ST : sTSOP
•ss : Speed -70 : 70ns
-85 : 85ns
•t: Temperature
-Blank : Commercial ( 0 ~ 70 °C)
-E: Extended ( -25 ~ 85 °C)
-I: Industrial ( -40 ~ 85 °C)
Note
-Capital Letter : Fixed Item
-Small Letter : Non-fixed Item (Except hynix)
HY6 2 V8100B
c c ST-s s t
y y w w pKOR
sTSOP
hynixKORE AhynixKORE A
HY6 2 V8100BHY6 2 V8100B
y y w w pc c G-sst y y w w pc c G-sst
SOP
hynixKORE A
HY6 2 V8100B
y y w w pc c T1-sst
TSOP-I
hynixKORE AhynixKORE A
HY6 2 V8100BHY6 2 V8100B
y y w w pc c T1-sst y y w w pc c T1-sst
TSOP-I
Package Marking Example
Index
•hynix :hynix Logo
•KOREA / KOR : Origin Country
•HY62V8100B : Part Name
•yy : Year ( ex : 00 = year 2000, 01 = year 2001 )
•ww : Work Week ( ex : 12 = ww12 )
•p: Process Code
•cc : Power Consumption
-L: Low Power
-LL : Low Low Power
•G / T1 / ST : Package Type
-G: SOP
-T1 : TSOP-I
-ST : sTSOP
•ss : Speed -70 : 70ns
-85 : 85ns
•t: Temperature
-Blank : Commercial ( 0 ~ 70 °C)
-E: Extended ( -25 ~ 85 °C)
-I: Industrial ( -40 ~ 85 °C)
Note
-Capital Letter : Fixed Item
-Small Letter : Non-fixed Item (Except hynix)
HY6 2 V8100B
c c ST-s s t
y y w w pKOR
HY6 2 V8100B
c c ST-s s t
y y w w pKOR
sTSOP