AUSTIN SEMICONDUCTOR, INC. AS5C4009LL 883 512K x 8 SRAM SRAM 912K x 8 SRAM LOW POWER, EVOLUTIONARY PINOUT AVAILABLE AS MILITARY SPECIFICATION * SMD 5962-95613 Pending * MILSTD-883 FEATURES * Ultra Low Power with 2V Data Retention * Fully Static, No Clocks Single +5V +10% power supply * Easy memory expansion with CE\ and OE\ options * All inputs and outputs are TTL-compatible OPTIONS MARKING Timing 55ns access -55 70ns access -70 85ns access -85 100ns access -100 Packages Ceramic Dip (600 mil) CW No. 112 Ceramic SOJ ECJ No. 502 NOTE: Not all combinations of operating temperature, speed, data retention and low power are necessarily available. Please contact the factory for availability of specific part number combinations. GENERAL DESCRIPTION The AS5C4009LL is organized as 524,288 x 8 SRAM utilizing a special low power design process. ASIs pinout adheres to the JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32 pin version allows for easy upgrades from the 1 meg SRAM design. For flexibility in high-speed memory applications, ASI offers chip enable (CE\) and output enable (OE\) capabilities. These features can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW. The device offers a reduced power standby mode PIN ASSIGNMENT (Top View) 32-Pin DIP 32-Pin SOJ ais L i }32 vec ais aL i} si als a4 3 i }30 a7 ae 4 [ i}e9 WEN ay OL i}es ais ae 6 L i]e7 as AS 7 | (|e6 Ag a4 8 [ ;}2e5 All As 9 [ Fle4 UES Ae 10 [ ;|2e3 Alo Alou | |@2 CEN ao lef || al 1/07 oo 13 | | |20 1/06 ol 14 | (| 19 1/05 oe 15 [ (| 18 1/04 VSS 16 | (| 17 1/03 when disabled, by lowering VCC to 2V and maintaining CE\=2V. This allows system designers to meet low standby power requirements. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL-compatible. AS5C4009LL REV.998 DS000017 Austin Semiconductor, Inc., reserves the rightto change products or specifications without notice.) AUSTIN SEMICONDUCTOR, INC. AS5C4009LL 883 512K x 8 SRAM ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss VOC ceesessrcressssrcecsesensncsesencsssssensnsssseneessssenessssseneessseenes -.5V to +7.0V Storage Temperature ...........ccsesesessescsereeenenees -55C to +150C Short Circuit Output Current (per I/O).......... cee 20mA Voltage on any Pin Relative to VS8...........::00+ -5V to Vect1 V Junction Temperature** 0... ceecssessesseenseeseesenes +150C *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional opera- tion of the device at these or any other conditions above those indicated in the operation section of this specifica- tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-BBC < TA < 125C; Vec = 5V 410%) DESCRIPTION CONDITIONS SYMBOL| MIN MAX UNITS | NOTES Input High (Logic 1) Voltage Vin 2.2 Voct-5 Vv 1 Input Low (Logic 0) Voltage ViL -0.5 0.8 Vv 1,2 Input Leakage Current OV <Vin< Voc ly 5 5 LA Output Leakage Current Output(s) disabled lLo 5 5 LA OV < Vout Voc Output High Voltage lon = -1.0MA Von 2.4 V 1 Output Low Voltage lop = 2.1MA VoL 0.4 V 1 Supply Voltage Voc 4.5 5.5 Vv 1 MAX DESCRIPTION CONDITIONS SYMBOL -55 -70 -85 -100 | UNITS |NOTES Power Supply CE\ < Vii; Voc = MAX Current: Operating f = MAX = 1/'RC loo 100 | so | 7o | 60 | mA 3 outputs open Power Supply CE\ > Vin; Voc = MAX Current: Standby f = MAX = 1/'RC lsat 10 | 10 | 10 | 10 | mA outputs open CE\ > Vog -0.2V; Veg = MAX Vin< Vsg +0.2V or Isao 1 1 1 1 mA Vin 2 Voc -0.2V; f= 0 CAPACITANCE DESCRIPTION CONDITIONS | SYMBOL| MAX UNITS | NOTES Output Capacitance |T, = 25C; 1 = MHz C, 8 pF 4 Input Capacitance Veco = 5V Co 10 pF 4 AS5C4009LL REV.998 DS000017 Austin Semiconductor, Inc., reserves the rightto change products or specifications without notice.AUSTIN SEMICONDUCTOR, INC. AS5C4009LL 883 512K x 8 SRAM ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes 5) (-55C <T , < 125C: Vog = BV 10%) DESCRIPTION SYM MIN T MAX MIN 1 MAX MIN MAX TaN MAK UNITS} NOTES READ Cycle READ cycle Time RC 55 70 85 100 ns Address access time "AA 55 70 85 100 ns Chip Enable access time ' ACE 55 70 85 100 ns Output hold from address change ' OH 10 10 10 10 ns Chip Enable to output in Low-Z ' LZCE 10 10 10 10 ns 4,6,7 Chip disable to output in High-Z ' HZCE 20 25 30 30 ns 4,6,7 Chip Enable to power-up time ' PU 0 0 0 0 ns 4 Chip disable to power-down time pp 55 70 85 100 ns 4 Output Enable access time AOE 30 35 40 45 ns Output Enable to output in Low-Z ' LZOE 5 5 5 5 ns 4,6,7 Output disable to output in High-Z ' HZOE 20 25 30 30 ns 4,6,7 WRITE Cycle WRITE cycle time we 55 70 85 100 ns Chip Enable to end of write ' CW 50 60 70 80 ns Address valid to end of write ' AW 50 60 70 80 ns Address setup time ' AS 0 0 0 0 ns Address hold from end of write ' AH 0 0 0 0 ns WRITE pulse width (OE\ HIGH) wet 45 50 55 60 ns WRITE pulse width (OE\ LOW) wee 45 50 55 60 ns Data setup time ps | 30 30 35 40 ns Data hold time DH 0 0 0 0 ns Write disable to output in Low-Z LZWE 5 5 5 5 ns 4,6,7 Write Enable to output in High-Z ' HZWE 25 25 30 30 ns 4,6,7 KSECA00SLL 3 Austin Semiconductor, Inc., reserves the rightto change products or specifications without notice. REV.998 DS000017AUSTIN SEMICONDUCTOR, INC. AS5C4009LL 883 512K x 8 SRAM AC TEST CONDITIONS Input pulse levels Input rise and fall times Output reference levels Input timing reference levels Vss to 3.0V 3ns 1.5V Output load oo... ee See Figures 1 and 2 Q 167 ohms Q 167 ohms T 1.73V T 1.73V | C=30pF | C=5pF Fig. 1 Output Load Equivalent Fig. 2 Output Load Equivalent NOTES . 1. All voltages referenced to V,. (GND). 8. WE\is HIGH for READ cycle. 2. -2V for pulse width < 20ns 9. Device is continuously selected. Chip enables and 3. 1, is dependent on output loading and cycle rates. output enables are held in their active state. 4. This parameter is guaranteed but not tested. 10. Address valid prior to, or coincident with, latest 5. Test conditions as specified with the output loading oceurnng chip enable. as shown in Fig. 1 unless otherwise noted. 11. RC=Read Cycle Time. a. 6. LZCE. 'LZWE. 'LZOE. 'HZCE. 'HZOE and UZWE 12. Chip enable and write enable can initiate and are specified with CL = 5pF as in Fig. 2. Transition is terminatea WRITE cycle. _ measured +200mV from steady state voltage. 13. Output enable (OE\) is inactive (HIGH). 7. At any given temperature and voltage condition, 14. Output enable (OE\)isactive(LOW). HZCE is less than'LZCE. and HZWE is less than 15. ASI does not warrant functionality nor reliability of LZWE. any product in which the junction temperature exceeds 150C. Care should be taken to limit power to acceptable levels. DATA RETENTION ELECTRICAL CHARACTERISTICS (L version only) DESCRIPTION CONDITIONS SYMBOL | MIN | MAX | UNITS | NOTES VCC for Retention Data Vor 2 V Data Retention Current CE 2 (Vee -0.2V) | VCC =2V | scpr 200 HA L version VIN > (VCC -0.2V) | VCC = 3V lecpa 400 pA Chip Deselect to Data cDR ) ns 4 Retention Time Operation Recovery tR tRc ns 4,11 Time eva 4 Austin Semiconductor, Inc., reserves the rightto change products or specifications without notice. DS000017AUSTIN SEMICONDUCTOR, INC. AS5C4009LL 883 512K x 8 SRAM LOW V_,,, DATA RETENTION WAVEFORM a VDR Vec 45V 4vV pte mi VDR CE\ | -VIH \ \ -VIL READ CYCLE NO. 1 ? (Write Enabled Controlled) i tRC ADDRESS | 4 VALID + tAA 10H>| \ DQ | PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 2 7:! (Write Enabled Controlled) RC >| CE\ \ tAQE (tHZOE tL ZOE j* OE\ \ +tLZCE> +#_tAC > tHZCE DQ ( DATA VALID +_1PU> <1PD> Icc \ KSECA00SLL 5 Austin Semiconductor, Inc., reserves the rightto change products or specifications without notice. REV.998 8000017AUSTIN SEMICONDUCTOR, INC. AS5C4009LL 883 512K x 8 SRAM WRITE CYCLE NO. | (Chip Enabled Controlled) < twc >| ADDRESS | a AH: +tAS tCW>] CEA wR we [Sa D DATA VAILD HIGH Z WRITE CYCLE NO. 2 2 (Write Enabled Controlled) . {we | ADDRESS | i < tAW: | AH < 1CW > CE\ \ >tAS < {WPI | WE\ \ DH D | DATA VALID i Q HIGH-Z KSECA00SLL Austin Semiconductor, Inc., reserves the rightto change products or specifications without notice. 8000017AUSTIN SEMICONDUCTOR, INC. AS5C4009LL 883 512K x 8 SRAM WRITE CYCLE NO. 3 7:4 (Write Enabled Controlled) < twC > ADDRESS | ADDRESS VALID } tAW- tAH < 1CW- > CE\ \ PAs H_ 1 XwP2> wen fs D | DATA VALID +1tLZWE <_1tHZWE>| Q | AS5C4009LL Austin Semiconductor, Inc., reserves the rightto change products or specifications without notice. DS000017