1
Motorola Bipolar Power Transistor Device Data
SWITCHMODE
NPN Bipolar Power Transistor
For Switching Power Supply Applications
The MJE/MJF13007 is designed for high–voltage, high–speed power switching
inductive circuits where fall time is critical. It is particularly suited for 115 and 220 V
switchmode applications such as Switching Regulators, Inverters, Motor Controls,
Solenoid/Relay drivers and Deflection circuits.
•VCEO(sus) 400 V
•Reverse Bias SOA with Inductive Loads @ TC = 100°C
•700 V Blocking Capability
•SOA and Switching Applications Information
•Two Package Choices: Standard TO–220 or Isolated TO–220
•MJF13007 is UL Recognized to 3500 VRMS, File #E69369
MAXIMUM RATINGS
Rating Symbol MJE13007 MJF13007 Unit
Collector–Emitter Sustaining Voltage VCEO 400 Vdc
Collector–Emitter Breakdown Voltage VCES 700 Vdc
Emitter–Base Voltage VEBO 9.0 Vdc
Collector Current — Continuous
Collector Current — Peak (1) IC
ICM 8.0
16 Adc
Base Current — Continuous
Base Current — Peak (1) IB
IBM 4.0
8.0 Adc
Emitter Current — Continuous
Emitter Current — Peak (1) IE
IEM 12
24 Adc
RMS Isolation Voltage
(for 1 sec, R.H. < 30%, TA = 25°C)
Test No. 1 Per Fig. 15
Test No. 2 Per Fig. 16
Test No. 3 Per Fig. 17
Proper strike and creepage distance must
be provided
VISOL
—
—
—
4500
3500
1500
V
Total Device Dissipation @ TC = 25°C
Derate above 25°CPD80
0.64 40*
0.32 Watts
W/°C
Operating and Storage Temperature TJ, Tstg – 65 to 150 °C
THERMAL CHARACTERISTICS
Thermal Resistance
— Junction to Case
— Junction to Ambient
RθJC
RθJA °1.56°
°62.5°°3.12°
°62.5°°C/W
Maximum Lead Temperature for Soldering
Purposes: 1/8″ from Case for 5 Seconds TL260 °C
(1) Pulse Test: Pulse Width = 5.0 ms, Duty Cycle ≤ 10%.
*Measurement made with thermocouple contacting the bottom insulated mountign surface of the
*package (in a location beneath the die), the device mounted on a heatsink with thermal grease applied
*at a mounting torque of 6 to 8•lbs.
Designer’s Data for “W orst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s and SWITCHMODE are trademarks of Motorola, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA Order this document
by MJE13007/D
Motorola, Inc. 1995
MJE13007
MJF13007
POWER TRANSISTOR
8.0 AMPERES
400 VOLTS
80/40 WATTS
CASE 221A–06
TO–220AB
MJE13007
CASE 221D–02
ISOLATED TO–220 TYPE
UL RECOGNIZED
MJF13007
2 Motorola Bipolar Power Transistor Device Data
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
*OFF CHARACTERISTICS
Collector–Emitter Sustaining Voltage
(IC = 10 mA, IB = 0) VCEO(sus) 400 — — Vdc
Collector Cutoff Current
(VCES = 700 Vdc)
(VCES = 700 Vdc, TC = 125°C)
ICES —
——
—0.1
1.0
mAdc
Emitter Cutoff Current
(VEB = 9.0 Vdc, IC = 0) IEBO — — 100 µAdc
SECOND BREAKDOWN
Second Breakdown Collector Current with Base Forward Biased IS/b See Figure 6
Clamped Inductive SOA with Base Reverse Biased — See Figure 7
*ON CHARACTERISTICS
DC Current Gain
(IC = 2.0 Adc, VCE = 5.0 Vdc)
(IC = 5.0 Adc, VCE = 5.0 Vdc)
hFE 8.0
5.0 —
—40
30
—
Collector–Emitter Saturation Voltage
(IC = 2.0 Adc, IB = 0.4 Adc)
(IC = 5.0 Adc, IB = 1.0 Adc)
(IC = 8.0 Adc, IB = 2.0 Adc)
(IC = 5.0 Adc, IB = 1.0 Adc, TC = 100°C)
VCE(sat) —
—
—
—
—
—
—
—
1.0
2.0
3.0
3.0
Vdc
Base–Emitter Saturation Voltage
(IC = 2.0 Adc, IB = 0.4 Adc)
(IC = 5.0 Adc, IB = 1.0 Adc)
(IC = 5.0 Adc, IB = 1.0 Adc, TC = 100°C)
VBE(sat) —
—
—
—
—
—
1.2
1.6
1.5
Vdc
DYNAMIC CHARACTERISTICS
Current–Gain — Bandwidth Product
(IC = 500 mAdc, VCE = 10 Vdc, f = 1.0 MHz) fT4.0 14 — MHz
Output Capacitance
(VCB = 10 Vdc, IE = 0, f = 0.1 MHz) Cob — 80 — pF
Collector to Heatsink Capacitance, MJF13007 Cc–hs — 3.0 — pF
SWITCHING CHARACTERISTICS
Resistive Load (Table 1)
Delay Time
(VCC = 125 Vdc, IC = 5.0 A,
IB1 = IB2 = 1.0 A, tp = 25 µs,
Duty Cycle ≤ 1.0%)
td— 0.025 0.1 µs
Rise Time
(VCC = 125 Vdc, IC = 5.0 A,
IB1 = IB2 = 1.0 A, tp = 25 µs,
Duty Cycle ≤ 1.0%)
tr— 0.5 1.5
Storage Time
IB1 = IB2 = 1.0 A, tp = 25 µs,
Duty Cycle ≤ 1.0%)
ts— 1.8 3.0
Fall Time
≤ 1.0%)
tf— 0.23 0.7
Inductive Load, Clamped (Table 1)
Voltage Storage Time VCC = 15 Vdc, IC = 5.0 A TC = 25°C
Vclamp = 300 Vdc TC = 100°Ctsv —
—1.2
1.6 2.0
3.0 µs
Crossover Time IB(on) = 1.0 A, IB(off) = 2.5 A TC = 25°C
LC = 200 µH TC = 100°Ctc—
—0.15
0.21 0.30
0.50 µs
Fall Time TC = 25°C
TC = 100°Ctfi —
—0.04
0.10 0.12
0.20 µs
* Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.
3
Motorola Bipolar Power Transistor Device Data
0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10
IC, COLLECTOR CURRENT (AMPS)
V
Figure 1. Base–Emitter Saturation Voltage
0.01
V
IC, COLLECTOR CURRENT (AMPS)
Figure 2. Collector–Emitter Saturation Voltage
0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 5 10
IB, BASE CURRENT (AMPS)
Figure 3. Collector Saturation Region
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
0.01 0.1 1 10
hFE, DC CURRENT GAIN
IC, COLLECTOR CURRENT (AMPS)
Figure 4. DC Current Gain
0.1 1 10 100 1000
VR, REVERSE VOLTAGE (VOLTS)
Figure 5. Capacitance
C, CAPACITANCE (pF)
BE(sat), BASE–EMITTER SATURATION
VOLTAGE (VOLTS)
CE(sat), COLLECTOR–EMITTER SATURATION
VOLTAGE (VOLTS)
1.4
1.2
1
0.8
0.6
0.4
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
3
2.5
2
1.5
1
0.5
0
100
10
1
10000
1000
100
10
0.02 0.05 0.1 0.2 0.5 1 2 5 10
IC/IB = 5
TC = –40
°
C
25
°
C
100
°
C
IC/IB = 5
TC = –40
°
C
25
°
C
100
°
C
TJ = 25
°
C
IC = 8 A
IC = 5 A
IC = 3 A
IC = 1 A
TJ = 100
°
C
25
°
C
40
°
C
VCE = 5 V
Cib
Cob
TJ = 25
°
C
4 Motorola Bipolar Power Transistor Device Data
There are two limitations on the power handling ability of a
transistor: average junction temperature and second break-
down. Safe operating area curves indicate IC— VCE limits of
the transistor that must be observed for reliable operation;
i.e., the transistor must not be subjected to greater dissipa-
tion than the curves indicate.
The data of Figure 6 is based on TC = 25°C; TJ(pk) is vari-
able depending on power level. Second breakdown pulse
limits are valid for duty cycles to 10% but must be derated
when TC ≥ 25°C. Second breakdown limitations do not der-
ate the same as thermal limitations. Allowable current at the
voltages shown on Figure 6 may be found at any case tem-
perature by using the appropriate curve on Figure 8.
At high case temperatures, thermal limitations will reduce
the power that can be handled to values less than the limita-
tions imposed by second breakdown.
Use of reverse biased safe operating area data (Figure 7)
is discussed in the applications information section.
100010 20 30 70 100 20050 300 500
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
Figure 6. Maximum Forward Bias
Safe Operating Area
IC, COLLECTOR CURRENT (AMPS)
0 100 200 300 400 500 600 700 800
IC, COLLECTOR CURRENT (AMPS)
VCEV, COLLECTOR–EMITTER CLAMP VOLTAGE (VOLTS)
Figure 7. Maximum Reverse Bias Switching
Safe Operating Area
20 40 60 80 100 120 140 160
TC, CASE TEMPERATURE (
°
C)
Figure 8. Forward Bias Power Derating
POWER DERATING FACTOR
0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 10 k
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
t, TIME (msec)
Figure 9. Typical Thermal Response for MJE13007
DUTY CYCLE, D = t1/t2
t1
R
θ
JC(t) = r(t) R
θ
JC
R
θ
JC = 1.56
°
C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) R
θ
JC(t)
P(pk)
t2
20
10
5
1
0.5
0.02
0.05
0.2
0.1
2
100
50
0.01
10
8
6
4
2
0
1
0.8
0.6
0.4
0.2
0
1
0.01
0.02
0.05
0.1
0.2
0.5
0.07
0.7
Extended SOA @ 1
µ
s, 10
µ
s
10
µ
s
1
µ
s
1 ms
5 ms
DC
TC = 25
°
C
BONDING WIRE LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
CURVES APPLY BELOW
RATED VCEO
TC
≤
100
°
C
GAIN
≥
4
LC = 500
µ
H
VBE(off)
–5 V
–2 V0 V
SECOND BREAKDOWN
DERATING
THERMAL
DERATING
D = 0.5
D = 0.2
D = 0.1
D = 0.05
D = 0.02
D = 0.01 SINGLE PULSE
5
Motorola Bipolar Power Transistor Device Data
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100 200
t, TIME (msec)
0.3 3 30 300 500 1K 2K 3K 5K 10K 20K 30K 50K 100K
Figure 10. Typical Thermal Response for MJF13007
DUTY CYCLE, D = t1/t2
t1
R
θ
JC(t) = r(t) R
θ
JC
R
θ
JC = 3.12
°
C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) R
θ
JC(t)
P(pk)
t2
1
0.01
0.02
0.05
0.1
0.2
0.5
0.03
0.3
D = 0.5
D = 0.2
D = 0.1
D = 0.05
SINGLE PULSE
SPECIFICATION INFORMATION FOR SWITCHMODE APPLICATIONS
INTRODUCTION
The primary considerations when selecting a power
transistor for SWITCHMODE applications are voltage and
current ratings, switching speed, and energy handling
capability. In this section, these specifications will be
discussed and related to the circuit examples illustrated in
Table 2.(1)
VOLTAGE REQUIREMENTS
Both blocking voltage and sustaining voltage are important
in SWITCHMODE applications.
Circuits B and C in Table 2 illustrate applications that
require high blocking voltage capability. In both circuits the
switching transistor is subjected to voltages substantially
higher than VCC after the device is completely off (see load
line diagrams at IC = Ileakage ≈ 0 in Table 2). The blocking
capability at this point depends on the base to emitter
conditions and the device junction temperature. Since the
highest device capability occurs when the base to emitter
junction is reverse biased (VCEV), this is the recommended
and specified use condition. Maximum ICEV at rated VCEV is
specified at a relatively low reverse bias (1.5 Volts) both at
25°C and 100°C. Increasing the reverse bias will give some
improvement in device blocking capability.
The sustaining or active region voltage requirements in
switching applications occur during turn–on and turn–off. If
the load contains a significant capacitive component, high
current and voltage can exist simultaneously during turn–on
and the pulsed forward bias SOA curves (Figure 6) are the
proper design limits.
For inductive loads, high voltage and current must be
sustained simultaneously during turn–off, in most cases, with
the base to emitter junction reverse biased. Under these
conditions the collector voltage must be held to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping,
RC snubbing, load line shaping, etc. The safe level for these
devices is specified as a Reverse Bias Safe Operating Area
(Figure 7) which represents voltage–current conditions that
can be sustained during reverse biased turn–off. This rating
is verified under clamped conditions so that the device is
never subjected to an avalanche mode.
(1) For detailed information on specific switching applications, see
(1) Motorola Application Note AN719, AN873, AN875, AN951.
6 Motorola Bipolar Power Transistor Device Data
TEST WAVEFORMS
t1 ADJUSTED TO
OBTAIN IC
TEST EQUIPMENT
SCOPE — TEKTRONIX
475 OR EQUIVALENT
t1
≈
Lcoil (ICM)
VCC
Lcoil (ICM)
Vclamp
t2
≈
CIRCUIT
VALUES
VCC = 125 V
RC = 25
Ω
D1 = 1N5820 OR EQUIV.
TEST CIRCUITS
REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING RESISTIVE
SWITCHING
Table 1. Test Conditions For Dynamic Performance
L = 10 mH
RB2 = 8
VCC = 20 Volts
IC(pk) = 100 mA
L = 200 mH
RB2 = 0
VCC = 15 Volts
RB1 selected for
desired IB1
L = 500 mH
RB2 = 0
VCC = 15 Volts
RB1 selected for
desired IB1
V(BR)CEO(sus) Inductive
Switching RBSOA
TYPICAL
WAVEFORMS
VCC
LMUR8100E
Vclamp = 300 Vdc
VCE
51
5.1 k
TUT
IB
IC
+15 V
+10 V
50
Ω
RB1
RB2
150
Ω
500
µ
F
1
µ
F
A
100
µ
F
Voff
COMMON
MTP8P10
MTP12N10
MPF930
MPF930 MTP8P10
MJE210 IB
MUR105
1
µ
F
3 W
100
Ω
3 W
150
Ω
3 W +125
V
SCOPE
RC
TUT
D1
RB
– 4 V
IC
VCE
ICM
t1tft
t
Vclamp
t2
TIME
VCEM
tf CLAMPEDtf UNCLAMPED
≈
t225
µ
s
+11 V
0
9 V
tr, tf < 10 ns
DUTY CYCLE = 1.0%
RB AND RC ADJUSTED
FOR DESIRED IB AND IC
VCE
VCE PEAK
IB
IB2
IB1
VOLTAGE REQUIREMENTS (continued)
In the four application examples (Table 2) load lines are
shown in relation to the pulsed forward and reverse biased
SOA curves.
In circuits A and D, inductive reactance is clamped by the
diodes shown. In circuits B and C the voltage is clamped by
the output rectifiers, however, the voltage induced in the pri-
mary leakage inductance is not clamped by these diodes and
could be large enough to destroy the device. A snubber net-
work or an additional clamp may be required to keep the
turn–off load line within the Reverse Bias SOA curve.
Load lines that fall within the pulsed forward biased SOA
curve during turn–on and within the reverse bias SOA curve
during turn–off are considered safe, with the following as-
sumptions:
(1)The device thermal limitations are not exceeded.
(2)The turn–on time does not exceed 10 µs (see standard
pulsed forward SOA curves in Figure 6).
(3)The base drive conditions are within the specified limits
shown on the Reverse Bias SOA curve (Figure 7).
CURRENT REQUIREMENTS
An efficient switching transistor must operate at the re-
quired current level with good fall time, high energy handling
capability and low saturation voltage. On this data sheet,
these parameters have been specified at 5.0 amperes which
represents typical design conditions for these devices. The
current drive requirements are usually dictated by the
VCE(sat) specification because the maximum saturation volt-
age is specified at a forced gain condition which must be du-
plicated or exceeded in the application to control the
saturation voltage.
SWITCHING REQUIREMENTS
In many switching applications, a major portion of the
transistor power dissipation occurs during the fall time (tfi).
For this reason considerable effort is usually devoted to
reducing the fall time. The recommended way to accomplish
this is to reverse bias the base–emitter junction during turn–
off. The reverse biased switching characteristics for inductive
loads are shown in Figures 13 and 14 and resistive loads in
Figures 11 and 12. Usually the inductive load components
will be the dominant factor in SWITCHMODE applications
and the inductive switching data will more closely represent
the device performance in actual application. The inductive
switching characteristics are derived from the same circuit
used to specify the reverse biased SOA curves, (see Table 1)
providing correlation between test procedures and actual
use conditions.
7
Motorola Bipolar Power Transistor Device Data
SWITCHING TIME NOTES
In resistive switching circuits, rise, fall, and storage times
have been defined and apply to both current and voltage
waveforms since they are in phase. However, for inductive
loads which are common to SWITCHMODE power supplies
and any coil driver, current and voltage waveforms are not in
phase. Therefore, separate measurements must be made on
each waveform to determine the total switching time. For this
reason, the following new terms have been defined.
tsv = Voltage Storage Time, 90% IB1 to 10% Vclamp
trv = Voltage Rise Time, 10–90% Vclamp
tfi = Current Fall Time, 90–10% IC
tti = Current Tail, 10–2% IC
tc = Crossover Time, 10% Vclamp to 10% IC
An enlarged portion of the turn–off waveforms is shown in
Figure 13 to aid in the visual identity of these terms. For the
designer, there is minimal switching loss during storage time
and the predominant switching power losses occur during the
crossover interval and can be obtained using the standard
equation from AN222A:
PSWT = 1/2 VCCIC(tc) f
Typical inductive switching times are shown in Figure 14. In
general, trv + tfi
≅
tc. However , at lower test currents this rela-
tionship may not be valid.
As is common with most switching transistors, resistive
switching is specified at 25°C and has become a benchmark
for designers. However, for designers of high frequency con-
verter circuits, the user oriented specifications which make
this a “SWITCHMODE” transistor are the inductive switching
speeds (tc and tsv) which are guaranteed at 100°C.
SWITCHING PERFORMANCE
1 2 3 4 5 6 7 8 9 10
t, TIME (ns)
IC, COLLECTOR CURRENT (AMP)
Figure 11. Turn–On Time (Resistive Load)
VCC = 125 V
IC/IB = 5
IB(on) = IB(off)
TJ = 25
°
C
PW = 25
µ
s
t, TIME (ns)
2 3 4 5 6 7 8 9 10
IC, COLLECTOR CURRENT (AMP)
Figure 12. Turn–Off Time (Resistive Load)
1
t, TIME (ns)
IC, COLLECTOR CURRENT (AMP)
0.1 0.2 0.3 0.5 0.7 1 2 3 5 7 10
Figure 13. Inductive Switching Measurements
TIME
Figure 14. Typical Inductive Switching Times
10000
1000
100
10
10000
100
200
500
700
1000
2000
5000
7000
10000
10
20
50
100
200
500
1000
2000
5000
VCC = 125 V
IC/IB = 5
IB(on) = IB(off)
TJ = 25
°
C
PW = 25
µ
s
IC/IB = 5
IB(off) = IC/2
Vclamp = 300 V
LC = 200
µ
H
VCC = 15 V
TJ = 25
°
C
ts
tf
td
tr
tc
tfi
tsv
IC
IB
Vclamp
90% IB1
90% Vclamp 90% ICVclamp
10%
Vclamp 10%
IC2%
IC
tsv trv tfi tti
tc
8 Motorola Bipolar Power Transistor Device Data
Notes:See AN569 for Pulse Power Derating Procedure.
1
11
Notes:See AN569 for Pulse Power Derating Procedure.
1
11
Notes:See AN569 for Pulse Power Derating Procedure.
1
11
2
2
2
Notes:See AN569 for Pulse Power Derating Procedure.
1
11
2
Table 2. Applications Examples of Switching Circuits
CIRCUIT LOAD LINE DIAGRAMS TIME DIAGRAMS
SERIES SWITCHING
REGULATOR
FLYBACK
INVERTER
PUSH–PULL
INVERTER/CONVERTER
SOLENOID DRIVER
A
B
C
D
VCC VO
VCC VO
N
VCC
VO
SOLENOID
VCC
16 A
TC = 100
°
C
8 ATURN–ON
TURN–OFF
VCC
400 V
TURN–ON (FORWARD BIAS) SOA
ton
≤
10
µ
s
DUTY CYCLE
≤
10%
PD = 3200 W
300 V TURN–OFF (REVERSE BIAS) SOA
1.5 V
≤
VBE(off)
≤
9 V
DUTY CYCLE
≤
10%
COLLECTOR VOLTAGE
COLLECTOR CURRENT
+700 V
ton toff
TIME t
IC
t
TIME
VCE
VCC
TC = 100
°
C
16 A
8 A
TURN–ON (FORWARD BIAS) SOA
ton
≤
10
µ
s
DUTY CYCLE
≤
10%
PD = 3200 W
300 V TURN–OFF (REVERSE BIAS) SOA
1.5 V
≤
VBE(off)
≤
9 V
DUTY CYCLE
≤
10%
COLLECTOR CURRENT
TURN–ON
TURN–OFF
700 V
400 V
VCC + N (Vo)
+ VCC
VCC + N (Vo)
+ LEAKAGE
SPIKE
COLLECTOR VOLTAGE t
t
LEAKAGE SPIKE
VCE
IC
VCC +
N (Vo)
VCC
ton
toff
16 A
8 A TURN–ON
TURN–OFF
+
TURN–ON (FORWARD BIAS) SOA
ton
≤
10
µ
s
DUTY CYCLE
≤
10%
PD = 3200 W
300 V TURN–OFF (REVERSE BIAS) SOA
1.5 V
≤
VBE(off)
≤
9 V
DUTY CYCLE
≤
10%
COLLECTOR CURRENT
2 VCC
700 V
400 V
VCC
COLLECTOR VOLTAGE t
t
toff
ton
VCE
IC
2 VCC
VCC
TC = 100
°
C
TC = 100
°
C
TURN–ON (FORWARD BIAS) SOA
ton
≤
10
µ
s
DUTY CYCLE
≤
10%
PD = 3200 W
300 V TURN–OFF (REVERSE BIAS) SOA
1.5 V
≤
VBE(off)
≤
9 V
DUTY CYCLE
≤
10%
700 V
400 V
16 A
8 A
+
TURN–OFF
TURN–ON
VCC
COLLECTOR VOLTAGE
COLLECTOR CURRENT
IC
ton toff
t
t
VCC
VCE
9
Motorola Bipolar Power Transistor Device Data
MOUNTED
FULLY ISOLATED
PACKAGE
LEADS
HEATSINK
0.110” MIN
Figure 15. Screw or Clip Mounting Position
for Isolation Test Number 1
*Measurement made between leads and heatsink with all leads shorted together
CLIP
MOUNTED
FULLY ISOLATED
PACKAGE
LEADS
HEATSINK
CLIP 0.107” MIN
MOUNTED
FULLY ISOLATED
PACKAGE
LEADS
HEATSINK
0.107” MIN
Figure 16. Clip Mounting Position
for Isolation Test Number 2 Figure 17. Screw Mounting Position
for Isolation Test Number 3
TEST CONDITIONS FOR ISOLATION TESTS*
4–40 SCREW
PLAIN WASHER
HEATSINK
COMPRESSION WASHER
NUT
CLIP
HEATSINK
Laboratory tests on a limited number of samples indicate, when using the screw and compression washer mounting technique, a screw
torque of 6 to 8 in .lbs is sufficient to provide maximum power dissipation capability. The compression washer helps to maintain a constant
pressure on the package over time and during large temperature excursions.
Destructive laboratory tests show that using a hex head 4–40 screw , without washers, and applying a torque in excess of 20 in .lbs will
cause the plastic to crack around the mounting hole, resulting in a loss of isolation capability.
Additional tests on slotted 4–40 screws indicate that the screw slot fails between 15 to 20 in .lbs without adversely affecting the package.
However, in order to positively ensure the package integrity of the fully isolated device, Motorola does not recommend exceeding 10 in .lbs
of mounting torque under any mounting conditions.
Figure 18. Typical Mounting Techniques
for Isolated Package
MOUNTING INFORMATION
**For more information about mounting power semiconductors see Application Note AN1040.
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10 Motorola Bipolar Power Transistor Device Data
PACKAGE DIMENSIONS
CASE 221A–06
TO–220AB
ISSUE Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.570 0.620 14.48 15.75
B0.380 0.405 9.66 10.28
C0.160 0.190 4.07 4.82
D0.025 0.035 0.64 0.88
F0.142 0.147 3.61 3.73
G0.095 0.105 2.42 2.66
H0.110 0.155 2.80 3.93
J0.018 0.025 0.46 0.64
K0.500 0.562 12.70 14.27
L0.045 0.060 1.15 1.52
N0.190 0.210 4.83 5.33
Q0.100 0.120 2.54 3.04
R0.080 0.110 2.04 2.79
S0.045 0.055 1.15 1.39
T0.235 0.255 5.97 6.47
U0.000 0.050 0.00 1.27
V0.045 ––– 1.15 –––
Z––– 0.080 ––– 2.04
B
Q
H
Z
L
V
G
N
A
K
F
1 2 3
4
D
SEATING
PLANE
–T–
C
S
T
U
R
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
STYLE 2:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
DIM
AMIN MAX MIN MAX
MILLIMETERS
0.621 0.629 15.78 15.97
INCHES
B0.394 0.402 10.01 10.21
C0.181 0.189 4.60 4.80
D0.026 0.034 0.67 0.86
F0.121 0.129 3.08 3.27
G0.100 BSC 2.54 BSC
H0.123 0.129 3.13 3.27
J0.018 0.025 0.46 0.64
K0.500 0.562 12.70 14.27
L0.045 0.060 1.14 1.52
N0.200 BSC 5.08 BSC
Q0.126 0.134 3.21 3.40
R0.107 0.111 2.72 2.81
S0.096 0.104 2.44 2.64
U0.259 0.267 6.58 6.78
–B–
–Y–
G
N
DL
KH
A
F
Q
3 PL
1 2 3
M
B
M
0.25 (0.010) Y
SEATING
PLANE
–T–
U
CS
JR
CASE 221D–02
ISOLATED TO–220 TYPE
ISSUE D
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