Automotive LPDDR SDRAM
MT46H128M16LF – 32 Meg x 16 x 4 Banks
MT46H64M32LF – 16 Meg x 32 x 4 Banks
Features
VDD/VDDQ = 1.70–1.95V
Bidirectional data strobe per byte of data (DQS)
Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
4 internal banks for concurrent operation
Data masks (DM) for masking write data; one mask
per byte
Programmable burst lengths (BL): 2, 4, 8, or 16
Concurrent auto precharge option is supported
Auto refresh and self refresh modes
1.8V LVCMOS-compatible inputs
Temperature-compensated self refresh (TCSR)2
Partial-array self refresh (PASR)
Deep power-down (DPD)
Status read register (SRR)
Selectable output drive strength (DS)
Clock stop capability
64ms refresh; 32ms for the automotive temperature
range
Table 1: Key Timing Parameters (CL = 3)
Speed Grade Clock Rate Access Time
-48 208 MHz 4.8ns
Options Mark
VDD/VDDQ
1.8V/1.8V H
Configuration
128 Meg x 16 (32 Meg x 16 x 4 banks) 128M16
64 Meg x 32 (16 Meg x 32 x 4 banks) 64M32
Addressing
JEDEC-standard LF
Plastic "green" package
60-ball VFBGA (8mm x 9mm) DD
90-ball VFBGA (8mm x 13mm) BQ
Timing – cycle time
4.8ns @ CL = 3 (208 MHz) -48
Special Options
Automotive (package-level burn-in) A
Operating temperature range
From –40˚C to +85˚C IT
From –40˚C to +105˚C1AT
Design revision :C
Notes: 1. Contact factory for availability.
2. Self refresh supported up to 85 ºC.
Table 2: Configuration Addressing – 2Gb
Architecture 128 Meg x 16 64 Meg x 32
Configuration 32 Meg x 16 x 4 banks 16 Meg x 32 x 4 banks
Refresh count 8K 8K
Row addressing 16K A[13:0] 16K A[13:0]
Column addressing 2K A11, A[9:0] 1K A[9:0]
2Gb: x16, x32 Automotive LPDDR SDRAM
Features
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Products and specifications discussed herein are subject to change by Micron without notice.
See Package Block Diagrams for descriptions of signal connections and die configurations for each respective ar-
chitecture.
Figure 1: 2Gb Mobile LPDDR Part Numbering
MT 46 H 64M32 LF KQ -6 A IT :C
Micron Technology
Product Family
46 = Mobile LPDDR
Operating Voltage
H = 1.8/1.8V
HC = 1.8/1.2V
Configuration (depth, width)
128 Meg x 16
64 Meg x 32
128 Meg x 32
256 Meg x 32
Addressing
LF = JEDEC-standard addressing
L2 = 2-die stack standard addressing
L4 = 4-die stack standard addressing
Design Revision
:C = Design generation
Operating Temperature
IT = Industrial (–40°C to +85°C)
AT = Automotive (–40°C to +105°C)
WT = Wireless (–25°C to +85°C)
Special Options
(Multiple processing codes are separated
by a space and are listed in hierarchical order.)
Blank = None
A = Automotive
Speed Grade
-48 = 4.8ns tCK
-5 = 5ns tCK
Package Codes
DD = 60-ball (8mm x 9mm) VFBGA, “green”
BQ = 90-ball (8mm x 13mm) VFBGA, “green”
KQ = 168-ball (12mm x 12mm) WFBGA, “green”
LE = 168-ball (12mm x 12mm) TFBGA, “green”
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.
2Gb: x16, x32 Automotive LPDDR SDRAM
Features
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Contents
Important Notes and Warnings ......................................................................................................................... 8
General Description ......................................................................................................................................... 8
Functional Block Diagrams ............................................................................................................................. 10
Ball Assignments ............................................................................................................................................ 12
Ball Descriptions ............................................................................................................................................ 14
Package Block Diagrams ................................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 17
Electrical Specifications .................................................................................................................................. 19
Electrical Specifications – IDD Parameters ........................................................................................................ 22
Electrical Specifications – AC Operating Conditions ......................................................................................... 28
Output Drive Characteristics ........................................................................................................................... 32
Functional Description ................................................................................................................................... 35
Commands .................................................................................................................................................... 36
DESELECT ................................................................................................................................................. 37
NO OPERATION ......................................................................................................................................... 37
LOAD MODE REGISTER ............................................................................................................................. 37
ACTIVE ...................................................................................................................................................... 37
READ ......................................................................................................................................................... 38
WRITE ....................................................................................................................................................... 39
PRECHARGE .............................................................................................................................................. 40
BURST TERMINATE ................................................................................................................................... 41
AUTO REFRESH ......................................................................................................................................... 41
SELF REFRESH ........................................................................................................................................... 42
DEEP POWER-DOWN ................................................................................................................................. 42
Truth Tables ................................................................................................................................................... 43
State Diagram ................................................................................................................................................ 48
Initialization .................................................................................................................................................. 49
Standard Mode Register .................................................................................................................................. 52
Burst Length .............................................................................................................................................. 53
Burst Type .................................................................................................................................................. 53
CAS Latency ............................................................................................................................................... 54
Operating Mode ......................................................................................................................................... 55
Extended Mode Register ................................................................................................................................. 56
Temperature-Compensated Self Refresh ...................................................................................................... 56
Partial-Array Self Refresh ............................................................................................................................ 57
Output Drive Strength ................................................................................................................................ 57
Status Read Register ....................................................................................................................................... 58
Bank/Row Activation ...................................................................................................................................... 60
READ Operation ............................................................................................................................................. 61
WRITE Operation ........................................................................................................................................... 72
PRECHARGE Operation .................................................................................................................................. 84
Auto Precharge ............................................................................................................................................... 84
Concurrent Auto Precharge ......................................................................................................................... 84
AUTO REFRESH Operation ............................................................................................................................. 90
SELF REFRESH Operation ............................................................................................................................... 91
Power-Down .................................................................................................................................................. 93
Deep Power-Down ..................................................................................................................................... 94
Clock Change Frequency ................................................................................................................................ 96
Revision History ............................................................................................................................................. 97
Rev. I – 05/18 .............................................................................................................................................. 97
2Gb: x16, x32 Automotive LPDDR SDRAM
Features
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Rev. H - 01/17 ............................................................................................................................................. 97
Rev. G - 02/15 ............................................................................................................................................. 97
Rev. F - 09/14 .............................................................................................................................................. 97
Rev. E – 07/14 ............................................................................................................................................. 97
Rev. D – 03/14 ............................................................................................................................................. 97
Rev. C – 02/14 ............................................................................................................................................. 97
Rev. B – 01/14 ............................................................................................................................................. 97
Rev. B – 11/13 ............................................................................................................................................. 97
Rev. A – 07/13 ............................................................................................................................................. 97
2Gb: x16, x32 Automotive LPDDR SDRAM
Features
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List of Figures
Figure 1: 2Gb Mobile LPDDR Part Numbering .................................................................................................. 2
Figure 2: Functional Block Diagram (x16) ....................................................................................................... 10
Figure 3: Functional Block Diagram (x32) ....................................................................................................... 11
Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 12
Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 13
Figure 6: Single Rank, Single Channel (1 Die) Package Block Diagram .............................................................. 16
Figure 7: 60-Ball VFBGA (8mm x 9mm), Package Code: DD ............................................................................. 17
Figure 8: 90-Ball VFBGA (8mm x 13mm), Package Code: BQ ............................................................................ 18
Figure 9: Typical Self Refresh Current vs. Temperature .................................................................................... 27
Figure 10: ACTIVE Command ........................................................................................................................ 38
Figure 11: READ Command ........................................................................................................................... 39
Figure 12: WRITE Command ......................................................................................................................... 40
Figure 13: PRECHARGE Command ................................................................................................................ 41
Figure 14: DEEP POWER-DOWN Command ................................................................................................... 42
Figure 15: Simplified State Diagram ............................................................................................................... 48
Figure 16: Initialize and Load Mode Registers ................................................................................................. 50
Figure 17: Alternate Initialization with CKE LOW ............................................................................................ 51
Figure 18: Standard Mode Register Definition ................................................................................................. 52
Figure 19: CAS Latency .................................................................................................................................. 55
Figure 20: Extended Mode Register ................................................................................................................ 56
Figure 21: Status Read Register Timing ........................................................................................................... 58
Figure 22: Status Register Definition .............................................................................................................. 59
Figure 23: READ Burst ................................................................................................................................... 62
Figure 24: Consecutive READ Bursts .............................................................................................................. 63
Figure 25: Nonconsecutive READ Bursts ........................................................................................................ 64
Figure 26: Random Read Accesses .................................................................................................................. 65
Figure 27: Terminating a READ Burst ............................................................................................................. 66
Figure 28: READ-to-WRITE ............................................................................................................................ 67
Figure 29: READ-to-PRECHARGE .................................................................................................................. 68
Figure 30: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x16) .................................................... 69
Figure 31: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x32) .................................................... 70
Figure 32: Data Output Timing – tAC and tDQSCK .......................................................................................... 71
Figure 33: Data Input Timing ......................................................................................................................... 73
Figure 34: Write – DM Operation .................................................................................................................... 74
Figure 35: WRITE Burst ................................................................................................................................. 75
Figure 36: Consecutive WRITE-to-WRITE ....................................................................................................... 76
Figure 37: Nonconsecutive WRITE-to-WRITE ................................................................................................. 76
Figure 38: Random WRITE Cycles .................................................................................................................. 77
Figure 39: WRITE-to-READ – Uninterrupting ................................................................................................. 78
Figure 40: WRITE-to-READ – Interrupting ...................................................................................................... 79
Figure 41: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 80
Figure 42: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 81
Figure 43: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 82
Figure 44: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting .......................................................... 83
Figure 45: Bank Read – With Auto Precharge ................................................................................................... 86
Figure 46: Bank Read – Without Auto Precharge .............................................................................................. 87
Figure 47: Bank Write – With Auto Precharge .................................................................................................. 88
Figure 48: Bank Write – Without Auto Precharge ............................................................................................. 89
Figure 49: Auto Refresh Mode ........................................................................................................................ 90
Figure 50: Self Refresh Mode .......................................................................................................................... 92
2Gb: x16, x32 Automotive LPDDR SDRAM
Features
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Figure 51: Power-Down Entry (in Active or Precharge Mode) ........................................................................... 93
Figure 52: Power-Down Mode (Active or Precharge) ........................................................................................ 94
Figure 53: Deep Power-Down Mode ............................................................................................................... 95
Figure 54: Clock Stop Mode ........................................................................................................................... 96
2Gb: x16, x32 Automotive LPDDR SDRAM
Features
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List of Tables
Table 1: Key Timing Parameters (CL = 3) ........................................................................................................... 1
Table 2: Configuration Addressing – 2Gb .......................................................................................................... 1
Table 3: Ball Descriptions .............................................................................................................................. 14
Table 4: Absolute Maximum Ratings .............................................................................................................. 19
Table 5: AC/DC Electrical Characteristics and Operating Conditions ............................................................... 19
Table 6: Capacitance (x16, x32) ...................................................................................................................... 21
Table 7: IDD Specifications and Conditions, –40°C to +85°C (x16) ..................................................................... 22
Table 8: IDD Specifications and Conditions, –40°C to +85°C (x32) ..................................................................... 23
Table 9: IDD Specifications and Conditions, –40°C to +105°C (x16) ................................................................... 24
Table 10: IDD Specifications and Conditions, –40°C to +105°C (x32) .................................................................. 25
Table 11: IDD6 Specifications and Conditions .................................................................................................. 26
Table 12: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 28
Table 13: Target Output Drive Characteristics (Full Strength) ........................................................................... 32
Table 14: Target Output Drive Characteristics (Three-Quarter Strength) .......................................................... 33
Table 15: Target Output Drive Characteristics (One-Half Strength) .................................................................. 34
Table 16: Truth Table – Commands ................................................................................................................ 36
Table 17: DM Operation Truth Table .............................................................................................................. 37
Table 18: Truth Table – Current State Bank n – Command to Bank n ................................................................ 43
Table 19: Truth Table – Current State Bank n – Command to Bank m ............................................................... 45
Table 20: Truth Table – CKE ........................................................................................................................... 47
Table 21: Burst Definition Table ..................................................................................................................... 53
2Gb: x16, x32 Automotive LPDDR SDRAM
Features
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Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-
nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
General Description
The 2Gb Mobile low-power DDR SDRAM is a high-speed CMOS, dynamic random-ac-
cess memory containing 2,147,483,648 bits. It is internally configured as a quad-bank
DRAM. Each of the x16’s 536,870,912-bit banks is organized as 16,384 rows by 2048 col-
2Gb: x16, x32 Automotive LPDDR SDRAM
Important Notes and Warnings
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umns by 16 bits. Each of the x32’s 536,870,912-bit banks is organized as 16,384 rows by
1024 columns by 32 bits.
Note:
1. Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ should
be interpreted as any and all DQ collectively, unless specifically stated otherwise. Addi-
tionally, the x16 is divided into 2 bytes: the lower byte and the upper byte. For the lower
byte (DQ[7:0]), DM refers to LDM and DQS refers to LDQS. For the upper byte
(DQ[15:8]), DM refers to UDM and DQS refers to UDQS. The x32 is divided into 4 bytes.
For DQ[7:0], DM refers to DM0 and DQS refers to DQS0. For DQ[15:8], DM refers to
DM1 and DQS refers to DQS1. For DQ[23:16], DM refers to DM2 and DQS refers to
DQS2. For DQ[31:24], DM refers to DM3 and DQS refers to DQS3.
2. Complete functionality is described throughout the document; any page or diagram
may have been simplified to convey a topic and may not be inclusive of all require-
ments.
3. Any specific requirement takes precedence over a general statement.
2Gb: x16, x32 Automotive LPDDR SDRAM
General Description
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Functional Block Diagrams
Figure 2: Functional Block Diagram (x16)
Row-
address
Mux
Control
logic
Column-
address
counter/
latch
Standard mode
register
Extended mode
register
Command
decode
Address
BA0, BA1
CKE
CK#
CK
CS#
WE#
CAS#
RAS#
Address
register
I/O gating
DM mask logic
Column
decoder
Bank 0
memory
array
Bank 0
row-
address
latch
and
decoder
Bank
control
logic
Bank 1
Bank 2
Bank 3
Refresh
counter
16
16
16
2
Input
registers
2
2
2
2
RCVRS
2
32
32
2
2
4
32
CK
out
Data
DQS
Mask
Data
CK
CK
in
DRVRS
MUX
DQS
generator
16
16
16
16
16
32
DQ[15:0]
LDQS,
UDQS
2
Read
latch
Write
FIFO
and
drivers
1
COL 0
COL 0
Sense amplifiers
LDM,
UDM
CK
2Gb: x16, x32 Automotive LPDDR SDRAM
Functional Block Diagrams
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Figure 3: Functional Block Diagram (x32)
RAS#
CAS#
Row-
address
MUX
CK
CS#
WE#
CK#
Control
logic
Column-
address
counter/
latch
Standard mode
register
Extended mode
register
Command
decode
Address,
BA0, BA1
CKE
Address
register
I/O gating
DM mask logic
Bank 0
memory
array
Bank 0
row-
address
latch
and
decoder
Bank
control
logic
Bank 1
Bank 2
Bank 3
Refresh
counter
32
2
2
32
32
2
Input
registers
4
4
4
4
RCVRS
4
64
64
8
64
CK
out
Data
DQS
Mask
Data
CK
CK
in
DRVRS
MUX
DQS
generator
32
32
32
32
32
64
DQ[31:0]
DQS0
DQS1
DQS2
DQS3
4
Read
latch
Write
FIFO
and
drivers
1
COL 0
COL 0
Sense amplifiers
DM0
DM1
DM2
DM3
CK
Column
decoder
2Gb: x16, x32 Automotive LPDDR SDRAM
Functional Block Diagrams
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Ball Assignments
Figure 4: 60-Ball VFBGA – Top View, x16 only
1 2 3 4 6 7 8 95
A
B
C
D
E
F
G
H
J
K
VSSQ
DQ14
DQ12
DQ10
DQ8
NC
CK#
A12
A8
A5
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CKE
A9
A6
VSS
DQ15
DQ13
DQ11
DQ9
UDQS
UDM
CK
A11
A7
A4
VDDQ
DQ1
DQ3
DQ5
DQ7
A13
WE#
CS#
A10/AP
A2
DQ0
DQ2
DQ4
DQ6
LDQS
LDM
CAS#
BA0
A0
A3
VDD
VSSQ
VDDQ
VDDQ
VDD
RAS#
BA1
A1
VDD
TEST1
Notes: 1. D9 is a test pin that must be tied to VSS or VSSQ in normal operations.
2. Unused address pins become RFU.
2Gb: x16, x32 Automotive LPDDR SDRAM
Ball Assignments
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Figure 5: 90-Ball VFBGA – Top View, x32 only
VSSQ
DQ30
DQ28
DQ26
DQ24
NC
CK#
A12
A8
A5
DQ8
DQ10
DQ12
DQ14
VSSQ
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VDD
CKE
A9
A6
A4
VSSQ
VDDQ
VSSQ
VDDQ
VSS
DQ31
DQ29
DQ27
DQ25
DQS3
DM3
CK
A11
A7
DM1
DQS1
DQ9
DQ11
DQ13
DQ15
VDDQ
DQ17
DQ19
DQ21
DQ23
A13
WE#
CS#
A10/AP
A2
DQ7
DQ5
DQ3
DQ1
VDDQ
DQ16
DQ18
DQ20
DQ22
DQS2
DM2
CAS#
BA0
A0
DM0
DQS0
DQ6
DQ4
DQ2
DQ0
VDD
VSSQ
VDDQ
VDDQ
VSS
RAS#
BA1
A1
A3
VDDQ
VSSQ
VDDQ
VSSQ
VDD
1 2 3 4 6 7 8 95
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TEST1
Notes: 1. D9 is a test pin that must be tied to VSS or VSSQ in normal operations.
2. Unused address pins become RFU.
2Gb: x16, x32 Automotive LPDDR SDRAM
Ball Assignments
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Ball Descriptions
The ball descriptions table is a comprehensive list of all possible balls for all supported
packages. Not all balls listed are supported for a given package.
Table 3: Ball Descriptions
Symbol Type Description
CK, CK# Input Clock: CK is the system clock input. CK and CK# are differential clock inputs. All ad-
dress and control input signals are sampled on the crossing of the positive edge of CK
and the negative edge of CK#. Input and output data is referenced to the crossing of
CK and CK# (both directions of the crossing).
CKE
CKE0, CKE1
Input Clock enable: CKE HIGH activates, and CKE LOW deactivates, the internal clock signals,
input buffers, and output drivers. Taking CKE LOW enables PRECHARGE power-down
and SELF REFRESH operations (all banks idle), or ACTIVE power-down (row active in
any bank). CKE is synchronous for all functions except SELF REFRESH exit. All input
buffers (except CKE) are disabled during power-down and self refresh modes.
CKE0 is used for a single LPDDR product.
CKE1 is used for dual LPDDR products and is considered RFU for single LPDDR MCPs.
CS#
CS0#, CS1#
Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for ex-
ternal bank selection on systems with multiple banks. CS# is considered part of the
command code.
CS0# is used for a single LPDDR product.
CS1# is used for dual LPDDR products and is considered RFU for single LPDDR MCPs.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered.
UDM, LDM (x16)
DM[3:0] (x32)
Input Input data mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is
sampled on both edges of DQS. Although DM balls are input-only, the DM loading is
designed to match that of DQ and DQS balls.
BA0, BA1 Input Bank address inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA0 and BA1 also determine which mode reg-
ister is loaded during a LOAD MODE REGISTER command.
A[13:0] Input Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ or WRITE commands, to select one loca-
tion out of the memory array in the respective bank. During a PRECHARGE command,
A10 determines whether the PRECHARGE applies to one bank (A10 LOW, bank selec-
ted by BA0, BA1) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE REGISTER command. The maximum address range is dependent
upon configuration. Unused address balls become RFU.
TEST Input Test pin: Must be tied to VSS or VSSQ in normal operations.
DQ[15:0] (x16)
DQ[31:0] (x32)
Input/
output
Data input/output: Data bus for x16 and x32.
LDQS, UDQS (x16)
DQS[3:0] (x32)
Input/
output
Data strobe: Output with read data, input with write data. DQS is edge-aligned with
read data, center-aligned in write data. It is used to capture data.
TQ Output Temperature sensor output: TQ HIGH when LPDDR TJ exceeds 85°C.
VDDQ Supply DQ power supply.
2Gb: x16, x32 Automotive LPDDR SDRAM
Ball Descriptions
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Table 3: Ball Descriptions (Continued)
Symbol Type Description
VSSQ Supply DQ ground.
VDD Supply Power supply.
VSS Supply Ground.
NC No connect: May be left unconnected.
RFU Reserved for future use. Balls marked RFU may or may not be connected internally.
These balls should not be used. Contact factory for details.
2Gb: x16, x32 Automotive LPDDR SDRAM
Ball Descriptions
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Package Block Diagrams
Figure 6: Single Rank, Single Channel (1 Die) Package Block Diagram
LPDDR
Die 0
VDD
VDDQ
VSS
VSSQ
CS0#
CKE0
CK
CK#
WE#
CAS#
RAS#
Address
BA0, BA1
DM[3:0]
DQ[31:0]
DQS[3:0]
2Gb: x16, x32 Automotive LPDDR SDRAM
Package Block Diagrams
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Package Dimensions
Figure 7: 60-Ball VFBGA (8mm x 9mm), Package Code: DD
Ball A1 ID
0.25 MIN
0.9 ±0.1
6.4 CTR
8 ±0.1
0.8 TYP
9 ±0.1
0.8 TYP
7.2 CTR
60X Ø0.45
Dimensions apply
to solder balls post-
reflow on Ø0.40
SMD ball pads.
Ball A1 ID
(covered by SR)
123789
0.1 A
A
B
C
D
E
F
G
H
J
K
A
Notes: 1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
2Gb: x16, x32 Automotive LPDDR SDRAM
Package Dimensions
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Figure 8: 90-Ball VFBGA (8mm x 13mm), Package Code: BQ
6.4 CTR
8 ±0.1
0.8 TYP
13 ±0.1
11.2 CTR
0.8 TYP 0.9 ±0.1
0.25 MIN
0.1 A
Ball A1 ID
(covered by SR) Ball A1 ID
90X Ø0.45
Dimensions apply
to solder balls post-
reflow on Ø0.40
SMD ball pads.
A
B
C
D
E
F
G
H
J
K
R
Seating plane
L
M
N
P
91
8 7 23
A
Notes: 1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
2Gb: x16, x32 Automotive LPDDR SDRAM
Package Dimensions
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Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Table 4: Absolute Maximum Ratings
Note 1 applies to all parameters in this table
Parameter Symbol Min Max Unit
VDD/VDDQ supply voltage relative to VSS VDD/VDDQ –1.0 2.4 V
Voltage on any pin relative to VSS VIN –0.5 2.4 or (VDDQ + 0.3V),
whichever is less
V
Storage temperature (plastic) TSTG –55 150 ˚C
Note: 1. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed
VDD.
Table 5: AC/DC Electrical Characteristics and Operating Conditions
Notes 1–5 apply to all parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Parameter/Condition Symbol Min Max Unit Notes
Supply voltage VDD 1.70 1.95 V 6, 7
I/O supply voltage VDDQ 1.70 1.95 V 6, 7
Address and command inputs
Input voltage high VIH 0.8 × VDDQ VDDQ + 0.3 V 8, 9
Input voltage low VIL –0.3 0.2 × VDDQ V 8, 9
Clock inputs (CK, CK#)
DC input voltage VIN –0.3 VDDQ + 0.3 V 10
DC input differential voltage VID(DC) 0.4 × VDDQ VDDQ + 0.6 V 10, 11
AC input differential voltage VID(AC) 0.6 × VDDQ VDDQ + 0.6 V 10, 11
AC differential crossing voltage VIX 0.4 × VDDQ 0.6 × VDDQ V 10, 12
Data inputs
DC input high voltage VIH(DC) 0.7 × VDDQ VDDQ + 0.3 V 8, 9, 13
DC input low voltage VIL(DC) –0.3 0.3 × VDDQ V 8, 9, 13
AC input high voltage VIH(AC) 0.8 × VDDQ VDDQ + 0.3 V 8, 9, 13
AC input low voltage VIL(AC) –0.3 0.2 × VDDQ V 8, 9, 13
Data outputs
DC output high voltage: Logic 1 (IOH = –0.1mA) VOH 0.9 × VDDQ V
DC output low voltage: Logic 0 (IOL = 0.1mA) VOL 0.1 × VDDQ V
Leakage current
Input leakage current
Any input 0V VIN VDD
(All other pins not under test = 0V)
II–1 1 μA
2Gb: x16, x32 Automotive LPDDR SDRAM
Electrical Specifications
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Table 5: AC/DC Electrical Characteristics and Operating Conditions (Continued)
Notes 1–5 apply to all parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Parameter/Condition Symbol Min Max Unit Notes
Output leakage current
(DQ are disabled; 0V VOUT VDDQ)
IOZ –1.5 1.5 μA
Operating temperature
Commercial TA0 70 ˚C
Wireless TA–25 85 ˚C
Industrial TA–40 85 ˚C
Automotive TA–40 105 ˚C
Notes: 1. All voltages referenced to VSS.
2. All parameters assume proper device initialization.
3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at
nominal supply voltage levels, but the related specifications and device operation are
guaranteed for the full voltage range specified.
4. Outputs measured with equivalent load; transmission line delay is assumed to be very
small:
I/O
20pF
I/O
10pF
Full drive strength Half drive strength
50 50
5. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment,
but input timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#). The
output timing reference voltage level is VDDQ/2.
6. Any positive glitch must be less than one-third of the clock cycle and not more than
+200mV or 2.0V, whichever is less. Any negative glitch must be less than one-third of the
clock cycle and not exceed either –150mV or +1.6V, whichever is more positive.
7. VDD and VDDQ must track each other and VDDQ must be less than or equal to VDD.
8. To maintain a valid level, the transitioning edge of the input must:
8a. Sustain a constant slew rate from the current AC level through to the target AC lev-
el, VIL(AC) Or VIH(AC).
8b. Reach at least the target AC level.
8c. After the AC target level is reached, continue to maintain at least the target DC lev-
el, VIL(DC) or VIH(DC).
9. VIH overshoot: VIHmax = VDDQ + 1.0V for a pulse width 3ns and the pulse width cannot
be greater than one-third of the cycle rate. VIL undershoot: VILmin = –1.0V for a pulse
width 3ns and the pulse width cannot be greater than one-third of the cycle rate.
10. CK and CK# input slew rate must be 1 V/ns (2 V/ns if measured differentially).
11. VID is the magnitude of the difference between the input level on CK and the input lev-
el on CK#.
12. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track
variations in the DC level of the same.
13. DQ and DM input slew rates must not deviate from DQS by more than 10%. 50ps must
be added to tDS and tDH for each 100 mV/ns reduction in slew rate. If slew rate exceeds
4 V/ns, functionality is uncertain.
2Gb: x16, x32 Automotive LPDDR SDRAM
Electrical Specifications
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Table 6: Capacitance (x16, x32)
Notes 1 and 2 apply to all the parameters in this table
Parameter Symbol Min Max Unit Notes
Input capacitance: CK, CK# CCK 1.0 2.0 pF
Delta input capacitance: CK, CK# CDCK 0 0.25 pF 3
Input capacitance: command and address CI1.0 2.0 pF
Delta input capacitance: command and address CDI – 0.5 0.5 pF 3
Input/output capacitance: DQ, DQS, DM CIO 1.25 2.5 pF
Delta input/output capacitance: DQ, DQS, DM CDIO – 0.6 0.6 pF 4
Notes: 1. This parameter is sampled. VDD/VDDQ = 1.70–1.95V, f = 100 MHz, TA = 25˚C, VOUT(DC) =
VDDQ/2, VOUT (peak-to-peak) = 0.2V. DM input is grouped with I/O pins, reflecting the
fact that they are matched in loading.
2. This parameter applies to die devices only (does not include package capacitance).
3. The input capacitance per pin group will not differ by more than this maximum amount
for any given device.
4. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maxi-
mum amount for any given device.
2Gb: x16, x32 Automotive LPDDR SDRAM
Electrical Specifications
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Electrical Specifications – IDD Parameters
Table 7: IDD Specifications and Conditions, –40°C to +85°C (x16)
Notes 1–5 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Parameter/Condition Symbol
Speed
Unit Notes-48
Operating 1 bank active precharge current: tRC = tRC (MIN); tCK = tCK (MIN);
CKE is HIGH; CS is HIGH between valid commands; Address inputs are switching
every 2 clock cycles; Data bus inputs are stable
IDD0 75 mA 6
Precharge power-down standby current: All banks idle; CKE is LOW; CS is HIGH;
tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are
stable
IDD2P 900 μA 7, 8
Precharge power-down standby current: Clock stopped; All banks idle; CKE is
LOW; CS is HIGH; CK = LOW, CK# = HIGH; Address and control inputs are switch-
ing; Data bus inputs are stable
IDD2PS 900 μA 7
Precharge nonpower-down standby current: All banks idle; CKE = HIGH; CS =
HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus in-
puts are stable
IDD2N 15 mA 9
Precharge nonpower-down standby current: Clock stopped; All banks idle; CKE
= HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Address and control inputs are
switching; Data bus inputs are stable
IDD2NS 9 mA 9
Active power-down standby current: 1 bank active; CKE = LOW; CS = HIGH; tCK
= tCK (MIN); Address and control inputs are switching; Data bus inputs are sta-
ble
IDD3P 5 mA 8
Active power-down standby current: Clock stopped; 1 bank active; CKE = LOW;
CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching;
Data bus inputs are stable
IDD3PS 5 mA
Active nonpower-down standby: 1 bank active; CKE = HIGH; CS = HIGH; tCK =
tCK (MIN); Address and control inputs are switching; Data bus inputs are stable
IDD3N 17 mA 6
Active nonpower-down standby: Clock stopped; 1 bank active; CKE = HIGH; CS =
HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data
bus inputs are stable
IDD3NS 14 mA 6
Operating burst read: 1 bank active; BL = 4; tCK = tCK (MIN); Continuous READ
bursts; Iout = 0mA; Address inputs are switching every 2 clock cycles; 50% data
changing each burst
IDD4R 90 mA 6
Operating burst write: 1 bank active; BL = 4; tCK = tCK (MIN); Continuous WRITE
bursts; Address inputs are switching; 50% data changing each burst
IDD4W 90 mA 6
Auto refresh: Burst refresh; CKE = HIGH; Address and con-
trol inputs are switching; Data bus inputs are stable
tRFC = 138ns IDD5 170 mA 10
tRFC = tREFI IDD5A 12 mA 10, 11
Deep power-down current: Address and control balls are stable; Data bus inputs
are stable
IDD8 10 μA 7, 13
2Gb: x16, x32 Automotive LPDDR SDRAM
Electrical Specifications – IDD Parameters
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Table 8: IDD Specifications and Conditions, –40°C to +85°C (x32)
Notes 1–5 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Parameter/Condition Symbol
Speed
Unit Notes-48
Operating 1 bank active precharge current: tRC = tRC (MIN); tCK = tCK (MIN);
CKE is HIGH; CS is HIGH between valid commands; Address inputs are switching
every 2 clock cycles; Data bus inputs are stable
IDD0 75 mA 6
Precharge power-down standby current: All banks idle; CKE is LOW; CS is HIGH;
tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are
stable
IDD2P 900 μA 7, 8
Precharge power-down standby current: Clock stopped; All banks idle; CKE is
LOW; CS is HIGH; CK = LOW, CK# = HIGH; Address and control inputs are switch-
ing; Data bus inputs are stable
IDD2PS 900 μA 7
Precharge nonpower-down standby current: All banks idle; CKE = HIGH; CS =
HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus in-
puts are stable
IDD2N 15 mA 9
Precharge nonpower-down standby current: Clock stopped; All banks idle; CKE
= HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Address and control inputs are
switching; Data bus inputs are stable
IDD2NS 9 mA 9
Active power-down standby current: 1 bank active; CKE = LOW; CS = HIGH; tCK
= tCK (MIN); Address and control inputs are switching; Data bus inputs are sta-
ble
IDD3P 5 mA 8
Active power-down standby current: Clock stopped; 1 bank active; CKE = LOW;
CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching;
Data bus inputs are stable
IDD3PS 5 mA
Active nonpower-down standby: 1 bank active; CKE = HIGH; CS = HIGH; tCK =
tCK (MIN); Address and control inputs are switching; Data bus inputs are stable
IDD3N 17 mA 6
Active nonpower-down standby: Clock stopped; 1 bank active; CKE = HIGH; CS =
HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data
bus inputs are stable
IDD3NS 14 mA 6
Operating burst read: 1 bank active; BL = 4; tCK = tCK (MIN); Continuous READ
bursts; Iout = 0mA; Address inputs are switching every 2 clock cycles; 50% data
changing each burst
IDD4R 90 mA 6
Operating burst write: 1 bank active; BL = 4; tCK = tCK (MIN); Continuous WRITE
bursts; Address inputs are switching; 50% data changing each burst
IDD4W 90 mA 6
Auto refresh: Burst refresh; CKE = HIGH; Address and con-
trol inputs are switching; Data bus inputs are stable
tRFC = 138ns IDD5 170 mA 10
tRFC = tREFI IDD5A 12 mA 10, 11
Deep power-down current: Address and control balls are stable; Data bus inputs
are stable
IDD8 10 μA 7, 13
2Gb: x16, x32 Automotive LPDDR SDRAM
Electrical Specifications – IDD Parameters
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Table 9: IDD Specifications and Conditions, –40°C to +105°C (x16)
Notes 1–5 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Parameter/Condition Symbol
Speed
Unit Notes-48
Operating 1 bank active precharge current: tRC = tRC (MIN); tCK = tCK (MIN);
CKE is HIGH; CS is HIGH between valid commands; Address inputs are switching
every 2 clock cycles; Data bus inputs are stable
IDD0 100 mA 6
Precharge power-down standby current: All banks idle; CKE is LOW; CS is HIGH;
tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are
stable
IDD2P 1500 μA 7, 8
Precharge power-down standby current: Clock stopped; All banks idle; CKE is
LOW; CS is HIGH; CK = LOW, CK# = HIGH; Address and control inputs are switch-
ing; Data bus inputs are stable
IDD2PS 1500 μA 7
Precharge nonpower-down standby current: All banks idle; CKE = HIGH; CS =
HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus in-
puts are stable
IDD2N 19 mA 9
Precharge nonpower-down standby current: Clock stopped; All banks idle; CKE
= HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Address and control inputs are
switching; Data bus inputs are stable
IDD2NS 13 mA 9
Active power-down standby current: 1 bank active; CKE = LOW; CS = HIGH; tCK
= tCK (MIN); Address and control inputs are switching; Data bus inputs are sta-
ble
IDD3P 9 mA 8
Active power-down standby current: Clock stopped; 1 bank active; CKE = LOW;
CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching;
Data bus inputs are stable
IDD3PS 9 mA
Active nonpower-down standby: 1 bank active; CKE = HIGH; CS = HIGH; tCK =
tCK (MIN); Address and control inputs are switching; Data bus inputs are stableS
IDD3N 21 mA 6
Active nonpower-down standby: Clock stopped; 1 bank active; CKE = HIGH; CS =
HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data
bus inputs are stable
IDD3NS 18 mA 6
Operating burst read: 1 bank active; BL = 4; tCK = tCK (MIN); Continuous READ
bursts; Iout = 0mA; Address inputs are switching every 2 clock cycles; 50% data
changing each burst
IDD4R 130 mA 6
Operating burst write: 1 bank active; BL = 4; tCK = tCK (MIN); Continuous WRITE
bursts; Address inputs are switching; 50% data changing each burst
IDD4W 130 mA 6
Auto refresh: Burst refresh; CKE = HIGH; Address and con-
trol inputs are switching; Data bus inputs are stable
tRFC = 138ns IDD5 170 mA 10
tRFC = tREFI IDD5A 13 mA 10, 11
Deep power-down current: Address and control balls are stable; Data bus inputs
are stable
IDD8 15 μA 7, 13
2Gb: x16, x32 Automotive LPDDR SDRAM
Electrical Specifications – IDD Parameters
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Table 10: IDD Specifications and Conditions, –40°C to +105°C (x32)
Notes 1–5 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Parameter/Condition Symbol
Speed
Unit Notes-48
Operating 1 bank active precharge current: tRC = tRC (MIN); tCK = tCK (MIN);
CKE is HIGH; CS is HIGH between valid commands; Address inputs are switching
every 2 clock cycles; Data bus inputs are stable
IDD0 100 mA 6
Precharge power-down standby current: All banks idle; CKE is LOW; CS is HIGH;
tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are
stable
IDD2P 1500 μA 7, 8
Precharge power-down standby current: Clock stopped; All banks idle; CKE is
LOW; CS is HIGH, CK = LOW, CK# = HIGH; Address and control inputs are switch-
ing; Data bus inputs are stable
IDD2PS 1500 μA 7
Precharge nonpower-down standby current: All banks idle; CKE = HIGH; CS =
HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs
are stable
IDD2N 19 mA 9
Precharge nonpower-down standby current: Clock stopped; All banks idle; CKE
= HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Address and control inputs are
switching; Data bus inputs are stable
IDD2NS 13 mA 9
Active power-down standby current: 1 bank active; CKE = LOW; CS = HIGH; tCK
= tCK (MIN); Address and control inputs are switching; Data bus inputs are sta-
ble
IDD3P 9 mA 8
Active power-down standby current: Clock stopped; 1 bank active; CKE = LOW;
CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching;
Data bus inputs are stable
IDD3PS 9 mA
Active nonpower-down standby: 1 bank active; CKE = HIGH; CS = HIGH; tCK =
tCK (MIN); Address and control inputs are switching; Data bus inputs are stable
IDD3N 21 mA 6
Active nonpower-down standby: Clock stopped; 1 bank active; CKE = HIGH; CS =
HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data
bus inputs are stable
IDD3NS 18 mA 6
Operating burst read: 1 bank active; BL = 4; CL = 3; tCK = tCK (MIN); Continuous
READ bursts; Iout = 0mA; Address inputs are switching every 2 clock cycles; 50%
data changing each burst
IDD4R 150 mA 6
Operating burst write: One bank active; BL = 4; tCK = tCK (MIN); Continuous
WRITE bursts; Address inputs are switching; 50% data changing each burst
IDD4W 150 mA 6
Auto refresh: Burst refresh; CKE = HIGH; Address and con-
trol inputs are switching; Data bus inputs are stable
tRFC = 138ns IDD5 170 mA 10
tRFC = tREFI IDD5A 13 mA 10, 11
Deep power-down current: Address and control pins are stable; Data bus inputs
are stable
IDD8 15 μA 7, 13
2Gb: x16, x32 Automotive LPDDR SDRAM
Electrical Specifications – IDD Parameters
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Table 11: IDD6 Specifications and Conditions
Notes 1–5, 7, and 12 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Parameter/Condition Symbol Value Units
Self refresh:
CKE = LOW; tCK = tCK (MIN); Address and control inputs
are stable; Data bus inputs are stable
Full array, 105˚C IDD6 n/a14 μA
Full array, 85˚C 2000 μA
Full array, 45˚C 900 μA
1/2 array, 85˚C 1450 μA
1/2 array, 45˚C 700 μA
1/4 array, 85˚C 1230 μA
1/4 array, 45˚C 600 μA
1/8 array, 85˚C 1090 μA
1/8 array, 45˚C 575 μA
1/16 array, 85˚C 1020 μA
1/16 array, 45˚C 550 μA
Notes: 1. All voltages referenced to VSS.
2. Tests for IDD characteristics may be conducted at nominal supply voltage levels, but the
related specifications and device operation are guaranteed for the full voltage range
specified.
3. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment,
but input timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#). The
output timing reference voltage level is VDDQ/2.
4. IDD is dependent on output loading and cycle rates. Specified values are obtained with
minimum cycle time with the outputs open.
5. IDD specifications are tested after the device is properly initialized and values are aver-
aged at the defined cycle rate.
6. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the
minimum absolute value for the respective parameter. tRAS (MAX) for IDD measure-
ments is the largest multiple of tCK that meets the maximum absolute value for tRAS.
7. Measurement is taken 500ms after entering into this operating mode to provide settling
time for the tester.
8. VDD must not vary more than 4% if CKE is not active while any bank is active.
9. IDD2N specifies DQ, DQS, and DM to be driven to a valid high or low logic level.
10. CKE must be active (HIGH) during the entire time a REFRESH command is executed.
From the time the AUTO REFRESH command is registered, CKE must be active at each
rising clock edge until tRFC later.
11. This limit is a nominal value and does not result in a fail. CKE is HIGH during REFRESH
command period (tRFC (MIN)) else CKE is LOW (for example, during standby).
12. Values for IDD6 85˚C are guaranteed for the entire temperature range. All other IDD6 val-
ues are estimated.
13. Typical values at 25˚C, not a maximum value.
14. Self refresh is not supported for AT (85˚C to 105˚C) operation.
2Gb: x16, x32 Automotive LPDDR SDRAM
Electrical Specifications – IDD Parameters
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Figure 9: Typical Self Refresh Current vs. Temperature
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
–45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85
Current [µA]
Temperature °C
Full Array
1/2 Array
1/4 Array
1/8 Array
1/16 Array
2Gb: x16, x32 Automotive LPDDR SDRAM
Electrical Specifications – IDD Parameters
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Electrical Specifications – AC Operating Conditions
Table 12: Electrical Characteristics and Recommended AC Operating Conditions
Notes 1–9 apply to all the parameters in this table; VDD/VDDQ = 1.70–1.95V
Parameter Symbol
-48 -5
Unit NotesMin Max Min Max
Access window of DQ from CK/CK# CL = 3 tAC 2.0 5.0 2.0 5.0 ns
CL = 2 2.0 6.5 2.0 6.5
Clock cycle time CL = 3 tCK 4.8 5.0 ns 10
CL = 2 12 12
CK high-level width tCH 0.45 0.55 0.45 0.55 tCK
CK low-level width tCL 0.45 0.55 0.45 0.55 tCK
CKE minimum pulse width (high and low) tCKE 1 1 tCK 11
Auto precharge write recovery + precharge
time
tDAL 12
DQ and DM input hold time relative to DQS
(fast slew rate)
tDHf0.48 0.48 ns 13, 14,
15
DQ and DM input hold time relative to DQS
(slow slew rate)
tDHs0.58 0.58 ns
DQ and DM input setup time relative to DQS
(fast slew rate)
tDSf0.48 0.48 ns 13, 14,
15
DQ and DM input setup time relative to DQS
(slow slew rate)
tDSs0.58 0.58 ns
DQ and DM input pulse width (for each in-
put)
tDIPW 1.8 1.8 ns 16
Access window of DQS from CK/CK# CL = 3 tDQSCK 2.0 5.0 2.0 5.0 ns
CL = 2 2.0 6.5 2.0 6.5 ns
DQS input high pulse width tDQSH 0.4 0.6 0.4 0.6 tCK
DQS input low pulse width tDQSL 0.4 0.6 0.4 0.6 tCK
DQS–DQ skew, DQS to last DQ valid, per
group, per access
tDQSQ 0.4 0.4 ns 13, 17
WRITE command to first DQS latching transi-
tion
tDQSS 0.75 1.25 0.75 1.25 tCK
DQS falling edge from CK
rising – hold time
tDSH 0.2 0.2 tCK
DQS falling edge to CK
rising – setup time
tDSS 0.2 0.2 tCK
Data valid output window (DVW) n/a tQH - tDQSQ ns 17
Half-clock period tHP tCH, tCL tCH, tCL ns 18
Data-out High-Z window from
CK/CK#
CL = 3 tHZ 5.0 5.0 ns 19, 20
CL = 2 6.5 6.5 ns
Data-out Low-Z window from CK/CK# tLZ 1.0 1.0 ns 19
2Gb: x16, x32 Automotive LPDDR SDRAM
Electrical Specifications – AC Operating Conditions
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Table 12: Electrical Characteristics and Recommended AC Operating Conditions (Continued)
Notes 1–9 apply to all the parameters in this table; VDD/VDDQ = 1.70–1.95V
Parameter Symbol
-48 -5
Unit NotesMin Max Min Max
Address and control input hold time (fast
slew rate)
tIHF0.9 0.9 ns 15, 21
Address and control input hold time (slow
slew rate)
tIHS1.1 1.1 ns
Address and control input
setup time (fast slew rate)
tISF0.9 0.9 ns 15, 21
Address and control input
setup time (slow slew rate)
tISS1.1 1.1 ns
Address and control input pulse width tIPW 2.3 2.3 ns 16
LOAD MODE REGISTER
command cycle time
tMRD 2 2 tCK
DQ–DQS hold, DQS to first DQ to go nonvalid,
per access
tQH tHP -
tQHS
tHP -
tQHS
ns 13, 17
Data hold skew factor tQHS 0.5 0.5 ns
ACTIVE-to-PRECHARGE command tRAS 38.4 70,000 40 70,000 ns 22, 23
ACTIVE to ACTIVE/ACTIVE to AUTO REFRESH
command period
tRC 52.8 55 ns 23
Active to read or write delay tRCD 14.4 15 ns
Refresh period tREF 64 64 ms 29
Average periodic refresh
interval: 64Mb, 128Mb, and 256Mb (x32)
tREFI 15.6 15.6 μs 29
Average periodic refresh
interval: 256Mb, 512Mb, 1Gb, 2Gb
tREFI 7.8 7.8 μs 29
AUTO REFRESH command
period
tRFC 72 72 ns
PRECHARGE command period tRP 14.4 15 ns
DQS read preamble CL = 3 tRPRE 0.9 1.1 0.9 1.1 tCK
CL = 2 tRPRE 0.5 1.1 0.5 1.1 tCK
DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK
Active bank a to active bank b command tRRD 9.6 10 ns
Read of SRR to next valid
command
tSRC CL + 1 CL + 1 tCK
SRR to read tSRR 2 2 tCK
Internal temperature sensor valid tempera-
ture output enable
tTQ 2 2 ms
DQS write preamble tWPRE 0.25 0.25 tCK
DQS write preamble setup time tWPRES 0 0 ns 24, 25
DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK 26
Write recovery time tWR 14.4 15 ns 27
2Gb: x16, x32 Automotive LPDDR SDRAM
Electrical Specifications – AC Operating Conditions
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Table 12: Electrical Characteristics and Recommended AC Operating Conditions (Continued)
Notes 1–9 apply to all the parameters in this table; VDD/VDDQ = 1.70–1.95V
Parameter Symbol
-48 -5
Unit NotesMin Max Min Max
Internal WRITE-to-READ
command delay
tWTR 2 2 tCK
Exit power-down mode to first valid com-
mand
tXP 2 2 tCK
Exit self refresh to first
valid command
tXSR 110 112.5 ns 28
Notes: 1. All voltages referenced to VSS.
2. All parameters assume proper device initialization.
3. Tests for AC timing and electrical AC and DC characteristics may be conducted at nomi-
nal supply voltage levels, but the related specifications and device operation are guar-
anteed for the full voltage ranges specified.
4. The circuit shown below represents the timing reference load used in defining the rele-
vant timing parameters of the device. It is not intended to be either a precise represen-
tation of the typical system environment or a depiction of the actual load presented by
a production tester. System designers will use IBIS or other simulation tools to correlate
the timing reference load to system environment. Specifications are correlated to pro-
duction test conditions (generally a coaxial transmission line terminated at the tester
electronics). For the half-strength driver with a nominal 10pF load, parameters tAC and
tQH are expected to be in the same range. However, these parameters are not subject to
production test but are estimated by design/characterization. Use of IBIS or other simu-
lation tools for system design validation is suggested.
I/O
20pF
I/O
10pF
Full drive strength Half drive strength
50 50
5. The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point
at which CK and CK# cross; the input reference voltage level for signals other than
CK/CK# is VDDQ/2.
6. A CK and CK# input slew rate 1 V/ns (2 V/ns if measured differentially) is assumed for
all parameters.
7. All AC timings assume an input slew rate of 1 V/ns.
8. CAS latency definition: with CL = 2, the first data element is valid at (tCK + tAC) after the
clock at which the READ command was registered; for CL = 3, the first data element is
valid at (2 × tCK + tAC) after the first clock at which the READ command was registered.
9. Timing tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input
timing is still referenced to VDDQ/2 or to the crossing point for CK/CK#. The output tim-
ing reference voltage level is VDDQ/2.
10. Clock frequency change is only permitted during clock stop, power-down, or self refresh
mode.
11. In cases where the device is in self refresh mode for tCKE, tCKE starts at the rising edge
of the clock and ends when CKE transitions HIGH.
12. tDAL = (tWR/tCK) + (tRP/tCK): for each term, if not already an integer, round up to the
next highest integer.
2Gb: x16, x32 Automotive LPDDR SDRAM
Electrical Specifications – AC Operating Conditions
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13. Referenced to each output group: for x16, LDQS with DQ[7:0]; and UDQS with DQ[15:8].
For x32, DQS0 with DQ[7:0]; DQS1 with DQ[15:8]; DQS2 with DQ[23:16]; and DQS3 with
DQ[31:24].
14. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the
DQ/DM/DQS slew rate is less than 1.0 V/ns, timing must be derated: 50ps must be added
to tDS and tDH for each 100 mV/ns reduction in slew rate. If the slew rate exceeds 4 V/ns,
functionality is uncertain.
15. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and ad-
dresses) are measured between VIL(DC) to VIH(AC) for rising input signals and VIH(DC) to
VIL(AC) for falling input signals.
16. These parameters guarantee device timing but are not tested on each device.
17. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ,
and tQH (tHP - tQHS). The data valid window derates directly proportional with the clock
duty cycle and a practical data valid window can be derived. The clock is provided a
maximum duty cycle variation of 45/55. Functionality is uncertain when operating be-
yond a 45/55 ratio.
18. tHP (MIN) is the lesser of tCL (MIN) and tCH (MIN) actually applied to the device CK and
CK# inputs, collectively.
19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions.
These parameters are not referenced to a specific voltage level, but specify when the
device output is no longer driving (tHZ) or begins driving (tLZ).
20. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition.
21. Fast command/address input slew rate 1 V/ns. Slow command/address input slew rate
0.5 V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated: tIS has an addi-
tional 50ps per each 100 mV/ns reduction in slew rate from the 0.5 V/ns. tIH has 0ps add-
ed, therefore, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is un-
certain.
22. READs and WRITEs with auto precharge must not be issued until tRAS (MIN) can be satis-
fied prior to the internal PRECHARGE command being issued.
23. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-
cesses to a particular row address may result in reduction of the product lifetime and/or
reduction in data retention ability.
24. This is not a device limit. The device will operate with a negative value, but system per-
formance could be degraded due to bus turnaround.
25. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command.
The case shown (DQS going from High-Z to logic low) applies when no WRITEs were
previously in progress on the bus. If a previous WRITE was in progress, DQS could be
HIGH during this time, depending on tDQSS.
26. The maximum limit for this parameter is not a device limit. The device will operate with
a greater value for this parameter, but system performance (bus turnaround) will de-
grade accordingly.
27. At least 1 clock cycle is required during tWR time when in auto precharge mode.
28. Clock must be toggled a minimum of two times during the tXSR period.
29. For the Automotive Temperature parts, tREF = tREF /2 and tREF I = tREF I/2 .
2Gb: x16, x32 Automotive LPDDR SDRAM
Electrical Specifications – AC Operating Conditions
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Output Drive Characteristics
Table 13: Target Output Drive Characteristics (Full Strength)
Notes 1–2 apply to all values; characteristics are specified under best and worst process variations/conditions
Voltage (V)
Pull-Down Current (mA) Pull-Up Current (mA)
Min Max Min Max
0.00 0.00 0.00 0.00 0.00
0.10 2.80 18.53 –2.80 –18.53
0.20 5.60 26.80 –5.60 –26.80
0.30 8.40 32.80 –8.40 –32.80
0.40 11.20 37.05 –11.20 –37.05
0.50 14.00 40.00 –14.00 –40.00
0.60 16.80 42.50 –16.80 –42.50
0.70 19.60 44.57 –19.60 –44.57
0.80 22.40 46.50 –22.40 –46.50
0.85 23.80 47.48 –23.80 –47.48
0.90 23.80 48.50 –23.80 –48.50
0.95 23.80 49.40 –23.80 –49.40
1.00 23.80 50.05 –23.80 –50.05
1.10 23.80 51.35 –23.80 –51.35
1.20 23.80 52.65 –23.80 –52.65
1.30 23.80 53.95 –23.80 –53.95
1.40 23.80 55.25 –23.80 –55.25
1.50 23.80 56.55 –23.80 –56.55
1.60 23.80 57.85 –23.80 –57.85
1.70 23.80 59.15 –23.80 –59.15
1.80 60.45 –60.45
1.90 61.75 –61.75
Notes: 1. Based on nominal impedance of 25Ω (full strength) at VDDQ/2.
2. The full variation in driver current from minimum to maximum, due to process, voltage,
and temperature, will lie within the outer bounding lines of the I-V curves.
2Gb: x16, x32 Automotive LPDDR SDRAM
Output Drive Characteristics
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Table 14: Target Output Drive Characteristics (Three-Quarter Strength)
Notes 1–3 apply to all values; characteristics are specified under best and worst process variations/conditions
Voltage (V)
Pull-Down Current (mA) Pull-Up Current (mA)
Min Max Min Max
0.00 0.00 0.00 0.00 0.00
0.10 1.96 12.97 –1.96 –12.97
0.20 3.92 18.76 –3.92 –18.76
0.30 5.88 22.96 –5.88 –22.96
0.40 7.84 25.94 –7.84 –25.94
0.50 9.80 28.00 –9.80 –28.00
0.60 11.76 29.75 –11.76 –29.75
0.70 13.72 31.20 –13.72 –31.20
0.80 15.68 32.55 –15.68 –32.55
0.85 16.66 33.24 –16.66 –33.24
0.90 16.66 33.95 –16.66 –33.95
0.95 16.66 34.58 –16.66 –34.58
1.00 16.66 35.04 –16.66 –35.04
1.10 16.66 35.95 –16.66 –35.95
1.20 16.66 36.86 –16.66 –36.86
1.30 16.66 37.77 –16.66 –37.77
1.40 16.66 38.68 –16.66 –38.68
1.50 16.66 39.59 –16.66 –39.59
1.60 16.66 40.50 –16.66 –40.50
1.70 16.66 41.41 –16.66 –41.41
1.80 42.32 –42.32
1.90 43.23 –43.23
Notes: 1. Based on nominal impedance of 37Ω (three-quarter drive strength) at VDDQ/2.
2. The full variation in driver current from minimum to maximum, due to process, voltage,
and temperature, will lie within the outer bounding lines of the I-V curves.
3. Contact factory for availability of three-quarter drive strength.
2Gb: x16, x32 Automotive LPDDR SDRAM
Output Drive Characteristics
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Table 15: Target Output Drive Characteristics (One-Half Strength)
Notes 1–3 apply to all values; characteristics are specified under best and worst process variations/conditions
Voltage (V)
Pull-Down Current (mA) Pull-Up Current (mA)
Min Max Min Max
0.00 0.00 0.00 0.00 0.00
0.10 1.27 8.42 –1.27 –8.42
0.20 2.55 12.30 –2.55 –12.30
0.30 3.82 14.95 –3.82 –14.95
0.40 5.09 16.84 –5.09 –16.84
0.50 6.36 18.20 –6.36 –18.20
0.60 7.64 19.30 –7.64 –19.30
0.70 8.91 20.30 –8.91 –20.30
0.80 10.16 21.20 –10.16 –21.20
0.85 10.80 21.60 –10.80 –21.60
0.90 10.80 22.00 –10.80 –22.00
0.95 10.80 22.45 –10.80 –22.45
1.00 10.80 22.73 –10.80 –22.73
1.10 10.80 23.21 –10.80 –23.21
1.20 10.80 23.67 –10.80 –23.67
1.30 10.80 24.14 –10.80 –24.14
1.40 10.80 24.61 –10.80 –24.61
1.50 10.80 25.08 –10.80 –25.08
1.60 10.80 25.54 –10.80 –25.54
1.70 10.80 26.01 –10.80 –26.01
1.80 26.48 –26.48
1.90 26.95 –26.95
Notes: 1. Based on nominal impedance of 55Ω (one-half drive strength) at VDDQ/2.
2. The full variation in driver current from minimum to maximum, due to process, voltage,
and temperature, will lie within the outer bounding lines of the I-V curves.
3. The I-V curve for one-quarter drive strength is approximately 50% of one-half drive
strength.
2Gb: x16, x32 Automotive LPDDR SDRAM
Output Drive Characteristics
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Functional Description
The Mobile LPDDR SDRAM uses a double data rate architecture to achieve high-speed
operation. The double data rate architecture is essentially a 2n-prefetch architecture,
with an interface designed to transfer two data words per clock cycle at the I/O. Single
read or write access for the device consists of a single 2n-bit-wide, one-clock-cycle data
transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-
cycle data transfers at the I/O.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the device during READs
and by the memory controller during WRITEs. DQS is edge-aligned with data for READs
and center-aligned with data for WRITEs. The x16 device has two data strobes, one for
the lower byte and one for the upper byte; the x32 device has four data strobes, one per
byte.
The LPDDR device operates from a differential clock (CK and CK#); the crossing of CK
going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Read and write accesses to the device are burst-oriented; accesses start at a selected lo-
cation and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, followed by a
READ or WRITE command. The address bits registered coincident with the ACTIVE
command are used to select the bank and row to be accessed. The address bits regis-
tered coincident with the READ or WRITE command are used to select the starting col-
umn location for the burst access.
The device provides for programmable READ or WRITE burst lengths of 2, 4, 8, or 16. An
auto precharge function can be enabled to provide a self-timed row precharge that is
initiated at the end of the burst access.
As with standard DDR SDRAM, the pipelined, multibank architecture of LPDDR sup-
ports concurrent operation, thereby providing high effective bandwidth by hiding row
precharge and activation time.
An auto refresh mode is provided, along with a power-saving power-down mode. Deep
power-down mode is offered to achieve maximum power reduction by eliminating the
power of the memory array. Data will not be retained after the device enters deep pow-
er-down mode.
Two self refresh features, temperature-compensated self refresh (TCSR) and partial-ar-
ray self refresh (PASR), offer additional power savings. TCSR is controlled by the auto-
matic on-chip temperature sensor. PASR can be customized using the extended mode
register settings. The two features can be combined to achieve even greater power sav-
ings.
The DLL that is typically used on standard DDR devices is not necessary on LPDDR de-
vices. It has been omitted to save power.
2Gb: x16, x32 Automotive LPDDR SDRAM
Functional Description
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Commands
A quick reference for available commands is provided in Table 16 and Table 17 (page
37), followed by a written description of each command. Three additional truth tables
(Table 18 (page 43), Table 19 (page 45), and Table 20 (page 47)) provide CKE com-
mands and current/next state information.
Table 16: Truth Table – Commands
CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN; all states and sequences not shown
are reserved and/or illegal
Name (Function) CS# RAS# CAS# WE# Address Notes
DESELECT (NOP) H X X X X 1
NO OPERATION (NOP) L H H H X 1
ACTIVE (select bank and activate row) L L H H Bank/row 2
READ (select bank and column, and start READ burst) L H L H Bank/column 3
WRITE (select bank and column, and start WRITE burst) L H L L Bank/column 3
BURST TERMINATE or DEEP POWER-DOWN (enter deep
power-down mode)
L H H L X 4, 5
PRECHARGE (deactivate row in bank or banks) L L H L Code 6
AUTO REFRESH (refresh all or single bank) or SELF RE-
FRESH (enter self refresh mode)
L L L H X 7, 8
LOAD MODE REGISTER L L L L Op-code 9
Notes: 1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide bank address and A[0:I] provide row address (where I = the most sig-
nificant address bit for each configuration).
3. BA0–BA1 provide bank address; A[0:I] provide column address (where I = the most sig-
nificant address bit for each configuration); A10 HIGH enables the auto precharge fea-
ture (nonpersistent); A10 LOW disables the auto precharge feature.
4. Applies only to READ bursts with auto precharge disabled; this command is undefined
and should not be used for READ bursts with auto precharge enabled and for WRITE
bursts.
5. This command is a BURST TERMINATE if CKE is HIGH and DEEP POWER-DOWN if CKE is
LOW.
6. A10 LOW: BA0–BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.”
7. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
8. Internal refresh counter controls row addressing; in self refresh mode all inputs and I/Os
are “Don’t Care” except for CKE.
9. BA0–BA1 select the standard mode register, extended mode register, or status register.
2Gb: x16, x32 Automotive LPDDR SDRAM
Commands
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Table 17: DM Operation Truth Table
Name (Function) DM DQ Notes
Write enable L Valid 1, 2
Write inhibit H X 1, 2
Notes: 1. Used to mask write data; provided coincident with the corresponding data.
2. All states and sequences not shown are reserved and/or illegal.
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the device. Operations already in progress are not affected.
NO OPERATION
The NO OPERATION (NOP) command is used to instruct the selected device to perform
a NOP. This prevents unwanted commands from being registered during idle or wait
states. Operations already in progress are not affected.
LOAD MODE REGISTER
The mode registers are loaded via inputs A[0:n]. See mode register descriptions in
Standard Mode Register and Extended Mode Register. The LOAD MODE REGISTER
command can only be issued when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to activate a row in a particular bank for a subsequent
access. The values on the BA0 and BA1 inputs select the bank, and the address provided
on inputs A[0:n] selects the row. This row remains active for accesses until a PRE-
CHARGE command is issued to that bank. A PRECHARGE command must be issued be-
fore opening a different row in the same bank.
2Gb: x16, x32 Automotive LPDDR SDRAM
Commands
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Figure 10: ACTIVE Command
CS#
WE#
CAS#
RAS#
CKE
Address Row
HIGH
BA0, BA1 Bank
CK
CK#
Don’t Care
READ
The READ command is used to initiate a burst read access to an active row. The values
on the BA0 and BA1 inputs select the bank; the address provided on inputs A[I:0] (where
I = the most significant column address bit for each configuration) selects the starting
column location. The value on input A10 determines whether auto precharge is used. If
auto precharge is selected, the row being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row will remain open for subsequent
accesses.
2Gb: x16, x32 Automotive LPDDR SDRAM
Commands
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Figure 11: READ Command
CS#
WE#
CAS#
RAS#
CKE
Column
Address
A10
BA0, BA1
HIGH
EN AP
DIS AP
Bank
CK
CK#
Don’t Care
Note: 1. EN AP = enable auto precharge; DIS AP = disable auto precharge.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The values
on the BA0 and BA1 inputs select the bank; the address provided on inputs A[I:0] (where
I = the most significant column address bit for each configuration) selects the starting
column location. The value on input A10 determines whether auto precharge is used. If
auto precharge is selected, the row being accessed will be precharged at the end of the
WRITE burst; if auto precharge is not selected, the row will remain open for subsequent
accesses. Input data appearing on the DQ is written to the memory array, subject to the
DM input logic level appearing coincident with the data. If a given DM signal is regis-
tered LOW, the corresponding data will be written to memory; if the DM signal is regis-
tered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be
executed to that byte/column location.
If a WRITE or a READ is in progress, the entire data burst must be complete prior to
stopping the clock (see Clock Change Frequency (page 96)). A burst completion for
WRITEs is defined when the write postamble and tWR or tWTR are satisfied.
2Gb: x16, x32 Automotive LPDDR SDRAM
Commands
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Figure 12: WRITE Command
CS#
WE#
CAS#
RAS#
CKE
Column
A10
BA0, BA1
HIGH
EN AP
DIS AP
Bank
CK
CK#
Don’t Care
Address
Note: 1. EN AP = enable auto precharge; DIS AP = disable auto precharge.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is issued. Input A10 determines
whether one or all banks will be precharged, and in the case where only one bank is pre-
charged, inputs BA0 and BA1 select the bank. Otherwise, BA0 and BA1 are treated as
“Don’t Care.” After a bank has been precharged, it is in the idle state and must be acti-
vated prior to any READ or WRITE commands being issued to that bank.
2Gb: x16, x32 Automotive LPDDR SDRAM
Commands
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Figure 13: PRECHARGE Command
CS#
WE#
CAS#
RAS#
CKE
A10
BA0, BA1
HIGH
All banks
Single bank
Bank
CK
CK#
Don’t Care
Address
Note: 1. If A10 is HIGH, bank address becomes “Don’t Care.”
BURST TERMINATE
The BURST TERMINATE command is used to truncate READ bursts with auto pre-
charge disabled. The most recently registered READ command prior to the BURST TER-
MINATE command will be truncated, as described in READ Operation. The open page
from which the READ was terminated remains open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the device and is analogous to
CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH com-
mand is nonpersistent and must be issued each time a refresh is required.
Addressing is generated by the internal refresh controller. This makes the address bits a
“Don’t Care” during an AUTO REFRESH command.
For improved efficiency in scheduling and switching between tasks, some flexibility in
the absolute refresh interval is provided. The auto refresh period begins when the AUTO
REFRESH command is registered and ends tRFC later.
2Gb: x16, x32 Automotive LPDDR SDRAM
Commands
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SELF REFRESH
The SELF REFRESH command is used to place the device in self refresh mode; self re-
fresh mode is used to retain data in the memory device while the rest of the system is
powered down. When in self refresh mode, the device retains data without external
clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command,
except that CKE is disabled (LOW). After the SELF REFRESH command is registered, all
inputs to the device become “Don’t Care” with the exception of CKE, which must re-
main LOW.
Micron recommends that, prior to self refresh entry and immediately upon self refresh
exit, the user perform a burst auto refresh cycle for the number of refresh rows. Alterna-
tively, if a distributed refresh pattern is used, this pattern should be immediately re-
sumed upon self refresh exit.
DEEP POWER-DOWN
The DEEP POWER-DOWN (DPD) command is used to enter DPD mode, which achieves
maximum power reduction by eliminating the power to the memory array. Data will not
be retained when the device enters DPD mode. The DPD command is the same as a
BURST TERMINATE command with CKE LOW.
Figure 14: DEEP POWER-DOWN Command
CS#
WE#
CAS#
RAS#
CKE
Address
BA0, BA1
CK
CK#
Don’t Care
2Gb: x16, x32 Automotive LPDDR SDRAM
Commands
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Truth Tables
Table 18: Truth Table – Current State Bank n – Command to Bank n
Notes 1–6 apply to all parameters in this table
Current State CS# RAS# CAS# WE# Command/Action Notes
Any H X X X DESELECT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle L L H H ACTIVE (select and activate row)
L L L H AUTO REFRESH 7
L L L L LOAD MODE REGISTER 7
Row active L H L H READ (select column and start READ burst) 10
L H L L WRITE (select column and start WRITE burst) 10
L L H L PRECHARGE (deactivate row in bank or banks) 8
Read (auto pre-
charge disabled)
L H L H READ (select column and start new READ burst) 10
L H L L WRITE (select column and start WRITE burst) 10, 12
L L H L PRECHARGE (truncate READ burst, start PRECHARGE) 8
L H H L BURST TERMINATE 9
Write (auto pre-
charge disabled)
L H L H READ (select column and start READ burst) 10, 11
L H L L WRITE (select column and start new WRITE burst) 10
L L H L PRECHARGE (truncate WRITE burst, start PRECHARGE) 8, 11
Notes: 1. This table applies when CKEn - 1 was HIGH, CKEn is HIGH and after tXSR has been met (if
the previous state was self refresh), after tXP has been met (if the previous state was
power-down), or after a full initialization (if the previous state was deep power-down).
2. This table is bank-specific, except where noted (for example, the current state is for a
specific bank and the commands shown are supported for that bank when in that state).
Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated with auto precharge disabled and has not yet ter-
minated or been terminated.
Write: A WRITE burst has been initiated with auto precharge disabled and has not yet
terminated or been terminated.
4. The states listed below must not be interrupted by a command issued to the same bank.
COMMAND INHIBIT or NOP commands, or supported commands to the other bank,
must be issued on any clock edge occurring during these states. Supported commands to
any other bank are determined by that bank’s current state.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is
met. After tRP is met, the bank will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when tRCD is
met. After tRCD is met, the bank will be in the row active state.
2Gb: x16, x32 Automotive LPDDR SDRAM
Truth Tables
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Read with auto-precharge enabled: Starts with registration of a READ command with
auto precharge enabled and ends when tRP has been met. After tRP is met, the bank will
be in the idle state.
Write with auto-precharge enabled: Starts with registration of a WRITE command with
auto precharge enabled and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
5. The states listed below must not be interrupted by any executable command; DESELECT
or NOP commands must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC
is met. After tRFC is met, the device will be in the all banks idle state.
Accessing mode register: Starts with registration of a LOAD MODE REGISTER command
and ends when tMRD has been met. After tMRD is met, the device will be in the all
banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
tRP is met. After tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks need to be precharged, each must be
in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of
bank.
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
11. Requires appropriate DM masking.
12. A WRITE command can be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
2Gb: x16, x32 Automotive LPDDR SDRAM
Truth Tables
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Table 19: Truth Table – Current State Bank n – Command to Bank m
Notes 1–6 apply to all parameters in this table
Current State CS# RAS# CAS# WE# Command/Action Notes
Any H X X X DESELECT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle X X X X Any command supported to bank m
Row activating,
active, or pre-
charging
L L H H ACTIVE (select and activate row)
L H L H READ (select column and start READ burst)
L H L L WRITE (select column and start WRITE burst)
L L H L PRECHARGE
Read (auto pre-
charge disabled)
L L H H ACTIVE (select and activate row)
L H L H READ (select column and start new READ burst)
L H L L WRITE (select column and start WRITE burst) 7
L L H L PRECHARGE
Write (auto pre-
charge disabled)
L L H H ACTIVE (select and activate row)
L H L H READ (select column and start READ burst)
L H L L WRITE (select column and start new WRITE burst)
L L H L PRECHARGE
Read (with auto
precharge)
L L H H ACTIVE (select and activate row)
L H L H READ (select column and start new READ burst)
L H L L WRITE (select column and start WRITE burst) 7
L L H L PRECHARGE
Write (with auto
precharge)
L L H H ACTIVE (select and activate row)
L H L H READ (select column and start READ burst)
L H L L WRITE (select column and start new WRITE burst)
L L H L PRECHARGE
Notes: 1. This table applies when CKEn - 1 was HIGH, CKEn is HIGH and after tXSR has been met (if
the previous state was self refresh), after tXP has been met (if the previous state was
power-down) or after a full initialization (if the previous state was deep power-down).
2. This table describes alternate bank operation, except where noted (for example, the cur-
rent state is for bank n and the commands shown are those supported for issue to bank
m, assuming that bank m is in such a state that the given command is supported). Excep-
tions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated and has not yet terminated or been terminated.
3a. Both the read with auto precharge enabled state or the write with auto precharge
enabled state can be broken into two parts: the access period and the precharge period.
2Gb: x16, x32 Automotive LPDDR SDRAM
Truth Tables
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© 2013 Micron Technology, Inc. All rights reserved.
For read with auto precharge, the precharge period is defined as if the same burst was
executed with auto precharge disabled and then followed with the earliest possible
PRECHARGE command that still accesses all of the data in the burst. For write with auto
precharge, the precharge period begins when tWR ends, with tWR measured as if auto
precharge was disabled. The access period starts with registration of the command and
ends when the precharge period (or tRP) begins. This device supports concurrent auto
precharge such that when a read with auto precharge is enabled or a write with auto
precharge is enabled, any command to other banks is supported, as long as that com-
mand does not interrupt the read or write data transfer already in process. In either
case, all other related limitations apply (i.e., contention between read data and write
data must be avoided).
3b. The minimum delay from a READ or WRITE command (with auto precharge enabled)
to a command to a different bank is summarized below.
From
Command To Command
Minimum Delay
(with Concurrent Auto
Precharge)
WRITE with
Auto Precharge
READ or READ with auto precharge
WRITE or WRITE with auto pre-
charge
PRECHARGE
ACTIVE
[1 + (BL/2)] tCK + tWTR
(BL/2) tCK
1 tCK
1 tCK
READ with
Auto Precharge
READ or READ with auto precharge
WRITE or WRITE with auto pre-
charge
PRECHARGE
ACTIVE
(BL/2) × tCK
[CL + (BL/2)] tCK
1 tCK
1 tCK
4. AUTO REFRESH and LOAD MODE REGISTER commands can only be issued when all
banks are idle.
5. All states and sequences not shown are illegal or reserved.
6. Requires appropriate DM masking.
7. A WRITE command can be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
2Gb: x16, x32 Automotive LPDDR SDRAM
Truth Tables
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Table 20: Truth Table – CKE
Notes 1–4 apply to all parameters in this table
Current State CKEn - 1 CKEnCOMMANDnACTIONnNotes
Active power-down L L X Maintain active power-down
Deep power-down L L X Maintain deep power-down
Precharge power-down L L X Maintain precharge power-down
Self refresh L L X Maintain self refresh
Active power-down L H DESELECT or NOP Exit active power-down 5
Deep power-down L H DESELECT or NOP Exit deep power-down 6
Precharge power-down L H DESELECT or NOP Exit precharge power-down
Self refresh L H DESELECT or NOP Exit self refresh 5, 7
Bank(s) active H L DESELECT or NOP Active power-down entry
All banks idle H L BURST TERMINATE Deep power-down entry
All banks idle H L DESELECT or NOP Precharge power-down entry
All banks idle H L AUTO REFRESH Self refresh entry
H H See Table 19 (page 45)
H H See Table 19 (page 45)
Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previ-
ous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of
COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on each clock edge occurring during the
tXP or tXSR period.
6. After exiting deep power-down mode, a full DRAM initialization sequence is required.
7. The clock must toggle at least two times during the tXSR period.
2Gb: x16, x32 Automotive LPDDR SDRAM
Truth Tables
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State Diagram
Figure 15: Simplified State Diagram
Power
on
Power
applied
SREF
LMR AREF
SREFX
ACT
CKEL
CKEL
CKEH
CKEH
PRE
PREALL
LMR
EMR
Deep
power-
down
Self
refresh
Idle:
all banks
precharged
Row
active
Burst
terminate
READING
READING
Automatic sequence
Command sequence
WRITING
WRITE
WRITE
WRITING
WRITE A
Precharging
Active
power-
down
Precharge
power-
down
Auto
refresh
PRE
WRITE A READ A
READ A
PRE
PRE
READ A
READ
READ
BST
DPD
DPDX
READ
SRR
SRR
READ
READ
PRE
LMR
ACT = ACTIVE DPDX = Exit deep power-down READ A = READ w/ auto precharge
AREF = AUTO REFRESH EMR = LOAD EXTENDED MODE REGISTER SREF = Enter self refresh
BST = BURST TERMINATE LMR = LOAD MODE REGISTER SREFX = Exit self refresh
CKEH = Exit power-down PRE = PRECHARGE SRR = STATUS REGISTER READ
CKEL = Enter power-down PREALL = PRECHARGE all banks WRITE = WRITE w/o auto precharge
DPD = Enter deep power-down READ = READ w/o auto precharge WRITE A = WRITE w/ auto precharge
WRITE
WRITE A
2Gb: x16, x32 Automotive LPDDR SDRAM
State Diagram
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Initialization
Prior to normal operation, the device must be powered up and initialized in a prede-
fined manner. Using initialization procedures other than those specified will result in
undefined operation.
If there is an interruption to the device power, the device must be re-initialized using
the initialization sequence described below to ensure proper functionality of the device.
To properly initialize the device, this sequence must be followed:
1. The core power (VDD) and I/O power (VDDQ) must be brought up simultaneously.
It is recommended that VDD and VDDQ be from the same power source, or VDDQ
must never exceed VDD. Standard initialization requires that CKE be asserted
HIGH (see Figure 16 (page 50)). Alternatively, initialization can be completed
with CKE LOW provided that CKE transitions HIGH tIS prior to T0 (see Figure 17
(page 51)).
2. When power supply voltages are stable and the CKE has been driven HIGH, it is
safe to apply the clock.
3. When the clock is stable, a 200μs minimum delay is required by the Mobile
LPDDR prior to applying an executable command. During this time, NOP or DE-
SELECT commands must be issued on the command bus.
4. Issue a PRECHARGE ALL command.
5. Issue NOP or DESELECT commands for at least tRP time.
6. Issue an AUTO REFRESH command followed by NOP or DESELECT commands
for at least tRFC time. Issue a second AUTO REFRESH command followed by NOP
or DESELECT commands for at least tRFC time. Two AUTO REFRESH commands
must be issued. Typically, both of these commands are issued at this stage as de-
scribed above.
7. Using the LOAD MODE REGISTER command, load the standard mode register as
desired.
8. Issue NOP or DESELECT commands for at least tMRD time.
9. Using the LOAD MODE REGISTER command, load the extended mode register to
the desired operating modes. Note that the sequence in which the standard and
extended mode registers are programmed is not critical.
10. Issue NOP or DESELECT commands for at least tMRD time.
After steps 1–10 are completed, the device has been properly initialized and is ready to
receive any valid command.
2Gb: x16, x32 Automotive LPDDR SDRAM
Initialization
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Figure 16: Initialize and Load Mode Registers
CKE
LVCMOS
HIGH LEVEL
DQ
BA0, BA1
Load standard
mode register Load extended
mode register
tMRD4
tMRD4
tRFC4tRFC4
Power-up: VDD and CK stable
T = 200µs
High-Z
DM
DQS High-Z
Address Row
A10 Row
CK
CK#
VDD
VDDQ
tCH tCL
tCK
Command1LMRNOP LMR
tIS tIH
BA0 = L,
BA1 = L BA0 = L,
BA1 = H
Op-code Op-code
tIS tIH
tIS tIH
tIS tIH
tIS tIH
Op-code Op-code
PRE
All banks
T0 T1 Ta0 Tb0 Tc0 Td0 Te0 Tf0
Don’t Care
Bank
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Notes: 1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command; AR = AUTO RE-
FRESH command; ACT = ACTIVE command.
2. NOP or DESELECT commands are required for at least 200μs.
3. Other valid commands are possible.
4. NOPs or DESELECTs are required during this time.
2Gb: x16, x32 Automotive LPDDR SDRAM
Initialization
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Figure 17: Alternate Initialization with CKE LOW
CKE LVCMOS
LOW level
CK
CK#
VDD
VDDQ
Command1LMR LMR
tIS
tIS
tCH tCL
tIH
PRE
T0 T1 Ta0 Tb0 Tc0 Td0 Te0 Tf0
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Power up: VDD and CK stable
T = 200µs
NOP
Don’t Care
Notes: 1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command; AR = AUTO RE-
FRESH command; ACT = ACTIVE command.
2. NOP or DESELECT commands are required for at least 200μs.
3. Other valid commands are possible.
2Gb: x16, x32 Automotive LPDDR SDRAM
Initialization
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Standard Mode Register
The standard mode register bit definition enables the selection of burst length, burst
type, CAS latency (CL), and operating mode, as shown in Figure 18. Reserved states
should not be used as this may result in setting the device into an unknown state or
cause incompatibility with future versions of LPDDR devices. The standard mode regis-
ter is programmed via the LOAD MODE REGISTER command (with BA0 = 0 and BA1 =
0) and will retain the stored information until it is programmed again, until the device
goes into deep power-down mode, or until the device loses power.
Reprogramming the mode register will not alter the contents of the memory, provided it
is performed correctly. The mode register must be loaded when all banks are idle and
no bursts are in progress, and the controller must wait tMRD before initiating the subse-
quent operation. Violating any of these requirements will result in unspecified opera-
tion.
Figure 18: Standard Mode Register Definition
M3 = 0
Reserved
2
4
8
16
Reserved
Reserved
Reserved
M3 = 1
Reserved
2
4
8
16
Reserved
Reserved
Reserved
M3
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst LengthCAS Latency
BT
0
A9 A7 A6 A5 A4 A3A8 A2 A1 A0
Standard mode register (Mx)
Address bus
9 7 6 5 4 38 2 1 0
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
Operating Mode
A10An ...
BA0
BA1
10...n
0
n + 1
n + 2
Mn
0
M10
0
M9
0
M8
0
Operating Mode
Normal operation
All other states reserved
0
0
1
1
Mode Register Definition
Standard mode register
Status register
Extended mode register
Reserved
Mn + 2
0
1
0
1
Mn + 1
M7
0
...
Note: 1. The integer n is equal to the most significant address bit.
2Gb: x16, x32 Automotive LPDDR SDRAM
Standard Mode Register
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Burst Length
Read and write accesses to the device are burst-oriented, and the burst length (BL) is
programmable. The burst length determines the maximum number of column loca-
tions that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4,
8, or 16 locations are available for both sequential and interleaved burst types.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap when a boundary is reached. The block is uniquely se-
lected by A[i:1] when BL = 2, by A[i:2] when BL = 4, by A[i:3] when BL = 8, and by A[i:4]
when BL = 16, where Ai is the most significant column address bit for a given configura-
tion. The remaining (least significant) address bits are used to specify the starting loca-
tion within the block. The programmed burst length applies to both READ and WRITE
bursts.
Burst Type
Accesses within a given burst can be programmed to be either sequential or interleaved
via the standard mode register.
The ordering of accesses within a burst is determined by the burst length, the burst
type, and the starting column address.
Table 21: Burst Definition Table
Burst
Length Starting Column Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
2 A0
0 0-1 0-1
1 1-0 1-0
4 A1 A0
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
8 A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
16 A3 A2 A1 A0
2Gb: x16, x32 Automotive LPDDR SDRAM
Standard Mode Register
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Table 21: Burst Definition Table (Continued)
Burst
Length Starting Column Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
0 0 0 0 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
0 0 0 1 1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E
0 0 1 0 2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D
0 0 1 1 3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C
0 1 0 0 4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B
0 1 0 1 5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A
0 1 1 0 6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9
0 1 1 1 7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8
1 0 0 0 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
1 0 0 1 9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6
1 0 1 0 A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5
1 0 1 1 B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4
1 1 0 0 C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3
1 1 0 1 D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2
1 1 1 0 E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1
1 1 1 1 F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0
CAS Latency
The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ
command and the availability of the first output data. The latency can be set to 2 or 3
clocks, as shown in Figure 19 (page 55).
For CL = 3, if the READ command is registered at clock edge n, then the data will be
nominally available at (n + 2 clocks + tAC). For CL = 2, if the READ command is regis-
tered at clock edge n, then the data will be nominally available at (n + 1 clock + tAC).
2Gb: x16, x32 Automotive LPDDR SDRAM
Standard Mode Register
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Figure 19: CAS Latency
CK
CK#
CK
CK#
T0 T1 T2 T2n T3 T3nT1n
Command
DQ
DQS
CL = 2
T0 T1 T2 T2n T3 T3n
Don’t CareTransitioning Data
READ NOP NOP NOP
Command
DQ
DQS
CL = 3
READ NOP NOP NOP
DOUT
n
DOUT
n + 1
DOUT
n + 3
DOUT
n + 2
DOUT
n
DOUT
n + 1
CL - 1 tAC
CL - 1 tAC
Operating Mode
The normal operating mode is selected by issuing a LOAD MODE REGISTER command
with bits A[n:7] each set to zero, and bits A[6:0] set to the desired values.
All other combinations of values for A[n:7] are reserved for future use. Reserved states
should not be used because unknown operation or incompatibility with future versions
may result.
2Gb: x16, x32 Automotive LPDDR SDRAM
Standard Mode Register
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Extended Mode Register
The EMR controls additional functions beyond those set by the mode registers. These
additional functions include drive strength, TCSR, and PASR.
The EMR is programmed via the LOAD MODE REGISTER command with BA0 = 0 and
BA1 = 1. Information in the EMR will be retained until it is programmed again, the de-
vice goes into deep power-down mode, or the device loses power.
Figure 20: Extended Mode Register
Extended mode
register (Ex)
Address bus
9 7 6 5 4 38 2 1
PASR TCSR1
DSOperation0
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
10...
E2
0
0
0
0
1
1
1
1
E1
0
0
1
1
0
0
1
1
E0
0
1
0
1
0
1
0
1
Partial-Array Self Refresh Coverage
Full array
1/2 array
1/4 array
Reserved
Reserved
1/8 array
1/16 array
Reserved
BA0
...
BA1
1
nn + 1n + 2 0
E10
0
...
0
En
0
E9
0
E8
0
Normal AR operation
All other states reserved
An
E6
0
0
1
1
0
0
1
1
E7
0
0
0
0
1
1
1
1
E5
0
1
0
1
0
1
0
1
Drive Strength
Full strength
1/2 strength
1/4 strength
3/4 strength
3/4 strength
Reserved
Reserved
Reserved
E7–E0
Valid
En + 2
0
0
1
1
En + 1
0
1
0
1
Mode Register Definition
Standard mode register
Status register
Extended mode register
Reserved
Notes: 1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no ef-
fect.
2. The integer n is equal to the most significant address bit.
Temperature-Compensated Self Refresh
This device includes a temperature sensor that is implemented for automatic control of
the self refresh oscillator. Programming the temperature-compensated self refresh
(TCSR) bits will have no effect on the device. The self refresh oscillator will continue to
refresh at the optimal factory-programmed rate for the device temperature.
2Gb: x16, x32 Automotive LPDDR SDRAM
Extended Mode Register
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Partial-Array Self Refresh
For further power savings during self refresh, the partial-array self refresh (PASR) feature
enables the controller to select the amount of memory to be refreshed during self re-
fresh. The refresh options include:
Full array: banks 0, 1, 2, and 3
One-half array: banks 0 and 1
One-quarter array: bank 0
One-eighth array: bank 0 with row address most significant bit (MSB) = 0
One-sixteenth array: bank 0 with row address MSB = 0 and row address MSB - 1 = 0
READ and WRITE commands can still be issued to the full array during standard opera-
tion, but only the selected regions of the array will be refreshed during self refresh. Data
in regions that are not selected will be lost.
Output Drive Strength
Because the device is designed for use in smaller systems that are typically point-to-
point connections, an option to control the drive strength of the output buffers is provi-
ded. Drive strength should be selected based on the expected loading of the memory
bus. The output driver settings are 25Ω, 37Ω, and 55Ω internal impedance for full, three-
quarter, and one-half drive strengths, respectively.
2Gb: x16, x32 Automotive LPDDR SDRAM
Extended Mode Register
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Status Read Register
The status read register (SRR) is used to read the manufacturer ID, revision ID, refresh
multiplier, width type, and density of the device, as shown in Figure 22 (page 59). The
SRR is read via the LOAD MODE REGISTER command with BA0 = 1 and BA1 = 0. The
sequence to perform an SRR command is as follows:
1. The device must be properly initialized and in the idle or all banks precharged
state.
2. Issue a LOAD MODE REGISTER command with BA[1:0] = 01 and all address pins
set to 0.
3. Wait tSRR; only NOP or DESELECT commands are supported during the tSRR
time.
4. Issue a READ command.
5. Subsequent commands to the device must be issued tSRC after the SRR READ
command is issued; only NOP or DESELECT commands are supported during
tSRC.
SRR output is read with a burst length of 2. SRR data is driven to the outputs on the first
bit of the burst, with the output being “Don’t Care” on the second bit of the burst.
Figure 21: Status Read Register Timing
Command
BA0, BA1
CK
CK#
Address
READ NOP NOP
T0 T1 T2 T3 T4 T5 T6
Don’t Care
NOP
DQS
DQ SRR
out4
tRP
tSRR tSRC
PRE1LMR NOP2NOP Valid
T8
BA0 = 1
BA1 = 0
0
Note 5
CL = 3
3
Transitioning Data
Notes: 1. All banks must be idle prior to status register read.
2. NOP or DESELECT commands are required between the LMR and READ commands
(tSRR), and between the READ and the next VALID command (tSRC).
3. CAS latency is predetermined by the programming of the mode register. CL = 3 is shown
as an example only.
4. Burst length is fixed to 2 for SRR regardless of the value programmed by the mode reg-
ister.
5. The second bit of the data-out burst is a “Don’t Care.”
2Gb: x16, x32 Automotive LPDDR SDRAM
Status Read Register
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Figure 22: Status Register Definition
Status register
I/O bus (CLK L->H edge)
9 7 6 5 4 38 2 1
Manufacturer ID
Reserved
Revision IDRefresh Rate
S12
DQ11
S11
DQ10
S10
DQ9
S9
DQ8
S8
DQ7
S7
DQ6
S6
DQ5
S5
DQ4
S4
DQ3
S3
DQ2
S2
DQ1
S1
DQ0
S0
101112
S2 S1 Manufacturer ID
Reserved
Samsung
Infineon
Elpida
Reserved
Reserved
DQ14
DQ12
S14
DQ31...DQ16
S31..S16
Reserved1
131431..16 0
S13
S3
11 1
1
11 0
1
10 1
1
10 0
1
01 1
1
01 0
1
00 1
1
00 0
1
11 1
0
11 0
0
10 1
0
10 0
0
01 1
0
01 0
0
00 1
0
00 0
0
Reserved
Reserved
Winbond
Reserved
Reserved
Reserved
Reserved
Micron
ESMT
NVM
S0
Width
Type
Density
DQ13
15
DQ15
S15
S6 S5 Revision ID
The manufacturer’s revision number starts at ‘0000’
and increments by ‘0001’ each time a change in the
specification (AC timings or feature set), IBIS (pull-
up or pull-down characteristics), or process occurs.
XX X
X
00 0
0
S4
... ... ...
...
S10 S9 Refresh Multiplier2
Reserved
Reserved
2X
1X
Reserved
11 1
11 0
10 1
10 0
01 1
01 0
00 1
00 0
0.25X
S8
S7
Device Width
32 bits
1
0
S11
16 bits
Device Type
LPDDR2
1
0
S12
LPDDR
S15 S14 Density
11 1
11 0
10 1
10 0
01 1
01 0
00 1
00 0
S13
2Gb
Reserved
Reserved
Reserved
1Gb
512Mb
256Mb
128Mb
Reserved
Notes: 1. Reserved bits should be set to 0 for future compatibility.
2. Refresh multiplier is based on the memory device on-board temperature sensor. Re-
quired average periodic refresh interval = tREFI × multiplier.
2Gb: x16, x32 Automotive LPDDR SDRAM
Status Read Register
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Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the device, a row
in that bank must be opened. This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see the ACTIVE Command figure).
After a row is opened with the ACTIVE command, a READ or WRITE command can be
issued to that row, subject to the tRCD specification.
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been precharged. The minimum time interval between
successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row access overhead. The mini-
mum time interval between successive ACTIVE commands to different banks is defined
by tRRD.
2Gb: x16, x32 Automotive LPDDR SDRAM
Bank/Row Activation
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READ Operation
READ burst operations are initiated with a READ command, as shown in Figure 11
(page 39). The starting column and bank addresses are provided with the READ com-
mand, and auto precharge is either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is precharged at the completion of the
burst. For the READ commands used in the following illustrations, auto precharge is
disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out ele-
ment will be valid nominally at the next positive or negative clock edge. Figure 23 (page
62) shows general timing for each possible CL setting.
DQS is driven by the device along with output data. The initial LOW state on DQS is
known as the read preamble; the LOW state coincident with the last data-out element is
known as the read postamble. The READ burst is considered complete when the read
postamble is satisfied.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go to High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out
window hold), and the valid data window is depicted in Figure 30 (page 69) and Figure
31 (page 70). A detailed explanation of tDQSCK (DQS transition skew to CK) and tAC
(data-out transition skew to CK) is depicted in Figure 32 (page 71).
Data from any READ burst can be truncated by a READ or WRITE command to the
same or alternate bank, by a BURST TERMINATE command, or by a PRECHARGE com-
mand to the same bank, provided that the auto precharge mode was not activated.
Data from any READ burst can be concatenated with or truncated with data from a sub-
sequent READ command. In either case, a continuous flow of data can be maintained.
The first data element from the new burst either follows the last element of a completed
burst or the last desired data element of a longer burst that is being truncated. The new
READ command should be issued x cycles after the first READ command, where x
equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 24 (page 63).
A READ command can be initiated on any clock cycle following a previous READ com-
mand. Nonconsecutive read data is shown in Figure 25 (page 64). Full-speed random
read accesses within a page (or pages) can be performed as shown in Figure 26 (page
65).
Data from any READ burst can be truncated with a BURST TERMINATE command, as
shown in Figure 27 (page 66). The BURST TERMINATE latency is equal to the READ
(CAS) latency; for example, the BURST TERMINATE command should be issued x cy-
cles after the READ command, where x equals the number of desired data element pairs
(pairs are required by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 28 (page 67). A READ burst can be followed by, or
truncated with, a PRECHARGE command to the same bank, provided that auto pre-
charge was not activated. The PRECHARGE command should be issued x cycles after
the READ command, where x equals the number of desired data element pairs. This is
shown in Figure 29 (page 68). Following the PRECHARGE command, a subsequent
2Gb: x16, x32 Automotive LPDDR SDRAM
READ Operation
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command to the same bank cannot be issued until tRP is met. Part of the row precharge
time is hidden during the access of the last data elements.
Figure 23: READ Burst
NOP NOP
DOUT n1 DOUT n + 1
NOP NOP NOPREAD
Bank a, Col n
T0 T1 T1n T2 T2n T3 T3n T4 T5
DOUT n + 2 DOUT n + 3
CK#
CK
Command
Address
DQS
DQ
CL = 2
NOP NOP NOP NOP NOPREAD
Bank a, Col n
T0 T1 T2 T2n T3 T3n T4 T5
CK#
CK
Command
Address
DQS
DQ
CL = 3
Don’t Care Transitioning Data
DOUT n DOUT n + 1 DOUT n + 2 DOUT n + 3
Notes: 1. DOUT n = data-out from column n.
2. BL = 4.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
2Gb: x16, x32 Automotive LPDDR SDRAM
READ Operation
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Figure 24: Consecutive READ Bursts
CK
CK#
CK
CK# T0 T1 T2 T3T2n T3n T4
T0 T1 T2 T3T2n T3n T4 T5T1n T4n T5n
T5
T4n T5n
Command READ NOP READ NOP NOP NOP
Address Bank,
Col n
Bank,
Col b
Command READ NOP READ NOP NOP NOP
Address Bank,
Col n
Bank,
Col b
Don’t Care Transitioning Data
DQ
DQS
CL = 2
DQ
DQS
CL = 3
DOUT
n1
DOUT
n + 1
DOUT
n + 3
DOUT
n + 2
DOUT
b
DOUT
b + 1
DOUT
b + 3
DOUT
b + 2
DOUT
n
DOUT
n + 1
DOUT
n + 3
DOUT
n + 2
DOUT
b
DOUT
b + 1
Notes: 1. DOUT n (or b) = data-out from column n (or column b).
2. BL = 4, 8, or 16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts
the first).
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
4. Example applies only when READ commands are issued to same device.
2Gb: x16, x32 Automotive LPDDR SDRAM
READ Operation
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Figure 25: Nonconsecutive READ Bursts
CK
CK# T0 T1 T2 T3T2n T3n T4 T5T1n T4n T5n T6
CK
CK# T0 T1 T2 T3T2n T3n T4 T5T1n T4n T5n T6
Command READ NOP NOP NOP NOP NOP
Address Bank,
Col n
READ
Bank,
Col b
Don’t Care Transitioning Data
DQ
DQS
CL = 2 CL = 2
Command READ NOP NOP NOP NOP NOP
Address Bank,
Col n
READ
Bank,
Col b
DQ
DQS
CL = 3 CL = 3
DOUT
n
DOUT
n + 1
DOUT
n + 3
DOUT
n + 2
DOUT
n1
DOUT
b
DOUT
n + 1
DOUT
n + 3
DOUT
n + 2
DOUT
b
DOUT
b + 1
DOUT
b + 2
Notes: 1. DOUT n (or b) = data-out from column n (or column b).
2. BL = 4, 8, or 16 (if burst is 8 or 16, the second burst interrupts the first).
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
4. Example applies when READ commands are issued to different devices or nonconsecu-
tive READs.
2Gb: x16, x32 Automotive LPDDR SDRAM
READ Operation
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Figure 26: Random Read Accesses
CK
CK# T0 T1 T2 T3T2n T3n T4 T5T1n T4n T5n
CK
CK# T0 T1 T2 T3T2n T3n T4 T5T1n T4n T5n
Command READ READ READ NOP NOP
Address Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col x
Bank,
Col b
READ
Bank,
Col g
Command
Address
READ READ READ NOP NOP
Bank,
Col n
READ
Bank,
Col g
Don’t Care Transitioning Data
DQ
DQS
CL = 2
DQ
DQS
CL = 3
DOUT
n1
DOUT
n + 1
DOUT
x + 1
DOUT
x
DOUT
b
DOUT
b + 1
DOUT
g + 1
DOUT
g
DOUT
n
DOUT
n + 1
DOUT
b
DOUT
b + 1
DOUT
x + 1
DOUT
x
Notes: 1. DOUT n (or x, b, g) = data-out from column n (or column x, column b, column g).
2. BL = 2, 4, 8, or 16 (if 4, 8, or 16, the following burst interrupts the previous).
3. READs are to an active row in any bank.
4. Shown with nominal tAC, tDQSCK, and tDQSQ.
2Gb: x16, x32 Automotive LPDDR SDRAM
READ Operation
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Figure 27: Terminating a READ Burst
CK
CK#
T0 T1 T2 T3T2n T4 T5T1n
CK
CK# T0 T1 T2 T3T2n T4 T5T3n
Command READ1BST2NOP NOP NOP NOP
Address Bank a,
Col n
Don’t Care Transitioning Data
DQ3
DQS
CL = 2
Command READ1BST2NOP NOP NOP NOP
Address
DQ3
DQS
CL = 3
DOUT
n
DOUT
n + 1
DOUT
n
DOUT
n + 1
Bank a,
Col n
Notes: 1. BL = 4, 8, or 16.
2. BST = BURST TERMINATE command; page remains open.
3. DOUT n = data-out from column n.
4. Shown with nominal tAC, tDQSCK, and tDQSQ.
5. CKE = HIGH.
2Gb: x16, x32 Automotive LPDDR SDRAM
READ Operation
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Figure 28: READ-to-WRITE
CK# T0 T1 T2 T3T2n T3n T4 T5T1n T4n T5n
CK
CK# T0 T1 T2 T3T2n T3n T4 T5T4n T5n
CK
Don’t Care Transitioning Data
Command READ1BST2NOP NOP NOP
Address Bank,
Col n
WRITE1
Bank,
Col b
DM
tDQSS
(NOM)
DQ3,4
DQS
CL = 2
Command READ1BST2NOP NOP
Address Bank,
Col n
WRITE1
Bank,
Col b
DM
tDQSS
(NOM)
DQ3,4
DQS
CL = 3
NOP
DOUT
n
DOUT
n + 1
D
IN
b + 1
DIN
b
DOUT
n
DOUT
n + 1
D
IN
b+1
D
IN
b+2
D
IN
b+3
DIN
b
Notes: 1. BL = 4 in the cases shown (applies for bursts of 8 and 16 as well; if BL = 2, the BST com-
mand shown can be NOP).
2. BST = BURST TERMINATE command; page remains open.
3. DOUT n = data-out from column n.
4. DIN b = data-in from column b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. CKE = HIGH.
2Gb: x16, x32 Automotive LPDDR SDRAM
READ Operation
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Figure 29: READ-to-PRECHARGE
CK
CK# T0 T1 T2 T3T2n T3n T4 T5T1n
CK
CK# T0 T1 T2 T3T2n T3n T4 T5T1n
Command READ1NOP PRE2NOP NOP ACT3
Address Banka,
Col n
Bank a,
(a or all)
Bank a,
Row
Banka,
Col n
Bank a,
(a or all)
Bank a,
Row
DQ4
DQS
CL = 2 tRP
READ1NOP PRE2NOP NOP ACT3
Command
Address
DQ4
DQS
CL = 3
tRP
Don’t Care Transitioning Data
DOUT
n
DOUT
n + 1
DOUT
n + 3
DOUT
n + 2
DOUT
n
DOUT
n + 1
DOUT
n + 3
DOUT
n + 2
Notes: 1. BL = 4, or an interrupted burst of 8 or 16.
2. PRE = PRECHARGE command.
3. ACT = ACTIVE command.
4. DOUT n = data-out from column n.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. READ-to-PRECHARGE equals 2 clocks, which enables 2 data pairs of data-out.
7. A READ command with auto precharge enabled, provided tRAS (MIN) is met, would
cause a precharge to be performed at x number of clock cycles after the READ com-
mand, where x = BL/2.
2Gb: x16, x32 Automotive LPDDR SDRAM
READ Operation
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Figure 30: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x16)
DQ (Last data valid)4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
LDQS3
DQ (Last data valid)4
DQ (First data no longer valid)4
DQ (First data no longer valid)4
DQ[7:0] and LDQS, collectively6
T2
T2
T2
T2n
T2n
T2n
T3
T3
T3
T3n
T3n
T3n
CK
CK#
T1 T2 T3 T4T2n T3n
tQH
5
tQH
5
tDQSQ
2
tDQSQ
2
tDQSQ
2
tDQSQ
2
Data valid
window
Data valid
window
DQ (Last data valid)7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
UDQS3
DQ (Last data valid)7
DQ (First data no longer valid)7
DQ (First data no longer valid)7
DQ[15:8] and UDQS, collectively6
T2
T2
T2
T2n
T2n
T2n
T3
T3
T3
T3n
T3n
T3n
tQH
5
tQH
5
tQH
5
tQH
5
tDQSQ
2
tDQSQ
2
tDQSQ
2
tDQSQ
2
tHP
1
tHP
1
tHP
1
tHP
1
tHP
1
tHP
1
tQH
5
tQH
5
Data valid
window
Data valid
window Data valid
window
Data valid
window
Data valid
window
Upper Byte
Lower Byte
Data valid
window
Notes: 1. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
2. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins
with DQS transition and ends with the last valid DQ transition.
3. DQ transitioning after DQS transitions define the tDQSQ window. LDQS defines the low-
er byte and UDQS defines the upper byte.
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
5. tQH is derived from tHP: tQH = tHP - tQHS.
6. The data valid window is derived for each DQS transitions and is defined as tQH - tDQSQ.
7. DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, or DQ15.
2Gb: x16, x32 Automotive LPDDR SDRAM
READ Operation
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Figure 31: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x32)
DQ (Last data valid)4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
DQS0/DQS1/DQS2/DQS3
DQ (Last data valid)
DQ (First data no longer valid)
DQ (First data no longer valid)4
DQ and DQS, collectively6,7
CK
CK#
Byte 0
Byte 1
Byte 2
Byte 3
Data valid
window
Data valid
window
Data valid
window
Data valid
window
T1 T2 T2n T3 T3n T4
tHP1
tDQSQ2,3 tDQSQ2,3 tDQSQ2,3 tDQSQ2,3
T2 T2n T3 T3n
T2 T2n T3 T3n
T2 T2n T3 T3n
tQH5tQH5tQH5
tHP1tHP1tHP1tHP1tHP1
tQH5
Notes: 1. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
2. DQ transitioning after DQS transitions define the tDQSQ window.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time; it begins with
DQS transition and ends with the last valid DQ transition.
4. Byte 0 is DQ[7:0], byte 1 is DQ[15:8], byte 2 is DQ[23:16], byte 3 is DQ[31:24].
5. tQH is derived from tHP: tQH = tHP - tQHS.
6. The data valid window is derived for each DQS transition and is tQH - tDQSQ.
7. DQ[7:0] and DQS0 for byte 0; DQ[15:8] and DQS1 for byte 1; DQ[23:16] and DQS2 for
byte 2; DQ[31:23] and DQS3 for byte 3.
2Gb: x16, x32 Automotive LPDDR SDRAM
READ Operation
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Figure 32: Data Output Timing – tAC and tDQSCK
CK
CK#
DQS or LDQS/UDQS2
T0 T1 T2 T3 T4 T5
T2n T3n T4n T5n T6
tRPST
tRPRE
tHZ
tHZ
Command NOP1NOP1NOP1
NOP1NOP1
All DQ values, collectively3T3
T2n T4n T5n
T5
tAC4 tAC4
CL = 3
NOP1
READ
T2
tLZ
tLZ
Don’t Care
T3n
T4
tDQSCK tDQSCK
Notes: 1. Commands other than NOP can be valid during this cycle.
2. DQ transitioning after DQS transitions define tDQSQ window.
3. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
4. tAC is the DQ output window relative to CK and is the long-term component of DQ
skew.
2Gb: x16, x32 Automotive LPDDR SDRAM
READ Operation
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WRITE Operation
WRITE bursts are initiated with a WRITE command, as shown in Figure 12 (page 40).
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is ena-
bled, the row being accessed is precharged at the completion of the burst. For the
WRITE commands used in the following illustrations, auto precharge is disabled. Basic
data input timing is shown in Figure 33 (page 73) (this timing applies to all WRITE op-
erations).
Input data appearing on the data bus is written to the memory array subject to the state
of data mask (DM) inputs coincident with the data. If DM is registered LOW, the corre-
sponding data will be written; if DM is registered HIGH, the corresponding data will be
ignored, and the write will not be executed to that byte/column location. DM operation
is illustrated in Figure 34 (page 74).
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be reg-
istered on successive edges of DQS. The LOW state of DQS between the WRITE com-
mand and the first rising edge is known as the write preamble; the LOW state of DQS
following the last data-in element is known as the write postamble. The WRITE burst is
complete when the write postamble and tWR or tWTR are satisfied.
The time between the WRITE command and the first corresponding rising edge of DQS
(tDQSS) is specified with a relatively wide range (75%–125% of one clock cycle). All
WRITE diagrams show the nominal case. Where the two extreme cases (that is, tDQSS
[MIN] and tDQSS [MAX]) might not be obvious, they have also been included. Figure 35
(page 75) shows the nominal case and the extremes of tDQSS for a burst of 4. Upon
completion of a burst, assuming no other commands have been initiated, the DQ will
remain High-Z and any additional input data will be ignored.
Data for any WRITE burst can be concatenated with or truncated by a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied after
either the last element of a completed burst or the last desired data element of a longer
burst that is being truncated. The new WRITE command should be issued x cycles after
the first WRITE command, where x equals the number of desired data element pairs
(pairs are required by the 2n-prefetch architecture).
Figure 36 (page 76) shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 37 (page 76). Full-speed random write accesses within a
page or pages can be performed, as shown in Figure 38 (page 77).
Data for any WRITE burst can be followed by a subsequent READ command. To follow a
WRITE without truncating the WRITE burst, tWTR should be met, as shown in Figure 39
(page 78).
Data for any WRITE burst can be truncated by a subsequent READ command, as shown
in Figure 40 (page 79). Note that only the data-in pairs that are registered prior to the
tWTR period are written to the internal array, and any subsequent data-in should be
masked with DM, as shown in Figure 41 (page 80).
Data for any WRITE burst can be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst, tWR should be met, as shown in
Figure 42 (page 81).
2Gb: x16, x32 Automotive LPDDR SDRAM
WRITE Operation
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Data for any WRITE burst can be truncated by a subsequent PRECHARGE command, as
shown in Figure 43 (page 82) and Figure 44 (page 83). Note that only the data-in
pairs that are registered prior to the tWR period are written to the internal array, and any
subsequent data-in should be masked with DM, as shown in Figure 43 (page 82) and
Figure 44 (page 83). After the PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met.
Figure 33: Data Input Timing
tDQSS
tDQSH tWPST
tDH
tDS
tDQSL
tDSS3 tDSH2tDSH2 tDSS3
CK
CK#
T01T1 T1n T2 T2n T3
DIN
b
Don’t Care
Transitioning Data
tWPRE
tWPRES
DQS4
DQ
DM5
Notes: 1. WRITE command issued at T0.
2. tDSH (MIN) generally occurs during tDQSS (MIN).
3. tDSS (MIN) generally occurs during tDQSS (MAX).
4. For x16, LDQS controls the lower byte; UDQS controls the upper byte. For x32, DQS0
controls DQ[7:0], DQS1 controls DQ[15:8], DQS2 controls DQ[23:16], and DQS3 controls
DQ[31:24].
5. For x16, LDM controls the lower byte; UDM controls the upper byte. For x32, DM0 con-
trols DQ[7:0], DM1 controls DQ[15:8], DM2 controls DQ[23:16], and DM3 controls
DQ[31:24].
2Gb: x16, x32 Automotive LPDDR SDRAM
WRITE Operation
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Figure 34: Write – DM Operation
CK
CK#
CKE
A10
BA0, BA1
tCH tCL
tIS
tIS
tIH
tIS
tIS
tIH
tIH
tIH
tIS tIH
Row
tRCD
tRAS tRP
tWR
T0 T1 T2 T3 T4 T5 T5n T6 T7 T8T4n
NOP1
Command ACTIVE
Row Col n
WRITE2NOP1
One bank
All banks
Bank xBank x
NOP1NOP1NOP11PRE3
tDQSL tDQSH tWPST
Bank x5
DQ6
DQS
DM
tDS tDH
Don’t Care Transitioning Data
Address
tWPRES tWPRE
DIN
n+2
DIN
n
NOP1
Note 4
tDQSS (NOM)
tCK
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 in the case shown.
3. PRE = PRECHARGE.
4. Disable auto precharge.
5. Bank x at T8 is “Don’t Care” if A10 is HIGH at T8.
6. DIN n = data-in from column n.
2Gb: x16, x32 Automotive LPDDR SDRAM
WRITE Operation
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Figure 35: WRITE Burst
DQS
tDQSS (MAX)
tDQSS (NOM)
tDQSS (MIN)
tDQSS
DM
DQ3
CK
CK#
Command WRITE1,2 NOP NOP
Address Bank a,
Col b
NOP
T0 T1 T2 T3T2n
DQS
DM
DQ3
DQS
DM
DQ3
DIN
b
Don’t Care Transitioning Data
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
tDQSS
tDQSS
Notes: 1. An uninterrupted burst of 4 is shown.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. DIN b = data-in for column b.
2Gb: x16, x32 Automotive LPDDR SDRAM
WRITE Operation
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Figure 36: Consecutive WRITE-to-WRITE
CK
CK#
Command WRITE1, 2 NOP WRITE1, 2 NOP NOP
Address Bank,
Col b
NOP
Bank,
Col n
T0 T1 T2 T3T2n T4 T5T4nT3nT1n
DQ3
DQS
DM
Don’t Care Transitioning Data
tDQSS (NOM)
DIN
b+1
DIN
b+2
DIN
b+3
DIN
n
DIN
n+1
DIN
n+2
DIN
n+3
DIN
b
Notes: 1. Each WRITE command can be to any bank.
2. An uninterrupted burst of 4 is shown.
3. DIN b (n) = data-in for column b (n).
Figure 37: Nonconsecutive WRITE-to-WRITE
CK
CK#
Command WRITE1, 2 NOP NOP NOP NOP
Address Bank,
Col b
Bank,
Col n
T0 T1 T2 T3T2n T4 T5T4nT1n T5n
DQ3
DQS
DM
tDQSS (NOM)
Don’t Care Transitioning Data
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DIN
n+1
DIN
n+2
DIN
n+3
WRITE1,2
DIN
n
Notes: 1. Each WRITE command can be to any bank.
2. An uninterrupted burst of 4 is shown.
3. DIN b (n) = data-in for column b (n).
2Gb: x16, x32 Automotive LPDDR SDRAM
WRITE Operation
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Figure 38: Random WRITE Cycles
tDQSS (NOM)
CK
CK#
Command WRITE1,2 NOP
Address Bank,
Col b
Bank,
Col x
Bank,
Col n
Bank,
Col g
Bank,
Col a
T0 T1 T2 T3T2n T4 T5T4nT1n T3n T5n
DQ3,4
DQS
DM
Don’t Care Transitioning Data
DIN
b’
DIN
x
DIN
x’
DIN
b
DIN
n’
DIN
a
DIN
a’
DIN
g
DIN
g’
DIN
n
WRITE1,2 WRITE1,2 WRITE1,2 WRITE1,2
Notes: 1. Each WRITE command can be to any bank.
2. Programmed BL = 2, 4, 8, or 16 in cases shown.
3. DIN b (or x, n, a, g) = data-in for column b (or x, n, a, g).
4. b' (or x, n, a, g) = the next data-in following DIN b (x, n, a, g) according to the program-
med burst order.
2Gb: x16, x32 Automotive LPDDR SDRAM
WRITE Operation
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Figure 39: WRITE-to-READ – Uninterrupting
tDQSSnom
CK
CK#
Command1WRITE2,3 NOP NOP READ NOP NOP
Address Bank a,
Col b
Bank a,
Col n
NOP
T0 T1 T2 T3T2n T4 T5T1n T6 T6n
tWTR4
CL = 2
DQ5
DQS
DM
tDQSS
tDQSSmin CL = 2
DQ5
DQS
DM
tDQSS
tDQSSmax CL = 2
DQ5
DQS
DM
tDQSS
Don’t Care Transitioning Data
T5n
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DOUT
n
DOUT
n + 1
DOUT
n
DOUT
n + 1
DOUT
n
DOUT
n + 1
Notes: 1. The READ and WRITE commands are to the same device. However, the READ and WRITE
commands may be to different devices, in which case tWTR is not required and the
READ command could be applied earlier.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. An uninterrupted burst of 4 is shown.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. DIN b = data-in for column b; DOUT n = data-out for column n.
2Gb: x16, x32 Automotive LPDDR SDRAM
WRITE Operation
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Figure 40: WRITE-to-READ – Interrupting
tDQSS (NOM)
CK
CK#
Command WRITE1,2 NOP NOP NOP NOP NOP
Address Bank a,
Col b
Bank a,
Col n
READ
T0 T1 T2 T3T2n T4 T5 T5nT1n T6 T6n
CL = 3
DQ5
DQS4
DM
tDQSS (MIN) CL = 3
DQ5
DQS4
DM
tDQSS (MAX) CL = 3
DQ5
DQS4
DM
Don’t Care Transitioning Data
tDQSS
tDQSS
tDQSS
DIN
b+1
DIN
b
DIN
b+1
DIN
b
DIN
b+1
DIN
b
DOUT
n
DOUT
n + 1
DOUT
n
DOUT
n + 1
DOUT
n
DOUT
n + 1
tWTR3
Notes: 1. An interrupted burst of 4 is shown; 2 data elements are written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. tWTR is referenced from the first positive CK edge after the last data-in pair.
4. DQS is required at T2 and T2n (nominal case) to register DM.
5. DIN b = data-in for column b; DOUT n = data-out for column n.
2Gb: x16, x32 Automotive LPDDR SDRAM
WRITE Operation
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Figure 41: WRITE-to-READ – Odd Number of Data, Interrupting
tDQSS (NOM)
CK
CK#
Command1WRITE2NOP NOP NOP NOP NOP
Address Bank a,
Col b
Bank a,
Col b
READ
T0 T1 T2 T3T2n T4 T5 T5nT1n T6 T6n
tWTR3
CL = 3
DQ5
DQS4
DM
tDQSS (MIN) CL = 3
DQ5
DQS4
DM
tDQSS (MAX) CL = 3
DQ5
DQS4
DM
Don’t Care Transitioning Data
tDQSS
tDQSS
tDQSS
DIN
b
DOUT
n
DOUT
n + 1
DIN
b
DIN
b
DOUT
n
DOUT
n + 1
DOUT
n
DOUT
n + 1
Notes: 1. An interrupted burst of 4 is shown; 1 data element is written, 3 are masked.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. tWTR is referenced from the first positive CK edge after the last data-in pair.
4. DQS is required at T2 and T2n (nominal case) to register DM.
5. DIN b = data-in for column b; DOUT n = data-out for column n.
2Gb: x16, x32 Automotive LPDDR SDRAM
WRITE Operation
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Figure 42: WRITE-to-PRECHARGE – Uninterrupting
CK
CK#
Command1WRITE2,4 NOP NOP NOP NOP
Address Bank a,
Col b
Bank
(a or all)
NOP
T0 T1 T2 T3T2n T4 T5T1n T6
DQ6
DQS
DM
DQ6
DQS
DM
DQ6
DQS
DM
Don’t Care Transitioning Data
tWR5
PRE3,4
tDQSS (NOM)
tDQSS (MIN)
tDQSS (MAX)
tDQSS
tDQSS
tDQSS
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
Notes: 1. An uninterrupted burst 4 of is shown.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. PRE = PRECHARGE.
4. The PRECHARGE and WRITE commands are to the same device. However, the PRE-
CHARGE and WRITE commands can be to different devices; in this case, tWR is not re-
quired and the PRECHARGE command can be applied earlier.
5. tWR is referenced from the first positive CK edge after the last data-in pair.
6. DIN b = data-in for column b.
2Gb: x16, x32 Automotive LPDDR SDRAM
WRITE Operation
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Figure 43: WRITE-to-PRECHARGE – Interrupting
tDQSS (NOM)
CK
CK#
Command1WRITE2NOP NOP NOP NOP
Address Bank a,
Col b
Bank
(a or all)
NOP
T0 T1 T2 T3T2n T4 T5T1n T6
DQ6
DQS5
DM
tDQSS
tDQSS (MIN)
DQ6
DQS5
DM
tDQSS
tDQSS (MAX)
DQ6
DQS5
DM
tDQSS
Don’t Care Transitioning Data
tWR4
PRE3
T4nT3n
DIN
b
DIN
b + 1
DIN
b
DIN
b + 1
DIN
b
DIN
b + 1
Notes: 1. An interrupted burst of 8 is shown; two data elements are written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. PRE = PRECHARGE.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. DQS is required at T4 and T4n to register DM.
6. DIN b = data-in for column b.
2Gb: x16, x32 Automotive LPDDR SDRAM
WRITE Operation
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Figure 44: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
tDQSS (NOM)
CK
CK#
Command1WRITE2NOP NOP NOP NOP
Address
Bank a,
Col b
Bank
(a or all)
NOP
T0 T1 T2 T3T2n T4 T5T1n T6
DQ7
DQS5, 6
DM6
tDQSS (MIN)
DQ7
DQS5, 6
DM6
tDQSS (MAX)
DQ7
DQS5, 6
DM6
tDQSS
tDQSS
tDQSS
Don’t Care Transitioning Data
DIN
b
DIN
b
DIN
b
tWR4
PRE3
T4nT3n
Notes: 1. An interrupted burst of 8 is shown; one data element is written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. PRE = PRECHARGE.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. DQS is required at T4 and T4n to register DM.
6. If a burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
7. DIN b = data-in for column b.
2Gb: x16, x32 Automotive LPDDR SDRAM
WRITE Operation
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PRECHARGE Operation
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access
some specified time (tRP) after the PRECHARGE command is issued. Input A10 deter-
mines whether one or all banks will be precharged, and in the case where only one bank
is precharged (A10 = LOW), inputs BA0 and BA1 select the bank. When all banks are pre-
charged (A10 = HIGH), inputs BA0 and BA1 are treated as “Don’t Care.” After a bank has
been precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued to that bank. A PRECHARGE command will be treated
as a NOP if there is no open row in that bank (idle state), or if the previously open row is
already in the process of precharging.
Auto Precharge
Auto precharge is a feature that performs the same individual bank PRECHARGE func-
tion described previously, without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
Auto precharge is nonpersistent; it is either enabled or disabled for each individual
READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. This earliest valid stage is determined as if an explicit PRECHARGE command
was issued at the earliest possible time without violating tRAS (MIN), as described for
each burst type in Table 19 (page 45). The READ with auto precharge enabled state or
the WRITE with auto precharge enabled state can each be broken into two parts: the ac-
cess period and the precharge period. The access period starts with registration of the
command and ends where tRP (the precharge period) begins. For READ with auto pre-
charge, the precharge period is defined as if the same burst was executed with auto pre-
charge disabled, followed by the earliest possible PRECHARGE command that still ac-
cesses all the data in the burst. For WRITE with auto precharge, the precharge period
begins when tWR ends, with tWR measured as if auto precharge was disabled. In addi-
tion, during a WRITE with auto precharge, at least one clock is required during tWR
time. During the precharge period, the user must not issue another command to the
same bank until tRP is satisfied.
This device supports tRAS lock-out. In the case of a single READ with auto precharge or
single WRITE with auto precharge issued at tRCD (MIN), the internal precharge will be
delayed until tRAS (MIN) has been satisfied.
Bank READ operations with and without auto precharge are shown in Figure 45 (page
86) and Figure 46 (page 87). Bank WRITE operations with and without auto pre-
charge are shown in Figure 47 (page 88) and Figure 48 (page 89).
Concurrent Auto Precharge
This device supports concurrent auto precharge such that when a READ with auto pre-
charge is enabled or a WRITE with auto precharge is enabled, any command to another
bank is supported, as long as that command does not interrupt the read or write data
transfer already in process. This feature enables the precharge to complete in the bank
in which the READ or WRITE with auto precharge was executed, without requiring an
2Gb: x16, x32 Automotive LPDDR SDRAM
PRECHARGE Operation
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explicit PRECHARGE command, thus freeing the command bus for operations in other
banks.
2Gb: x16, x32 Automotive LPDDR SDRAM
Auto Precharge
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Figure 45: Bank Read – With Auto Precharge
CK
CK#
CKE
A10
BA0, BA1
tCK tCH tCL
tIS
tIS
tIH
tIS
tIS
tIH
tIH
tIH
tIS tIH
Row
tRCD
tRAS
tRC
tRP
CL = 2
DM
T0 T1 T2 T3 T4 T5 T5n T6nT6 T7 T8
DQ4,5
DQS4
Case 1: tAC (MIN) and tDQSCK (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
DQ4,5
DQS4
tHZ (MAX)
NOP1
NOP1
Command ACTIVE
Row Col n
READ2
Bank x
Row
Row
Bank x
ACTIVE
Bank x
NOP1NOP1NOP1
Don’t Care Transitioning Data
Address
NOP1
tRPRE
tDQSCK (MAX)
tAC (MAX)
DOUT
n
DOUT
n + 1
DOUT
x
DOUT
x + 1
DOUT
n
DOUT
n + 1
DOUT
x
DOUT
x + 1
tDQSCK (MIN)
tAC (MIN)
tLZ (MIN)
tRPRE
tRPST
tLZ (MIN)
Note 3
tRPST
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 in the case shown.
3. Enable auto precharge.
4. Refer to Figure 30 (page 69) and Figure 31 (page 70) for detailed DQS and DQ timing.
5. DOUT n = data-out from column n.
2Gb: x16, x32 Automotive LPDDR SDRAM
Auto Precharge
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Figure 46: Bank Read – Without Auto Precharge
CK
CK#
CKE
A10
BA0, BA1
tCK tCH tCL
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
Row
tRCD
tRAS6
tRC
tRP
CL = 2
DM
T0 T1 T2 T3 T4 T5 T5n T6nT6 T7 T8
DQ7,8
DQS7
Case 1: tAC (MIN) and tDQSCK (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
DQ7,8
DQS7
tHZ (MAX)
NOP1
NOP1
Command ACTIVE
Row Col n
READ2
Bank x
Row
Row
Bank x
ACTIVE
Bank x
NOP1NOP1NOP1
Don’t Care Transitioning Data
Address
PRE3
Bank x5
tRPRE
tRPRE
tAC (MAX)
All banks
One bank
DOUT
n
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
DOUT
n
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
tLZ (MIN)
tLZ (MIN)
tDQSCK (MIN)
tAC (MIN)
tRPST
tRPST
tDQSCK (MAX)
Note 4
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 in the case shown.
3. PRE = PRECHARGE.
4. Disable auto precharge.
5. Bank x at T5 is “Don’t Care” if A10 is HIGH at T5.
6. The PRECHARGE command can only be applied at T5 if tRAS (MIN) is met.
7. Refer to Figure 30 (page 69) and Figure 31 (page 70) for DQS and DQ timing details.
8. DOUT n = data out from column n.
2Gb: x16, x32 Automotive LPDDR SDRAM
Auto Precharge
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Figure 47: Bank Write – With Auto Precharge
CK
CK#
CKE
A10
BA0, BA1
tCK tCH tCL
tIS
tIS
tIH
tIS
tIS
tIH
tIH
tIH
tIS tIH
Row
tRCD
tRAS tRP
tWR
T0 T1 T2 T3 T4 T5 T5n T6 T7 T8T4n
NOP4
NOP4
Command
Note 3
ACTIVE
Row Col n
WRITE2NOP4
Bank x
NOP4
Bank x
NOP4NOP4NOP4
tDQSL tDQSH tWPST
DQ1
DQS
DM
DIN
b
tDS tDH
tDQSS (NOM)
Don’t Care Transitioning Data
tWPRES tWPRE
Address
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 in the case shown.
3. Enable auto precharge.
4. DIN n = data-out from column n.
2Gb: x16, x32 Automotive LPDDR SDRAM
Auto Precharge
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Figure 48: Bank Write – Without Auto Precharge
CK
CK#
CKE
A10
BA0, BA1
tCK tCH tCL
tIS
tIS
tIH
tIS
tIS
tIH
tIH
tIH
tIS tIH
Row
tRCD
tRAS tRP
tWR
T0 T1 T2 T3 T4 T5 T5n T6 T7 T8T4n
NOP1NOP1
Command ACTIVE
Row Col n
WRITE2NOP1
One bank
All banks
Bank x
PRE3
Bank x
NOP1NOP1NOP1
tDQSL tDQSH tWPST
Bank x5
DQ6
DQS
DM
DIN
b
tDS
tDH Don’t Care Transitioning Data
tDQSS (NOM)
tWPRE
tWPRES
Address
Note 4
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 in the case shown.
3. PRE = PRECHARGE.
4. Disable auto precharge.
5. Bank x at T8 is “Don’t Care” if A10 is HIGH at T8.
6. DOUT n = data-out from column n.
2Gb: x16, x32 Automotive LPDDR SDRAM
Auto Precharge
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AUTO REFRESH Operation
Auto refresh mode is used during normal operation of the device and is analogous to
CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH com-
mand is nonpersistent and must be issued each time a refresh is required.
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command.
For improved efficiency in scheduling and switching between tasks, some flexibility in
the absolute refresh interval is provided. The auto refresh period begins when the AUTO
REFRESH command is registered and ends tRFC later.
Figure 49: Auto Refresh Mode
CK
CKE
CK#
Command1NOP2
ValidValid
NOP2NOP2
PRE
Row
A10
BA0, BA1 Bank(s)5Bank
AR NOP2, 3 AR4NOP2, 3 ACTIVENOP2
One bank
All banks
tCK tCH tCL
tIS
tIS
tIH
tIH
Row
(
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DM6
DQS6
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tRFC4
tRP tRFC
T0 T1 T2 T3 T4 Ta0 Tb0
Ta1 Tb1 Tb2
Don’t Care
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(
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Address
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Notes: 1. PRE = PRECHARGE; AR = AUTO REFRESH.
2. NOP commands are shown for ease of illustration; other commands may be valid during
this time. CKE must be active during clock positive transitions.
3. NOP or COMMAND INHIBIT are the only commands supported until after tRFC time; CKE
must be active during clock positive transitions.
4. The second AUTO REFRESH is not required and is only shown as an example of two
back-to-back AUTO REFRESH commands.
5. Bank x at T1 is “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than
one bank is active (for example, must precharge all active banks).
6. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
Although it is not a JEDEC requirement, CKE must be active (HIGH) during the auto re-
fresh period to provide support for future functional features. The auto refresh period
begins when the AUTO REFRESH command is registered and ends tRFC later.
2Gb: x16, x32 Automotive LPDDR SDRAM
AUTO REFRESH Operation
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SELF REFRESH Operation
The SELF REFRESH command can be used to retain data in the device while the rest of
the system is powered down. When in self refresh mode, the device retains data without
external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command, except that CKE is disabled (LOW). All command and address input signals
except CKE are “Don’t Care” during self refresh.
During self refresh, the device is refreshed as defined in the extended mode register.
(see Partial-Array Self Refresh (page 57).) An internal temperature sensor adjusts the re-
fresh rate to optimize device power consumption while ensuring data integrity. (See
Temperature-Compensated Self Refresh (page 56).)
The procedure for exiting self refresh requires a sequence of commands. First, CK must
be stable prior to CKE going HIGH. When CKE is HIGH, the device must have NOP
commands issued for tXSR to complete any internal refresh already in progress.
During SELF REFRESH operation, refresh intervals are scheduled internally and may
vary. These refresh intervals may differ from the specified tREFI time. For this reason,
the SELF REFRESH command must not be used as a substitute for the AUTO REFRESH
command.
2Gb: x16, x32 Automotive LPDDR SDRAM
SELF REFRESH Operation
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Figure 50: Self Refresh Mode
CK1
CK#
Command NOP AR3
Address
CKE1,2
Valid
DQ
DM
DQS
ValidNOP
tRP4
tCH tCL tCK
tIS
tXSR5
tIS
tIH
tIH
tIS
tIS tIH
tIS
Enter self refresh mode Exit self refresh mode
(
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(
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(
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T0 T1 Tb0Ta1
(
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(
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Don’t Care
(
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)
(
)(
)
Ta01
(
)(
)
tCKE
Notes: 1. Clock must be stable, cycling within specifications by Ta0, before exiting self refresh
mode.
2. CKE must remain LOW to remain in self refresh.
3. AR = AUTO REFRESH.
4. Device must be in the all banks idle state prior to entering self refresh mode.
5. Either a NOP or DESELECT command is required for tXSR time with at least two clock
pulses.
2Gb: x16, x32 Automotive LPDDR SDRAM
SELF REFRESH Operation
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Power-Down
Power-down is entered when CKE is registered LOW. If power-down occurs when all
banks are idle, this mode is referred to as precharge power-down; if power-down occurs
when there is a row active in any bank, this mode is referred to as active power-down.
Entering power-down deactivates all input and output buffers, including CK and CK#
and excluding CKE. Exiting power-down requires the device to be at the same voltage as
when it entered power-down and received a stable clock. Note that the power-down du-
ration is limited by the refresh requirements of the device.
When in power-down, CKE LOW must be maintained at the inputs of the device, while
all other input signals are “Don’t Care.” The power-down state is synchronously exited
when CKE is registered HIGH (in conjunction with a NOP or DESELECT command).
NOP or DESELECT commands must be maintained on the command bus until tXP is
satisfied. See Figure 57 for a detailed illustration of power-down mode.
Figure 51: Power-Down Entry (in Active or Precharge Mode)
CS#
RAS#, CAS#, WE#
CKE
CK
CK#
Don’t Care
Address
RAS#, CAS#, WE#
CS#
BA0, BA1
Or
2Gb: x16, x32 Automotive LPDDR SDRAM
Power-Down
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Figure 52: Power-Down Mode (Active or Precharge)
CK
CK#
Command Valid2NOP
Address
CKE
DQ
DM
DQS
tCK tCH tCL
tIS
tIS
tIH
tIS
tIS tIH
tIH
Enter3
power-down
mode
Exit
power-down
mode
Must not exceed refresh device limits
(
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)(
)
(
)(
)
(
)(
)
T0 T1 Ta0 Ta1 Ta2T2
NOP
Don’t Care
(
)(
)
(
)(
)
Valid
Tb1
tXP1
tCKE1
tCKE
Valid
No read/write
access in progress
Valid
(
)(
)
Notes: 1. tCKE applies if CKE goes LOW at Ta2 (entering power-down); tXP applies if CKE remains
HIGH at Ta2 (exit power-down).
2. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVE (or if
at least 1 row is already active), then the power-down mode shown is active power-
down.
3. No column accesses can be in progress when power-down is entered.
Deep Power-Down
Deep power-down (DPD) is an operating mode used to achieve maximum power reduc-
tion by eliminating power to the memory array. Data will not be retained after the de-
vice enters DPD mode.
Before entering DPD mode the device must be in the all banks idle state with no activity
on the data bus (tRP time must be met). DPD mode is entered by holding CS# and WE#
LOW with RAS# and CAS# HIGH at the rising edge of the clock while CKE is LOW. CKE
must be held LOW to maintain DPD mode. The clock must be stable prior to exiting
DPD mode. To exit DPD mode, assert CKE HIGH with either a NOP or DESELECT com-
mand present on the command bus. After exiting DPD mode, a full DRAM initialization
sequence is required.
2Gb: x16, x32 Automotive LPDDR SDRAM
Power-Down
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Figure 53: Deep Power-Down Mode
Notes: 1. Clock must be stable prior to CKE going HIGH.
2. DPD = deep power-down.
3. Upon exit of deep power-down mode, a full DRAM initialization sequence is required.
4. DQ and DQS bus may not be High-Z during this period. Packages or applications that
share the data bus are not allowed to have other activity on the data bus for 200µs after
the deep power-down exit.
2Gb: x16, x32 Automotive LPDDR SDRAM
Power-Down
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© 2013 Micron Technology, Inc. All rights reserved.
Clock Change Frequency
One method of controlling the power efficiency in applications is to throttle the clock
that controls the device. The clock can be controlled by changing the clock frequency or
stopping the clock.
The device enables the clock to change frequency during operation only if all timing pa-
rameters are met and all refresh requirements are satisfied.
The clock can be stopped altogether if there are no DRAM operations in progress that
would be affected by this change. Any DRAM operation already in process must be
completed before entering clock stop mode; this includes the following timings: tRCD,
tRP, tRFC, tMRD, tWR, and tRPST. In addition, any READ or WRITE burst in progress
must be complete. (See READ Operation and WRITE Operation.)
CKE must be held HIGH with CK = LOW and CK# = HIGH for the full duration of the
clock stop mode. One clock cycle and at least one NOP or DESELECT is required after
the clock is restarted before a valid command can be issued.
Figure 54: Clock Stop Mode
Exit clock stop mode
CKE
CK
CK#
Command
()()
()()
()()
()()
NOP NOP
Ta1 Ta2 Tb3 Tb4
Don’t Care
Address
DQ, DQS
()()
()()
()()
()()
Enter clock stop mode
(
)(
)
()()
()()
()()
()()
(
)(
)
CMD2
Valid
CMD2
Valid
NOP1
()()
()()
()()
()()
()()
()()
(
)(
)
All DRAM activities must be complete
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
Notes: 1. Prior to Ta1, the device is in clock stop mode. To exit, at least one NOP is required before
issuing any valid command.
2. Any valid command is supported; device is not in clock suspend mode.
2Gb: x16, x32 Automotive LPDDR SDRAM
Clock Change Frequency
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© 2013 Micron Technology, Inc. All rights reserved.
Revision History
Rev. I – 05/18
Added Important Notes and Warnings section for further clarification aligning to in-
dustry standards
Rev. H - 01/17
Removed non-automotive line items and speed grades. No content changes for auto-
motive line items.
Updated further tRAS, tRC footnote clarification.
Rev. G - 02/15
Added LE package and removed SA package
Rev. F - 09/14
Replaced KK package with KQ package
11/14 - corrected package typo from VFBGA to WFBGA on KQ package
Rev. E – 07/14
Updated IDD0, IDD4R, and IDD4W for WT and IT grades
Rev. D – 03/14
Added special options
Updated part numbering chart
Rev. C – 02/14
Updated Deep Power-Down Mode figure and added Note 4
Rev. B – 01/14
Corrected BQ and DD dimensions in Figure 1
Rev. B – 11/13
Replaced B7, CX, JV, KQ, MA, and MC packages with BQ, DD, KK, and SA packages co-
des
Added -48 speed grade
To Production
Rev. A – 07/13
Initial release; Reference document: 2Gb x16, x32 Automotive Mobile LPDDR SDRAM
data sheet; Doc Version: t79m_ait_aat_mobile_lpddr.pdf - Rev. A 08/12 EN; PDF:
09005aef84e25f2e; Preliminary status
2Gb: x16, x32 Automotive LPDDR SDRAM
Revision History
09005aef8541eee0
t89m_auto_lpddr.pdf - Rev. I 05/18 EN 97 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000
www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
2Gb: x16, x32 Automotive LPDDR SDRAM
Revision History
09005aef8541eee0
t89m_auto_lpddr.pdf - Rev. I 05/18 EN 98 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.