19-0030; Rev 0; 9/92 MA AAI 500ksps, 12-Bit ADCs with Track/Hold and Reference General Description The MAX120 and MAX122 complete, BICMOS, sampling 12-bit analog-to-digital converters (ADCs) combine an on- chip track/hold (T/H) and a low-drift voltage reference with fast conversion speeds and low power consumption. The T/H's 350ns acquisition time combined with the MAX120's 1.6us conversion time results in throughput rates as high as 500k samples per second (ksps). Throughput rates of 333ksps are possible with the 2.6us conversion time of the MAX122. The MAX120/MAX122 accept analog input voltages from -5V to +5V. The only external components needed are decoupling capacitors for the power-supply and refer- ence voltages. The MAX120 operates with clocks in the 0.1MHz to 8MHz frequency range. The MAX122 accepts 0.1MHz to SMHz clock frequencies. The MAX120/MAX122 employ a standard microproces- sor (uP) interface. Three-state data outputs are config- ured to operate with 12-bit data buses. Data-access and bus-release timing specifications are compatible with most popular uPs without resorting to wait states. In Features @ 12-Bit Resolution @ No Missing Codes Over Temperature @ 20ppm/C -5V Internal Reference @ 1.6us Conversion Time/500ksps Throughput (MAX120) 2.6us Conversion Time/333ksps Throughput (MAX122) @ Low Noise and Distortion: 70 dB Min SINAD; -77 dB Max THD (MAX122) # Low Power Dissipation: 210mW # Separate Track/Hold Control Input # Continuous-Conversion Mode Available @ +5V Input Range, Overvoltage Tolerant to +15V @ 24-Pin Narrow DIP, Wide SO and SSOP Packages Ordering Information addition, the MAX120/MAX122 can interface directly to a INL first in, first out (FIFO) buffer, virtually eliminating uP PART TEMP.RANGE PIN-PACKAGE 1 cg) interrupt Overhead. All logic inputs and outputs are MAX120CNG 0Cto+70C 24Narrow Plastic DIP +1 TTL/CMOS compatible. For applications requiring a - ; 4 serial interface, refer to the new MAX121. |MAX120CWG__O'C to +70"C 24 Wide SO +1 A li ti MAX120CAG OC to+70C 24SSOP 4 PP ications | MAX120C/D OC to+70C Dice* +4 Digital-Signal Processing MAX120ENG -40C 10 +85C 24 Narrow Plastic DIP. #1 Audio and Telecom Processing MAX120EWG -40C 10 +85C 24 Wide SO +1 Speech Recognition and Synthesis HighGoesd Data A Ordering Information continued on last page. Igh-opee ata Acquisition Contact factory for dice specifications. Spectrum Analysis . . P aay Functional Diagram Data Logging Systems = 2 e Vop Pin Configuration A a BUFFER gaeepernnk etn TRACK/HOLD| me OP VIEW 3k oe inf | T a 4 lier mooe [+] fs] RO | Vs Vss [2] 23] CS VREF ay DAC XID Voo [3] 22] INT/BUSY MAX122 AIN [4] AEAXLAAT() cLKiN MAX120 VREF [5] jyay7z2 [eo] CONVST AGND [6] ns} 00 J SAR si E a 01 REFERENCE | | L D10 Ls 17} 02 |) _LATCH AND mL a ee otra! |) 08 fa} ps] D4 NTIBUST {1 CONTROL LOGIC / D7 fir | 14] D5 . 1 po DGND fi2| ia} 06 | alle |g! S!/e DIP/SO/SSOP = & E MAAXILAA Maxim Integrated Products 1 Call toll free 1-800-998-8800 for free samples or literature. cc hLXVIN/OCLXVINMAX120/MAX1 22 500ksps,12-Bit ADCs with Track/Hold and Reference ABSOLUTE MAXIMUM RATINGS VpoptoDGND......... Levene s -O0.3V to +6V Operating Temperature Ranges: Vss toDGND ............ 000.00 veces +0.3V to -17V PAA Tee te sgn pundit ow alle bapa OC to +70C AINMOAGND vec come ce Fie we enced eWeek ge a bea go 8 +15V PA i yea vie V4 Fs es x go es REE -40C to +85C AGND to DGND. ..0. 0505 Seg eke daue ders bedea ae Fe HOBV REAR MGs nde o's a va a boek gs ode ead -55C to +125C Digital Inputs/Outputs toDGND........ -0.3V to (Vop + 0.3V) Storage Temperature Range .............. -65C to +160C Continuous Power Dissipation (Ta = +70C) Lead Temperature (soldering, 10sec) .............. +300C Narrow Plastic DIP (derate 13.33mMW/"C above +70C) 1067mW SO (derate 11.76mW/"C above +70C) ........... 941mW SSOP (derate 8.00mW/C above +70C) .......... 640mWw Narrow CERDIP (derate 12.50W/C above +70C).. 1000mW Stresses neces those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions tor extended periods may aifect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +4.75V to +5.25V, Vss = -10.8V to -15.75V, fcLK = 8MHz for MAX120 and S5MHz for MAX122, Ta = TMIN to TMAx, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX UNITS ACCURACY Resolution RES 12 Bits , MAX122AC/AE +3/4 12-bit no missing : a codes over temp. range | MAX120C/E, +H Differential Nonlinearity (Note 1) DNL MAX122BC/BE/BM LSB gottes over tems range | MAX120M te MAX122AC/AE +3/4 Integral Nonlinearity (Note 1) INL Se eee +1 LSB MAX120M +2 : Code 00..00 to 00..01 transition, near AIN = OV +3 LSB Bipolar Zero Error (Note 1) = monet Temperature drift +0.005 LSB/C Full-Scale Error (Notes 1, 2) pee ig adjusted for bipolar zero +8 LSB Full-Scale Temperature Drift Excluding reference +1 ppm/C Vpp only, 5V +5% +1/4 +3/4 (Change RFS Nog) | PSRR. [Vos only, -12V+10% 1/4 #1 LSB Vss only, -15V +5% +1/4 +4 ANALOG INPUT Input Range Ee) 5 Vv Input Current AIN = +5V (approximately 6kQ to REF) 2.5 mA Input Capacitance (Note 4) 10 pF Full-Power Input Bandwidth 1.6 MHz REFERENCE Output Voltage No external load, AIN = 5V, Ta = +25C -5.02 -4.98 V External Load Regulation OmA < ISINK < 5mA, AIN = OV 5 mV Temperature Drift (Note 5) lea ae ppm/'C MAX12_M +30 Q MA AXILAA500ksps, 12-Bit ADCs with Track/Hold and Reference ELECTRICAL CHARACTERISTICS (continued) (VOD = +4.75V to +5.25V, Vss = -10.8V to -15.75V, fcLK = 8MHz for MAX120 and 5MHz for MAX122, Ta = TIN to TMAX, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX| UNITS DYNAMIC PERFORMANCE (MAX120: fs = 500kHz, Ain = +5Vp-p, 100kHz; MAX122: fs = 333kHz, AIN = +5Vp-p, 50kHz Ta = +25C MAX120, MAX122 70 72 Signal-to-Noise Plus Distortion SINAD MAX122AC/AE 70 dB MAX 122BC/BE/BM 69 _ MAX120 $2077 Total Harmonic Distortion MAX 122 85-78 (First Five Harmonics) THD MAX122AC/AE vi. gB MAX122BC/BE/BM -75 Taw 28S MAX120 77 82 MAX122 78 85 Spurious-Free Dynamic Range SFDR dB MAX122AC/AE 77 | MAX122BC/BE/BM % CONVERSION TIME Synchronous tconv | 13tcLK i: is MAX122 2.60 Clock Frequency fCLK = ee zs MHz MAX122 0.1 5 DIGITAL INPUTS (CLKIN, CONVST, RD, CS) Input High Voltage VK 2.4 Vv Input Low Voltage Vit 0.8 V Input Capacitance (Note 4) 10 pF | input Current VIN = OV or VDD +5 uA DIGITAL OUTPUTS (INT/BUSY, D11-D0) Output Low Valtage : VOL ISINK = 1.6mA 0.4 Vv Output High Voltage VOH ISOURCE = 1MA 'Vop -0.5 Leakage Current ILKG VIN = OV or Vop, D11-DO 5 pA Output Capacitance (Note 4) 10 pF POWER REQUIREMENTS | Positive Supply Voltage Vop Guaranteed by supply rejection test 4.75 5.25 V Negative Supply Voltage Vss Guaranteed by supply rejection test -10.80 715.75 V Positive Supply Current (Note 6) IDD VbD = 5.25V, Vss = -15.75V, AIN = OV 9 15 mA | Negative Supply Current (Note 6) Iss VpD = 5.25V, Vss = -15.75V, AIN = OV 14 20 mA Power Dissipation (Note 6) Vpp = 5V, Vss = -12V, AIN = OV 210 315 mw Note 1: These tests are performed at Vop = 5V, Vss = -15V. Operation over supply is guaranteed by supply rejection tests. Note 2: Ideal full-scale transition is at +5V - 3/2LSB = +4.9963V, adjusted for offset error. Note 3: Supply rejection defined as change in full-scale transition voltage with the specified change in supply voltage = (FS at nominal supply) - (FS at nominal supply + tolerance), expressed in LSBs. Note 4: For design guidance only, not tested. Note 5: Temperature drift is defined as the change in output voltage from +25C to TMIN or Tmax. It is calculated as TC = (AVREEVREF)/(AT) Note 6: CS = RD = CONVST = OV, MODE = 5V SA AXIAM 3 coLXVIN/OC LXVMAX120/MAX122 500ksps,12-Bit ADCs with Track/Hold and Reference TIMING CHARACTERISTICS (Vop = +5V, Vss = -12V to -15V, 100% tested, Ta = TMIN to Tmax, unless otherwise noted.) (Note 7) PARAMETER SYMBOL | CONDITIONS oT ee UNITS MIN TYP MAX| MIN TYP MAX! MIN TYP MAX CS to RD Setup Time tcs 0 0 0 ns CS to RD Hold Time tCH 0 0 fs) ns CONVST Pulse Width tcw 30 30 30 ns RD Pulse Width trw tDA toa tDA ns Data-Access Time tDA CL = 100pF 40 75 100 120 ns Bus-Relinquish Time {DH 30 50 65 80 ns RD or CONVST to BUSY tBo CL = 50pF 30 75 100 120 | ns CLKIN to BUSY or INT {Bt C_ = 50pF 70 =110 150 180 | ns CLKIN to BUSY Low tB2 In mode 5 45 90 120 150 | ns RD to INT High tlH CL = 50pF 30 36.50 75 90 ns C (Data) = BUSY or INT to Data Valid tBD Oat BUSY) 20 30 35 ns = 50pF Acquisition Time (Note 8) tag 350 350 400 ns Aperture Delay (Note 8) tap 10 ns Aperture Jitter (Note 8) 30 ps Note 7: Control inputs specified with tr = tp = Sns (10% to 90% of +5V) and timed from a 1.6V voltage level. Output delays are measured to +0.8V if going low, or +2.4V if going high. For bus-relinquish time, a change of 0.5V is measured. See Figures 1 and 2 for load circuits. Note 8: For design guidance only, not tested. Pin Description PIN NAME FUNCTION Mode Input - hard-wire to set operational mode. 1 MODE Vpp: Single conversion, INT Output OPEN: Single conversion, BUSY Output DGND: Continuous conversions, BUSY Output 2 Vss__ | Negative Power Supply, -12V or -15V 3 Vpp | Positive Power Supply, +5V 4 AIN Sampling Analog Input, +5V bipolar input range 5 VREF | -5V Reference Output - bypass to AGND with 22uF || 0.1uF 4 MAXLAA500ksps, 12-Bit ADCs with Track/Hold and Reference Pin Description (continued) PIN NAME FUNCTION 6 AGND_ |} Analog Ground g aig D11-D0 | Three-State Data Outputs D11 (MSB) to DO (LSB) 12 DGND | Digital Ground 20 | CONVST | Convert Start Input initiates conversions on its falling edge. 21 CLKIN | Clock Input. Drive with TTL-compatible clock from 0.1MHz to 8MHz (MAX120), 0.1MHz to 5MHz (MAX122). D9 INT/BUSY Interrupt or Busy Output indicates converter status. If MODE is connected to Vop, configure for an INT output. If MODE is open or connected to DGND, configure for a BUSY output. See operational diagrams. 23 GS Chip Select Input - active low. When RD is low, enables the three-state outputs. If CONVST and RD are low, a conversion is initiated on the falling edge of CS. 24 RD Read Input - active low. When CS is low, RD enables the three-state outputs. If CONVST and CS are low, a = convsersion is initiated on the falling edge of RD. The MAX120/MAX 122 use successive approximation and input T/H circuitry to convert an analog signal to a series Detailed Description ADC Operation on = 3k VA of 12-bit digital-output codes. The control logic interfaces easily to most pPs, requiring only a few passive compo- DN DN nents for most applications. The T/H does not require an external capacitor. Figure 3 shows the MAX120/MAX122 3k = & CL in the simplest operational configuration. | 1 DGND = a Figure 4 shows the equivalent input circuit, illustrating the sampling architecture of the ADCs analog comparator. An internal buffer charges the hold capacitor to minimize the required acquisition time between conversions. The analog input appears as a 6kQ resistor in parallel with a 10pF capacitor. +5V Between conversions, the buffer input is connected to AIN through the input resistance, When a conversion starts, the buffer input disconnects from AIN, thus sampling the DGND a. High-2 to VOH (toa) and VoL to VoH (tBp) +b. High-Z to VoL (toa) and Vou to Vor (tep) Analog Input Track/Hold Figure 1, Load Circuits for Access Time input. At the end of the conversion, the buffer input ON DN reconnects to AIN, and the hold capacitor once again charges to the input voltage. 3k = 10pF 10pF The T/His in tracking mode whenever a conversion is NOT L [ [ in progress. Hold mode starts approximately 10ns after = DGND = OGND a conversion is initiated. Variation in this delay from one conversion to the next (aperture jitter) is typically 30ps. Figures 7 through 11 detail the T/H mode and interface timing for the various interface modes. MA AXLAN a. VoH to High-Z (oH) b. Vow to High-2 (tox) Figure 2. Load Circuits for Bus-Relinquish Time cc kXVW/OCLXVINMAX 120/MAX1 22 500ksps,12-Bit ADCs with Track/Hold and Reference MAAXLAA MAX120 MAX122 VF co MODE RD -15V Vss _ _& 45V Von INT/BUSY STATUS OUTPUT ANALOG INPUT AIN CLKIN ~ CLK INPUT" VREF CONVST Lb uo AGND bo - OU D1 D10 D2 _ ps b3} D8 D4} 07 DS } | DGNO om ~~ * (0. 1MH2 - 6MHz MAX120) 4 12-BIT DIGITAL QUPUTS (0.1MHz - SMH2 MAX122) SAMPLING COMPARATOR 3k TRACK gurreR HOL0 AIN + al CPACKAGE TL 10pF HOLD | 3k CswitcH _L. 2pF VREF SAR Figure 3. MAX120/MAX 122 in the Simplest Operational Mode (Continuous Conversion) Internal Reference The MAX120/MAX122 -5.00V buried-zener reference biases the internal DAC. The reference output is avail- able at the VREF pin and must be bypassed to the AGND pin with a 0.1uF ceramic capacitor in parallel with a 22uF or greater electrolytic capacitor. The elec- trolytic capacitors equivalent series resistance (ESR) must be 100mQ or less to properly compensate the reference output buffer. Sanyo's organic semiconduc- tor works well. Sanyo Video Components (USA) Phone: (619) 661-6835 FAX: (619) 661-1055 Sanyo Electric Company, LTD. (Japan) Phone: 0720-70-1005 FAX: 0720-70-1174 Sanyo Fisher Vertriebs GmbH (Germany) Phone: 06102-27041, ext. 44 FAX: 06102-27045 Proper bypassing minimizes reference noise and main- tains a low impedance at high frequencies. The internal reference output buffer can sink up to a 5mA external load. An external reference voltage can be used to overdrive the MAX120/MAX122's internal reference if it ranges from -5.05V to -5.10V and is capable of sinking a minimum of 5mA. The external VREF bypass capacitors are still re- quired. Figure 4. Equivalent Input Circuit Digital Interface External Clock The MAXK120/MAX122 require a TTL-compatible clock for proper operation. The MAX120 accepts clocks in the 0.1MHz to 8MHz frequency range when operating in modes 1-4 (see Operating Modes section). The maxi- mum clock frequency is limited to 6MHz when operating in mode 5. The MAX122 requires a 0.1MHz to SMHz clock for operation in all five modes. The minimum clock frequency for both the MAX120 and MAX122 is limited to 0.1MHz, due to the T/Hs droop rate. Clock and Control Synchronization If the clock and convert start inputs (CONVST or RD and CS - see Operating Modes section) are not synchronized, the conversion time can vary from 13 to 14 clock cycles. The successive approximation register (SAR) always changes state on the CLKIN input's rising edge. To ensure a fixed conversion time, refer to Figure 5 and the following guidelines. For a conversion time of 13 clock cycles, the convert start input(s) should go low at least 50ns before CLKINs next rising edge. For a conversion time of 14 clock cycles, the convert start input(s) should go low within 10ns of CLKIN's next rising edge. If the convert start input(s) go low from 10ns to 50ns before CLKINs next rising edge, the number of clock cycles required is undefined and can be either 13 or 14. For best analog performance, syn- chronize the convert start inputs with the clock input. MAXIM500ksps, 12-Bit ADCs with Track/Hold and Reference CONVST or C , i CLKIN THE TIMING RELATIONSHIP BETWEEN CLKIN AND CONVST OR RD DETERMINES IF A CLOCK CYCLE SLIPS OR NOT. USE THE FOLLOWING RULES: IF ck < 10ns, CONVERSION TIME = 147 CLOCK EDGES IF tck > 50ns, CONVERSION TIME = 137 CLOCK EDGES IF 10ns <tck <50ns, CONVERSION TIME IS INDETERMINATE (13 OR 14) CONVST , le CLKIN }, tew \ NT NS NGS IAMINS NS NS NS RD+CS INTBUSY aw a MODE = Von { iINT/BUSY _| ter UH MODE = OPEN toa toH tBo HIGH IMPEDANCE DATA OUT NEW DAT les {AP D11-D0 HOLD | [wy TRACK TRACK 4 a = ae Figure 5. Clock and Control Synchronization DATA OUT HIGH DATA VALID | HIGH IMPEDANCE IMPEDANCE 011-D0 Figure 6. Data-Access and Bus-Relinquish Timing Output Data Format The conversion result is output on a 12-bit data bus with a 75ns data-access time. The output data format is twos-complement. The three input control signals (CS, RD, and CONVST), the INT/BUSY converter status output, and the 12 bits of output data can interface directly to a 16-bit data bus. See Figure 6 for data-access timing. Timing and Control The MAX120/MAX122 have five operational modes as outlined in Figures 7-11 and discussed in the Operating Modes section. Full-control mode (mode 1) provides maximum control to the user for convert start and data-read operations. SA AXIM Figure 7. Full-Control Mode (Mode 1) Full-control mode is for uPs with or without wait-state capability. Stand-alone mode (mode 2) and continu- ous-conversion mode (mode 5) are for systems without uPs, or for uwP-based systems where the ADC and the uP are linked through first in, first out (FIFO) buffers or direct memory access (DMA) ports. Slow-memory mode (mode 3) is intended for uPs that can be forced into a wait state during the ADC's conversion time, ROM mode (mode 4) is for pPs that cannot be forced into a wait state. In all five operating modes, the start of a conversion is controlled by one of three digital inputs: CONVST, RD, or CS. Figure 12 shows the logic equivalent for the conversion circuitry. In any operating mode, CONVST must be low for a conversion to occur. Once the conver- sion is in progress, it cannot be restarted. Read operations are controlled by RD and CS. Both of these digital inputs must be low to read output data. The INT/BUSY output indicates the converter's status and determines when the data from the most recent conver- sion_is available. The MODE input configures the INT/BUSY output as follows: If MODE = Vpp, INT/BUSY functions as an INTER- RUPT output. In this configuration, INT/BUSY goes low when the conversion is complete and returns high after the conversion data has been read. If MODE is left open or tied to DGND, INT/BUSY functions as a BUSY output. In this case, INT/BUSY goes low at the start of a conversion and remains low until the conversion is complete and the data is available at DO-D11. oo LXVW/OC LXVMAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference cONVST , \ -e Icw 4 cuKin InT/USY DATA OUT OLD DATA NEW DATA D11-D0 D11-D0 jam} AP HOLD 7 r TRACK HOLD = - tag CLKIN 1 2 12 13 RD+CS INT/BUSY HIGH DATA OUT IMPEDANCE] tap OLD DATA lee 011-D0 011-00 HOLD TRACK TRACK /RACK HOLD - laa 4 Figure 8. Stand-Alone Mode (Mode 2) Initialization After Power-Up On power-up, the first MAX120/MAX122 conversion is valid if the following conditions are met: 1) Allow 14 clock cycles for the internal T/H to enter the track mode, plus a minimum of 350ns in the track mode for the data-acquisition time. 2) Make sure the reference voltage has settled. Allow 0.5ms for each 1yF of reference bypass capaci- tance (11ms for a 22uF capacitor). Operating Modes Mode 1: (Full-Control Mode) Figure 7 shows the timing diagram for full-control mode (mode 1). In this mode, the uP controls the conversion- start and data-read operations independently. A falling edge on CONVST places the T/H into hold mode and starts a conversion in the SAR. The conversion is complete in 13 or 14 clock cycles as discussed in the Clock and Control Synchronization section. A change in the INT/BUSY output state signals the end of a conversion as follows: If MODE = Vpp, the end of conversion is signaled by the INT/BUSY output falling edge. If MODE = OPEN or DGND, the INT/BUSY output goes low while the conversion is in progress and returns high when the conversion is complete. Figure 9. Slow-Memory Mode (Mode 3) When the conversion is complete, the data can be read without initiating a new conversion by pulling RD and CS low and leaving CONVST high. To start anew conversion without reading data, RD and CS should remain high while CONVST is driven low. To simultaneously read data and initiate a new conversion, CONVST, RD, and CS should all be pulled low. Note: Allow at least 350ns for T/H acquisition time between the end of one conversion and the beginning of the next. Mode 2: Stand-Alone Operation (MODE = OPEN, RD = CS = DGND) For systems that do not use or require full-bus interfacing, the MAX120/MAX122 can be operated in stand-alone mode directly linked to memory through DMA ports or a FIFO buffer. In stand-alone mode, a conversion is initi- ated by a falling edge on CONVST. The data outputs are always enabled; data changes at the end of a conversion as indicated by a rising edge on INT/BUSY. See Figure 8 for stand-alone mode timing. Mode 3: Slow-Memory Mode (CONVST = GND, MODE = OPEN) Taking RD and CS low places the T/H into hold mode and starts a conversion. INT/BUSY remains low while the con- version is in progress and can be used as a wait input to the uP. Data from the previous conversion appears on the data bus until the conversion end is indicated by INT/BUSY. See Figure 9 for slaw-memory mode timing. MAAXLAA500ksps, 12-Bit ADCs with Track/Hold and Reference INT/BUSY HIGH DATA OUT OLD OATA) WPEDANCE NEW DATA D11-DO HOLD | HOLD TRACK | TRACK tAPo] be tag ENABLE DIGITAL QUTPUTS = START CS _ CONVERSION RD f Q a i SINGLE SHOT | ~ ee ADC NVST JL AU ant fa BUSY SINGLE SHOT Figure 10. ROM Mode (Mode 4) INT/BUSY tgp ! NEW DATA HOLD TRACK HOLD ke tag DATA QUT OLD DATA HOLD - TRACK [ Figure 11. Continuous-Conversion Mode (Mode 5) Mode 4: ROM Mode (MODE = OPEN, CONVST = GND) In ROM mode, the MAX120/MAX122 behave like a fast- access memory location and avoid placing the yP into a wait state. Pulling RD and CS low places the T/H in hold mode, starts a conversion, and reads data from the previous conversion. Data from the first read in a se- quence is often disregarded when this interface mode is used. A second read operation accesses the first conversions result and also starts anew conversion. The time between successive read operations must be longer than the sum of the T/H acquisition time and the MAX120/MAX122 conversion time. See Figure 10 for ROM-mode timing. Mode 5: Continuous-Conversion Mode (CONVST = RD = CS = MODE = GND) For systems that do not use or require full-bus interfacing, the MAX120/MAX122 can operate in continuous-conver- MAXLAN Figure 12. Conversion-Control Logic sion mode, directly linked to memory through DMA ports or a FIFO buffer. In this mode, conversions are per- formed continuously at the rate of one conversion for every 14 clock cycles, which includes 2 clock cycles for the T/H acquisition time. To satisfy the 350ns minimum acquisition time requirement within 2 clock cycles, the MAX120's maximum clock frequency is GMHz when op- erating in mode 5. The data outputs are always enabled and "new" data appears on the output bus at the end of a conversion as indicated by the INT/BUSY output rising edge. The MODE input should be hard-wired to GND. Pulling CS, RD, or CONVST high stops conversions. See Figure 11 for continuous-conver- sion mode timing. Applications Information Using FIFO Buffers Using FIFO memory to buffer blocks of data from the MAX120 reduces uP interrupt overhead time by enabling the uP to process data while the MAX120, unassisted, writes conversion results to the FIFO. To retrieve a block of data, the uP reads from the FIFO via a read-interrupt cycle. Read and write oper- ations for the FIFO are completely asynchronous. Figure 13 shows the MAX120 operating in continuous-conversion mode - (mode 5), writing data directly into the two IDT7200 256 x 9 FIFO buffers at the rate of 428ksps. The yP is interrupted to read the accumulated data by the FIFO's halffull (HF) flag approxi mately three times per millisecond. For operation at 500ksps, use an 8MH7Z clock, and pulse CONVST at 500kHz. The full flag (FF) indicates that the FIFO is full. If this flag is ignored, data may be lost. If necessary, conversions can be inhibited by pull- ing CS, RD, or CONVST high. The FIFO's read cycle times are as fasts 15ns, satisfying most system speed requirements. The RESET input resets all data in the FIFO to zero. coLXVIN/OC LXVMAX120/MAX122 500ksps,12-Bit ADCs with Track/Hold and Reference +5V +5V -15V Vee FURT << ae ae |}]_-___ FULL FLAG eT Se ++, no F 10p1F O.1pF 0.4pF 10uF XO/HF -/}--> HALF-FULL FLAG ro. ee i Se Se F } __________ EMPTY FLAG Vob Vss ne a WS wy a Se MODE _ INT/BUSY RS 7 CS AAAXLAA IDT7200 Rhee __ MAX120 RO Dt \ D0 a0 RUN/STOP + CONVST 03 DB 08 i Xl GND 6MHz CLOCK ] CLKIN DO i DATA OUT To for] VREF aon PROCESSOR 22uF O.1pF Voc FL/RT < AGND Qo = DGND a W 2 ate i ni ES L__\\ | po Rie READ D2 RS RESET IDT7200 FJ D3 10 D8 Xl GND Figure 13. Using MAX120 with FIFO Memory For synchronous operation, the CONVST pin may be used to initiate conversions, as described in the Operat- ing Modes section (Mode 2: Stand-Alone Operation). Digital-Bus Noise lf the ADCs data bus is active during a conversion, coupling from the data pins to the ADC comparator can cause errors. Using slow-memory mode (mode 3) avoids this problem by placing the uP in a wait state during the conversion. If the data bus is active during the conver- sion in either mode 1 or 4, use three-state drivers to isolate the bus from the ADC. In ROM mode (mode 4), considerable digital noise is generated in the ADC when RD or CS go high, disabling the output buffers after a conversion is started. This noise can Cause errors if it occurs at the same instant the SAR latches a_ comparator decision. To avoid this problem, RD and CS should be active for less than 1 clock cycle. If this is not possible, RD or CS should go high coinciding with CLKIN's falling edge, since the comparator output is always latched at CLKINs rising edge. 10 Layout, Grounding, and Bypassing For best system performance, use printed circuit boards with separate analog and digital ground planes. Wire- wrap boards are not recommended. The two ground planes should be tied together at the low-impedance power-supply source, as shown in Figure 14. The board layout should ensure that digital and analog signal lines are kept separate from each other as much as possible. Do not run analog and digital (especially clock) lines parallel to one another. The ADC's high-speed comparator is sensitive to high- frequency noise in the VoD and Vss power supplies. Bypass these supplies to the analog ground plane with 0.1uF and 10uF bypass capacitors. Minimize capacitor lead lengths for best noise rejection. If the +5V power supply is very noisy, connect a 5Q resistor, as shown in Figure 14. Figure 15 shows the negative power-supply (Vss) rejection vs. frequency. Figure 16 shows the pos- itive power-supply (VDD) rejection vs. frequency, with and without the optional 5Q resistor. MMAXLAA500ksps, 12-Bit ADCs with Track/Hold and Reference FREQUENCY (Hz) Figure 15. Vss Power-Supply Rejection vs. Frequency Gain and Offset Adjustment Figure 17 plots the bipolar input/output transfer function for the MAX120/MAX122. Code transitions occur halfway between successive integer LSB values. Output coding is twos-complement binary with 1LSB = 2.44mV (10V/4096). In applications where gain (full-scale range) adjustment is required, Figure 18's circuit can be used. If both offset and gain (full-scale range) need adjustment, either of the circuits in Figures 19 and 20 can be used. Offset should be adjusted before gain for either of these circuits. MAXIM ANALOG DIGITAL SUPPLY SUPPLY 60 | | t+ | TT +15V_-15V_AGND +5V-OGND WITH PIFILTER 7 al neren 50 = 5Q to 4H a Voo MAX120 = NN +v VV VF Vp PIN = z zi X "Our T ale O.1pF ey ie OPTIONAL # N | | ae ee S N x3 PI sie He RESISTOR = 4 ~~ -15V AGND +5V DGND +5V DGND TA= 496C AL | MAXIAA DIGITAL 20 MAX120/MAX 122 CIRCUITRY is 100k FREQUENCY (Hz) Figure 14. Power-Supply Grounding Figure 16. Vop Power-Supply Rejection vs. Frequency To adjust bipolar offset with Figure 19s circuit, apply +1/2LSB (0.61mV) to the noninverting amplifier inout and a adjust R4 for output-code flicker between 0000 0000 | 0000 and 0000 0000 0001. For full scale, apply FS - 1/2LSB (2.4988V) to the amplifier input and adjust R2 so the output code flickers between 0111 1111 1110 and BS 50 0111 1111 1111. There may be some interaction be- = im tween these adjustments. The MAX120/MAX122 trans- = fer function used in conjunction with Figure 19's circuit is el mA the same as Figure 17, except the full-scale range is 8 40 MN reduced to 2.5V. ss To adjust bipolar offset with Figure 20's circuit, apply Ta=425C -1/2LSB (-1.22mV) at VIN and adjust R5 for output-code | | | | flicker between 0000 0000 0000 and 0000 0000 0001. For Te Te a? gain adjustment, apply -FS + 1/2LSB (-4.9951V) at Vin and adjust R1 so the output code flickers between 0111 11114 1110 and 0111 1111 1111. As with Figure 20's circuit, the offset and gain adjustments may interact. Figure 21 plots the transfer function for Figure 20's circuit. Dynamic Performance High-speed sampling capability and 500ksps throughput (333ksps for the MAX122) make the MAX120/MAX122 ideal for wideband-signal processing. To support these and other related applications, fast fourier transform (FFT) test techniques are used to guarantee the ADC's dynamic frequency response, distortion, and noise at the rated throughput. Specifically, this involves applying a low-dis- tortion sin wave to the ADC input and recording the digital conversion results for a specified time. The data is then analyzed using an FFT algorithm, which deter- mines its spectral content. 11 cco kXVW/O2 LXVMAX 120/MAX122 500ksps,12-Bit ADCs with Track/Hold and Reference O11... ee 000... 000... 000... TAT...0: TAT wd 111... 100... 100... VIN (+2.5V to -2.5V) TO AIN Rl 150k R? (GAIN ADJUSTMENT) R3 150k R5 +5V 5tk 1802 = (OFFSETADJUSTMENT) TO Vrer (-5V) Figure 19. Offset and Gain Adjustment (Noninverting) VIN MAN120/ P MAX122 AIn VIN (-5V to +5V) ai : | 70 AIN (GAIN ADJUSTMENT) RS 680k T z a 0 VREF (-5V) R5 20k (OFF ADJUSTMENT) Figure 18. Trim Circuit for Gain Only ADCs have traditionally been evaluated by specifications such as zero and full-scale error, integral nonlinearity (INL), and differential nonlinearity (DNL). Such parame- ters are widely accepted for specifying performance with DC and slowly varying signals, but are less useful in signal processing applications where the ADC's impact on the system transfer function is the main concern. The sig- nificance of various DC errors does not translate well to the dynamic case, so different tests are required. Signal-to-Noise Ratio and Effective Number of Bits The signal-to-noise plus distortion ratio (SINAD) is the ratio of the fundamental input frequencys RMS amplitude to the RMS amplitude of all other ADC output signals. The output band is limited to frequencies above DC and below one-half the ADC sample rate. 12 Figure 20. Offset and Gain Adjustment (inverting) The theoretical minimum ADC noise is caused by quan- tization error and is a direct result of the ADC's resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. A perfect 12-bit ADC can, therefore, do no better than 74dB. An FFT plot shows the output level in various spectral bands. Figure 22 shows the result of sampling a pure 100kHz sinusoid at a 500ksps rate with the MAX120. By transposing the equation that converts resolution to SNR, we can, from the measured SINAD, determine the effective resolution (or effective number of bits) the ADC provides: N = (SINAD - 1.76)/6.02. Figure 22 shows the effective number of bits as a function of the input frequency for the MAX120. The MAX122 performs similarly. MAXIM500ksps, 12-Bit ADCs with Track/Hold and Reference xe. Ke sy a o11...111 Hank Le 000... 000... 000... 1... iis. i ! a 100... 001+ 100... 000 t$5 Sy -4.9975V ov +5V Figure 21. Inverting Bipolar Transfer Function EFFECTIVE BITS MAX120 Fs = SOOkHz Ta=+25C 10k 100k 1M 10M INPUT FREQUENCY (Hz) 0 | | fs = 500kHz -20 fiN=100kKHz J SINAD = 72dB a Ja=425C 2 S -40 = = = -60 z 5 w -B0 [- AAR LA -100 we Vv VY yW* 0 0 50 100 150 = 200 250 FREQUENCY (kHz) Figure 22. MAX120 FFT Plot Total Harmonic Distortion Ifa pure sine wave is sampled by an ADC at greater than the Nyquist frequency, the nonlinearities in the ADC's transfer function create harmonics of the input frequency in the sampled output data. Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics (in the frequency band above DC and below one-half the sample rate, but not including the DC component) to the RMS amplitude of the fundamental frequency. This is expressed as follows: Wo24V374V47...+VN- V4 THD = 20log MA AXLM Figure 23. Effective Bits vs. Input Frequency where V1 is the fundamental RMS amplitude, and V2 to VN are the amplitudes of the 2nd through Nth harmonics. The THD specification in the Electrical Characteristics table includes the 2nd through 5th harmonics. Intermodulation Distortion lf the ADC input signal consists of more than one spectral component, the ADC transfer function non- linearities produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequency fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function create distortion products at sum and difference frequencies of mfa + nfo, where m and n = 0, 1, 2, 3, etc. THD includes those distortion products with m or n equal to zero, Intermodulation distortion consists of all distortion products for which neither m nor n equal zero. For example, the 2nd-order IMD terms include (fa + fb) and (fa - fo) while the 3rd-order IMD terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd-order IMD products can be expressed by the following formula: amplitude at (fa + =| IMD (fa + fb) = 20log amplitude at fa 13 ooLXVIN/OCLXVINMAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Spurious-Free Dynamic Range Spurious-free dynamic range is the ratio of the fundamen- tal RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually the next largest spectral component occurs at some harmonic of the input frequency. However, if the ADC is exceptionally linear, it may occur only at a random peak in the ADC's noise floor. Chip Topography test! > * 0.122" 0.118" (2,997 mm) MAX120/MAX122 TRANSISTOR COUNT 1920; SUBSTRATE CONNECTED TO Vpp. 14 _ Ordering Information (continued) (3.099 mm) PART TEMP.RANGE PIN-PACKAGE (LSBs) MAX120EAG -40C to +85C_ 24 SSOP + MAX120MRG = -55C to +125C 24NarrowCERDIP +2 MAX122ACNG 0C to +70C 24NarrowPlastic DIP +3/4 MAX122BCNG OC to +70C 24NarrowPlasticDIP +1 MAX122ACWG = OC to +70C. 24 Wide SO +3/4 MAX122BCWG O'C to +70C 24 Wide SO +1 MAX122ACAG O'C to +70C 24 SSOP 43/4 | MAX122BCAG _OC to +70C 24 SSOP +1 MAX122BC/D OC to +70C_ Dice" +1 MAX1224ENG -40C to +85C 24 .NarrowPlastic DIP +3/4 MAX122BENG_ -40C to +85C 24 NarrowPlastic DIP +1 MAX122AEWG -40C to +85C 24 Wide SO +3/4 MAX122BEWG -40C to +85C 24 WideSO +1 MAX122AEAG -40C to +85C 24 SSOP +3/4 MAX122BEAG -40C to +85C 24SSOP +1 MAX122BMRG -55C to +125C 24NarrowCERDIP #4 MAXIQEVKITDP = 0C to +70C_ Plastic DIP - Through Hole * Contact factory for dice specifications, t MAX120 EV kit can be used to evaluate the MAX 122: when ordering the EV kil, ask for a free sample of the MAX 122. JM AXIMA500ksps,12-Bit ADCs with Track/Hold and Reference Package Information DIM INCHES MILLIMETERS MIN MAX MIN MAX A = 0.200 - 5.08 a Al 0.015 = 0.38 os 0.125 | 0.150 3.18 3.81 0.055 | 0.080 1.40 2.03 0.016 | 0.022 0.41 0.56 0.050 | 0.065 L:27 1.65 0.008 | 0.012 0.20 0.30 1.235 | 1.265 | 31.37 | 32.19 0.050 0.080 1.27 2.03 0.300 | 0.325 7.62 8.26 0.240 0.280 6.10 7.11 0.100 BSC 2.54 BSC 0.300 BSC 7.62 BSC - 0.400 - 10.16 0.115 0.150 2.92 3.81 0 15 0 15 21-337A 24-PIN PLASTIC DUAL-IN-LINE (NARROW) PACKAGE INCHES MILLIMETERS DIM MIN MAX MIN MAX 0.093 | 0.104 2.35 2.65 0.004 | 0.012 0.10 0.30 0.014 | 0.019 0.35 0.49 0.009 | 0.013 0.23 0.32 0.598 | 0.614 | 15.20 | 15.60 0.291 0.299 7.40 7.60 0.050 BSC 1.27 BSC 0.394 | 0.419 | 10.00 | 10.65 0.010 | 0.030 0.25 0.75 0.016 | 0.050 0.40 1.27 O 3 0 8 21-338A oy oy on on on oy og cy oy oy oy lea 2 |rj|s|zlo |mlolo}w|z|> . hx 45 7] ~~ i . 4 24-PIN PLASTIC SMALL-OUTLINE PACKAGE MA AXLMA 15 cc LXVIW/0ELXVINMAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Package Information (continued) DIM INCHES MILLIMETERS MIN MAX MIN MAX A 0.068 0.078 1.73 1.99 Al 0.002 0.008 0.05 0.21 B 0.010 0.015 0.25 0.38 Cc 0.005 0.009 0.13 0.22 D 0.317 0.328 .807 8.33 H E | 0.205 | 0.212 | 5.20 | 5.38 e 0.0256 BSC 0.65 BSC H 0.301 0.311 7.65 7.90 L 0.022 0.037 0.55 0.95 a 0 8 o 8 21-0002A D _ oy a TY ooh - wick tape > segelbig OReae + 4 24-PIN PLASTIC a \ SHRINK . SMALL-OUTLINE PACKAGE Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time 16 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 1994 Maxim Integrated Products Printed USA MAAXIAA is a registered trademark of Maxim Integrated Products.