Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Cautions
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better
and more reliable, but th ere is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regar ding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corporation product best suited to the customer's application; they do not convey any
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Corporation or a third party.
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contained therein.
HM6216514I Series
Wide Temperature Range Version
8 M SRAM (512-kword × 16-bit)
ADE-203-1303B (Z)
Rev. 1.0
Oct. 23, 2002
Description
The Hitachi HM6216514I Series is 8-Mbit static RAM organized 524,288-word × 16-bit. HM6216514I
Series has realized higher density, higher performance and low power consumption by employing CMOS
process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is
suitable for battery backup systems. It is packaged in standard 44-pin plastic TSOPII.
Features
• Single 5.0 V supply: 5.0V ± 10 %
• Fast access time: 55 ns (Max)
• Power dissipation:
Active: 10 mW/MHz (Typ)
Standby: 7.5 µW (Typ)
• Completely static memory.
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output.
Three state output
• Battery backup operation.
• Temperature range: –40 to +85°C
HM6216514I Series
2
Ordering Information
Type No. Access time Package
HM6216514LTTI-5SL 55 ns 400-mil 44-pin plastic TSOPII (normal-bend type) (TTP-44DE)
HM62162514I Series
3
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CS
I/O0
I/O1
I/O2
I/O3
V
V
I/O4
I/O5
I/O6
I/O7
WE
A18
A17
A16
A15
A14
CC
SS
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
V
V
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
A12
A13
CC
SS
(Top view)
44-pin TSOP
Pin Description
Pin name Function
A0 to A18 Address input
I/O0 to I/O15 Data input/output
CS Chip select
WE Write enable
OE Output enable
LB Lower byte select
UB Upper byte select
VCC Power supply
VSS Ground
HM6216514I Series
4
Block Diagram
•
•
•
•
•
•
••
•
•
•
I/O0
I/O15
WE
OE
V
V
CC
SS
Row
decoder Memory matrix
2,048 x 2,048
Column I/O
Column decoder
Input
data
control
Control logic
CS
LB
UB
LSB
MSB
LSB MSB
A5
A6
A7
A4
A3
A8
A9
A10
A11
A12
A13
A15 A16 A17 A0 A2 A14
A1A18
HM62162514I Series
5
Operation Table
CS WE OE UB LB I/O0 to I/O7 I/O8 to I/O15 Operation
H ××××High-Z High-Z Standby
×××H H High-Z High-Z Standby
L H L L L Dout Dout Read
L H L H L Dout High-Z Lower byte read
L H L L H High-Z Dout Upper byte read
LL×L L Din Din Write
LL×H L Din High-Z Lower byte write
LL×L H High-Z Din Upper byte write
LHH××High-Z High-Z Output disable
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter Symbol Value Unit
Power supply voltage relative to VSS VCC –0.5 to + 7.0 V
Terminal voltage on any pin relative to VSS VT–0.5*1 to VCC + 0.3*2V
Power dissipation PT1.0 W
Storage temperature range Tstg –55 to +125 °C
Storage temperature range under bias Tbias –40 to +85 °C
Notes: 1. VT min: –3.0 V for pulse half-width ≤ 30 ns.
2. Maximum voltage is +7.0 V.
DC Operating Conditions
Parameter Symbol Min Typ Max Unit Note
Supply voltage VCC 4.5 5.0 5.5 V
VSS 000V
Input high voltage VIH 2.2 — VCC + 0.3 V
Input low voltage VIL –0.3 — 0.8 V 1
Ambient temperature range Ta –40 — 85 °C
Note: 1. VIL min: –3.0 V for pulse half-width ≤ 30 ns.
HM6216514I Series
6
DC Characteristics
Parameter Symbol Min Typ*1Max Unit Test conditions
Input leakage current |ILI| ——1 µA Vin = VSS to VCC
Output leakage current |ILO| ——1 µACS = VIH or OE = VIH or
WE = VIL or, L B = UB =V IH
,
VI/O = VSS to VCC
Operating current ICC ——20mACS = VIL, Others = VIH/VIL,
II/O = 0 mA
Average operating current ICC1 — 16 35 mA Min. cycle, duty = 100%,
II/O = 0 mA, CS = VIL,
Others = VIH/VIL
ICC2 — 2 5 mA Cycle time = 1 µs, duty = 100%,
II/O = 0 mA, CS ≤ 0.2 V,
VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V
Standby current ISB — 0.1 0.3 mA CS = VIH
Standby current ISB1 — 0.8 10 µA 0 V ≤ Vin
(1) CS ≥ VCC – 0.2 V or
(2) LB = UB ≥ VCC – 0.2 V,
CS ≤ 0.2 V
Output high voltage VOH 2.4 — — V IOH = –1 mA
Output low voltage VOL — — 0.4 V IOL = 2.1 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter Symbol Min Typ Max Unit Test conditions Note
Input capacitance Cin — — 8 pF Vin = 0 V 1
Input/output capacitance CI/O — — 10 pF VI/O = 0 V 1
Note: 1. This parameter is sampled and not 100% tested.
HM62162514I Series
7
AC Characteristics (Ta = –40 to +85°C, VCC = 5.0 V ± 10 %, unless otherwise noted.)
Test Conditions
• Input pulse levels: VIL = 0.4 V, VIH = 2.2 V
• Input rise and fall time: 5 ns
• Input and output timing reference levels: 1.5 V
• Output load: 1 TTL Gate + CL (50 pF) (Including scope and jig)
Read Cycle
HM6216514I
-5
Parameter Symbol Min Max Unit Notes
Read cycle time tRC 55 — ns
Address access time tAA —55ns
Chip select access time tACS —55ns
Output enable to output valid tOE —35ns
Output hold from address change tOH 10 — ns
LB, UB access time tBA —55ns
Chip select to output in low-Z tCLZ 10 — ns 2, 3
LB, UB enable to low-z tBLZ 5 — ns 2, 3
Output enable to output in low-Z tOLZ 5 — ns 2, 3
Chip deselect to output in high-Z tCHZ 0 20 ns 1, 2, 3
LB, UB disable to high-Z tBHZ 0 20 ns 1, 2, 3
Output disable to output in high-Z tOHZ 0 20 ns 1, 2, 3
HM6216514I Series
8
Write Cycle
HM6216514I
-5
Parameter Symbol Min Max Unit Notes
Write cycle time tWC 55 — ns
Address valid to end of write tAW 50 — ns
Chip selection to end of write tCW 50 — ns 5
Write pulse width tWP 40 — ns 4
LB, UB valid to end of write tBW 50 — ns
Address setup time tAS 0 — ns 6
Write recovery time tWR 0 — ns 7
Data to write time overlap tDW 25 — ns
Data hold from write time tDH 0—ns
Output active from end of write tOW 5 — ns 2
Output disable to output in high-Z tOHZ 0 20 ns 1, 2
Write to output in high-Z tWHZ 0 20 ns 1, 2
Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit
conditions and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device
and from device to device.
4. A write occures during the overlap of a low CS, a low WE and a low LB or a low UB. A write begins
at the latest transition among CS going low, WE going low and LB going low or UB going low. A
write ends at the earliest transition among CS going high, WE going high and LB going high or UB
going high. tWP is measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS going low to the end of write.
6. tAS is measured from the address valid to the beginning of write.
7. tWR is measured from the earliest of CS or WE going high to the end of write cycle.
HM62162514I Series
9
Timing Waveform
Read Cycle
tAA tACS
tCLZ
tBLZ
tBA
tOH
tRC
Valid data
Address
Dout
Valid address
High impedance
CS
LB, UB
OE
*1, 2, 3
*1, 2, 3
*2, 3
*2, 3
*1, 2, 3
tOLZ*2, 3
tOE
tCHZ
tBHZ
tOHZ
HM6216514I Series
10
Write Cycle (1) (WE Clock)
Address
WE
tWC
tAW
tWP*4
tWR*7
tCW*5
tBW
tAS*6
tOW*2
tWHZ*1, 2
tDW tDH
Valid address
Valid data
CS
LB, UB
Dout
Din
High impedance
HM62162514I Series
11
Write Cycle (2) (CS Clock, OE = VIH)
Address
WE
tWC
tAW
tWP*4
tWR*7
tCW*5
tBW
tAS*6
tDW tDH
Valid address
Valid data
LB, UB
Dout
Din
High impedance
CS
HM6216514I Series
12
Write Cycle (3) (LB, UB Clock, OE = VIH)
Address
WE
tWC
tAW
tWP*4
tCW*5
tBW
tWR*7
tDW tDH
Valid address
Valid data
LB, UB
Dout
Din
High impedance
CS
tAS*6
HM62162514I Series
13
Low VCC Data Retention Characteristics (Ta = –40 to +85°C)
Parameter Symbol Min Typ*2Max Unit Test conditions*1
VCC for data retention VDR 2.0 — — V Vin ≥ 0V
(1) CS ≥ VCC – 0.2 V or
(2) LB = UB ≥ VCC – 0.2 V
CS ≤ 0.2 V
Data retention current ICCDR — 0.8 10 µAV
CC = 3.0 V, Vin ≥ 0V
(1) CS ≥ VCC – 0.2 V or
(2) LB = UB ≥ VCC – 0.2 V
CS ≤ 0.2 V
Chip deselect to data retention time tCDR 0 — — ns See retention waveform
Operation recovery time tRtRC*3——ns
Notes: 1. CS controls address buffer, WE buffer, OE buffer, LB, UB buffer and Din buffer. If CS controls data
retention mode, Vin levels (address, WE, OE, LB, UB, I/O) can be in the high impedance state. If
LB, UB controls data retention mode, LB, UB must be LB = UB ≥ VCC – 0.2 V, CS must be CS ≤ 0.2
V. The other input levels (address, WE, OE, I/O) can be in the high impedance state.
2. Typical values are at VCC = 3.0 V, Ta = +25˚C and not guaranteed.
3. tRC = read cycle time.
HM6216514I Series
14
Low VCC Data Retention Timing Waveform (1) (CS Controlled)
CC
V
2.2 V
4.5 V
0 V
CS
tCDR tR
CS V – 0.2 V
CC
≥
DR
V
Data retention mode
Low VCC Data Retention Timing Waveform (2) (LB, UB Controlled)
CC
V
2.2 V
4.5 V
0 V
LB, UB
tCDR tR
LB, UB V – 0.2 V
CC
≥
DR
V
Data retention mode
HM62162514I Series
15
Package Dimensions
HM6216514LTTI Series (TTP-44DE)
Hitachi Code
JEDEC
JEITA
Mass
(reference value)
TTP-44DE
—
—
0.43 g
*Dimension including the plating thickness
Base material dimension
0.13 M
0.10
0.80
44 23
122
18.41
18.81 Max
*0.27 ± 0.07
1.20 Max
10.16
0.13 ± 0.05
11.76 ± 0.20 0˚ – 5˚
*0.145 ± 0.05
1.005 Max
0.50 ± 0.10
0.68
0.80
0.25 ± 0.05
0.125 ± 0.04
As of January, 2002
Unit: mm
HM6216514I Series
16
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: (03) 3270-2111 Fax: (03) 3270-5109
Copyright
C
Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.
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Tel : <65>-6538-6533/6538-8577
Fax : <65>-6538-6933/6538-3877
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URL http://www.hitachisemiconductor.com/
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(Taipei Branch Office)
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For further information write to:
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