ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 1 - Revision 1.42
ISD5100 SERIES
SINGLE-CHIP
1 TO 16 MINUTES DURATION
VOICE RECORD/PLAYBACK DEVICES
WITH DIGITAL STORAGE CAPABILITY
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 2 - Revision 1.42
1. GENERAL DESCRIPTION ................................................................................................................ 4
2. FEATURES ........................................................................................................................................ 5
3. BLOCK DIAGRAM ............................................................................................................................. 6
4. PIN CONFIGURATION ...................................................................................................................... 7
5. PIN DESCRIPTION ............................................................................................................................ 8
6. FUNCTIONAL DESCRIPTION .......................................................................................................... 9
6.1. Overview .................................................................................................................................... 9
6.1.1 Speech/Voice Quality .......................................................................................................... 9
6.1.2 Duration .............................................................................................................................. 9
6.1.3 Flash Technology ................................................................................................................ 9
6.1.4 Microcontroller Interface ..................................................................................................... 9
6.1.5 Programming .................................................................................................................... 10
6.2. Functional Details ..................................................................................................................... 10
6.2.1 Internal Registers .............................................................................................................. 11
6.2.2 Memory Architecture ......................................................................................................... 11
6.3. Operational Modes Description ................................................................................................ 12
6.3.1 I2C Interface ...................................................................................................................... 12
6.3.2 I2C Control Registers ........................................................................................................ 16
6.3.3 Opcode Summary ............................................................................................................. 17
6.3.4 Data Bytes ......................................................................................................................... 19
6.3.5 Configuration Register Bytes ............................................................................................ 20
6.3.6 Power-up Sequence ......................................................................................................... 21
6.3.7 Feed Through Mode ......................................................................................................... 22
6.3.8 Call Record ....................................................................................................................... 24
6.3.9 Memo Record ................................................................................................................... 25
6.3.10 Memo and Call Playback .................................................................................................. 26
6.3.11 Message Cueing ............................................................................................................... 27
6.4. Analog Mode ............................................................................................................................ 28
6.4.1 Aux In and Ana In Description .......................................................................................... 28
6.4.2 ISD5100 Series Analog Structure (left half) Description ................................................... 29
6.4.3 ISD5100 Series Aanalog Structure (right half) Description ............................................... 30
6.4.4 Volume Control Description .............................................................................................. 31
6.4.5 Speaker and Aux Out Description..................................................................................... 32
6.4.6 Ana Out Description .......................................................................................................... 33
6.4.7 Analog Inputs .................................................................................................................... 33
ISD5100 SERIES
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6.5. Digital Mode ............................................................................................................................. 36
6.5.1 Erasing Digital Data .......................................................................................................... 36
6.5.2 Writing Digital Data ........................................................................................................... 36
6.5.3 Reading Digital Data ......................................................................................................... 37
6.5.4 Example Command Sequences ....................................................................................... 37
6.6. Pin Details ................................................................................................................................ 48
6.6.1 Digital I/O Pins .................................................................................................................. 48
6.6.2 Analog I/O Pins ................................................................................................................. 50
6.6.3 Power and Ground Pins .................................................................................................... 54
6.6.4 PCB Layout Examples ...................................................................................................... 55
7. TIMING DIAGRAMS ........................................................................................................................ 55
7.1 I2C Timing Diagram .................................................................................................................. 55
7.2 Playback and Stop Cycle ......................................................................................................... 58
7.3 Example of Power Up Command (first 12 bits) ........................................................................ 59
8. ABSOLUTE MAXIMUM RATINGS................................................................................................... 60
9. ELECTRICAL CHARACTERISTICS ................................................................................................ 62
9.1. General Parameters ................................................................................................................. 62
9.2. Timing Parameters ................................................................................................................... 63
9.3. Analog Parameters .................................................................................................................. 65
9.4. Characteristics of The I2C Serial Interface ............................................................................... 69
9.5. I2C Protocol .............................................................................................................................. 72
10. TYPICAL APPLICATION CIRCUIT .................................................................................................. 74
11. PACKAGE SPECIFICATION ........................................................................................................... 75
11.1. 28-Lead 300-Mil Plastic Small Outline Integrated Circuit (SOIC) ............................................. 75
11.2. 28-Lead 600-Mil Plastic Dual Inline Package (PDIP) ............................................................... 76
11.3. ISD5116 Die Information .......................................................................................................... 77
11.4. ISD5108 Die Information .......................................................................................................... 79
11.5. ISD5104 Die Information .......................................................................................................... 81
11.6. ISD5102 Die Information .......................................................................................................... 83
12. ORDERING INFORMATION ........................................................................................................... 85
13. VERSION HISTORY ........................................................................................................................ 86
ISD5100 SERIES
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1. GENERAL DESCRIPTION
The ISD5100 ChipCorder Series provide high quality, fully integrated, single-chip Record/Playback
solutions for 1- to 16-minute messaging applications that are ideal for use in cellular phones,
automotive communications, GPS/navigation systems and other portable products. The ISD5100
Series products are an enhancement of the ISD5000 architecture, providing: 1) the I2C serial port -
address, control and duration selection are accomplished through an I2C interface to minimize pin
count (ONLY two control lines required); 2) the capability of storing digital data, in addition to analog
data. This feature allows customers to store phone numbers, system configuration parameters and
message address locations for message management capability; 3) Various internal circuit blocks can
be individually powered-up or -down for power saving.
The ISD5100 Series include:
ISD5116 from 8 to 16 minutes
ISD5108 from 4 to 8 minutes
ISD5104 from 2 to 4 minutes
ISD5102 from 1 to 2 minutes
Analog functions and audio gating have also been integrated into the ISD5100 Series products to allow
easy interface with integrated digital cellular chip sets on the market. Audio paths have been designed
to enable full duplex conversation record, voice memo, answering machine (including outgoing
message playback) and call screening features. This product enables playback of messages while the
phone is in standby, AND both simplex and duplex playback of messages while on a phone call.
Additional voice storage features for digital cellular phones include: 1) a personalized outgoing
message can be sent to the person by getting caller-ID information from the host chipset, 2) a private
call announce while on call can be heard from the host by giving caller-ID on call waiting information
from the host chipset.
Logic Interface Options of 2.0V and 3.0V are supported by the ISD5100 Series to accommodate
portable communication products (2.0- and 3.0-volt required).
Like other ChipCorder® products, the ISD5100 Series integrate the sampling clock, anti-aliasing and
smoothing filters, and the multi-level storage array on a single-chip. For enhanced voice features, the
ISD5100 Series eliminate external circuitry by integrating automatic gain control (AGC), a power
amplifier/speaker driver, volume control, summing amplifiers, analog switches, and a car kit interface.
Input level adjustable amplifiers are also included, providing a flexible interface for multiple
applications.
Recordings are stored into on-chip nonvolatile memory cells, providing zero-power message storage.
This unique, single-chip solution is made possible through Nuvoton‘s patented multilevel storage
technology. Voice and audio signals are stored directly into solid-state memory in their natural,
uncompressed form, providing superior quality on voice and music reproduction.
ISD5100 SERIES
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2. FEATURES
Fully-Integrated Solution
Single-chip voice record/playback solution
Dual storage of digital and analog data
Durations
Device
ISD5102
ISD5104
ISD5108
ISD5116
Duration
1 to 2 minutes
2 to 4 minutes
4 to 8 minutes
8 to 16 minutes
Low Power Consumption
Supply Voltage
Commercial Temperature = +2.7V to +3.3V
Industrial Temperature = +2.7V to +3.3V (+2.7V to +3.6V for ISD5108 only)
Supports 2.0V and 3.0V interface logic
Operating Current:
ICC Play = 15 mA (typical)
ICC Rec = 30 mA (typical)
ICC Feedthrough = 12 mA (typical)
Standby Current:
ISB = 1A (typical)
Most stages can be individually powered down to minimize power consumption
Enhanced Voice Features
One or two-way conversation record
One or two-way message playback
Voice memo record and playback
Private call screening
In-terminal answering machine
Personalized outgoing message
Private call announce while on call
Digital Memory Features
Device
ISD5102
ISD5104
ISD5108
ISD5116
Storage
Up to 512Kb
Up to 1 Mb
Up to 2 Mb
Up to 4 Mb
Storage of phone numbers, system configuration parameters and message address table in some application
Easy-to-use and Control
No compression algorithm development required
User-controllable sampling rates
Programmable analog interface
Standard & Fast mode I2C serial interface (100kHz – 400 kHz)
Fully addressable for multiple messages
High Quality Solution
High quality voice and music reproduction
Nuvoton‘s standard 100-year message retention (typical)
100K record cycles (typical) for analog data
10K record cycles (typical) for digital data
Options
Available in die form, SOIC and PDIP (ISD5116 Only)
Temperature: Commercial – Packaged (0 to +70°C) & die (0 to +50°C); Industrial (-40 to +85°C)
Pb-free package
ISD5100 SERIES
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3. BLOCK DIAGRAM
ISD5100-Series Block Diagram
AUX IN
AMP
1.0 / 1.4 / 2.0 / 2.8
AGC
SUM1 MUX
Vol
MUX
Filter
MUX
Low Pass
Filter
SUM1
FTHRU
INP
ANA OUT MUX
VOL
SUM2
ANA IN
VOL
SP+
SP-
SPEAKER
AUX OUT
ANA OUT-
ANA OUT+
MIC+
MIC -
AGCCAP
MICROPHONE
AUX IN
XCLK
ANA IN
V
SSA
V
CCA
V
SSA
V
SSD
V
SSD
V
CCD
V
CCD
64-bit/samp.
ARRAY OUTPUT MUX
ARRAY
INPUT
MUX
Input Source MUX
Array I/O
Mux
FILTO
SUM1
INP
ANA IN
SUM2
FILTO
SUM2
SUM1
Summing
AMP
ANA IN
AMP
0.625/0.883/1.25/1.76
6dB
SUM2
Summing
AMP
Output MUX
Volume
Control
MIC IN
AUX IN
FILTO
ANA IN
SUM1
ANA IN
FILTO
SUM2
(ANALOG)
ARRAY
INP
SUM1 MUX
CTRL
(DIGITAL)
64-bit/samp.
ARRAY OUT
(ANALOG)
ARRAY OUT
(DIGITAL)
ARRAY
Spkr
.
AMP
AUX
OUT
AMP
Power Conditioning
RAC
INT
SDA
SCL
A1
A0
Device Control
Internal
Clock
Multilevel/Digital
Storage Array
ANA
OUT
AMP
2
( )
VLS0
VLS1
2
( )
AIG0
AIG1
2
( )
AXG0
AXG1
2
( )
S1S0
S1S1
2
( )
S1M0
S1M1
2
( )
S2M0
S2M1
( )
OPA0
OPA1
2
( )
OPS0
OPS1
2
( )
FLD0
FLD1
2
(INS0)
1
1
(AXPD)
1
(AGPD)
1
(FLPD)
1
(FLS0)
1
(AIPD)
1
(AOPD)
( )
3
AOS0
AOS1
AOS2
3
( )
VOL0
VOL1
VOL2
1
(V
LPD
)
ISD5100 SERIES
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4. PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCCD
VCCD
XCLK
INT
RAC
VSSA
NC
NC
AUX OUT
AUX IN
ANA IN
VCCA
SP+
VSSA
SCL
A1
SDA
A0
VSSD
VSSD
NC
MIC+
VSSA
MIC-
ANA OUT+
ANA OUT-
ACAP
SP-
PDIP
ISD5116
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCCD
VCCD
XCLK
INT
RAC
VSSA
NC
NC
AUX OUT
AUX IN
ANA IN
VCCA
SP+
VSSA
SCL
A1
SDA
A0
VSSD
VSSD
NC
MIC+
VSSA
MIC-
ANA OUT+
ANA OUT-
ACAP
SP-
ISD5116
ISD5108
ISD5104
ISD5102
ISD5100 SERIES
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5. PIN DESCRIPTION
Pin Name
SOIC/PDIP
Functionality
SCL
1
I2C Serial Clock Line: to clock the data into and out of the I2C interface.
A1
2
Input pin that supplies the LSB +1 bit for the I2C Slave Address.
SDA
3
I2C Serial Data Line: Data is passed between devices on the bus over
this line.
A0
4
Input pin that supplies the LSB for the I2C Slave Address.
VSSD
5,6
Digital Ground.
NC
7,21,22
No Connect.
MIC+
8
Differential Positive Input for the microphone amplifier.
VSSA
9,15,23
Analog Ground.
MIC-
10
Differential Negative Input for the microphone amplifier.
ANA OUT+
11
Differential Positive Analog Output for ANA OUT.
ANA OUT-
12
Differential Negative Analog Output for ANA OUT.
ACAP
13
AGC/AutoMute Capacitor: Required for the on-chip AGC amplifier during
record and AutoMute function during playback.
SP-
14
Differential Negative Speaker Output: When the speaker outputs are in
use, the AUX OUT output is disabled.
SP+
16
Differential Positive Speaker Output.
VCCA
17
Analog Supply Voltage: This pin supplies power to the analog sections
of the device. It should be carefully bypassed to Analog Ground to
insure correct device operation.
ANA IN
18
Analog Input: one of the analog inputs with selectable gain.
AUX IN
19
Auxiliary Input: one of the analog inputs with selectable gain.
AUX OUT
20
Auxiliary Output: one the analog outputs of the device. When this
output is used, the SP+ and SP- outputs are disabled.
RAC
24
Row Address Clock; an open drain output. The RAC pin goes LOW
TRACL[1] before the end of each row of memory and returns HIGH at
exactly the end of each row of memory.
INT
25
Interrupt Output; an open drain output that indicates that a set EOM bit
has been found during Playback or that the chip is in an Overflow (OVF)
condition. This pin remains LOW until a Read Status command is
executed.
XCLK
26
This pin must be grounded for utilizing internal clock. For precision
timing control, external clock signal can be applied through this pin.
VCCD
27,28
Digital Supply Voltage. These pins supply power to the digital sections
of the device. They must be carefully bypassed to Digital Ground to
insure correct device operation.
[1] See the Parameters section
ISD5100 SERIES
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6. FUNCTIONAL DESCRIPTION
6.1. OVERVIEW
6.1.1 Speech/Voice Quality
The ISD5100 ChipCorder Series can be configured via software to operate at 4.0, 5.3, 6.4 or 8.0 kHz
sampling frequency to select appropriate voice quality. Increasing the duration decreases the sampling
frequency and bandwidth, which affects audio quality. The table in the following section shows the
relationship between sampling frequency, duration and filter pass band.
6.1.2 Duration
To meet system requirements, the ISD5100 Series are single-chip solution, which provide 1 to 16
minutes of voice record and playback, depending upon the sample rates chosen.
Sample Rate
(kHz)
Duration [1]
Typical Filter
Knee (kHz)
ISD5116
ISD5108
ISD5104
ISD5102
8.0
8 min 44 sec
4 min 22 sec
2 min 11 sec
1 min 5 sec
3.4
6.4
10 min 55 sec
5 min 27 sec
2 min 43 sec
1 min 21 sec
2.7
5.3
13 min 6 sec
6 min 33 sec
3 min 17 sec
1 min 38 sec
2.3
4.0
17 min 28 sec
8 min 44 sec
4 min 22 sec
2 min 11 sec
1.7
[1] Minus any pages selected for digital storage
6.1.3 Flash Technology
One of the benefits of Nuvoton‘s ChipCorder technology is the use of on-chip Flash memory, which
provides zero-power message storage. The message is retained for up to 100 years (typically) without
power. In addition, the device can be re-recorded over 10,000 times (typically) for the digital data and
over 100,000 times (typically) for the analog messages.
A new feature has been added that allows memory space in the ISD5100 Series to be allocated to
either digital or analog storage when recorded. The fact that a section has been assigned digital or
analog data is stored in the Message Address Table by the system microcontroller when the recording
is made.
6.1.4 Microcontroller Interface
The ISD5100 Series are controlled through an I2C 2-wire interface. This synchronous serial port allows
commands, configurations, address data, and digital data to be loaded into the device, while allowing
status, digital data and current address information to be read back from the device. In addition to the
serial interface, two other status pins can feedback to the microcontroller for enhanced interface.
ISD5100 SERIES
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These are the
RAC
timing pin and the
INT
pin for interrupts to the controller. Communications with
all the internal registers of any operations are through the serial bus, as well as digital memory Read
and Write operations.
6.1.5 Programming
The ISD5100 Series are also ideal for playback-only applications, where single or multiple messages
may be played back when desired. Playback is controlled through the I2C interface. Once the desired
message configuration is created, duplicates can easily be generated via a third-party programmer. For
more information on available application tools and programmers, please see the Nuvoton web site at
www.Nuvoton-usa.com
6.2. FUNCTIONAL DETAILS
The ISD5100 Series are single chip solutions for analog and digital data storage. The array can be
divided between analog and digital storage according to user‘s choice, when the device is configured.
The below block diagram shows that the ISD5116 device can be easily designed into a telephone
answering machine (TAD). Both Mic inputs transmit the voice input signal from the microphone to
perform OGM recording, as well as to record the speech during phone conversation (simplex).
When the TAD is activated, the voice of the other party from the phone line feeds into the AUX IN, and
is recorded into the ISD5116 device. Then the new messge is usually indicated with blinking new
message LED. Hence, during playback, the recorded message is sent out to speaker with volume
control. Two I2C pins are used for all communications between the ChipCorder and the
microcontroller for analog and/or digital storage, and the two outputs, INT and RAC are feedback to
microcontroller for message management.
For duplex recording, speech from Mic inputs and message from received path can be directly
recorded into the array simultaneously, then playback afterwards. In addition, for speaker phone
Speaker
ISD5116
SP+
SP-
MIC+
MIC-
Microcontroller
I2C
(INT, RAC)
NV
Memory
Display &
Push buttons
AUX IN AUX OUT
DAA
Phone Line
DTMF Detect,
Caller ID
ANA OUT+
ISD5100 SERIES
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operation, voice from Mic inputs are fed to AUX OUT and transmitted to the phone line, while message
from other party is input from the AUX IN, then fed through to the speaker for listening.
The ISD5100 device has the flexibility for other applications, because the audio paths can be
configured differently, with each circuit block being powered-up or –down individually, according to the
applications requirement.
6.2.1 Internal Registers
The ISD5100 Series have multiple internal registers that are used to store the address information and
the configuration or set-up of the device. The two 16-bit configuration registers control the audio paths
through the device, the sample frequency, the various gains and attenuations, power up and down of
different sections, and the volume settings. These registers are discussed in detail in section 7.3.5.
6.2.2 Memory Architecture
The ISD5100 Series memory array are arranged in various pages (or rows) of each 2048 bits as
follows. The primary addressing for the pages are handled by 11 bits of address input in the analog
mode.
A memory page is 2048 bits organized as thirty-two 64-bit "blocks" when used for digital storage. The
contents of a page are either analog or digital. This is determined by instruction (opcode) at the time
the data is written. A record of where is analog and where is digital, is stored in a message address
table (MAT) by the system microcontroller. The MAT is a table kept in the microcontroller memory that
defines the status of each message ―page‖. It can be stored back into the ISD5100 Series if the power
fails or the system is turned off. Using this table allows efficient message management. Segments of
messages can be stored wherever there is available space in the memory array. [This is explained in
detail for the ISD5008 in Applications Note #9 and will be similarly described in a later Note for the
ISD5100-Series.]
Products
Pages (Rows)
Bits/Page
Memory Size
ISD5116
2048
2048
4,194,304 bits
ISD5108
1024
2048
2,097,152 bits
ISD5104
512
2048
1,048,576 bits
ISD5102
256
2048
524,288 bits
When a page is used for analog storage, the same 32 blocks are present but there are 8 EOM (End-of-
Message) markers. This means that for each 4 blocks there is an EOM marker at the end. Thus,
when recording, the analog recording will stop at any one of eight positions. At 8 kHz sampling
frequency, this results in a resolution of 32 msec when ENDING an analog recording. Beginning an
analog recording is limited to the 256 msec resolution provided by the 11-bit address. A recording
does not immediately stop when the Stop command is given, but continues until the 32 millisecond
block is filled. Then a bit is placed in the EOM memory to develop the interrupt that signals a
message is finished playing in the Playback mode.
ISD5100 SERIES
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Digital data is sent and received serially over the I2C interface. The data is serial-to-parallel converted
and stored in one of two alternating (commutating) 64-bit shift registers. When an input register is full, it
becomes the register that is parallel written into the array. The prior write register becomes the new
serial input register. A mechanism is built-in to ensure there is always a register available for storing
new data.
Storing data in the memory is accomplished by accepting data one byte at a time and issuing an
acknowledge. If data is coming in faster than it can be written, the chip issues an acknowledge to the
host microcontroller, but holds SCL LOW until it is ready to accept more data. (See section 7.5.2 for
details).
The read mode is the opposite of the write mode. Data is read into one of two 64-bit registers from the
array and serially sent to the I2C interface. (See section 7.5.3 for details).
6.3. OPERATIONAL MODES DESCRIPTION
6.3.1 I2C Interface
To use more than four ISD5100 Series devices in an application requires some external switching of
the I2C interface.
I2C interface
Important note: The rest of this data sheet will assume that the reader is familiar with the
I2C serial interface. Additional information on I2C may be found in section 10 on page 72 of
this document. If you are not familiar with this serial protocol, please read this section to
familiarize yourself with it. A large amount of additional information on I2C can also be
found on the Philips web page at http://www.philips.com/.
I2C Slave Address
The ISD5100 Series have 7-bit slave address of <100 00xy> where x and y are equal to the state,
respectively, of the external address pins A1 and A0. Because all data bytes are required to be 8 bits,
the LSB of the address byte is the Read/Write selection bit that tells the slave whether to transmit or
receive data. Therefore, there are 8 possible slave addresses for the ISD5100-Series. These are:
ISD5100 SERIES
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Pinout Table
A1
A0
Slave Address
R/W
Bit
HEX Value
0
0
<100 0000>
0
80
0
1
<100 0001>
0
82
1
0
<100 0010>
0
84
1
1
<100 0011>
0
86
0
0
<100 0000>
1
81
0
1
<100 0001>
1
83
1
0
<100 0010>
1
85
1
1
<100 0011>
1
87
ISD5100 Series I2C Operation Definitions
There are many control functions used to operate the ISD5100-Series. Among them are:
6.3.1.1. Read Status Command:
The Read Status command is a read request from the Host processor to the ISD5100 Series
without delivering a Command Byte. The Host supplies all the clocks (SCL). In each case, the
entity sending the data drives the data line (SDA). The Read Status Command is executed by the
following I2C sequence.
1. Host executes I2C START
2. Send Slave Address with R/W bit = ―1‖ (Read) 81h
3. Slave (ISD5100-Series) responds back to Host an Acknowledge (ACK) followed by 8-bit Status
word
4. Host sends an Acknowledge (ACK) to Slave
5. Wait for SCL to go HIGH
6. Slave responds with Upper Address byte of internal address register
7. Host sends an ACK to Slave
8. Wait for SCL to go HIGH
9. Slave responds with Lower Address byte of internal address register (A[4:0] will always return
set to 0.)
10. Host sends a NO ACK to Slave, then executes I2C STOP
Note that the processor could have sent an I2C STOP
after the Status Word data transfer and aborted the
transfer of the Address bytes.
ISD5100 SERIES
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A graphical representation of this operation is found
below. See the caption box above for more
explanation.
S
SLAVE ADDRESS
A
A
DATA
P
R
DATA
DATA
A
N
Status
Word
High Addr.
Byte
Low Addr.
Byte
Conventions used in I2C Data
Transfer Diagrams
= START Condition
= STOP Condition
= 8-bit data transfer
= ―1‖ in the R/W bit
= ―0‖ in the R/W bit
= ACK (Acknowledge)
= No ACK
S
SLAVE ADDRESS
A
DATA
P
= Host to Slave (Gray)
= Slave to Host (White)
The Box color indicates the direction
of data flow
= 7-bit Slave
Address
N
R
W
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6.3.1.2. Load Command Byte Register (Single Byte Load):
A single byte may be written to the Command Byte Register in order to power up the device, start
or stop Analog Record (if no address information is needed), or do a Message Cueing function.
The Command Byte Register is loaded as follows:
1. Host executes I2C START
2. Send Slave Address with R/W bit = ―0‖ (Write) [80h]
3. Slave responds back with an ACK.
4. Wait for SCL to go HIGH
5. Host sends a command byte to Slave
6. Slave responds with an ACK
7. Wait for SCL to go HIGH
8. Host executes I2C STOP
6.3.1.3. Load Command Byte Register (Address Load)
For the normal addressed mode the Registers are loaded as follows:
1. Host executes I2C START
2. Send Slave Address with R/W bit = ―0‖ (Write)
3. Slave responds back with an ACK.
4. Wait for SCL to go HIGH
5. Host sends a byte to Slave - (Command Byte)
6. Slave responds with an ACK
7. Wait for SCL to go HIGH
8. Host sends a byte to Slave - (High Address Byte)
9. Slave responds with an ACK
10. Wait for SCL to go HIGH
11. Host sends a byte to Slave - (Low Address Byte)
12. Slave responds with an ACK
13. Wait for SCL to go HIGH
14. Host executes I2C STOP
S
SLAVE ADDRESS
A
DATA
P
W
Command Byte
A
S
SLAVE ADDRESS
A
P
W
Command
Byte
DATA
A
DATA
A
DATA
A
High Addr.
Byte
Low Addr.
Byte
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6.3.2 I2C Control Registers
The ISD5100 Series are controlled by loading commands to, or, reading from, the internal command,
configuration and address registers. The Command byte sent is used to start and stop recording, write
or read digital data and perform other functions necessary for the operation of the device.
Command Byte
Control of the ISD5100 Series are implemented through an 8-bit command byte, sent after the 7-bit
device address and the 1-bit Read/Write selection bit. The 8 bits are:
Global power up bit
DAB bit: determines whether device is performing an analog or digital function
3 function bits: these determine which function the device is to perform in conjunction
with the DAB bit.
3 register address bits: these determine if and when data is to be loaded to a register
C7
C6
C5
C4
C3
C2
C1
C0
PU
DAB
FN2
FN1
FN0
RG2
RG1
RG0
Function Bits
Register Bits
Function Bits
The command byte function bits are
detailed in the table to the right. C6, the
DAB bit, determines whether the device
is performing an analog or digital
function. The other bits are decoded to
produce the individual commands. Not
all decode combinations are currently
used, and are reserved for future use.
Out of 16 possible codes, the ISD5100
Series uses 7 for normal operation. The
other 9 are undefined
Function Bits
Function
C6
C5
C4
C3
DAB
FN2
FN1
FN0
0
0
0
0
STOP (or do nothing)
0
1
0
1
Analog Play
0
0
1
0
Analog Record
0
1
1
1
Analog MC
1
1
0
0
Digital Read
1
0
0
1
Digital Write
1
0
1
0
Erase (row)
Power Up
Bit
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Register Bits
The register load may be used to modify a command
sequence (such as load an address) or used with the null
command sequence to load a configuration or test register.
Not all registers are accessible to the user. [RG2 is always
0 as the four additional combinations are undefined.]
6.3.3 Opcode Summary
OpCode Command Description
The following commands are used to access the chip through the I2C interface.
Play: analog play command
Record: analog record command
Message Cue: analog message cue command
Read: digital read command
Write: digital write command
Erase: digital page and block erase command
Power up: global power up/down bit. (C7)
Load CFG0: load configuration register 0
Load CFG1: load configuration register 1
Read STATUS: Read the interrupt status and address register, including a hardwired device ID
RG2
RG1
RG0
Function
C2
C1
C0
0
0
0
No action
0
0
1
Reserved
0
1
0
Load CFG0
0
1
1
Load CFG1
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OPCODE COMMAND BYTE TABLE
Pwr
Function Bits
Register Bits
OPCODE
HEX
PU
DAB
FN2
FN1
FN0
RG2
RG1
RG0
COMMAND BIT NUMBER
CMD
C7
C6
C5
C4
C3
C2
C1
C0
POWER UP
80
1
0
0
0
0
0
0
0
POWER DOWN
00
0
0
0
0
0
0
0
0
STOP (DO NOTHING) STAY ON
80
1
0
0
0
0
0
0
0
STOP (DO NOTHING) STAY OFF
00
0
0
0
0
0
0
0
0
LOAD CFG0
82
1
0
0
0
0
0
1
0
LOAD CFG1
83
1
0
0
0
0
0
1
1
RECORD ANALOG
90
1
0
0
1
0
0
0
0
RECORD ANALOG @ ADDR
91
1
0
0
1
0
0
0
1
PLAY ANALOG
A8
1
0
1
0
1
0
0
0
PLAY ANALOG @ ADDR
A9
1
0
1
0
1
0
0
1
MSG CUE ANALOG
B8
1
0
1
1
1
0
0
0
MSG CUE ANALOG @ ADDR
B9
1
0
1
1
1
0
0
1
ENTER DIGITAL MODE
C0
1
1
0
0
0
0
0
0
EXIT DIGITAL MODE
40
0
1
0
0
0
0
0
0
DIGITAL ERASE PAGE
D0
1
1
0
1
0
0
0
0
DIGITAL ERASE PAGE @ ADDR
D1
1
1
0
1
0
0
0
1
DIGITAL WRITE
C8
1
1
0
0
1
0
0
0
DIGITAL WRITE @ ADDR
C9
1
1
0
0
1
0
0
1
DIGITAL READ
E0
1
1
1
0
0
0
0
0
DIGITAL READ @ ADDR
E1
1
1
1
0
0
0
0
1
READ STATUS1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1. See section 7.2 on page 12 for details.
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6.3.4 Data Bytes
In the I2C write mode, the device can accept data sent after the command byte. If a register load option
is selected, the next two bytes are loaded into the selected register. The format of the data is MSB first,
the I2C standard. Thus to load DATA<15:0> into the device, DATA<15:8> is sent first, the byte is
acknowledged, and DATA<7:0> is sent next. The address register consists of two bytes. The format of
the address is as follows:
ADDRESS<15:0> = PAGE_ADDRESS<10:0>, BLOCK_ADDRESS<4:0>
Note: if an analog function is selected, the block address bits must be set to 00000. Digital
Read and Write are block addressable.
When the device is polled with the Read Status command, it will return three bytes of data. The first
byte is the status byte, the next the upper address byte and the last the lower address byte. The status
register is one byte long and its bit function is:
STATUS<7:0> = EOM, OVF, READY, PD, PRB, DEVICE_ID<2:0>
Lower address byte will always return the block address bits as zero, either in digital or analog mode.
The functions of the bits are:
EOM
BIT 7
Indicates whether an EOM interrupt has occurred.
OVF
BIT 6
Indicates whether an overflow interrupt has occurred.
READY
BIT 5
Indicates the internal status of the device – if READY is LOW
no new commands should be sent to device, i.e. Not Ready.
PD
BIT 4
Device is powered down if PD is HIGH.
PRB
BIT 3
Play/Record mode indicator. HIGH=Play/LOW=Record.
DEVICE_ID
BIT 0, 1, 2
An internal device ID. ISD5116 = 001; ISD5108 = 010;
ISD5104 = 100 and ISD5102 = 101.
It is recommended that you read the status register after a Write or Record operation to ensure that the
device is ready to accept new commands. Depending upon the design and the number of pins
available on the controller, the polling overhead can be reduced. If
INT
and
RAC
are tied to the
microcontroller, it does not have to poll as frequently to determine the status of the ISD5100-SERIES.
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6.3.5 Configuration Register Bytes
The configuration register bytes are defined, in detail, in the drawings of section 7.4 on page 29. The
drawings display how each bit enables or disables a function of the audio paths in the ISD5100-Series.
The tables below give a general illustration of the bits. There are two configuration registers, CFG0 and
CFG1, so there are four 8-bit bytes to be loaded during the set-up of the device.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0
Configuration Register 0 (CFG0)
AIG1 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD
Volume Control Power Down
SPKR & AUX OUT Control (2 bits)
OUTPUT MUX Select (2 bits)
ANA OUT Power Down
AUXOUT MUX Select (3 bits)
INPUT SOURCE MUX Select (1 bit)
AUX IN Power Down
AUX IN AMP Gain SET (2 bits)
ANA IN Power Down
ANA IN AMP Gain SET (2 bits)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0
Configuration Register 0 (CFG0)
AIG1 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD
Volume Control Power Down
SPKR & AUX OUT Control (2 bits)
OUTPUT MUX Select (2 bits)
ANA OUT Power Down
AUXOUT MUX Select (3 bits)
INPUT SOURCE MUX Select (1 bit)
AUX IN Power Down
AUX IN AMP Gain SET (2 bits)
ANA IN Power Down
ANA IN AMP Gain SET (2 bits)
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AGC AMP Power Down
Filter Power Down
SAMPLE RATE (& Filter) Set up (2 bits)
FILTER MUX Select
SUM 2 SUMMING AMP Control (2 bits)
SUM 1 SUMMING AMP Control (2 bits)
SUM 1 MUX Select (2 bits)
VOLUME CONTROL (3 bits)
VOLUME CONT. MUX Select (2 bits)
Configuration Register 1 (CFG1)
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S 2M0 FLS0 FLD1 FLD0 FLPD AGPD
D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0
AGC AMP Power Down
Filter Power Down
SAMPLE RATE (& Filter) Set up (2 bits)
FILTER MUX Select
SUM 2 SUMMING AMP Control (2 bits)
SUM 1 SUMMING AMP Control (2 bits)
SUM 1 MUX Select (2 bits)
VOLUME CONTROL (3 bits)
VOLUME CONT. MUX Select (2 bits)
Configuration Register 1 (CFG1)
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S 2M0 FLS0 FLD1 FLD0 FLPD AGPD
D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S 2M0 FLS0 FLD1 FLD0 FLPD AGPD
D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S 2M0 FLS0 FLD1 FLD0 FLPD AGPD
D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0
6.3.6 Power-up Sequence
This sequence prepares the ISD5100 Series for an operation to follow, waiting the Tpud time before
sending the next command sequence.
1. Send I2C POWER UP
2. Send one byte 10000000 {Slave Address, R/W = 0} 80h
3. Slave ACK
4. Wait for SCL High
5. Send one byte 10000000 {Command Byte = Power Up} 80h
6. Slave ACK
7. Wait for SCL High
8. Send I2C STOP
Playback Mode
The command sequence for an analog Playback operation can be handled several ways. The most
straightforward approach would be to incorporate a single four byte exchange, which consists of the
Slave Address (80h), the Command Byte (A9h) for Play Analog @ Address, and the two address
bytes.
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Record Mode
The command sequence for an Analog Record would be a four byte sequence consisting of the Slave
Address (80h), the Command Byte (91h) for Record Analog @ Address, and the two address bytes.
See ―Load Command Byte Register (Address Load)‖ in section 7.3.2 on page 17.
6.3.7 Feed Through Mode
The previous examples were dependent upon the device already being powered up and the various
paths being set through the device for the desired operation. To set up the device for the various
paths requires loading the two 16-bit Configuration Registers with the correct data. For example, in
the Feed Through Mode the device only needs to be powered up and a few paths selected.
This mode enables the ISD5100 Series to connect to a cellular or cordless base band phone chip set
without affecting the audio source or destination. There are two paths involved, the transmit path and
the receive path. The transmit path connects the Nuvoton chip‘s microphone source through to the
microphone input on the base band chip set. The receive path connects the base band chip set‘s
speaker output through to the speaker driver on the Nuvoton chip. This allows the Nuvoton chip to
substitute for those functions and incidentally gain access to the audio to and from the base band chip
set.
To set up the environment described above, a series of commands need to be sent to the ISD5100-
Series. First, the chip needs to be powered up as described in this section. Then the Configuration
Registers must be filled with the specific data to connect the paths desired. In the case of the Feed
Through Mode, most of the chip can remain powered down. The following figure illustrates the
affected paths.
The figure above shows the part of the ISD5100 Series block diagram that is used in Feed Through
Mode. The rest of the chip will be powered down to conserve power. The bold lines highlight the audio
paths. Note that the Microphone to ANA OUT +/– path is differential.
Microphone
Mic+
Mic-
Chip Set
ANA OUT+
ANA OUT-
Chip Set
ANA IN
Speaker
SP+
SP-
OUTPUT
MUX
ANA IN
AMP
6 dB
ANA OUT
MUX
FTHRU
INP
FILTO
SUM1
SUM2
VOL
VOL
FILTO
ANA IN AMP
SUM2
3 [AOS2,AOS1,AOS0]
1 [AOPD]
2 [OPA1,OPA0]
2 [OPS1,OPS0]
2 [AIG1,AIG0]
1 [APD]
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To select this mode, the following control bits must be configured in the ISD5100 Series configuration
registers. To set up the transmit path:
1. Select the FTHRU path through the ANA OUT MUX—Bits AOS0, AOS1 and AOS2 control the
state of the ANA OUT MUX. These are the D6, D7 and D8 bits respectively of Configuration
Register 0 (CFG0) and they should all be ZERO to select the FTHRU path.
2. Power up the ANA OUT amplifier—Bit AOPD controls the power up state of ANA OUT. This is
bit D5 of CFG0 and it should be a ZERO to power up the amplifier.
To set up the receive path:
1. Set up the ANA IN amplifier for the correct gain—Bits AIG0 and AIG1 control the gain settings
of this amplifier. These are bits D14 and D15 respectively of CFG0. The input level at this pin
determines the setting of this gain stage. The ANA IN Amplifier Gain Settings table on page
36 will help determine this setting. In this example, we will assume that the peak signal never
goes above 1 volt p-p single ended. That would enable us to use the 9 dB attenuation setting,
or where D14 is ONE and D15 is ZERO.
2. Power up the ANA IN amplifier—Bit AIPD controls the power up state of ANA IN. This is bit
D13 of CFG0 and should be a ZERO to power up the amplifier.
3. Select the ANA IN path through the OUTPUT MUX—Bits OPS0 and OPS1 control the state of
the OUTPUT MUX. These are bits D3 and D4 respectively of CFG0 and they should be set to
the state where D3 is ONE and D4 is ZERO to select the ANA IN path.
4. Power up the Speaker Amplifier—Bits OPA0 and OPA1 control the state of the Speaker and
AUX amplifiers. These are bits D1 and D2 respectively of CFG0. They should be set to the
state where D1 is ONE and D2 is ZERO. This powers up the Speaker Amplifier and configures
it for its higher gain setting for use with a piezo speaker element and also powers down the
AUX output stage.
The status of the rest of the functions in the ISD5100 Series chip must be defined before the con-
figuration registers settings are updated:
1. Power down the Volume Control Element—Bit VLPD controls the power up state of the
Volume Control. This is bit D0 of CFG0 and it should be set to a ONE to power down this
stage.
2. Power down the AUX IN amplifier—Bit AXPD controls the power up state of the AUX IN input
amplifier. This is bit D10 of CFG0 and it should be set to a ONE to power down this stage.
3. Power down the SUM1 and SUM2 Mixer amplifiers—Bits S1M0 and S1M1 control the SUM1
mixer and bits S2M0 and S2M1 control the SUM2 mixer. These are bits D7 and D8 in CFG1
and bits D5 and D6 in CFG1 respectively. All 4 bits should be set to a ONE to power down
these two amplifiers.
4. Power down the FILTER stage—Bit FLPD controls the power up state of the FILTER stage in
the device. This is bit D1 in CFG1 and should be set to a ONE to power down the stage.
5. Power down the AGC amplifier—Bit AGPD controls the power up state of the AGC amplifier.
This is bit D0 in CFG1 and should be set to a ONE to power down this stage.
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6. Don‘t Care bits—The following stages are not used in Feed Through Mode. Their bits may be
set to either level. In this example, we will set all the following bits to a ZERO. (a). Bit INS0, bit
D9 of CFG0 controls the Input Source Mux. (b). Bits AXG0 and AXG1 are bits D11 and D12
respectively in CFG0. They control the AUX IN amplifier gain setting. (c). Bits FLD0 and FLD1
are bits D2 and D3 respectively in CFG1. They control the sample rate and filter band pass
setting. (d). Bit FLS0 is bit D4 in CFG1. It controls the FILTER MUX. (e). Bits S1S0 and S1S1
are bits D9 and D10 of CFG1. They control the SUM1 MUX. (f). Bits VOL0, VOL1 and VOL2
are bits D11, D12 and D13 of CFG1. They control the setting of the Volume Control. (g). Bits
VLS0 and VLS1 are bits D14 and D15 of CFG1. They control the Volume Control MUX.
The end result of the above set up is
CFG0=0100 0100 0000 1011 (hex 440B)
and
CFG1=0000 0001 1110 0011 (hex 01E3).
Since both registers are being loaded, CFG0 is loaded, followed by the loading of CFG1. These two
registers must be loaded in this order. The internal set up for both registers will take effect synchro-
nously with the rising edge of SCL.
6.3.8 Call Record
The call record mode adds the ability to record an incoming phone call. In most applications, the
ISD5100 Series would first be set up for Feed Through Mode as described above. When the user
wishes to record the incoming call, the setup of the chip is modified to add that ability. For the purpose
of this explanation, we will use the 6.4 kHz sample rate during recording.
The block diagram of the ISD5100 Series shows that the Multilevel Storage array is always driven from
the SUM2 SUMMING amplifier. The path traces back from there through the LOW PASS Filter, THE
FILTER MUX, THE SUM1 SUMMING amplifier, the SUM1 MUX, then from the ANA in amplifier. Feed
Through Mode has already powered up the ANA IN amp so we only need to power up and enable the
path to the Multilevel Storage array from that point:
1. Select the ANA IN path through the SUM1 MUX—Bits S1S0 and S1S1 control the state of the
SUM1 MUX. These are bits D9 and D10 respectively of CFG1 and they should be set to the
state where both D9 and D10 are ZERO to select the ANA IN path.
2. Select the SUM1 MUX input (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1
control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8 respectively of
CFG1 and they should be set to the state where D7 is ONE and D8 is ZERO to select the
SUM1 MUX (only) path.
3. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the
state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the
SUM1 SUMMING amplifier path.
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4. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
5. Select the 6.4 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 6.4 kHz sample rate, D2 must be set to ONE and D3 set to ZERO.
6. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier—Bits S2M0 and
S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6
respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to
select the LOW PASS FILTER (only) path.
In this mode, the elements of the original PASS THROUGH mode do not change. The sections of the
chip not required to add the record path remain powered down. In fact, CFG0 does not change and
remains
CFG0=0100 0100 0000 1011 (hex 440B).
CFG1 changes to
CFG1=0000 0000 1100 0101 (hex 00C5).
Since CFG0 is not changed, it is only necessary to load CFG1. Note that if only CFG0 was changed, it
would be necessary to load both registers.
6.3.9 Memo Record
The Memo Record mode sets the chip up to record from the local microphone into the chip‘s Multilevel
Storage Array. A connected cellular telephone or cordless phone chip set may remain powered down
and is not active in this mode. The path to be used is microphone input to AGC amplifier, then through
the INPUT SOURCE MUX to the SUM1 SUMMING amplifier. From there the path goes through the
FILTER MUX, the LOW PASS FILTER, the SUM2 SUMMING amplifier, then to the MULTILEVEL
STORAGE ARRAY. In this instance, we will select the 5.3 kHz sample rate. The rest of the chip may
be powered down.
1. Power up the AGC amplifier—Bit AGPD controls the power up state of the AGC amplifier. This
is bit D0 of CFG1 and must be set to ZERO to power up this stage.
2. Select the AGC amplifier through the INPUT SOURCE MUX—Bit INS0 controls the state of
the INPUT SOURCE MUX. This is bit D9 of CFG0 and must be set to a ZERO to select the
AGC amplifier.
3. Select the INPUT SOURCE MUX (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1
control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8 respectively of
CFG1 and they should be set to the state where D7 is ZERO and D8 is ONE to select the
INPUT SOURCE MUX (only) path.
4. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the
state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the
SUM1 SUMMING amplifier path.
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5. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
6. Select the 5.3 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 5.3 kHz sample rate, D2 must be set to ZERO and D3 set to ONE.
7. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier—Bits S2M0 and
S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6
respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to
select the LOW PASS FILTER (only) path.
To set up the chip for Memo Record, the configuration registers are set up as follows:
CFG0=0010 0100 0010 0001 (hex 2421).
CFG1=0000 0001 0100 1000 (hex 0148).
Only those portions necessary for this mode are powered up.
6.3.10 Memo and Call Playback
This mode sets the chip up for local playback of messages recorded earlier. The playback path is from
the MULTILEVEL STORAGE ARRAY to the FILTER MUX, then to the LOW PASS FILTER stage.
From there, the audio path goes through the SUM2 SUMMING amplifier to the VOLUME MUX, through
the VOLUME CONTROL then to the SPEAKER output stage. We will assume that we are driving a
piezo speaker element. This audio was previously recorded at 8 kHz. All unnecessary stages will be
powered down.
1. Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX—Bit FLS0, the
state of the FILTER MUX. This is bit D4 of CFG1 and must be set to ONE to select the
MULTILEVEL STORAGE ARRAY.
2. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
3. Select the 8.0 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 8.0 kHz sample rate, D2 and D3 must be set to ZERO.
4. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier —Bits S2M0 and
S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6
respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to
select the LOW PASS FILTER (only) path.
5. Select the SUM2 SUMMING amplifier path through the VOLUME MUX—Bits VLS0 and VLS1
control the state VOLUME MUX. These bits are bits D14 and D15, respectively of CFG1. They
should be set to the state where D14 is ONE and D15 is ZERO to select the SUM2 SUMMING
amplifier.
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 27 - Revision 1.42
6. Power up the VOLUME CONTROL LEVEL—Bit VLPD controls the power-up state of the
VOLUME CONTROL attenuator. This is Bit D0 of CFG0. This bit must be set to a ZERO to
power-up the VOLUME CONTROL.
7. Select a VOLUME CONTROL LEVEL—Bits VOL0, VOL1, and VOL2 control the state of the
VOLUME CONTROL LEVEL. These are bits D11, D12, and D13, respectively, of CFG1. A
binary count of 000 through 111 controls the amount of attenuation through that state. In most
cases, the software will select an attenuation level according to the desires of the current users
of the product. In this example, we will assume the user wants an attenuation of –12 dB. For
that setting, D11 should be set to ONE, D12 should be set to ONE, and D13 should be set to a
ZERO.
8. Select the VOLUME CONTROL path through the OUTPUT MUX—These are bits D3 and D4,
respectively, of CFG0. They should be set to the state where D3 is ZERO and D4 is a ZERO to
select the VOLUME CONTROL.
9. Power up the SPEAKER amplifier and select the HIGH GAIN mode—Bits OPA0 and OPA1
control the state of the speaker (SP+ and SP–) and AUX OUT outputs. These are bits D1 and
D2 of CFG0. They must be set to the state where D1 is ONE and D2 is ZERO to power-up the
speaker outputs in the HIGH GAIN mode and to power-down the AUX OUT.
To set up the chip for Memo or Call Playback, the configuration registers are set up as follows:
CFG0=0010 0100 0010 0100 (hex 2424).
CFG1=0101 1001 1101 0001 (hex 59D1).
Only those portions necessary for this mode are powered up.
6.3.11 Message Cueing
Message cueing allows the user to skip through analog messages without knowing the actual physical
location of the message. This operation is used during playback. In this mode, the messages are
skipped 512 times faster than in normal playback mode. It will stop when an EOM marker is reached.
Then, the internal address counter will be pointing to the next message.
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 28 - Revision 1.42
6.4. ANALOG MODE
6.4.1 Aux In and Ana In Description
The AUX IN is an additional audio input to the ISD5100-Series, such as from the microphone circuit in
a mobile phone ―car kit.‖ This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB).
See the AUX IN Amplifier Gain Settings table on page 37. Additional gain is available in 3 dB steps
(controlled by the I2C serial interface) up to 9 dB.
The ANA IN pin is the analog input from the telephone chip set. It can be switched (by the serial bus) to
the speaker output, the array input or to various other paths. This pin is designed to accept a nominal
1.11 Vp-p when at its minimum gain (6 dB) setting. See the ANA IN Amplifier Gain Settings table on
page 37. There is additional gain available in 3 dB steps controlled from the I2C interface, if required,
up to 15 dB.
AUX IN
Input Amplifier
AUX IN
Input
CCOUP=0.1 F
Ra
Rb
Internal to the device
NOTE: fCUTOFF=
2RaCCOUP
1
ANA IN
Input Amplifier
ANA IN
Input
CCOUP=0.1 F
Ra
Rb
Internal to the device
NOTE: fCUTOFF=
2RaCCOUP
1
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 29 - Revision 1.42
6.4.2 ISD5100 Series Analog Structure (left half) Description
INPUT
AGC AMP SUM1
2 (S1M1,S1M0)
SOURCE
MUX
SUM1 SUMMING
AMP
AUX IN AMP
FILTO
SUM1
MUX
ANA IN AMP
ARRAY
2 (S1S1,S1S0)
(INS0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AIG1 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD CFG1
INP
INSO
Source
0
AGC AMP
1
AUX IN AMP
S1M1
S1M0
SOURCE
0
0
BOTH
0
1
SUM1 MUX ONLY
1
0
INP Only
1
1
Power Down
S1S1
S1S0
SOURCE
0
0
ANA IN
0
1
ARRAY
1
0
FILTO
1
1
N/C
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
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6.4.3 ISD5100 Series Aanalog Structure (right half) Description
SUM1
SUM2
2 (S2M1,S2M0)
FILTER
MUX SUM2 SUMMING
AMP
ARRAY
2
FILTO
LOW PASS
FILTER
INTERNAL
CLOCK
MULTILEVEL
STORAGE
ARRAY
1
(FLS0) 1
(FLPD)
ARRAY
ANA IN AMP
XCLK
(FLD1,FLD0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD CFG1
FLS0
SOURCE
0
SUM1
1
ARRAY
FLPD
CONDITION
0
Power Up
1
Power Down
S2M1
S2M0
SOURCE
0
0
BOTH
0
1
ANA IN ONLY
1
0
FILTO ONLY
1
1
Power Down
FLD1
FLD0
SAMPLE
RATE
FILTER
BANDWIDTH
0
0
8 KHz
3.6 KHz
0
1
6.4 KHz
2.9 KHz
1
0
5.3 KHz
2.4 KHz
1
1
4.0 KHz
1.8 KHz
FILTER
MUX
FILTO
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 31 - Revision 1.42
6.4.4 Volume Control Description
VOL
SUM2
VOL
MUX
SUM1
INP
2
ANA IN AMP
VOLUME
CONTROL
(VLS1,VLS0) 3
(VOL2,VOL1,VOL0)1 (VLPD)
VLPD
CONDITION
0
Power Up
1
Power Down
VLS1
VLS0
SOURCE
0
0
ANA IN AMP
0
1
SUM2
1
0
SUM1
1
1
INP
VOL2
VOL1
VOL0
ATTENUATION
0
0
0
0 dB
0
0
1
4 dB
0
1
0
8 dB
0
1
1
12 dB
1
0
0
16 dB
1
0
1
20 dB
1
1
0
24 dB
1
1
1
28 dB
INS0
AIG1 AIG0 AIPD AXG1 AXG0 AXPD AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLS1 VLS0 VOL2 VOL1 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD CFG1
VOL0
ISD5100 SERIES
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6.4.5 Speaker and Aux Out Description
Speaker
SP+
SP–
AUX OUT Car Kit
(1 Vp-p Max)
ANA IN AMP
OUTPUT
MUX
FILTO
SUM2
2
VOL
(OPS1,OPS0)
2
(OPA1, OPA0)
INS0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AIG1 AIG0 AIPD AXG1 AXG0 AXPD AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0
OPS1
OPS0
SOURCE
0
0
VOL
0
1
ANA IN
1
0
FILTO
1
1
SUM2
OPA1
OPA0
SPKR DRIVE
AUX OUT
0
0
Power Down
Power Down
0
1
3.6 VP-P @ 150
Power Down
1
0
23.5 mWatt @ 8
Power Down
1
1
Power Down
1 VP-P Max @ 5 K
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
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6.4.6 Ana Out Description
Chip Set
ANA OUT+
ANA OUT–
*VOL
*FILTO
*SUM2
3 (AOS2,AOS1,AOS0)
*FTHRU
1
(AOPD)
*INP
*SUM1
(1 Vp-p max. from AUX IN or ARRAY)
(694 mVp-p max. from microphone input)
INS0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AIG1 AIG0 AIPD AXG1 AXG0 AXPD AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0
6.4.7 Analog Inputs
Microphone Inputs
The microphone inputs transfer the voice signal to the on-chip AGC preamplifier or directly to the ANA
OUT MUX, depending on the selected path. The direct path to the ANA OUT MUX has a gain of 6 dB
so a 208 mV p-p signal across the differential microphone inputs would give 416 mV p-p across the
ANA OUT pins. The AGC circuit has a range of 45 dB in order to deliver a nominal 694 mV p-p into the
storage array from a typical electric microphone output of 2 to 20 mV p-p. The input impedance is
typically 10kΩ.
The ACAP pin provides the capacitor connection for setting the parameters of the microphone AGC
circuit. It should have a 4.7 µF capacitor connected to ground. It cannot be left floating. This is because
the capacitor is also used in the playback mode for the AutoMute circuit. This circuit reduces the
amount of noise present in the output during quiet pauses. Tying this pin to ground gives maximum
gain; to VCCA gives minimum gain for the AGC amplifier but will cancel the AutoMute function.
AOS2
AOS1
AOS0
SOURCE
0
0
0
FTHRU
0
0
1
INP
0
1
0
VOL
0
1
1
FILTO
1
0
0
SUM1
1
0
1
SUM2
1
1
0
N/C
1
1
1
N/C
AOPD
CONDITION
0
Power Up
1
Power Down
*DIFFERENTIAL PATH
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
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MIC+
MIC–
ACAP
FTHRU
AGC
1 (AGPD)
6 dB
To AutoMute
(Playback Only)
*
* Differential Path
AGC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD CFG1
ANA IN (Analog Input)
The ANA IN pin is the analog input from the telephone chip set. It can be switched (by the I2C
interface) to the speaker output, the array input or to various other paths. This pin is designed to accept
a nominal 1.11 V p-p when at its minimum gain (6 dB) setting. There is additional gain available, if
required, in 3 dB steps, up to 15 dB. The gain settings are controlled from the I2C interface.
ANA IN Amplifier Gain Settings
AGPD
CONDITION
0
Power Up
1
Power Down
MIC IN
Gain
Setting
Resistor Ratio
(Rb/Ra)
Gain
Gain2
(dB)
00
63.9 / 102
0.625
-4.1
01
77.9 / 88.1
0.883
-1.1
10
92.3 / 73.8
1.250
1.9
11
106 / 60
1.767
4.9
Note: Ra & Rb are in k
Setting(1)
0TLP Input
VP-P(3)
CFG0
Gain(2)
Array
In/Out VP-P
Speaker
Out VP-P(4)
AIG1
AIG0
6 dB
1.110
0
0
0.625
0.694
2.22
9 dB
0.785
0
1
0.883
0.694
2.22
12 dB
0.555
1
0
1.250
0.694
2.22
15 dB
0.393
1
1
1.767
0.694
2.22
ANA IN
Input
ANA IN
Input Amplifier
NOTE: fCUTTOFF
2xRaCCOUP
1
Ra
Rb
CCOUP = 0.1 µF
Internal to the device
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 35 - Revision 1.42
1. Gain from ANA IN to SP+/-
2. Gain from ANA IN to ARRAY IN
3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is
typically 3 dB below clipping
4. Speaker Out gain set to 1.6 (High). (Differential)
AUX IN (Auxiliary Input)
The AUX IN is an additional audio input to the ISD5100-Series, such as from the microphone circuit in
a mobile phone ―car kit.‖ This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB).
See the following table. Additional gain is available in 3 dB steps (controlled by the I2C interface) up to
9 dB.
AUX IN Input Modes
AUX IN Amplifier Gain Settings
Setting(1)
0TLP Input
VP-P(3)
CFG0
Gain(2)
Array
In/Out VP-P
Speaker
Out VP-P(4)
AXG1
AXG0
0 dB
0.694
0
0
1.00
0.694
0.694
3 dB
0.491
0
1
1.41
0.694
0.694
6 dB
0.347
1
0
2.00
0.694
0.694
9 dB
0.245
1
1
2.82
0.694
0.694
1. Gain from AUX IN to ANA OUT
2. Gain from AUX IN to ARRAY IN
3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB
below clipping
4. Differential
Gain
Setting
Resistor Ratio
(Rb/Ra)
Gain
Gain(2)
(dB)
00
40.1 / 40.1
1.0
0
01
47.0 / 33.2
1.414
3
10
53.5 / 26.7
2.0
6
11
59.2 / 21
2.82
9
Note: Ra & Rb are in k
AUX IN
Input
ANA IN
Input Amplifier
NOTE: fCUTTOFF
2xRaCCOUP
1
Ra
Rb
CCOUP = 0.1 µF
Internal to the device
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 36 - Revision 1.42
6.5. DIGITAL MODE
6.5.1 Erasing Digital Data
The Digital Erase command can only erase an entire page at a time. This means that the D1 command
only needs to include the 11-bit page address; the 5-bit for block address are left at 00000.
Once a page has been erased, each block may be written separately, 64 bits at a time. But, if a block
has been previously written then the entire page of 2048 bits must be erased in order to re-write (or
change) a block.
A sequence might be look like:
- read the entire page
- store it in RAM
- change the desired bit(s)
- erase the page
- write the new data from RAM to the entire page
6.5.2 Writing Digital Data
The Digital Write function allows the user to select a portion of the array to be used as digital memory.
The partition between analog and digital memory is left up to the user. A page can only be either Digital
or Analog, but not both. The minimum addressable block of memory in the digital mode is one block
or 64 bits, when reading or writing. The address sent to the device is the 11-bit row (or page) address
with the 5-bit scan (or block) address. However, one must send a Digital Erase before attempting to
change digital data on a page. This means that even when changing only one of the 32 blocks, all 32
blocks will need to be rewritten to the page. Command Sequence: The chip enters digital mode by
sending the ENTER DIGITAL MODE command from power down. Send the DIGITAL WRITE @
ADDR command with the row address. After the address is entered, the data is sent in one-byte
packets followed by an I2C acknowledge generated by the chip. Data for each block is sent MSB first.
The data transfer is ended when the master generates an I2C STOP condition. If only a partial block of
data is sent before the STOP condition, ―zero‖ is written in the remaining bytes; that is, they are left at
the erase level. An erased page (row) will be read as all zeros. The device can buffer up to two blocks
of data. If the device is unable to accept more data due to the internal write process, the SCL line will
be held LOW indicating to the master to halt data transfer. If the device encounters an overflow
condition, it will respond by generating an interrupt condition and an I2C Not Acknowledge signal after
the last valid byte of data. Once data transfer is terminated, the device needs up to two cycles (64 us)
to complete its internal write cycle before another command is sent. If an active command is sent
before the internal cycle is finished, the part will hold SCL LOW until the current command is finished.
After writing is complete, send the EXIT DIGITAL MODE command.
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 37 - Revision 1.42
6.5.3 Reading Digital Data
The Digital Read command utilizes the combined I2C command format. That is, a command is sent to
the chip using the write data direction. Then the data direction is reversed by sending a repeated start
condition, and the slave address with R/W set to 1. After this, the slave device (ISD5100-Series)
begins to send data to the master until the master generates a NACK. If the part encounters an
overflow condition, the
INT
pin is pulled LOW. No other communication with the master is possible
due to the master generating ACK signals.
Digital Write and Digital Read can be done a ―block‖ at a time. Thus, only 64 bits need be read in
each Digital Read command sequence.
6.5.4 Example Command Sequences
An explanation and graphical representation of the Erase, Write and Read operations are found below.
Note: All sequences assumes that the chip is in power-down mode before the commands are sent.
6.5.4.1. Erase Digital Data
Erase
=====
I2CStart
SendByte(0x80) - Write, Slave address zero
WaitACK
WaitSCLHigh
SendByte(0xc0) - Enter Digital Mode Command
WaitACK
WaitSCLHigh
I2CStop
I2CStart
SendByte(0x80) - Write, Slave address zero
WaitACK
WaitSCLHigh
SendByte(0xd1) - Digital Erase Command
WaitACK
WaitSCLHigh
SendByte(row/256) - high address byte
ISD5100 SERIES
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WaitACK
WaitSCLHigh
SendByte(row%256) - low address byte
WaitACK
WaitSCLHigh
I2CStop
repeat until the number of RAC pulses are one less
than the number of rows to delete
{
wait RAC low
WAIT RAC high
}
Note: If only one row is going to be erased,
send the following STOP command immediately after
ERASE command and skip the loop above
I2CStart
SendByte(0x80) - Write, Slave address zero
WaitACK
WaitSCLHigh
SendByte(0xc0) - Stop digital erase
WaitACK
WaitSCLHigh
I2CStop
wait until erase of the last row has completed
{
wait RAC low
WAIT RAC high
}
I2CStart
SendByte(0x80) - Write, Slave address zero
WaitACK
ISD5100 SERIES
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WaitSCLHigh
SendByte(0x40) - Exit Digital Mode Command
WaitACK
WaitSCLHigh
I2Cstop
Notes
1. Erase operations must be addressed on a Row boundary. The 5 LSB bits of the Low Address
Byte will be ignored.
2. I2C bus is released while erase proceeds. Other devices may use the bus until it is time to
execute the STOP command that causes the end of the Erase operation.
3. Host processor must count RAC cycles to determine where the chip is in the erase process,
one row per RAC cycle. RAC pulses LOW for 0.25 millisecond at the end of each erased
row. The erase of the "next" row begins with the rising edge of RAC. See the Digital Erase
RAC timing diagram on page 51.
4. When the erase of the last desired row begins, the following STOP command (Command Byte
= 80 hex) must be issued. This command must be completely given, including receiving the
ACK from the Slave before the RAC pin goes HIGH at the end of the row.
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 40 - Revision 1.42
S
SLAVE ADDRESS
A
W
40h
A
P
S
SLAVE ADDRESS
A
W
CON
A
P
A
S
SLAVE ADDRESS
W
Command Byte
D1h
A
DATA
A
DATA
A
High Addr. Byte
Low Addr. Byte
P
Erase starts on falling
edge of Slave
acknowledge
Note 2
A
S
SLAVE ADDRESS
W
Command Byte
80h
"N" RAC cycles
Note 3.
Last erased row
Note 4.
A
P
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
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SUGGESTED FLOW FOR DIGITAL ERASE IN
ISD5100-Series
ENTER DIGITAL
MODE
SEND ERASE
COMMAND
SEND STOP
COMMAND
BEFORE RAC
WAIT FOR
RAC
EXIT DIGITAL
MODE
DEVICE
POWERS DOWN
AUTOMATICALLY
YES
NO
COUNT RAC
FOR n-1
SEND STOP
COMMAND
BEFORE NEXT
RAC
TO ERASE
MULTIPLE (n) PAGES
(ROWS)
YES
NO
6/20/2002 BOJ
Revision B
WAIT FOR
RAC
NO
YES
RAC\ SIGNAL
125 uS
1.25 ms
80,C0
80,D1,nn,nn
80,C0
80,40
80,C0
STOP COMMAND MUST BE FINISHED BEFORE RAC\ RISES
80 = PowerUp or Stop
C0 = Enter Digital Mode
D1 = Erase Digital Page@
40 = Exit Digital Mode
COMMANDS
RAC\ ~ 125 uSRAC\ ~ 125 uS
RAC\ ~ 250 uS
250 uS
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
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6.5.4.2. Write Digital Data
Write
=====
I2CStart
SendByte(0x80) - Write, Slave address zero
WaitACK
WaitSCLHigh
SendByte(0xc0) - Enter Digital Mode Command
WaitACK
WaitSCLHigh
I2CStop
I2CStart
SendByte(0x80) - Write, Slave address zero
WaitACK
WaitSCLHigh
SendByte(0xc9) - Write Digital Data Command
WaitACK
WaitSCLHigh
SendByte(row/256) - high address byte
WaitACK
WaitSCLHigh
SendByte(row%256) - low address byte
WaitACK
WaitSCLHigh
repeat until all data is sent
{
SendByte(data) - send data byte
WaitACK()
WaitSCLHigh()
}
I2CStop
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
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I2CStart
SendByte(0x80) - Write, Slave address zero
WaitACK
WaitSCLHigh
SendByte(0x40) - Exit Digital Mode Command
WaitACK
WaitSCLHigh
I2CStop
S
SLAVE ADDRESS
A
W
Command Byte
C9h
A
DATA
A
DATA
A
High Addr. Byte
Low Addr. Byte
~
~
DATA
A
DATA
A
~
~
DATA
A
P
S
SLAVE ADDRESS
A
W
40h
A
P
S
SLAVE ADDRESS
A
W
CON
A
P
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 44 - Revision 1.42
SUGGESTED FLOW FOR DIGITAL WRITE IN ISD5100-Series
ENTER DIGITAL
MODE
SEND WRITE
COMMAND W/
START ADDRESS
EXIT DIGITAL
MODE
DEVICE
POWERS DOWN
AUTOMATICALLY
YES
6/24/2002 BOJ
Revision N/C
80,C0
80,C9,nn,nn
80,40
80 = PowerUp or Stop
C0 = Enter Digital Mode
C9 = Write Digital Page@
40 = Exit Digital Mode
COMMANDS
BYTE
COUNTER
=256?
NO
WAIT for SCL
HIGH
SEND
DATA
BYTE
(SEND
NEXT
BYTE)
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
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6.5.4.3. Read Digital Data
Read
=====
I2CStart
SendByte(0x80) - Write, Slave address zero
WaitACK
WaitSCLHigh
SendByte(0xc0) - Enter Digital Mode
WaitACK
WaitSCLHigh
I2CStop
I2CStart
SendByte(0x80) - Write, Slave address zero
WaitACK
WaitSCLHigh
SendByte(0xe1) - Read Digital Data Command
WaitACK
WaitSCLHigh
SendByte(row/256) - high address byte
WaitACK
WaitSCLHigh()
SendByte(row%256) - low address byte
WaitACK
WaitSCLHigh
I2CStart - Send repeat start command
SendByte(0x81) - Read, Slave address zero
repeat until all data is read
{
data = ReadByte() - send clocks to read data byte
SendACK - send NACK on the last byte
WaitSCLHigh - The only flow control available
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
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}
I2CStop()
I2CStart
SendByte(0x80) - Write, Slave address zero
WaitACK
WaitSCLHigh
SendByte(0x40) - Exit Digital Mode
WaitACK
WaitSCLHigh
I2CStop
A
S
SLAVE ADDRESS
W
Command Byte
E1h
A
DATA
A
DATA
A
High Addr. Byte
Low Addr. Byte
S
SLAVE ADDRESS
A
W
40h
A
P
S
SLAVE ADDRESS
A
W
CON
A
P
DATA
A
DATA
A
~
~
~
~
P
DATA
N
A
S
SLAVE ADDRESS
R
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 47 - Revision 1.42
SUGGESTED FLOW FOR DIGITAL READ IN ISD5100-Series
ENTER DIGITAL
MODE
SEND READ
COMMAND W/
START ADDRESS
EXIT DIGITAL
MODE
DEVICE
POWERS DOWN
AUTOMATICALLY
YES
6/24/2002 BOJ
Revision N/C
80,C0
80,E1,nn,nn
80,40
80 = PowerUp or Stop
C0 = Enter Digital Mode
E1 = Read Digital Page@
40 = Exit Digital Mode
COMMANDS
BYTE
COUNTER
=256?
NO
WAIT for SCL
HIGH
READ
DATA
BYTE
(READ
NEXT
BYTE)
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 48 - Revision 1.42
6.6. PIN DETAILS
6.6.1 Digital I/O Pins
SCL (Serial Clock Line)
The Serial Clock Line is a bi-directional clock line. It is an open-drain line requiring a pull-up resistor
to Vcc. It is driven by the "master" chips in a system and controls the timing of the data exchanged
over the Serial Data Line.
SDA (Serial Data Line)
The Serial Data Line carries the data between devices on the I2C interface. Data must be valid on this
line when the SCL is HIGH. State changes can only take place when the SCL is LOW. This is a bi-
directional line requiring a pull-up resistor to Vcc.
RAC (Row Address Clock)
RAC is an open drain output pin that normally marks the end of a row. At the 8 kHz sample frequency,
the duration of this period is 256 ms. RAC stays HIGH for 248 ms and stays LOW for the remaining 8
ms before it reaches the end of a row. There are 2048 rows of memory in the ISD5116 devices, 1024
rows in the ISD5108, 512 rows in the ISD5104 and 256 rows in the ISD5102.
1 ROW
RAC Waveform
During 8 KHz Operation
256 msec
TRAC 8 msec
TRACL
The RAC pin remains HIGH for 500 µsec and stays LOW for 15.6 µsec under the Message Cueing
mode. See the Timing Parameters table on page 64 for RAC timing information at other sample
rates. When a record command is first initiated, the RAC pin remains HIGH for an extra TRACML period,
to load sample and hold circuits internal to the device. The RAC pin can be used for message
management techniques.
1 ROW
RAC Waveform
During Message Cueing
@ 8KHz Operation 500 usec
TRACM 15.6 us
TRACML
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 49 - Revision 1.42
RAC Waveform During Digital Erase @ 8kHz Operation
1.25 ms
TRACE
.25 ms
TRACEL
INT
(Interrupt)
INT
is an open drain output pin. The ISD5100 Series interrupt pin goes LOW and stays LOW when an
Overflow (OVF) or End of Message (EOM) marker is detected. Each operation that ends in an EOM or
OVF generates an interrupt, including the message cueing cycles. The interrupt is cleared by a READ
STATUS instruction that will give a status byte out the SDA line.
XCLK (External Clock Input)
This is the external clock input. To use internal clock, this pin must be grounded (suggest connecting to
VSSD). While in internal clock mode, the ISD5100 Series are operated at one of four internal rates
selected for its internal oscillator by the Sample Rate Select bits. For precision timing control, external
clock signal can be applied through this pin. In the external clock mode, the device can be clocked
through the XCLK pin at 4.096 MHz as described in section 7.4.3 on page 32.
Because the anti-aliasing and smoothing filters track the Sample Rate Select bits, one must, for
optimum performance, maintain the external clock at 4.096 MHz AND set the Sample Rate
Configuration bits to one of the four values to properly set the filters to the correct cutoff frequency as
described in section 7.4.3 on page 32. The duty cycle on the input clock is not critical, as the clock is
immediately divided by two internally.
External Clock Input Table
ISD5116
Duration
(Minutes)
ISD5108
Duration
(Minutes)
ISD5104
Duration
(Minutes)
ISD5102
Duration
(Minutes)
Sample
Rate
(kHz)
Required
Clock
(kHz)
FLD1
FLD0
Filter
Knee
(kHz)
8.73
4.36
2.18
1.08
8.0
4096
0
0
3.4
10.9
5.45
2.72
1.35
6.4
4096
0
1
2.7
13.1
6.55
3.27
1.63
5.3
4096
1
0
2.3
17.5
8.75
4.37
2.18
4.0
4096
1
1
1.7
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 50 - Revision 1.42
A0, A1 (Address Pins)
These two pins are normally strapped for the desired address that the ISD5100 Series will have on the
I2C serial interface. If there are four of these devices on the bus, then each must be strapped
differently in order to allow the Master device to address them individually. The possible addresses
range from 80h to 87h, depending upon whether the device is being written to, or read from, by the
host. The ISD5100 Series have a 7-bit slave address of which only A0 and A1 are pin programmable.
The eighth bit (LSB) is the R/W bit. Thus, the address will be 1000 0xy0 or 1000 0xy1. (See the
table in section 7.3.1 on page 13.)
6.6.2 Analog I/O Pins
MIC+, MIC- (Microphone Input +/-)
The microphone input transfers the voice signal to the on-chip AGC preamplifier or directly to the ANA
OUT MUX, depending on the selected path. The direct path to the ANA OUT MUX has a gain of 6 dB
so a 208 mV p-p signal across the differential microphone inputs would give 416 mV p-p across the
ANA OUT pins. The AGC circuit has a range of 45 dB in order to deliver a nominal 694 mV p-p into the
storage array from a typical electret microphone output of 2 to 20 mV p-p. The input impedance is
typically 10kΩ.
ANA OUT+, ANA OUT- (Analog Output +/-)
This differential output is designed to go to the microphone input of the telephone chip set. It is de-
signed to drive a minimum of 5 kΩ between the ―+‖ and ―–‖ pins to a nominal voltage level of 694 mV p-
p. Both pins have DC bias of approximately 1.2 VDC. The AC signal is superimposed upon this analog
ground voltage. These pins can be used single-ended, getting only half the voltage. Do NOT ground
the unused pin.
+
Internal to the device
NOTE: fCUTOFF=
2RaCCOUP
1
FTHRU
CCOUP=0.1 F
Ra=10k
6 dB
MIC IN
10k
0.1
F
1.5k
Electret
Microphone
WM-54B
Panasonic
220 F
1.5k
1.5k
AGC
MIC+
MIC-
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 51 - Revision 1.42
ACAP (AGC Capacitor)
This pin provides the capacitor connection for setting the parameters of the microphone AGC circuit. It
should have a 4.7 µF capacitor connected to ground. It cannot be left floating. This is because the
capacitor is also used in the playback mode for the AutoMute circuit. This circuit reduces the amount of
noise present in the output during quiet pauses. Tying this pin to ground gives maximum gain; tying it
to VCCA gives minimum gain for the AGC amplifier but cancels the AutoMute function.
SP +, SP- (Speaker +/-)
This is the speaker differential output circuit. It is designed to drive an 8Ω speaker connected across
the speaker pins up to a maximum of 23.5 mW RMS power. This stage has two selectable gains, 1.32
and 1.6, which can be chosen through the configuration registers. These pins are biased to ap-
proximately 1.2 VDC and, if used single-ended, must be capacitively coupled to their load. Do NOT
ground the unused pin.
AUX OUT (Auxiliary Output)
The AUX OUT is an additional audio output pin to be used, for example, to drive the speaker circuit in
a ―car kit.‖ It drives a minimum load of 5kΩ and up to a maximum of 1V p-p. The AC signal is
superimposed on approximately 1.2 VDC bias and must be capacitively coupled to the load.
Speaker
SP+
SP–
AUX OUT Car Kit
(1 Vp-p Max)
ANA IN AMP
OUTPUT
MUX
FILTO
SUM2
2
VOL
(OPS1,OPS0)
2
(OPA1, OPA0)
INS0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AIG1 AIG0 AIPD AXG1 AXG0 AXPD AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0
OPS1
OPS0
SOURCE
0
0
VOL
0
1
ANA IN
1
0
FILTO
1
1
SUM2
OPA1
OPA0
SPKR DRIVE
AUX OUT
0
0
Power Down
Power Down
0
1
3.6 Vp.p @150
Power Down
1
0
23.5 mWatt @ 8
Power Down
1
1
Power Down
1 Vp.p Max @ 5K
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 52 - Revision 1.42
ANA IN (Analog Input)
The ANA IN pin is the analog input from the telephone chip set. It can be switched (by the I2C
interface) to the speaker output, the array input or to various other paths. This pin is designed to accept
a nominal 1.11 V p-p when at its minimum gain (6 dB) setting. There is additional gain available, if
required, in 3 dB steps, up to 15 dB. The gain settings are controlled from the I2C interface.
ANA IN Input Modes
ANA IN Amplifier Gain Settings
Setting(1)
0TLP Input
VP-P(3)
CFG0
Gain(2)
Array
In/Out VP-P
Speaker
Out VP-P(4)
AIG1
AIG0
6 dB
1.110
0
0
0.625
0.694
2.22
9 dB
0.785
0
1
0.883
0.694
2.22
12 dB
0.555
1
0
1.250
0.694
2.22
15 dB
0.393
1
1
1.767
0.694
2.22
1. Gain from ANA IN to SP+/-
2. Gain from ANA IN to ARRAY IN
3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3
dB below clipping
4. Speaker Out gain set to 1.6 (High). (Differential)
Gain
Setting
Resistor
Ration (Rb/Ra)
Gain
Gain2
(dB)
00
63.9 / 102
0.625
-4.1
01
77.9 / 88.1
0.88
-1.1
10
92.3 / 73.8
1.25
1.9
11
106 / 60
1.77
4.9
Note: Ra & Rb are in k
ANA IN
Input
ANA IN
Input Amplifier
NOTE: fCUTTOFF
2xRaCCCUP
1
Ra
Rb
CCOUP = 0.1 ìF
Internal to the device
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 53 - Revision 1.42
AUX IN (Auxiliary Input)
The AUX IN is an additional audio input to the ISD5100-Series, such as from the microphone circuit in
a mobile phone ―car kit.‖ This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB).
See the AUX IN Amplifier Gain Settings table on page 56. Additional gain is available in 3 dB steps
(controlled by the I2C interface) up to 9 dB.
AUX IN Input Modes
AUX IN Amplifier Gain Settings
Setting(1)
0TLP Input
VP-P(3)
CFG0
Gain(2)
Array
In/Out VP-P
Speaker
Out VP-P(4)
AXG1
AXG0
0 dB
0.694
0
0
1.00
0.694
0.694
3 dB
0.491
0
1
1.41
0.694
0.694
6 dB
0.347
1
0
2.00
0.694
0.694
9 dB
0.245
1
1
2.82
0.694
0.694
1. Gain from AUX IN to ANA OUT
2. Gain from AUX IN to ARRAY IN
3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB
below clipping
4. Differential
Gain
Setting
Resistor Ratio
(Rb/Ra)
Gain
Gain(2)
(dB)
00
40.1 / 40.1
1.0
0
01
47.0 / 33.2
1.414
3
10
53.5 / 26.7
2.0
6
11
59.2 / 21
2.82
9
Note: Ra & Rb are in k
AUX IN
Input
ANA IN
Input Amplifier
NOTE: fCUTTOFF
2xRaCCCUP
1
Ra
Rb
CCOUP = 0.1 ìF
Internal to the device
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 54 - Revision 1.42
6.6.3 Power and Ground Pins
VCCA, VCCD (Voltage Inputs)
To minimize noise, the analog and digital circuits in the ISD5100 Series devices use separate power
busses. These +3 V busses lead to separate pins. Tie the VCCD pins together as close as possible and
decouple both supplies as near to the package as possible.
VSSA, VSSD (Ground Inputs)
The ISD5100 Series utilizes separate analog and digital ground busses. The analog ground (VSSA) pins
should be tied together as close to the package as possible and connected through a low-impedance
path to power supply ground. The digital ground (VSSD) pin should be connected through a separate
low impedance path to power supply ground. These ground paths should be large enough to ensure
that the impedance between the VSSA pins and the VSSD pin is less than 3Ω. The backside of the die is
connected to VSSD through the substrate resistance. In a chip-on-board design, the die attach area
must be connected to VSSD.
NC (Not Connect)
These pins should not be connected to the board at any time. Connection of these pins to any signal,
ground or VCC, may result in incorrect device behavior or cause damage to the device.
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 55 - Revision 1.42
6.6.4 PCB Layout Examples
For SOIC package :
PC board traces and the three chip capacitors are on the bottom side of the board.
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
V
C
C
D
XCLK
Analog Ground
1
VSSA
To
VCCA
V
S
S
D
(Digital Ground)
Note 1: VSSD traces should be kept
separated back to the VSS supply feed
point..
Note 2: VCCD traces should be kept
separate back to the VCC Supply feed
point.
Note 3: The Digital and Analog grounds
tie together at the power supply. The
VCCA and VCCD supplies will also need
filter capacitors per good engineering
practice (typ. 50 to 100 uF).
C1
C2
C3
Note 1
Note 2
C1=C2=C3=0.1 uF chip Capacitors
Note 3
Note 3
7. TIMING DIAGRAMS
7.1 I2C TIMING DIAGRAM
t
LOW
t
SCLK
t
HIGH
t
f
t
r
t
SU-DAT
t
SU-STO
t
f
START
SDA
SCL
STOP
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 56 - Revision 1.42
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 57 - Revision 1.42
I2C INTERFACE TIMING
STANDARD-MODE
FAST-MODE
PARAMETER
SYMBOL
MIN.
MAX.
MIN.
MAX.
UNIT
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START
condition. After this period, the first
clock pulse is generated
tHD-STA
4.0
-
0.6
-
μs
LOW period of the SCL clock
tLOW
4.7
-
1.3
-
μs
HIGH period of the SCL clock
tHIGH
4.0
-
0.6
-
μs
Set-up time for a repeated START
condition
tSU-STA
4.7
-
0.6
-
μs
Data set-up time
tSU-DAT
250
-
100(1)
-
ns
Rise time of both SDA and SCL
signals
tr
-
1000
20 + 0.1Cb(2)
300
ns
Fall time of both SDA and SCL
signals
tf
-
300
20 + 0.1Cb(2)
300
ns
Set-up time for STOP condition
tSU-STO
4.0
-
0.6
-
μs
Bus-free time between a STOP and
START condition
tBUF
4.7
-
1.3
-
μs
Capacitive load for each bus line
Cb
-
400
-
400
pF
Noise margin at the LOW level for
each connected device (including
hysteresis)
VnL
0.1 VDD
-
0.1 VDD
-
V
Noise margin at the HIGH level for
each connected device (including
hysteresis)
VnH
0.2 VDD
-
0.2 VDD
-
V
1. A Fast-mode I2C-interface device can be used in a Standard-mode I2C-interface system, but the
requirement tSU;DAT > 250 ns must then be met. This will automatically be the case if the device does
not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line; tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C -interface specification)
before the SCL line is released.
2. Cb = total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall-times are
allowed.
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 58 - Revision 1.42
7.2 PLAYBACK AND STOP CYCLE
SDA
SCL
ANA IN
ANA OUT
DATA CLOCK PULSES
STOP
PLAY AT ADDR
tSTOP
tSTART
STOP
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 59 - Revision 1.42
7.3 EXAMPLE OF POWER UP COMMAND (FIRST 12 BITS)
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 60 - Revision 1.42
8. ABSOLUTE MAXIMUM RATINGS
ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)(1)
Condition
Value
Junction temperature
1500C
Storage temperature range
-650C to +1500C
Voltage Applied to any pins
(VSS - 0.3V) to (VCC + 0.3V)
Voltage applied to any pin (Input current limited to +/-20 mA)
(VSS – 1.0V) to (VCC + 1.0V)
Lead temperature (soldering – 10 seconds)
3000C
VCC - VSS
-0.3V to +5.5V
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
ABSOLUTE MAXIMUM RATINGS (DIE)(1)
Condition
Value
Junction temperature
1500C
Storage temperature range
-650C to +1500C
Voltage Applied to any pads
(VSS - 0.3V) to (VCC + 0.3V)
VCC - VSS
-0.3V to +5.5V
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 61 - Revision 1.42
OPERATING CONDITIONS (PACKAGED PARTS)
Conditions
Values
Commercial operating temperature [1]
0C to +70C
Supply voltage (VCC) [2]
+2.7V to +3.3V
Ground voltage (VSS) [3]
0V
Voltage Applied to any pins
(VSS - 0.3V) to (VCC + 0.3V)
Conditions
Values
Industrial operating temperature [1]
-40C to +85C
Supply voltage (VCC) [2]
ISD5102, ISD5104, ISD5116
+2.7V to +3.3V
ISD5108
+2.7V to +3.6V
Ground voltage (VSS) [3]
0V
Voltage Applied to any pins
(VSS - 0.3V) to (VCC + 0.3V)
OPERATING CONDITIONS (DIE)
Conditions
Values
Die operating temperature range [1]
0C to +50C
Supply voltage (VCC) [2]
+2.7V to +3.3V
Ground voltage (VSS) [3]
0V
Voltage Applied to any pads
(VSS - 0.3V) to (VCC + 0.3V)
[1] Case temperature [2] VCC = VCCA = VCCD [3] VSS = VSSA = VSSD
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 62 - Revision 1.42
9. ELECTRICAL CHARACTERISTICS
9.1. GENERAL PARAMETERS
Symbol
Parameters
Min(2)
Typ(1)
Max(2)
Units
Conditions
VIL
Input Low Voltage
VCC x 0.2
V
VIH
Input High Voltage
VCC x 0.8
V
VOL
SCL, SDA Output Low Voltage
0.4
V
IOL = 3 µA
VIL2V
Input low voltage for 2V
interface
0.4
V
Apply only to
SCL, SDA
VIH2V
Input high voltage for 2V
interface
1.6
V
Apply only to
SCL, SDA
VOL1
RAC, INT Output Low Voltage
0.4
V
IOL = 1 mA
VOH
Output High Voltage
VCC – 0.4
V
IOL = -10 µA
ICC
VCC Current (Operating)
- Playback
- Record
- Feedthrough
15
30
12
25
40
15
mA
mA
mA
No Load(3)
No Load(3)
No Load(3)
ISB
VCC Current (Standby)
1
10
µA
[3]
IIL
Input Leakage Current
1
µA
[1] Typical values: TA = 25°C and Vcc = 3.0 V.
[2] All min/max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all
specifications are 100 percent tested.
[3] All VCC and VSS are connected appropriately and others are floated.
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 63 - Revision 1.42
9.2. TIMING PARAMETERS
Symbol
Parameters
Min(2)
Typ(1)
Max(2)
Units
Conditions
FS
Sampling Frequency
8.0
6.4
5.3
4.0
kHz
kHz
kHz
kHz
(5)
(5)
(5)
(5)
FCF
Filter Knee
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
3.4
2.7
2.3
1.7
kHz
kHz
kHz
kHz
Knee Point(3)(7)
Knee Point(3)(7)
Knee Point(3)(7)
Knee Point(3)(7)
TREC
Record Duration
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
ISD5116
ISD5108
ISD5104
ISD5102
min
min
min
min
(6)
(6)
(6)
(6)
8.73
10.9
13.1
17.5
4.36
5.45
6.55
8.75
2.18
2.72
3.27
4.37
1.08
1.35
1.63
2.18
TPLAY
Playback Duration
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
ISD5116
ISD5108
ISD5104
ISD5102
min
min
min
min
(6)
(6)
(6)
(6)
8.73
10.9
13.1
17.5
4.36
5.45
6.55
8.75
2.18
2.72
3.27
4.37
1.08
1.35
1.63
2.18
TPUD
Power-Up Delay
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
1
1
1
1
msec
msec
msec
msec
TSTOP/
PAUSE
Stop or Pause
Record or Play
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
32
40
48
64
msec
msec
msec
msec
TRAC
RAC Clock Period
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
256
320
384
msec
msec
msec
(9)
(9)
(9)
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 64 - Revision 1.42
4.0 kHz (sample rate)
512
msec
(9)
TRACL
RAC Clock Low Time
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
8
10
12.1
16
msec
msec
msec
msec
TRACM
RAC Clock Period in
Message Cueing Mode
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
500
625
750
1000
µsec
µsec
µsec
µsec
TRACML
RAC Clock Low Time in
Message Cueing Mode
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
15.6
19.5
23.4
31.2
µsec
µsec
µsec
µsec
TRACE
RAC Clock Period in
Digital Erase Mode
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
1.25
1.56
1.87
2.50
msec
msec
msec
msec
TRACEL
RAC Clock Low Time in
Digital Erase mode
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
0.25
0.31
0.37
0.50
msec
msec
msec
msec
THD
Total Harmonic
Distortion
ANA IN to ARRAY,
ARRAY to SPKR
1
1
2
2
%
%
@1 kHz at
0TLP, sample
rate = 5.3 kHz
ISD5100 SERIES
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9.3. ANALOG PARAMETERS
MICROPHONE INPUT(14)
Symbol
Parameters
Min(2)
Typ(1)(14)
Max(2)
Units
Conditions
VMIC+/-
MIC +/- Input Voltage
300
mV
Peak-to-Peak(4)(8)
VMIC (0TLP)
MIC +/- input reference
transmission level point
(0TLP)
208
mV
Peak-to-Peak(4)(10)
AMIC
Gain from MIC +/- input to
ANA OUT
5.5
6.0
6.5
dB
1 kHz at VMIC
(0TLP)(4)
AMIC (GT)
MIC +/- Gain Tracking
+/-0.1
dB
1 kHz, +3 to –40
dB 0TLP Input
RMIC
Microphone input resistance
10
k
MIC- and MIC+
pins
AAGC
Microphone AGC Amplifier
Range
6
40
dB
Over 3-300 mV
Range
ANA IN(14)
Symbol
Parameters
Min(2)
Typ(1)(14)
Max(2)
Units
Conditions
VANA IN
ANA IN Input Voltage
1.6
V
Peak-to-Peak (6 dB
gain setting)
VANA IN (0TLP)
ANA IN (0TLP) Input
Voltage
1.1
V
Peak-to-Peak (6 dB
gain setting)(10)
AANA IN (sp)
Gain from ANA IN to SP+/-
+6 to +15
dB
4 Steps of 3 dB
AANA IN (AUX OUT)
Gain from ANA IN to AUX
OUT
-4 to +5
dB
4 Steps of 3 dB
AANA IN (GA)
ANA IN Gain Accuracy
-0.5
+0.5
dB
(11)
AANA IN (GT)
ANA IN Gain Tracking
+/-0.1
dB
1000 Hz, +3 to –45
dB 0TLP Input,
6 dB setting
RANA IN
ANA IN Input Resistance (6
dB to +15 dB)
10 to 100
k
Depending on ANA
IN Gain
ISD5100 SERIES
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AUX IN(14)
Symbol
Parameters
Min(2)
Typ(1)(14)
Max(2)
Units
Conditions
VAUX IN
AUX IN Input Voltage
1.0
V
Peak-to-Peak (0 dB
gain setting)
VAUX IN (0TLP)
AUX IN (0TLP) Input
Voltage
694.2
mV
Peak-to-Peak (0 dB
gain setting)
AAUX IN (ANA OUT)
Gain from AUX IN to ANA
OUT
0 to +9
dB
4 Steps of 3 dB
AAUX IN (GA)
AUX IN Gain Accuracy
-0.5
+0.5
dB
(11)
AAUX IN (GT)
AUX IN Gain Tracking
+/-0.1
dB
1000 Hz, +3 to –45
dB 0TLP Input, 0
dB setting
RAUX IN
AUX IN Input Resistance
10 to 100
k
Depending on AUX
IN Gain
SPEAKER OUTPUTS(14)
Symbol
Parameters
Min(2)
Typ(1)(14)
Max(2)
Units
Conditions
VSPHG
SP+/- Output Voltage (High
Gain Setting)
3.6
V
Peak-to-Peak,
differential load =
150, OPA1,
OPA0 = 01
RSPLG
SP+/- Output Load Imp.
(Low Gain)
8
OPA1, OPA0 = 10
RSPHG
SP+/- Output Load Imp.
(High Gain)
70
150
OPA1, OPA0 = 01
CSP
SP+/- Output Load Cap.
100
pF
VSPAG
SP+/- Output Bias Voltage
(Analog Ground)
1.2
VDC
VSPDCO
Speaker Output DC Offset
+/-100
mV
DC
With ANA IN to
Speaker, ANA IN
AC coupled to VSSA
ICNANA IN/(SP+/-)
ANA IN to SP+/- Idle
Channel Noise
-65
dB
Speaker Load =
150(12)(13)
CRT(SP+/-)/ANA
OUT
SP+/- to ANA OUT Cross
Talk
-65
dB
1 kHz 0TLP input
to ANA IN, with
MIC+/- and AUX IN
AC coupled to VSS,
and measured at
ANA OUT feed
through mode (12)
PSRR
Power Supply Rejection
Ratio
-55
dB
Measured with a 1
kHz, 100 mV p-p
ISD5100 SERIES
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sine wave input at
VCC and VCC pins
FR
Frequency Response (300-
3400 Hz)
+0.5
dB
With 0TLP input to
ANA IN, 6 dB
setting (12)
Guaranteed by
design
POUTLG
Power Output (Low Gain
Setting)
23.5
mW
RMS
Differential load at
8
SINAD
SINAD ANA IN to SP+/-
62.5
dB
0TLP ANA In input
minimum gain,
150 load (12)(13)
ANA OUT (14)
Symbol
Parameters
Min (2)
Type
(1)(14)
Max (2)
Units
Conditions
SINAD
SINAD, MIC IN to ANA OUT
62.5
dB
Load = 5k(12)(13)
SINAD
SINAD, AUX IN to ANA OUT
(0 to 9 dB)
62.5
dB
Load = 5k(12)(13)
ICONIC/ANA OUT
Idle Channel Noise –
Microphone
-65
dB
Load = 5k(12)(13)
ICN AUX IN/ANA
OUT
Idle Channel Noise – AUX
IN (0 to 9 dB)
-65
dB
Load = 5k(12)(13)
PSRR (ANA OUT)
Power Supply Rejection
Ratio
-40
dB
Measured with a 1
kHz, 100 mV P-P
sine wave to VCCA,
VCCD pins
VBIAS
ANA OUT+ and ANA OUT-
1.2
VDC
Inputs AC coupled
to VSSA
VOFFSET
ANA OUT+ to ANA OUT-
+/- 100
mV
DC
Inputs AC coupled
to VSSA
RL
Minimum Load Impedance
5
k
Differential Load
FR
Frequency Response (300-
3400 Hz)
+0.5
dB
0TLP input to
MIC+/- in
feedthrough mode.
0TLP input to AUX
IN in feedthrough
mode(12)
CRTANA OUT/(SP+/-)
ANA OUT to SP+/- Cross
Talk
-65
dB
1 kHz 0TLP output
from ANA OUT,
with ANA IN AC
coupled to VSSA,
and measured at
SP+/-(12)
ISD5100 SERIES
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CRTANA OUT/AUX
OUT
ANA OUT to AUX OUT
Cross Talk
-65
dB
1 kHz 0TLP output
from ANA OUT,
with ANA IN AC
coupled to VSSA,
and measured at
AUX OUT(12)
AUX OUT(14)
Symbol
Parameters
Min(2)
Typ(1(14))
Max(2)
Units
Conditions
VAUX OUT
AUX OUT – Maximum
Output Swing
1.0
V
5k Load
RL
Minimum Load Impedance
5
K
CL
Maximum Load Capacitance
100
pF
VBIAS
AUX OUT
1.2
VDC
SINAD
SINAD – ANA IN to AUX
OUT
62.5
dB
0TLP ANA IN input,
minimum gain, 5k
load(12)(13)
ICN(AUX OUT)
Idle Channel Noise – ANA
IN to AUX OUT
-65
dB
Load=5k(12)(13)
CRTAUX OUT/ANA
OUT
AUX OUT to ANA OUT
Cross Talk
-65
dB
1 kHz 0TLP input
to ANA IN, with
MIC +/- and AUX
IN AC coupled to
VSSA, measured at
SP+/-, load = 5k.
Referenced to
nominal 0TLP @
output
VOLUME CONTROL(14)
Symbol
Parameters
Min(2)
Typ(1)(14)
Max(2)
Units
Conditions
AOUT
Output Gain
-28 to 0
dB
8 steps of 4 dB,
referenced to
output
Tolerance for each step
-1.0
+1.0
dB
ANA IN 1.0 kHz
0TLP, 6 dB gain
setting m eas ured
differentially at
SP+/-
ISD5100 SERIES
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Conditions
1. Typical values: TA = 25°C and Vcc = 3.0V.
2. All min/max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all
specifications are 100 percent tested.
3. Low-frequency cut off depends upon the value of external capacitors (see Pin Descriptions).
4. Differential input mode. Nominal differential input is 208 mV p-p. (0TLP)
5. Sampling frequency can vary as much as –6/+4 percent over the industrial temperature and voltage
ranges. For greater stability, an external clock can be utilized (see Pin Descriptions).
6. Playback and Record Duration can vary as much as –6/+4 percent over the industrial temperature
and voltage ranges. For greater stability, an external clock can be utilized (See Pin Descriptions).
7. Filter specification applies to the low pass filter.
8. For optimal signal quality, this maximum limit is recommended.
9. When a record command is sent, TRAC = TRAC + TRACL on the first page addressed.
10. The maximum signal level at any input is defined as 3.17 dB higher than the reference transmission
level point. (0TLP) This is the point where signal clipping may begin.
11. Measured at 0TLP point for each gain setting. See the ANA IN table and AUX IN table on pages 54
and 55 respectively.
12. 0TLP is the reference test level through inputs and outputs. See the ANA IN table and AUX IN table
on pages 54 and 55 respectively.
13. Referenced to 0TLP input at 1 kHz, measured over 300 to 3,400 Hz bandwidth.
14. For die, only typical values are applicable.
9.4. CHARACTERISTICS OF THE I2C SERIAL INTERFACE
The I2C interface is for bi-directional, two-line communication between different ICs or modules. The
two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a
positive supply via a pull-up resistor. Data transfer may be initiated only when the interface bus is not
busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable
during the HIGH period of the clock pulse, as changes in the data line at this time will be interpreted as
a control signal.
ISD5100 SERIES
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Start and stop conditions
Both data and clock lines remain HIGH when the interface bus is not busy. A HIGH-to-LOW transition
of the data line while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition
of the data line while the clock is HIGH is defined as the stop condition (P).
System configuration
A device generating a message is a ‗transmitter‘; a device receiving a message is the ‗receiver‘. Th
System Configuration
A device generating a message is a ‗transmitter‘; a device receiving a message is the ‗receiver‘. The
device that controls the message I sthe ‗master‘ and the devices that are controlled by the master are
the ‗slaves‘.
SDA
SCL
S
P
START condition
STOP condition
Definition of START and STOP conditions
SDA
SCL
SDA
SCL
data line
stable;
data valid
changed
of data
allowed
Bit transfer on the I2C-Bus
ISD5100 SERIES
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Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is
a HIGH level signal put on the interface bus by the transmitter during which time the master generates
an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. In addition, a master receiver must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that
the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave.
In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop
condition.
Example of an I2C-bus configuration using two microcontrollers
SDA
SCL
MICRO-
CONTROLLER
LCD
DRIVER
STATIC
RAM OR
EEPROM
GATE
ARRAY
ISD 5116
8
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
not acknowledge
acknowledge
dock pulse for
acknowledgement
S
START
condition
Acknowledge on the I2C-bus
1
2
9
ISD5100 SERIES
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9.5. I2C PROTOCOL
Since the I2C protocol allows multiple devices on the bus, each device must have an address. This
address is known as a ―Slave Address‖. A Slave Address consists of 7 bits, followed by a single bit that
indicates the direction of data flow. This single bit is 1 for a Write cycle, which indicates the data is
being sent from the current bus master to the device being addressed. This single bit is a 0 for a Read
cycle, which indicates that the data is being sent from the device being addressed to the current bus
master. For example, the valid Slave Addresses for the ISD5100 Series device, for both Write and
Read cycles, are shown in section 7.3.1 on page 13 of this datasheet.
Before any data is transmitted on the I2C interface, the current bus master must address the slave it
wishes to transfer data to or from. The Slave Address is always sent out as the 1st byte following the
Start Condition sequence. An example of a Master transmitting an address to a ISD5100 Series slave
is shown below. In this case, the Master is writing data to the slave and the R/W bit is ―0‖, i.e. a Write
cycle. All the bits transferred are from the Master to the Slave, except for the indicated Acknowledge
bits. The following example details the transfer explained in section 7.3.1-2-3 on pages 13-20 of this
datasheet.
Master Transmits to Slave Receiver (Write) Mode
S W A A A A P
SLAVE ADDRESS
COMMAND BYTE
High ADDR. BYTE
Low ADDR. BYTE
acknowledgement
from slave acknowledgement
from slave acknowledgement
from slave acknowledgement
from slave
R/W
Start Bit Stop Bit
A common procedure in the ISD5100 Series is the reading of the Status Bytes. The Read Status
condition in the ISD5100 Series is triggered when the Master addresses the chip with its proper Slave
Address, immediately followed by the R/W bit set to a ―1‖ and without the Command Byte being sent.
This is an example of the Master sending to the Slave, immediately followed by the Slave sending data
back to the Master. The ―N‖ not-acknowledge cycle from the Master ends the transfer of data from the
Slave. The following example details the transfer explained in section 7.3.1 on page 13 of this
datasheet.
ISD5100 SERIES
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Master Reads from Slave immediately after first byte (Read Mode)
R/W
From
Master
Start Bit
From
Master
Stop Bit
From
Master
acknowledgement
from slave
acknowledgement
from Master
not-acknowledged
from Master
acknowledgement
from Master
From Master
From Slave From SlaveFrom Slave
S R A A A
NP
Low ADDR BYTE
SLAVE ADDRESS
STATUS WORD
High ADDR. BYTE
Another common operation in the ISD5100 Series is the reading of digital data from the chip‘s memory
array at a specific address. This requires the I2C interface Master to first send an address to the
ISD5100 Series Slave device, and then receive data from the Slave in a single I2C operation. To
accomplish this, the data direction R/W bit must be changed in the middle of the command. The
following example shows the Master sending the Slave address, then sending a Command Byte and 2
bytes of address data to the ISD5100-Series, and then immediately changing the data direction and
reading some number of bytes from the chip‘s digital array. An unlimited number of bytes can be read
in this operation. The ―N‖ not-acknowledge cycle from the Master forces the end of the data transfer
from the Slave. The following example details the transfer explained in section 7.5.4 on page 47 of this
datasheet.
Master Reads from the Slave after setting data address in Slave (Write data address, READ Data)
S W A A A A
SLAVE ADDRESS
COMMAND BYTE
High ADDR. BYTE
Low ADDR. BYTE
acknowledgement
from slave acknowledgement
from slave acknowledgement
from slave acknowledgement
from slave
R/W
From
Master
Start Bit
From
Master
S R A A A
NP
8 BITS of DATA
SLAVE ADDRESS
8 BITS of DATA
8 BITS of DATA
R/W
From
Master
Start Bit
From
Master
Stop Bit
From
Master
acknowledgement
from slave
acknowledgement
from Master
not-acknowled
from Master
acknowledgement
from Master
From Master
From Slave From SlaveFrom Slave
ISD5100 SERIES
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10. TYPICAL APPLICATION CIRCUIT
The following typical application example on ISD5100 series is for references only. They make no
representation or warranty that such applications shall be suitable for the use specified. It‘s
customer‘s obligation to verify the design in its own system for the functionalities, voice quality,
current consumption, and etc.
In addition, the below notes apply to the following application examples:
* The suggested values are for references only. Depending on system requirements, they can
be adjusted for functionalities and better performance.
It is important to have a separate path for each ground and power back to the related terminals to
minimize the noise. Besides, the power supplies should be decoupled as close to the device as
possible.
Also, it is crucial to follow good audio design practices in layout and power supply decoupling. See
recommendations in Application Notes from our websites.
Example #1: Recording via microphone
SCL
SDA
A1
A0
MIC+
MIC-
ACAP
SP+
SP-
5100
1
2
3
4
16
14
To C
I2C Interface &
Address Setting
μ
SOIC / PDIP
8
10
13
VCC
220
F*
μ
Electret
microphone
C I/O
μ
XCLK
ANA IN
AUX IN
ANA OUT+
ANA OUT-
AUX OUT
26
18
19
11
12
20
VCCD
VCCD
VSSD
VSSD
27
28
5
6
VCC
0.1 F
μ
RAC
INT
24
25
To C I/O for message
management (optional)
μ
VSSA
VSSA
VSSA
9
15
23
VCCA 17
0.1 F
μ
1.5k *
Ω
1.5k *
Ω
1.5k *
Ω
0.1 F*
μ
0.1 F*
μ
4.7 F*
μ
ISD5100 SERIES
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11. PACKAGE SPECIFICATION
11.1. 28-LEAD 300-MIL PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT (SOIC)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1234 5 6 7 8910 11 12 13 14
A
D
EF
B
G
C
H
Min Nom Max Min Nom Max
A0.701 0.706 0.711 17.81 17.93 18.06
B0.097 0.101 0.104 2.46 2.56 2.64
C0.292 0.296 0.299 7.42 7.52 7.59
D0.005 0.009 0.0115 0.127 0.22 0.29
E0.014 0.016 0.019 0.35 0.41 0.48
F0.050 1.27
G0.400 0.406 0.410 10.16 10.31 10.41
H0.024 0.032 0.040 0.61 0.81 1.02
Note: Lead coplanarity to be within 0.004 inches.
Plastic Small Outline Integrated Circuit (SOIC) Dimensions
INCHES
MILLIMETERS
ISD5100 SERIES
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11.2. 28-LEAD 600-MIL PLASTIC DUAL INLINE PACKAGE (PDIP)
Plastic Dual Inline Package (PDIP) (P) Dimensions
INCHES
MILLIMETERS
Min
Nom
Max
Min
Nom
Max
A
1.445
1.450
1.455
36.70
36.83
36.96
B1
0.150
3.81
B2
0.065
0.070
0.075
1.65
1.78
1.91
C1
0.600
0.625
15.24
15.88
C2
0.530
0.540
0.550
13.46
13.72
13.97
D
0.19
4.83
D1
0.015
0.38
E
0.125
0.135
3.18
3.43
F
0.015
0.018
0.022
0.38
0.46
0.56
G
0.055
0.060
0.065
1.40
1.52
1.65
H
0.100
2.54
J
0.008
0.010
0.012
0.20
0.25
0.30
S
0.070
0.075
0.080
1.78
1.91
2.03
0
0°
15°
0°
15°
ISD5100 SERIES
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11.3. ISD5116 DIE INFORMATION
≈
ISD5116
≈
VSSA
MIC +
MIC -
ANA OUT +
ANA OUT -
ACAP
SP -VSSA [2] SP +
VCCA [2] ANA IN AUX IN
AUX OUT
VSSD
VSSD A0SDA A1
SCL VCCDXCLK RAC
VSSA
INT
VCCD
ISD5116 Device
Die Dimensions
X: 4125 µm
Y: 8030 µm
Die Thickness [3]
292.1 µm ± 12.7 µm
Pad Opening
Single pad: 90 x 90 µm
Double pad: 180 x 90 µm
Notes
1. The backside of die is internally connected to Vss. It MUST NOT be connected to any other potential or
damage may occur.
2. Double bond recommended, if treated as single doubled-pad.
3. This figure reflects the current die thickness. Please contact Nuvoton as this thickness may change in
the future.
ISD5100 SERIES
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ISD5116 Pad Coordinates
(with respect to die center in µm)
Pad
Pad Name
X Axis
Y Axis
VSSA
Analog Ground
1879.45
3848.65
RAC
Row Address Clock
1536.20
3848.65
INT
Interrupt
787.40
3848.65
XCLK
External Clock Input
475.60
3848.65
VCCD
Digital Supply Voltage
288.60
3848.65
VCCD
Digital Supply Voltage
73.20
3848.65
SCL
Serial Clock Line
-201.40
3848.65
A1
Address 1
-560.90
3848.65
SDA
Serial Data Address
-818.20
3848.65
A0
Address 0
-1369.40
3848.65
VSSD
Digital Ground
-1671.30
3848.65
VSSD
Digital Ground
-1842.90
3848.65
VSSA
Analog Ground
-1948.00
-3841.60
MIC+
Non-inverting Microphone Input
-1742.20
-3841.60
MIC-
Inverting Microphone Input
-1509.70
-3841.60
ANA OUT+
Non-inverting Analog Output
-1248.00
-3841.60
ANA OUT-
Inverting Analog Output
-913.80
-3841.60
ACAP
AGC/AutoMute Cap
-626.50
-3841.60
SP-
Speaker Negative
-130.70
-3841.60
VSSA
Analog Ground
202.90
-3841.60
VSSA
Analog Ground
292.90
-3841.60
SP+
Speaker Positive
626.50
-3841.60
VCCA
Analog Supply Voltage
960.10
-3841.60
VCCA
Analog Supply Voltage
1050.10
-3841.60
ANA IN
Analog Input
1257.40
-3841.60
AUX IN
Auxiliary Input
1523.00
-3841.60
AUX OUT
Auxiliary Output
1767.20
-3841.60
ISD5100 SERIES
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11.4. ISD5108 DIE INFORMATION
≈
ISD5108
≈
VSSA
MIC + MIC -
ANA OUT +
ANA OUT -ACAPSP -VSSA [2] SP +
VCCA [2] ANA IN AUX IN
AUX OUT
VSSD
VSSD A0SDA A1
SCL VCCDXCLK RAC
VSSA
INT
VCCD
ISD5108 Device
Die Dimensions (include scribe line)
X: 4230 µm
Y: 6090 µm
Die Thickness [3]
292.1 µm ± 12.7 µm
Pad Opening
Single pad: 90 x 90 µm
Double pad: 180 x 90 µm
Notes
1. The backside of die is internally connected to Vss. It MUST NOT be connected to any other potential or
damage may occur.
2. Double bond recommended, if treated as single doubled-pad.
3. This figure reflects the current die thickness. Please contact Nuvoton as this thickness may change in
the future.
ISD5100 SERIES
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ISD5108 Pad Coordinates
(with respect to die center in µm)
Pad
Pad Name
X Axis
Y Axis
VSSA
Analog Ground
1882.40
2820.65
RAC
Row Address Clock
1539.15
2820.65
INT
Interrupt
790.35
2820.65
XCLK
External Clock Input
478.55
2820.65
VCCD
Digital Supply Voltage
291.55
2820.65
VCCD
Digital Supply Voltage
76.15
2820.65
SCL
Serial Clock Line
-198.45
2820.65
A1
Address 1
-557.95
2820.65
SDA
Serial Data Address
-815.25
2820.65
A0
Address 0
-1366.45
2820.65
VSSD
Digital Ground
-1668.35
2820.65
VSSD
Digital Ground
-1839.95
2820.65
VSSA
Analog Ground
-1945.05
-2821.60
MIC+
Non-inverting Microphone Input
-1739.25
-2821.60
MIC-
Inverting Microphone Input
-1506.75
-2821.60
ANA OUT+
Non-inverting Analog Output
-1245.05
-2821.60
ANA OUT-
Inverting Analog Output
-910.85
-2821.60
ACAP
AGC/AutoMute Cap
-623.55
-2821.60
SP-
Speaker Negative
-127.75
-2821.60
VSSA
Analog Ground
205.85
-2821.60
VSSA
Analog Ground
295.85
-2821.60
SP+
Speaker Positive
629.45
-2821.60
VCCA
Analog Supply Voltage
963.05
-2821.60
VCCA
Analog Supply Voltage
1053.05
-2821.60
ANA IN
Analog Input
1260.35
-2821.60
AUX IN
Auxiliary Input
1525.95
-2821.60
AUX OUT
Auxiliary Output
1770.15
-2821.60
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 81 - Revision 1.42
11.5. ISD5104 DIE INFORMATION
≈
ISD5104
≈
VSSA
MIC + MIC -
ANA OUT +
ANA OUT -ACAPSP -VSSA [2] SP +
VCCA [2] ANA IN AUX IN
AUX OUT
VSSD VSSD A0SDA A1
SCL VCCD
XCLK RAC
VSSA
INT
VCCD
ISD5104 Device
Die Dimensions (include scribe line)
X: 4230 µm
Y: 5046 µm
Die Thickness [3]
292.1 µm ± 12.7 µm
Pad Opening
Single pad: 90 x 90 µm
Double pad: 180 x 90 µm
Notes
1. The backside of die is internally connected to Vss. It MUST NOT be connected to any other potential or
damage may occur.
2. Double bond recommended, if treated as single doubled-pad.
3. This figure reflects the current die thickness. Please contact Nuvoton as this thickness may change in
the future.
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 82 - Revision 1.42
ISD5104 Pad Coordinates
(with respect to die center in µm)
Pad
Pad Name
X Axis
Y Axis
VSSA
Analog Ground
1882.4
2306.65
RAC
Row Address Clock
1539.15
2306.65
INT
Interrupt
790.35
2306.65
XCLK
External Clock Input
478.55
2306.65
VCCD
Digital Supply Voltage
291.55
2306.65
VCCD
Digital Supply Voltage
76.15
2306.65
SCL
Serial Clock Line
-198.45
2306.65
A1
Address 1
-557.95
2306.65
SDA
Serial Data Address
-815.25
2306.65
A0
Address 0
-1366.45
2306.65
VSSD
Digital Ground
-1839.95
2306.65
VSSD
Digital Ground
-1668.35
2306.65
VSSA
Analog Ground
-1945.05
-2311.60
MIC+
Non-inverting Microphone Input
-1739.25
-2311.60
MIC-
Inverting Microphone Input
-1506.75
-2311.60
ANA OUT+
Non-inverting Analog Output
-1245.05
-2311.60
ANA OUT-
Inverting Analog Output
-910.85
-2311.60
ACAP
AGC/AutoMute Cap
-623.55
-2311.60
SP-
Speaker Negative
-127.75
-2311.60
VSSA
Analog Ground
205.85
-2311.60
VSSA
Analog Ground
295.85
-2311.60
SP+
Speaker Positive
629.45
-2311.60
VCCA
Analog Supply Voltage
963.05
-2311.60
VCCA
Analog Supply Voltage
1053.05
-2311.60
ANA IN
Analog Input
1260.35
-2311.60
AUX IN
Auxiliary Input
1525.95
-2311.60
AUX OUT
Auxiliary Output
1770.15
-2311.60
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 83 - Revision 1.42
11.6. ISD5102 DIE INFORMATION
≈
ISD5102
≈
VSSA
MIC + MIC -
ANA OUT +
ANA OUT -ACAPSP -VSSA [2] SP +
VCCA [2] ANA IN AUX IN
AUX OUT
VSSD VSSD A0SDA A1
SCL VCCD
XCLK RAC
VSSA
INT
VCCD
ISD5102 Device
Die Dimensions (include scribe line)
X: 4230 µm
Y: 5046 µm
Die Thickness [3]
292.1 µm ± 12.7 µm
Pad Opening
Single pad: 90 x 90 µm
Double pad: 180 x 90 µm
Notes
1. The backside of die is internally connected to Vss. It MUST NOT be connected to any other potential or
damage may occur.
2. Double bond recommended, if treated as single doubled-pad.
3. This figure reflects the current die thickness. Please contact Nuvoton as this thickness may change in
the future.
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 84 - Revision 1.42
ISD5102 Pad Coordinates
(with respect to die center in µm)
Pad
Pad Name
X Axis
Y Axis
VSSA
Analog Ground
1882.4
2306.65
RAC
Row Address Clock
1539.15
2306.65
INT
Interrupt
790.35
2306.65
XCLK
External Clock Input
478.55
2306.65
VCCD
Digital Supply Voltage
291.55
2306.65
VCCD
Digital Supply Voltage
76.15
2306.65
SCL
Serial Clock Line
-198.45
2306.65
A1
Address 1
-557.95
2306.65
SDA
Serial Data Address
-815.25
2306.65
A0
Address 0
-1366.45
2306.65
VSSD
Digital Ground
-1839.95
2306.65
VSSD
Digital Ground
-1668.35
2306.65
VSSA
Analog Ground
-1945.05
-2311.60
MIC+
Non-inverting Microphone Input
-1739.25
-2311.60
MIC-
Inverting Microphone Input
-1506.75
-2311.60
ANA OUT+
Non-inverting Analog Output
-1245.05
-2311.60
ANA OUT-
Inverting Analog Output
-910.85
-2311.60
ACAP
AGC/AutoMute Cap
-623.55
-2311.60
SP-
Speaker Negative
-127.75
-2311.60
VSSA
Analog Ground
205.85
-2311.60
VSSA
Analog Ground
295.85
-2311.60
SP+
Speaker Positive
629.45
-2311.60
VCCA
Analog Supply Voltage
963.05
-2311.60
VCCA
Analog Supply Voltage
1053.05
-2311.60
ANA IN
Analog Input
1260.35
-2311.60
AUX IN
Auxiliary Input
1525.95
-2311.60
AUX OUT
Auxiliary Output
1770.15
-2311.60
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 85 - Revision 1.42
12. ORDERING INFORMATION
Nuvoton Part Number Description
When ordering the devices, please refer to the following valid ordering numbers. For the shaded part
numbers, please contact the local Nuvoton Sales Representatives for availability.
Type
Duration
ISD5102
ISD5104
ISD5108
ISD5116
Package
Part #
Order #
Part #
Order #
Part #
Order #
Part #
Order #
Die
ISD5102X
I5102X
ISD5104X
I5104X
ISD5108X
I5108X
ISD5116X
I5116X
Lead-Free
PDIP
N/A
N/A
N/A
N/A
N/A
N/A
ISD5116PY
I5116P
Y
SOIC
ISD5102SY
I5102S
Y
ISD5104SY
I5104SY
ISD5108SY
I5108S
Y
ISD5116SY
I5116S
Y
ISD5102SY
I
I5102S
YI
ISD5104SY
I
I5104SY
I
ISD5108SY
I
I5108S
YI
ISD5116SY
I
I5116S
YI
For the latest product information, access Nuvoton’s worldwide website at
http://www.Nuvoton-usa.com
Lead-Free:
Y = Lead-free
Product Series
ISD5100-Series
ISD 5 1
Duration:
02 = 1 to 2 min
04 = 2 to 4 min
08 = 4 to 8 min
16 = 8 to 16 min
}
}
Temperature:
Blank = Commercial Packaged (0°C to +70°C)
or Commercial Die (0°C to +50°C)
I = Industrial (–40°C to +85°C)
Package Type:
X = Die
P = 28-Lead 600-Mil Plastic Dual Inline Package (PDIP)
S = 28-Lead 300-Mil Plastic Small Outline Package (SOIC)
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 86 - Revision 1.42
13. VERSION HISTORY
VERSION
DATE
DESCRIPTION
0.1
Mar 2003
New data sheet for the ISD5100-Series
0.2
Oct 2003
Add I5102 and I5104 products
Utilize TAD application in Functional Details
Reserve Load Address feature for factory uses
Simplify Playback mode
AnaIn: add k for Ra & Rb
AuxIn: add k for Ra & Rb, remove duplicate diagram, correct
parameter names in gain setting table & fix typos
Add application diagram
Add PCB layout example for TSOP package
I2C protocol: revise R/W bit =1 for reading status
Packaging: revise unit to mil instead of inch for SOIC & PDIP
Fix other typos
1.0
Jul 2004
Vcc: Industrial temp: 2.7 – 3.3V (5108: 2.7- 3.6V)
Section 7.3.10 CFG0: Select 8 speaker output
Section 7.6.2 AuxOut: Correct parameter name to OPA1
Application diagram: Revise pin # on SDA & A1
1.1
Nov 2004
Revise Operating conditions sections
Add Pb-free option to Ordering Info
1.2
Apr 2005
Revise Ordering Info section
Update disclaim section
1.3
Oct. 2005
Revise Packaging information.
1.4
May. 2007
Remove leaded package offer
Update XCLK description
Revise application diagram
1.42
Oct 31, 2008
Change logo.
1.43
March, 2017
Removed 28-Lead 8x13.4mm Package (TSOP) option no
recommended for new design.
ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 87 - Revision 1.42
Headquarters Nuvoton Technology Corporation America Nuvoton Technology (Shanghai) Ltd.
No. 4, Creation Rd. III 2727 North First Street, San Jose, 27F, 299 Yan An W. Rd. Shanghai,
Science-Based Industrial Park, CA 95134, U.S.A. 200336 China
Hsinchu, Taiwan TEL: 1-408-9436666 TEL: 86-21-62365999
TEL: 886-3-5770066 FAX: 1-408-5441798 FAX: 86-21-62356998
FAX: 886-3-5665577 http://www.Nuvoton-usa.com/
http://www.Nuvoton.com.tw/
Taipei Office Nuvoton Technology Corporation Japan Nuvoton Technology (H.K.) Ltd.
9F, No. 480, Pueiguang Rd. 7F Daini-ueno BLDG, 3-7-18 Unit 9-15, 22F, Millennium City,
Neihu District, Shinyokohama Kohoku-ku, No. 378 Kwun Tong Rd.,
Taipei, 114, Taiwan Yokohama, 222-0033 Kowloon, Hong Kong
TEL: 886-2-81777168 TEL: 81-45-4781881 TEL: 852-27513100
FAX: 886-2-87153579 FAX: 81-45-4781800 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
This product incorporates SuperFlash® technology licensed From SST.
Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment
intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or
sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could
result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Nuvoton for any damages resulting from such improper use or sales.
The contents of this document are provided only as a guide for the applications of Nuvoton products. Nuvoton makes no
representation or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice.
No license, whether express or implied, to any intellectual property or other right of Nuvoton or others is granted by this
publication. Except as set forth in Nuvoton's Standard Terms and Conditions of Sale, Nuvoton assumes no liability
whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or
infringement of any Intellectual property.
The contents of this document are provided ―AS IS‖, and Nuvoton assumes no liability whatsoever and disclaims any
express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual
property. In no event, shall Nuvoton be liable for any damages whatsoever (including, without limitation, damages for loss
of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this
documents, even if Nuvoton has been advised of the possibility of such damages.
Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only
and Nuvoton makes no representation or warranty that such applications shall be suitable for the use specified.
The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in the
Nuvoton Reliability Report, and are neither warranted nor guaranteed by Nuvoton. This product incorporates
SuperFlash®.
Information contained in this ISD® ChipCorder® datasheet supersedes all data for the ISD ChipCorder products published
by ISD® prior to August, 1998.
This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD® ChipCorder® product
specifications. In the event any inconsistencies exist between the information in this and other product documentation,
or in the event that other product documentation contains information in addition to the information in this, the information
contained herein supersedes and governs such other information in its entirety. This datasheet is subject to change
without notice.
Copyright© 2005, Nuvoton Technology Corporation. All rights reserved. ChipCorder® and ISD® are trademarks of
Nuvoton Technology Corporation. SuperFlash® is the trademark of Silicon Storage Technology, Inc. All other trademarks
are properties of their respective owners.
