TOSHIBA TMP47C440A/940A CMOS 4-BIT MICROCONTROLLER TMP47C440AN TMP47C440AF The 47C440A has 8-bit A/D converter and watchdog timer based on the TLCS-47 CMOS series. PART No. ROM RAM PACKAGE PIGGYBACK TMP47C440AN SDIPA2 TMP47CO40AE } 4096xB-bit | 256x4-bit f---=~--~----}--~~---~~- =~ TMP47C440AF QFP44 TMP47C940AG FEATURES @4-bit single chip microcomputer @ instruction execution time : 1.9p5 (at 4.2MHz)} #90 basic instructions @ Table look-up instructions a @5-bit to 8-bit data conversion instruction a @Subroutinenesting : 15 levels max. #6 interrupt sources (External : 2, Internal : 4) All sources have independent latches each, and multiple interrupt control is available @1/O port (34 pins) QFpaa @ Input 2ports 5pins Output 2ports 8pins 0 6ports 21pins pe a Interval timer C2 ae @ Two 12-bit Timer/Counters 25g Timer, event counter, and pulse width measurement mode Watchdog Timer @ Serial Interface with 4-bit buffer External/internal clock, leading/trailing edge shift mode @8-bit successive approximate type A/D converter e With sample and hold 8analog inputs e Convertingtime : 48s (4MHz) @ High current outputs LED direct drive capability (typ. 20mA x 8bits) @ Hold function Battery/Capacitor back-up QFc4a4 @Real Time Emulator : BM47214A SDIP42 a | a Ca a melt. at TMP47C440AN TMP47C440AF SDIC42 TMP47C940AG 260290 5-259TOSHIBA TMP47C440A/940A PIN ASSIGNMENTS (TOP VIEW) (4) SDIP42 (2) QFP44 varee e() i VA 42 { voo vass *(2 a1 [Je R92 (5CK) Rag {aino) ~={] 3 a0 [J 91 (50} Rai {AIn1) ~=(] 4 39 <> Ro0 (50 Raz (AIN2) ~+>{]5 38 fe Raa (71) Raz (AIN3) +>] 6 37 fJ< Rez (int?) RSO (AINA) ~e>(] 7 36 Ra (T2) R51 (ains) ~[] 3 35 [<> Rao (INT2) RS2(Ain6) *=(]9 34 [Je HOLD (KEO) aszaine) =O 10 33 =~ Reset RBR(T1) R69 es 32, xour aa1 tao) = ror = 12 31 J~ xIN R92 (SCK) rez (13 30 [J< test NC. Rox ~>(] 14 29 []= x03 vance _. arg ee [] 15 28 [J ko2 VASS a7i(wTo) ~~*() 16 27 [J< kor RAG (AINO) <> RQ1(AIN1) > pig [a7 26 [< xoo Ra? (AIN2) <> p11 + (ie 25 [] p23 pi2 ~ (Jig 2a [] p22 p13 ~~ [J 20 23 (> pa vss mela 22 [] p20 BLOCK DIAGRAM 3 Power Supply 4 vpo {vss o IN lo I nf fe an /2 jw a pe fae ee wet tO fw - N- GO ls waZzaumn e oon 1Owo-woos eee (Tle x Ke ww 30 29 28 27 26 25 24 23 PIZ P12 Pil P10 R60 ~ RET ee R62 R63 > R70 ~~ R71 (VTO) = a z 4 moe Nm TWA ww cre oe we BOUIN A} gee BOINS) ete AING} =e AOIN 7} qa Accumulator KR LR Data Memory PC RAM address buffer (RAM) Program Memory qo ROM Hod input HOLD STACK Pw { } (Sense impul) (REO) Hold controller EIR ElF TCi | TCL | OC Data table Interrupt controller Resetinput RESET System controller Test pin TEST Timing Generator Interval Timer f abt bit Serial B-bit Ose XIN i a-bit Sera -br Connecting | XOUT Clock Generator TimerfCounter Interface A/D converter om (2ch) Watchdog Timer R71 {WTO} R63 P23 PV3 RB3 {TI R92 ( } VAREF R43(AIN3} RS3(AIN7) KOZ R70 4 R82 {INT1) R9V(5O) VASS 5 WO port R60 P20 P10, RB1{T2) R90 {51} RAQ(AINO} = RSOC(AINA) KOO Watchdog timer WO port RBOCINT 2) ( output High current 10 port VO port Analog vO port Input port output port TAC input, (Serial port) reference {Analog input} ( interrupt input voltage 260290 5-260TOSHIBA TMP47C440A/940A PIN FUNCTION PIN NAME Input/Output FUNCTIONS KO03 - KQO Input 4-bit input port P13 - P10 Output 4-bit output port with latch. ulpu . . . P23. P20 8-bit data are output by the 5-bit lo 8-bit dala conversion instruction [OUTB @HL]. R43 (AIN3) . 4-bit 1/0 port with latch. R40 (AINO. ; . ane 0 (Input) When used as input port or analog input, | a/D converter analog input R53 (AIN7) the latch must be set to t", R50 (AING) R63 - R60 vo 4-bit I/O port with latch R71 (WTO) 0 (Output) 2-bit VO port with jatch. Watchdog timer output Co Poeeeees* : When used as input port or watchdog timer (00 oo R70 vO output, the latch must be set to "1". R83 (T1) Timer/Counter 1 external input : 4-bit YO port with latch. : vs R82 (INT1) . External interrupt 1 input covet teens /0 (input) When used as input port, external interrupt fo ccec cet srerererentens RBI (T2) input pin, or timer/counter external input | timerCounter 2 external input bocettentereeeees pin, the latch must be set to "1". boob vette tttseteee teeter evtttensrrseeseeey R80 (INT2) External interrupt 2 input $cKk YOO} . . Serial clock /O R92 ($6 ) ee 3-bit VO port with latch. be deceeaeetevavteevereceuetercvtrevenvrrnes R91 (SO) VO (Output) When used as input port or serial port, the | Serial data output coi ttteteteeecttef eect cnc cteeeeserseees latch must be set to 1. ee sores ne aaeininais R90 ($1) VO (Input) Serial data input XIN Input . : Oo le | Resonator connecting pins. XOUT Output For inputting external clock, XIN is used and XOUT is opened. RESET Input Reset signal input FOLD (KEG) Input (Input) HOLD request/release signal input Sense inpul TEST Input Test pin for out-going test. Be opened or fixed to low level. VDD + 5V VSS OV (GND) Power supply VAREF A/D converter analog reference voltage (High) ef LAN SOWErTOr analog relerence ona Be VASS A/D converter analog reference voltage (Low) 260290 5-261TOSHIBA TMP47C440A/940A OPERATIONAL DESCRIPTION Conserning the 47C440A, the hardware configuration and operation of hardwares are described. As the description is porvided with priority on those parts deffering from the 47C400A, the technical data sheets for the 47C400A shall also be referred to. 1. SYSTEM CONFIGURATION (1) I/O Ports (2) A/D Converter (3) Watchdog Timer 2. PERIPHERAL HARDWARE FUNCTION 2.1 Ports The 47C440A4 has 10 I/O ports (34 pins) each as follows: Mi KO ; 4-bitinput 2) P1,P2 > 4-bit output 3 R4,R5 ; 4-bitinput/output (shared with the A/D converter analog inputs) id) RG ; 4-bit input/output (5: R7 ; 2-bit input/output (shared with the watchdog timer output) 6 R8 ; 4-bit input/output(shared with external interrupt request input an timer/counter input} ( RI 3-bit inputYoutput (shared with serial port) i8) KE 1-bit sense input (shared with hold request/release signal input) This section describes ports of (3) and ) which are changed from the 47C400A. Table 2-1 lists the port address assignments and the I/O instructions that can access the ports. (1) Ports R4 (R43-R40), R5 (R53-R50) Ports R4 and RS are 4-bit I/O ports with latch shared by the analog inputs for A/D convert d er. When used as an input ports or analog inputs, the latch should be set to 1. If other port is used as an output, be careful not to execute the output instruction for any port during A/D conversion in order to keep accuracy of conversion. The latch is initialized to 1 and analog input is selected R40 (AINQ) pin during reset. Port R4 (Portaddress OP04/iP04) Analog input selector 3 2 1 0 Analog input Ra3 Raz Ral R40 IN/TEST/ TESTP (AIN3) (AIN2) (AIN1) (AINO) Input data -~ J SET/CLR Port RS (Portaddress OPOS/ IPOS) 3 2 1 0 R53 R52 R51 R50 (AIN7) (AIN6} (AINS) (AiN4) Output data LATCH | P > Jen Figure 2-1. PortR4 and R5 (2) Port R7 (R71, R70) Port R7 is 2-bits I/O port with latch. R71 pin is shared by the ween timer output. To use R71 " pin for the watchdog timer output, the latch should be set to 1. The latch is mal ed to 1 during reset. R70 pin is normal \/O pin. R72 and R73 pins do not exist actually but 1 is read when an input instruction is executed, IN / TEST / TESTP SET/CLR Port R7 (Portaddress OPQ7/IPQ7) 3 2 1 Q SO R7t R70 Output data *LATCH (WTO) Input data _ WTO output Figure 2-2. Port R? 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Block Diagram of A/D Converter 2.2.2. Controlof A/D converter The operation of A/D converter is controlled by a command. The command register is accessed as port adderesses OP12 and OP13. A/D converted value and end of conversion flag (EOCF) can be known by accessing port addresses IPOD and |POC. (1) Analog input selector Analog inputs (AINO through AIN7) are selected by values of this register. Analog input select command register (Portaddress OP12) 3 2 1 0 SAIN (Initial value 0000 ) Analog input selection Nolte. *; don't care Figure 2-4, Analog input selector 0000: 0001: 0010: OOt1: 0100: 0101: 0110: Ott: lewa R40(AINO) R41(AIN1) R42(AiN2) R43(AIN3) R50(AIN4) R51(AINS) R52(AIN6) R53(AIN7} : Analog input is not selected. 260290 5-264TOSHIBA TMP47C440A/940A (2) Start of A/D conversion A/D conversion is started when ADS is set to "1". After the conversion is started, ADS is cleared by hardware. If the restart is requested during the conversion, the conversion is started again at the time. A/D conversion start command register (Portaddress OP13) 3 veered cee 0 ADS (Initial value 0000 ) A/D conversion enable L.| 1: A/D conversion is started (clears after starting} Figure 2-5. A/D conversion start register (3) A/D converted value register An A/D converted value is read by accessing port address IPOD. An A/D converted value is read by splitting into upper 4 bits and lower 4 bits by a value of LRo (LSB of the L registers). A/D converted value register (Portaddress tPOD) 3 2 } 0 | oD 3 | D 2 | D1 | D OQ When LRg = 0, lower 4 bils of the converted value 1s read. | D 7? | D 6 | D 5S | D 4 | When LRo = 1, upper 4 bits of the converted value is read. Figure 2-6. A/D converted value register (4) A/D converter status register End of Conversion Flag (EQCF) is a single bit flag showing the end of conversion and is set to "1" when conversion ended. When both upper 4 bits and lower 4 bits of a converted value are read or A/D conversion is started, EOCF is cleared to "0". A/O converter status reqister (Port address IPOC) End of conversion flag Q: Under A/D conversion or before A/D conversion t: End of A/D conversion Figure 2-7. A/D converter status register 260290 5-265TOSHIBA TMP47C440A/940A 2.2.3 How to use A/D converter Apply positive of analog reference voltage to the VAREF pin and negative to the VASS pin. The A/D conversion is carried out by splitting reference voltage between VAREF and VASS to bit corresponding voltage by a ladder resistor and making a judgement by comparing it with analog input voltage. (4) (3) Start of A/D conversion Prior to conversion, select one of the analog input AINO through AIN7 by the analog input selector. Place output of the analog input, which is to be A/D converted, in the high impedance state by setting "1". If other port is used as an output, be careful not to execute the output instruction for any port during conversion in order to keep accuracy of conversion. A/D conversion is started by setting ADS (bit 1 of the A/D conversion start register). When conversion ends after 24 instruction cycles, EOCF showing the end of conversion is set to 1. Reading of an A/D converted value After the end of conversion, read an A/D converted value is read by splitting into lower 4 bits and upper 4 bits by the A/D converted value register (IPOD). Lower 4 bits of the A/D converted value can be read when LRo = 0 and upper 4 bits when LRo = 1. Usually an A/D converted value is stored in RAM by an instruction [IN %p, @HL). Further, if an A/D converted value is read during the conversion, it becomes an indefinite value. A/D conversion with HOLD operation When the HOLD operation is started during the conversion, the conversion is terminated and an A/D converted value becomes indefinite. Therefore, EOCF is kept clear to 0 after release from the HOLD operation. However, if the HOLD operation is started after the end of A/D conversion (after EOCF has been set), A/D converted value and status of EOCF are held. Example: Selecting analog input (AIN4), starting A/D conversion, monitoring EOCF and storing lower 4 bits and upper 4 bits of a converted value to RAM [10q] and RAM [114] respectively. LD A, #4 : Selects analog input (AIN4) OUT A, %0P12 LD A, #1 : Startof A/D conversion QUT A, %0P13 SLOOP : TEST %IPOC, 3 ; To wait until EOCF goes to "1" B SLOOP LD HL, #10H > HLe 10H IN %IPOD, @HL > RAM[i0q] Lower 4 bits INC L ; Increment of L registers IN %1P0D, @HL RAM [11y] Upper 4 bits 260290 5-266TOSHIBA TMP47C440A/940A 2.3 Watchdog Timer (WDT) The purpose of the watchdog timer is to detect the malfunction (ranaway) of program due to external noise or other causes and return the operation to the normal condition. The watchdog timer output is output to R71 must be set to "1". Further, during reset, the output latch of R71 isset to 1, and the watchdog timer becomes disable state. The initialization at time of runaway will become possible when the WTO pin and RESET pin are connected each other. 2.3.1 Configuration of Watchdog Timer The watchdog timer consists of 3-stage binary counter, flip-flop (F/F), and its control circuit. The F/F is set to "1" during reset, and cleared to "0" at the rising edge of the binary counter output. Binary Counter CPU reset 214/ fc t oe *=E Pe g ' 1} 243 : External Circuit FF 16 2t6/ fc 5 Q Selector Clear Request 1 218 / fc 4 1 R71 (WTO) Control Circuit 221) f Sr Interval Timer OP1S opo7, | Pewee Dae ee ee 3 2 1 0 3 2 1 0 ap 4 r Simplified ' power-on-reset 1 So Internal Bus 4 ' ay Figure 2-8. Watchdog Timer 2.3.2 Control of watchdog timer The watchdog timer is controlled by the command register (OP 15). This command register is initialized to 10003 during reset. The following are procedure to detect the malfunction (runaway) of CPU by the watchdog timer. At first, detection time of the watchdog timer should be set and binary counter should be cleared. 2 The watchdog timer shouid be become enable. 3: Binary counter must be cleared before the detection time of the watchdog timer. When the runaway of CPU is taken place for some reason and binary counter is not cleared, the F/F is cleared to O"at the rising edge of the binary counter and signal of runaway detection is become active (WTO output is L ). 260290 5-267TOSHIBA TMP47C440A/940A Watchdog Timer contro] command register (Port address OP15} 3 2 ] 0 RWT | EwT | TWT | (initial value 1000) Clears binary counter Q : Clears binary counter (After clear, automatically 1 is set) Enable/Disable 0 : Disable 1: Enable L Setting of watchdog timer detection time Example : At fo=4.19MHz oo : 2s fe [sec] ~ 31.25 [ms] O1 : 2197 fc oe 125 10. : 2217 fc tees 500 11: 2247 fe so 4000 Note. fc; Basic clock frequency [Hz] Lo Figure 2-9. Command Register Example: Toset the watchdog detection time (22! / fc[sec} ). And to enable the watchdog timer. LD A, #0010B ; OP15 + 0010, (Sets WDT detection time. Clears binary counter) OUT A, *0P15 LD A, #11108 ; OP15 1110, (Enables WDT) QUT A, %0P15 Within WDT detection time : LO A, #0110B : OP15 0110, (Clears binary counter) OUT A, ZOP15 Note. /t is not necessary to set RWT to 1. Note that both EWT (Enable Watchdog Timer) and RWT should not besetto I at the same time, 260290 5-268TOSHIBA TMP47C440A/940A ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (Vs5 = OV) PARAMETER SYMBOL PINS RATING UNIT Supply Voltage Voo -O0.5to? Vv Input Vollage VIN -0.5toVpp + 0.5 Vv Vout Except sink open drain pin -0.5 loVpp + 0.5 Output Voltage Voute2 PortsP?, P2, R6-R9 -0.5t0 10 V Vout3 Analog inputs -O5to Voop + 0.5 loutt Ports Pt, P2 30 Output Current (Per 1 pin) mA lout2 Ports R6- R9 3.2 Output Current (Total) Yiours [| PortsP1, P2 120 mA Power Dissipation [Top = 70C] PD 600 mw Soldering Temperature (time) Tod 260 (10sec) Storage Temperature Tyg ~55 to 125 *C Operating Temperature Topr - 30to 70 C | RECOMMENDED OPERATING CONDITIONS (Vs55 = OV, Topr = 30 to 70C) PARAMETER SYMBOL PINS CONDITIONS Min. Max. UNIT In the Normal mode 4s Supply Voltage Voo 6.0 Vv in the HOLD mode 2.0 Viet Except Hysteresis Input Vop x 0.7 Vpp 24.5V Input High Voltage Ving Hysteresis Input Vop x 0.75 Vpo Vv Ving Vop <4.5V Vpn x 0.9 Vigg Except Hysteresis Input Vop x 0.3 Vo0 = 4.5V input Low Voltage Viz Hysteresis Input 0 Vop x 0.25 Vv Ving Vop<4.5V Voox0.i Clock Frequency fc 0.4 42 MHz Note. Input voltage Vin3z, Vin3 in the HOLD mode 2FO290 5-269TOSHIBA TMP47C440A/940A D.C. CHARACTERISTICS (Vs5 = OV, Topr = - 30 to 70C) PARAMETER SYMBOL PINS CONDITIONS Min. | Typ. | Max. | UNIT Hysteresis Voitage Vus Hysteresis Input - 0.7 - Vv Port KO, TEST, l eee ee iN ESET, HOLD Vop = 5.5, Input Current Vin = 5.5V/0V - - +2 pA lina Ports & (open drain) Low Input Current hi Ports R (push-pull) Vop = 5.5V, Vin = 0.4V - - -2 | mA Rint Port KO with pull-up/pull-down 30 70 150 Input Resistance KQ Ring | RESET 100 | 220 | 450 Output Leakage Current lo Ports R (open drain) Vop = 5.5V, Vout = 5.5V _ 2 pA Qutput Low Voltage Vor2 | Except XOUT, ports P Voo = 4.5V, Io. = 1.6mA - - 0.4 Vv Low output Current lout Ports P1, P2 Vop = 4.5V, Vo. = 1.0V - 20 _ mA supply Current oo Vop = 5.5V, fc = 4MHz - 3 6 | mA (in the Normal mode) Supply Current Voc =5.5V _ (in the HOLD mode) | 2% ob= 5 05 | 10 | pa Note 1. Typ. values show those at Topr = 25C, Vop =5V. Note 2. {nput Currently, ;The current through resistor is not included, when the input resistor (pull- up/pull-down) is contained. Note 3. Supply Currentlopp. ipo; Vin = 5.3V/0.2V The KO port is open when the input resistor is contained. The voltage applied to the R port is within the valid range. A/D CONVERSION CHARACTERISTICS (Topr = -30 to 70C) PARAMETER SYMBOL CONDITIONS Min. Typ. Max, UNIT VaREF Voo- 1.5 - Vpo Analog Reference Voltage Vv Vass Vs5 - 5 Analog Reference Voltage Range AVarer | Varee - Vass 2.5 - _ Vv Anaiog input Voltage Vain Vass _ VaRer Vv Analog Supply Current Inge - 60.5 1.0 mA Nonlinearity Error _ _ +1 Vop = 9.0V, Vs5 = 0.0V Zero Point Error _ > +1 Vaner = 5.000V LSB Full Scale Error - = +1 Vass =O0.000V Total Error - - +2 260290 5-270TOSHIBA TMP47C440A4/940A A.C. CHARACTERISTICS (V5, = OV, Vpp =4.5 to 6.0V, Topr = 30 to 70C} PARAMETER SYMBOL CONDITIONS Min. Typ. Max. | UNIT Instruction Cycle Time ty 1.9 - 20 ps High level Clock pulse Width tweu External clock mode 30 - - ns Low level Clock pulse Width twee A/D Sampling Time tain fc = 4MHz - 4 - ys Shift Data Hold Time boon 0.5t. - 300 - - ns Note. Shift Data Hold Time . . oe Serial port (completion of transmission) External circuit for SCK pin and SO pin VDD 5cK 1.8V 10KQ sa] SOpF : o XXX Ah RECOMMENDED OSCILLATING CONDITIONS (Vs55 =OV, Vop =4.5 to 6.0V, Topr = -30 to 70C) (1) 4MHz XIN XOUT Ceramic Resonator CSA4. GOMG (MURATA) Cxin = Cxgut = 30pF 4MHz KBR-4, OOMS (KYOCERA) Cxin = Cxout = 30pF Crystal Oscillator my T Cxour 204B-6F 4. 0000 (TOYOCOM) Cyn = Cxout = 20pF (2) 400KHz XIN XOUT Ceramic Resonator CSB400B (MURATA) Cxin = Cxout = 220pF, Rxout = 6.8KQ 400KHz Rxour KBR-400B (KYOCERA) Cxin = Cxout = 100pF, Rxout = 10K2 0 Cxour +4 oT 260290 5-271TOSHIBA TMP47C440A/940A TYPICAL CHARACTERISTICS R-Ta KO port R-Ta RESET pin R R (KO) Vop=5.4V (KQ) Vpp=5.5V 100 a 400 va 300 = 50 200 a 100 0 Ta 0 Ta -40 0 40 80 (C) 40 0 40 80 (C) loir- Vou R port lou- YOu PL, P2 port lon, lon, (mA)j] Yon = 45V GnA}| Yoo =4.5 Ta= 25C Ta = 25C 8 / A0 6 7 30 4 4 7 20 7 LA 4 7 id 0 Von 0 Vo. 0.4 0.8 1.2(V) 0.4 0.8 1.2(V) Ipp- Von Ipp-fe Ipqy top v Cay (mA) Ta = 25C (nA)} YOD= 2.9 Pas 25C Va= 25C 4 4 3 3 y fo=4Mbiz 2 2 / i l wa 0 Von Q fe 3 5 7 (V) 0.1 0.4 4 10 (MHz) 260290 5-272TOSHIBA TMP47C440A/940A INPUT/OUTPUT CIRCUITRY {i} Centro! pins The input/output circuitries of the 47C440A control pins are similar to that of the 47C400A. {2} 1/0 Ports The input/output circuitries of the 47C440A I/O ports are shown below, any one of the circuitries can be chosen by a code (SA-SC) as a mask option. PORT vO INPUT/OUTPUT CIRCUITRY and CODE REMARKS SA SB SC Pull-up/ pull-down VDD . R resistor KO | Input R Rin Tv i] Rin Rin = 7OKQ (typ.) R R= 1KQ (typ.) Sink open drain output Pi Initial Hi-2 P? Dutput t . High current lop = 20mA (typ.) 7 Sink open drain f output Initial Hi-Z R4 VO AiN selector R R = 1KQ(typ.) RS a Ca Ra Analog input | Ra = 5KQ (typ) Ca = 12pF (typ.) Sink open drain RE output a7 VO _f>o-+| Initial Hi-2" R = 1KQ (typ.) Sink open drain R output Initial Hi-Z R8 vO R RS q Hysteresis input R= 1KQ (typ.) 260290 5-273TOSHIBA TMP47C440A/940A This Page Intentionally Left Blank- 260290 -AT4TOSHIBA TMP47C440A/940A CMOS 4-BIT MICROCONTROLLER TMP47C940AE TMP47C940AG The 47C940A, which is equipped with an EPROM as program memory, is a piggyback type evaluator chip used for development and operational confirmation of the 47C4404/242A application systems (programs). The 47C940A is pin compatible with the 47C440A which are mask-programed ROM devices. Also, pin compatibility with the 47C242A is possible by using the 42-to-30 pin conversion adapter socket (BM1113). PIN ASSIGNMENT (TOP VIEW) E abe 2 A [2 le sash ez2 5DICa2 QFc4aa f fi 2 lee i i ; VAREE d 3 LJ ab yoo 33 32 31 30 29 28 27 26 VASS__ Cl 2 @) vec vce al D> R92 CK) RAQ{AING) =e Cf 3 vec vec GA) 40 PS RIN (SO) R83 (1434 22=3K00 ROT(AINI) eC) 4 39 De R90 (51) nese ROXAIN2) te 5 ar vec (6) 38 D~ R83 (11) R90 (SNES ag @9 Qo 3 RaHAIN3) 0 6 AG AB 23) 37 Oe 292 ONT) R91 (50) 36 vee a 20[/--Pp22 RSC(AING) =F] 7 36 D~> agi (12) R92 (SEK) O37 eg @ fF eI RSI{AINS) eC) 8 AS Ag 4) 35 D~> rao fINT2) n. Co38 vec a 18[-1 P26 RS52(AING) eC] 9 Aa 411 Q3) 34 PAOLOREO) voo 39 we 6 V7oONC Rexam sR az GE Q2) 3 LS Nur VAREFL40 op GQ 16 v55 R61 aC 12 A2 A10 2") 31 D<xin vassC7a1 ayy GQ ou 15" IP 13 R62 ~ () 13 Al CE (9) 30 D +TEST RAO(AIND)CA2 Ag @ a 14-1 P12 R63 > (] 14 29 P<+K03 ray (Aint) C43 D@O OOGI Been Ao 7 _R70 (J t5 C3) 23 D<xor Ra? (ain?) 44 12027) P10 RIVWWTO) + O16 10 16 (8) 27 D<xkoi P10 {] 17 1 5 26 D0 <~x00 oO P1i ~{ 18 @ 25 [> P23 12345 67 8 9 1011 MILES Geno Bboeen VOUUTUU UU P13 J 20 GND 23 (+ p21 ieee en boa Sgggseeseks 45984 5 nen m Is eeeee PIN FUNCTION (Top of the package) PIN NAME input f Output FUNCTIONS All ~ AO Output Program memory address output 17 ~ 10 Input Program memory data inpul CE Chip enable signal output Output OE Output enable signal output vce + 5V (connected with VDD) beens Power supply boot ecte teens wees . GND OV (connected with VSS) A.C. CHARACTERISTICS PARAMETER SYMBOL CONDITIONS Min. UNIT Address Delay Time tap = ns Veg = OV, Voo = 4.5 lo 6.0V Data Setup Time lis C. = 100pF 150 ns . Topr= - 30 to 70C Data Hold Time tia 50 ns 260290 5-275TOSHIBA TMP47C440A/940A NOTES FOR USE (1) Program memory The program area are as shown in Figure 1. When this chip is used as evaluator of the 47C242, data conversion table for [OUTB @HL] instruction must be allocated at two areas and they must be the same contents as shown in Figure 1{b). 64K 64K RAM 0000 a 00001, 00x Zero-page OF Don't use Don't use Don'tuse 1000 1000 ve OL J : Program 80 Program : : 90 7EO {Data conversion : 17FE table Don't use Data area TFEO [Data conversion 1FEO }=[Data conversion : 1FFR [table 1ERF [table FF (a) 474a04 (b) 47242A (in case of a7c242A ) Figure 1. Program area Figure2. RAM addressing (2) Data memory The 47C940A contains 256 x 4-bit (equivalent to 47C440A) data memory. When the 47C940A is used as evaluator of the 47C242A, programming should be performed assuming that the RAM is assigned to addresses OO~OFY and 90~FFY as show in Figure 2 by considering the application software evaluation, (3) I/O ports Input/Output circuitries of I/O ports in the 47C940A are similar to the code TA of the 47C440A. When this chip is used as evaluator with other /O code, it is nacessary to provide the external resistors. This is also the same when used as the 47C242A evaluator (the 47C242A does not have ports R5 and R6}. 4 a KO port { 70KQ . 70KQ 1 KOport --d 4 (a) Code: SB (b} Code: Sc Figure 3. I/O code and external circuitry 260290 5-276