LMR62421
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SNVS734B –OCTOBER 2011–REVISED APRIL 2013
LMR62421 SIMPLE SWITCHER
®
24Vout, 2.1A Step-Up Voltage Regulator in SOT-23
Check for Samples: LMR62421
1FEATURES DESCRIPTION
The LMR62421 is an easy-to-use, space-efficient
2• Input Voltage Range of 2.7V to 5.5V 2.1A low-side switch regulator ideal for Boost and
• Output Voltage up to 24V SEPIC DC-DC regulation. It provides all the active
• Switch Current up to 2.1A functions to provide local DC/DC conversion with fast-
transient response and accurate regulation in the
• 1.6 MHz Switching Frequency smallest PCB area. Switching frequency is internally
• Low Shutdown Iq, 80 nA set to 1.6 MHz, allowing the use of extremely small
• Cycle-by-Cycle Current Limiting surface mount inductor and chip capacitors while
providing efficiencies near 90%. Current-mode control
• Internally Compensated and internal compensation provide ease-of-use,
• Internal Soft-Start minimal component count, and high-performance
• 5-Pin SOT-23 (2.92 x 2.84 x 1mm) and 6-Pin regulation over a wide range of operating conditions.
WSON (3 x 3 x 0.8 mm) Packaging External shutdown features an ultra-low standby
current of 80 nA ideal for portable applications. Tiny
• Fully Enabled for WEBENCH® Power Designer 5-pin SOT-23 and 6-pin WSON packages provide
space-savings. Additional features include internal
PERFORMANCE BENEFITS soft-start, circuitry to reduce inrush current, pulse-by-
• Extremely Easy to Use pulse current limit, and thermal shutdown.
• Tiny Overall Solution Reduces System Cost
APPLICATIONS
• Boost / SEPIC Conversions from 3.3V, 5V Rails
• Space Constrained Applications
• Embedded Systems
• LCD Displays
• LED Applications
System Performance
Efficiency vs Load Current Efficiency vs Load Current
VOUT = 20V VOUT = 12V
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
2
3
6
5
4
AGND
FB
SW
VIN
EN
PGND
2
1
3
5
4EN
GND
FB
VIN
SW
4
2
5
3
1
C1
C2
VIN
L1D1
R2
R1
C3
GND
R3
VOUT
LMR62421
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
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Typical Application
Connection Diagrams
Figure 1. 5-Pin SOT-23 (Top View) Figure 2. 6-Pin WSON (Top View)
See DBV Package See NGG0006A Package
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PIN DESCRIPTIONS - 5-Pin SOT-23
Pin Name Function
1 SW Switch node. Connect to the inductor, output diode.
2 GND Signal and power ground pin. Place the bottom resistor of the feedback network as close as possible to this pin.
3 FB Feedback pin. Connect FB to external resistor divider to set output voltage.
4 EN Shutdown control input. Logic high enables operation. Do not allow this pin to float or be greater than VIN + 0.3V.
5 VIN Supply voltage for power stage, and input supply voltage.
PIN DESCRIPTIONS - 6-Pin WSON
Pin Name Function
1 PGND Power ground pin. Place PGND and output capacitor GND close together.
2 VIN Supply voltage for power stage, and input supply voltage.
3 EN Shutdown control input. Logic high enables operation. Do not allow this pin to float or be greater than VIN + 0.3V.
4 FB Feedback pin. Connect FB to external resistor divider to set output voltage.
5 AGND Signal ground pin. Place the bottom resistor of the feedback network as close as possible to this pin & pin 4.
6 SW Switch node. Connect to the inductor, output diode.
DAP GND Signal & Power ground. Connect to pin 1 & pin 5 on top layer. Place 4-6 vias from DAP to bottom layer GND plane.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
VIN -0.5V to 7V
SW Voltage -0.5V to 26.5V
FB Voltage -0.5V to 3.0V
EN Voltage -0.5V to VIN + 0.3V
ESD Susceptibility(3) 2kV
Junction Temperature(4) 150°C
Storage Temp. Range -65°C to 150°C
For soldering specifications: SNOA549
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specified specifications and the test
conditions, see Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin.
(4) Thermal shutdown will occur if the junction temperature exceeds the maximum junction temperature of the device.
Operating Ratings(1)
VIN 2.7V to 5.5V
VEN(2) 0V to VIN
Junction Temperature Range −40°C to +125°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specified specifications and the test
conditions, see Electrical Characteristics.
(2) Do not allow this pin to float or be greater than VIN +0.3V.
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Electrical Characteristics(1)(2)
Limits in standard type are for TJ= 25°C only; limits in boldface type apply over the junction temperature range of
(TJ= -40°C to 125°C). Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values
represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. VIN = 5V unless
otherwise indicated under the Conditions column.
Symbol Parameter Conditions Min Typ Max Units
−40°C ≤to TJ≤+125°C (SOT-23) 1.230 1.255 1.280
0°C ≤to TJ≤+125°C (SOT-23) 1.236 1.255 1.274
VFB Feedback Voltage V
−40°C ≤to TJ≤+125°C (WSON) 1.225 1.255 1.285
−0°C ≤to TJ≤+125°C (WSON) 1.229 1.255 1.281
ΔVFB/VIN Feedback Voltage Line Regulation VIN = 2.7V to 5.5V 0.06 %/V
IFB Feedback Input Bias Current 0.1 1µA
FSW Switching Frequency 1200 1600 2000 kHz
DMAX Maximum Duty Cycle 88 96 %
DMIN Minimum Duty Cycle 5 %
SOT-23 170 330
RDS(ON) Switch On Resistance mΩ
WSON 190 350
ICL Switch Current Limit 2.1 3 A
SS Soft Start 4 ms
Quiescent Current (switching) 7.0 11 mA
IQQuiescent Current (shutdown) VEN = 0V 80 nA
Undervoltage Lockout VIN Rising 2.3 2.65 V
UVLO VIN Falling 1.7 1.9
Shutdown Threshold Voltage See (3) 0.4
VEN_TH V
Enable Threshold Voltage See (3) 1.8
I-SW Switch Leakage VSW = 24V 1.0 µA
I-EN Enable Pin Current Sink/Source 100 nA
WSON 80
Junction to Ambient
θJA °C/W
0 LFPM Air Flow(4) SOT-23 118
WSON 18
θJC Junction to Case °C/W
SOT-23 60
TSD Thermal Shutdown Temperature(5) 160 °C
Thermal Shutdown Hysteresis 10
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
(3) Do not allow this pin to float or be greater than VIN +0.3V.
(4) Applies for packages soldered directly onto a 3” x 3” PC board with 2oz. copper on 4 layers in still air.
(5) Thermal shutdown will occur if the junction temperature exceeds the maximum junction temperature of the device.
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Typical Performance Characteristics
Current Limit vs Temperature FB Pin Voltage vs Temperature
Figure 3. Figure 4.
Oscillator Frequency vs Temperature Typical Maximum Output Current vs VIN
Figure 5. Figure 6.
RDSON vs Temperature Efficiency vs Load Current, Vo = 20V
Figure 7. Figure 8.
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Typical Performance Characteristics (continued)
Efficiency vs Load Current, Vo = 12V Output Voltage Load Regulation
Figure 9. Figure 10.
Output Voltage Line Regulation
Figure 11.
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cv
1.6 MHz S
R
R
Q
+
-
+
-
+
-
-
+
EN VIN
ThermalSHDN
SW
ILIMIT
NMOS
UVLO = 2.3V
ISENSE-AMP
Internal
Compensation
Soft-Start
Corrective - Ramp Oscillator
Control Logic
VREF = 1.255V
FB
GND
LMR62421
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
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Simplified Internal Block Diagram
Figure 12. Simplified Block Diagram
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+-
+
-
+
-
Control ( )
tO
V
( )
tC
I
( )
tL
I( )
tL
V1
D
1
Q
( )
tSW
V1
C
1
L
IN
V
LMR62421
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SNVS734B –OCTOBER 2011–REVISED APRIL 2013
APPLICATION INFORMATION
THEORY OF OPERATION
The following operating description of the LMR62421 will refer to the Simplified Block Diagram (Figure 12) the
simplified schematic (Figure 13), and its associated waveforms (Figure 14). The LMR62421 supplies a regulated
output voltage by switching the internal NMOS control switch at constant frequency and variable duty cycle. A
switching cycle begins at the falling edge of the reset pulse generated by the internal oscillator. When this pulse
goes low, the output control logic turns on the internal NMOS control switch. During this on-time, the SW pin
voltage (VSW) decreases to approximately GND, and the inductor current (IL) increases with a linear slope. ILis
measured by the current sense amplifier, which generates an output proportional to the switch current. The
sensed signal is summed with the regulator’s corrective ramp and compared to the error amplifier’s output, which
is proportional to the difference between the feedback voltage and VREF. When the PWM comparator output goes
high, the output switch turns off until the next switching cycle begins. During the switch off-time, inductor current
discharges through diode D1, which forces the SW pin to swing to the output voltage plus the forward voltage
(VD) of the diode. The regulator loop adjusts the duty cycle (D) to maintain a constant output voltage .
Figure 13. Simplified Schematic
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t
t
DO VV +
t
t
t
v
'
IN
V
( )
tsw
V
L
i
VIN -VOUT -D
V
( )
tL
V
( )
tL
I
( )
tDIODE
I
( )
tCapacitor
I
( )
tOUT
V
S
T
S
DT
OUT
-i
( )
-
L
iOUT
-i
LMR62421
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
www.ti.com
Figure 14. Typical Waveforms
CURRENT LIMIT
The LMR62421 uses cycle-by-cycle current limiting to protect the internal NMOS switch. It is important to note
that this current limit will not protect the output from excessive current during an output short circuit. The input
supply is connected to the output by the series connection of an inductor and a diode. If a short circuit is placed
on the output, excessive current can damage both the inductor and diode.
Design Guide
ENABLE PIN / SHUTDOWN MODE
The LMR62421 has a shutdown mode that is controlled by the Enable pin (EN). When a logic low voltage is
applied to EN, the part is in shutdown mode and its quiescent current drops to typically 80 nA. Switch leakage
adds up to another 1 µA from the input supply. The voltage at this pin should never exceed VIN + 0.3V.
THERMAL SHUTDOWN
Thermal shutdown limits total power dissipation by turning off the output switch when the IC junction temperature
exceeds 160°C. After thermal shutdown occurs, the output switch doesn’t turn on until the junction temperature
drops to approximately 150°C.
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L
t
L
i
L
i'
S
T
S
DT
( )
tL
I
L
VIN VV OUT
IN -
K
=c
D
VOUT
VIN
D = VOUT -IN
V
OUT
V
-D111
=c
D
=
VOUT
VIN ¸
¹
·
¨
©
§
LMR62421
www.ti.com
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
SOFT-START
This function forces VOUT to increase at a controlled rate during start up. During soft-start, the error amplifier’s
reference voltage ramps to its nominal value of 1.255V in approximately 4.0ms. This forces the regulator output
to ramp up in a more linear and controlled fashion, which helps reduce inrush current.
INDUCTOR SELECTION
The Duty Cycle (D) can be approximated quickly using the ratio of output voltage (VO) to input voltage (VIN):
(1)
Therefore:
(2)
Power losses due to the diode (D1) forward voltage drop, the voltage drop across the internal NMOS switch, the
voltage drop across the inductor resistance (RDCR) and switching losses must be included to calculate a more
accurate duty cycle (See Calculating Efficiency and Junction Temperature for a detailed explanation). A more
accurate formula for calculating the conversion ratio is:
where
•ηequals the efficiency of the LMR62421 application. (3)
The inductor value determines the input ripple current. Lower inductor values decrease the size of the inductor,
but increase the input ripple current. An increase in the inductor value will decrease the input ripple current.
Figure 15. Inductor Current
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L = VIN
2 x 'iLx DTS
¨
©
§¸
¹
·
¸
¸
¹
·
¨
¨
©
§
=2L
IN
V
L
ÂixS
DT
¨
¨
©
§
=L
VIN
'i2 L
DTS¸
¸
¹
·
LMR62421
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
www.ti.com
(4)
A good design practice is to design the inductor to produce 10% to 30% ripple of maximum load. From the
previous equations, the inductor value is then obtained.
where
• 1/TS= FSW = switching frequency (5)
One must also ensure that the minimum current limit (2.1A) is not exceeded, so the peak current in the inductor
must be calculated. The peak current (ILPK ) in the inductor is calculated by:
ILpk = IIN +ΔIL(6)
or ILpk = IOUT / D' + ΔIL(7)
When selecting an inductor, make sure that it is capable of supporting the peak input current without saturating.
Inductor saturation will result in a sudden reduction in inductance and prevent the regulator from operating
correctly. Because of the speed of the internal current limit, the peak current of the inductor need only be
specified for the required maximum input current. For example, if the designed maximum input current is 1.5A
and the peak current is 1.75A, then the inductor should be specified with a saturation current limit of >1.75A.
There is no need to specify the saturation or peak current of the inductor at the 3A typical switch current limit.
Because of the operating frequency of the LMR62421, ferrite based inductors are preferred to minimize core
losses. This presents little restriction since the variety of ferrite-based inductors is huge. Lastly, inductors with
lower series resistance (DCR) will provide better operating efficiency. For recommended inductors see Example
Circuits.
INPUT CAPACITOR
An input capacitor is necessary to ensure that VIN does not drop excessively during switching transients. The
primary specifications of the input capacitor are capacitance, voltage, RMS current rating, and ESL (Equivalent
Series Inductance). The recommended input capacitance is 10 µF to 44 µF depending on the application. The
capacitor manufacturer specifically states the input voltage rating. Make sure to check any recommended
deratings and also verify if there is any significant change in capacitance at the operating input voltage and the
operating temperature. The ESL of an input capacitor is usually determined by the effective cross sectional area
of the current path. At the operating frequencies of the LMR62421, certain capacitors may have an ESL so large
that the resulting impedance (2πfL) will be higher than that required to provide stable operation. As a result,
surface mount capacitors are strongly recommended. Multilayer ceramic capacitors (MLCC) are good choices for
both input and output capacitors and have very low ESL. For MLCCs it is recommended to use X7R or X5R
dielectrics. Consult capacitor manufacturer datasheet to see how rated capacitance varies over operating
conditions.
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REF
V
¨
¨
©
§OUT
V
=
2
R1¸
¸
¹
·
- x 1
R
LOAD
R
O
V
3
C
2
R
1
R
FB
V
¨
¨
©
§
+
x
=ESRLOUT RÂIÂVxxx OUTLoadSW CRF2 x
OUT DV
¹
¸
¸
·
LMR62421
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SNVS734B –OCTOBER 2011–REVISED APRIL 2013
OUTPUT CAPACITOR
The LMR62421 operates at frequencies allowing the use of ceramic output capacitors without compromising
transient response. Ceramic capacitors allow higher inductor ripple without significantly increasing output ripple.
The output capacitor is selected based upon the desired output ripple and transient response. The initial current
of a load transient is provided mainly by the output capacitor. The output impedance will therefore determine the
maximum voltage perturbation. The output ripple of the converter is a function of the capacitor’s reactance and
its equivalent series resistance (ESR):
(8)
When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the
output ripple will be approximately sinusoidal and 90° phase shifted from the switching action .
Given the availability and quality of MLCCs and the expected output voltage of designs using the LMR62421,
there is really no need to review any other capacitor technologies. Another benefit of ceramic capacitors is their
ability to bypass high frequency noise. A certain amount of switching edge noise will couple through parasitic
capacitances in the inductor to the output. A ceramic capacitor will bypass this noise while a tantalum will not.
Since the output capacitor is one of the two external components that control the stability of the regulator control
loop, most applications will require a minimum at 4.7 µF of output capacitance. Like the input capacitor,
recommended multilayer ceramic capacitors are X7R or X5R. Again, verify actual capacitance at the desired
operating voltage and temperature.
SETTING THE OUTPUT VOLTAGE
The output voltage is set using the following equation where R1 is connected between the FB pin and GND, and
R2 is connected between VOUT and the FB pin.
Figure 16. Setting Vout
A good value for R1 is 10kΩ.
(9)
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10 100 1k 10k 100k 1M
FREQUENCY
-80
-60
-40
-20
0
20
40
60
80
dB
-180
-90
0
90
180
RHP-Zero
Ext (Cf)
gm-Pole
RC-Pole
Vi = 5V
Vo = 12V
Io = 500 mA
Co = 10 mF
Lo = 5 mH
Ext (Cf)-Pole
gm-zero
-Zero
D = 0.625
Cf = 220 pF
Fz-cf = 8 kHz
RHP-Zero = 107 kHz
Fp-rc = 660 Hz
Fp-cf = 77 kHz
10 100 1k 10k 100k 1M
FREQUENCY
-80
-60
-40
-20
0
20
40
60
80
dB
-180
-90
0
90
180
RHP-Zero
gm-Zero
gm-Pole
RC-Pole
Vi = 5V
Vo = 12V
Io = 500 mA
Co = 10 PF
Lo = 5 PH
LMR62421
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
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COMPENSATION
The LMR62421 uses constant frequency peak current mode control. This mode of control allows for a simple
external compensation scheme that can be optimized for each application. A complicated mathematical analysis
can be completed to fully explain the LMR62421’s internal & external compensation, but for simplicity, a
graphical approach with simple equations will be used. Below is a Gain & Phase plot of a LMR62421 that
produces a 12V output from a 5V input voltage. The Bode plot shows the total loop Gain & Phase without
external compensation.
Figure 17. LMR62421 Without External Compensation
One can see that the Crossover frequency is fine, but the phase margin at 0dB is very low (22°). A zero can be
placed just above the crossover frequency so that the phase margin will be bumped up to a minimum of 45°.
Below is the same application with a zero added at 8 kHz.
Figure 18. LMR62421 With External Compensation
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LOAD
R
O
V
3
C
2
R
1
R
FB
V
=1
(RLoadCOUT)2S
FRCP-
10 kHz5 kHzo
=
=1
( )
R2xCf
2S
FCFZERO-
REF
V
¨
¨
©
§OUT
V
=
2
R1¸
¸
¹
·
- x 1
R
LMR62421
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SNVS734B –OCTOBER 2011–REVISED APRIL 2013
The simplest method to determine the compensation component value is as follows.
Set the output voltage with the following equation.
where
• R1 is the bottom resistor
and • R2 is the resistor tied to the output voltage. (10)
The next step is to calculate the value of C3. The internal compensation has been designed so that when a zero
is added between 5 kHz & 10 kHz the converter will have good transient response with plenty of phase margin
for all input & output voltage combinations.
(11)
Lower output voltages will have the zero set closer to 10 kHz, and higher output voltages will usually have the
zero set closer to 5 kHz. It is always recommended to obtain a Gain/Phase plot for your actual application. One
could refer to the Typical Appplication section to obtain examples of working applications and the associated
component values.
Pole @ origin due to internal gm amplifier:
FP-ORIGIN (12)
Pole due to output load and capacitor:
(13)
This equation only determines the frequency of the pole for perfect current mode control (CMC). Therefore, it
doesn’t take into account the additional internal artificial ramp that is added to the current signal for stability
reasons. By adding artificial ramp, you begin to move away from CMC to voltage mode control (VMC). The
artifact is that the pole due to the output load and output capacitor will actually be slightly higher in frequency
than calculated. In this example it is calculated at 650 Hz, but in reality it is around 1 kHz.
The zero created with capacitor C3 & resistor R2:
Figure 19. Setting External Pole-Zero
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D = O
V
O
V + IN
V
Vo
VIN =D'
D
=( ) RLoad
2
D'
Lx2S
RHPZERO
1
=F CFPOLE-2S((R1 R2) x C3)
=1
( )
R2xC3
2S
FCFZERO-
LMR62421
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
www.ti.com
(14)
There is an associated pole with the zero that was created in the above equation.
(15)
It is always higher in frequency than the zero.
A right-half plane zero (RHPZ) is inherent to all boost converters. One must remember that the gain associated
with a right-half plane zero increases at 20dB per decade, but the phase decreases by 45° per decade. For most
applications there is little concern with the RHPZ due to the fact that the frequency at which it shows up is well
beyond crossover, and has little to no effect on loop stability. One must be concerned with this condition for large
inductor values and high output currents.
(16)
There are miscellaneous poles and zeros associated with parasitics internal to the LMR62421, external
components, and the PCB. They are located well over the crossover frequency, and for simplicity are not
discussed.
PCB Layout Considerations
When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The
most important consideration when completing a Boost Converter layout is the close coupling of the GND
connections of the COUT capacitor and the LMR62421 PGND pin. The GND ends should be close to one another
and be connected to the GND plane with at least two through-holes. There should be a continuous ground plane
on the bottom layer of a two-layer board. The FB pin is a high impedance node and care should be taken to
make the FB trace short to avoid noise pickup and inaccurate regulation. The feedback resistors should be
placed as close as possible to the IC, with the AGND of R1 placed as close as possible to the GND (pin 5 for the
WSON) of the IC. The VOUT trace to R2 should be routed away from the inductor and any other traces that are
switching. High AC currents flow through the VIN, SW and VOUT traces, so they should be as short and wide as
possible. However, making the traces wide increases radiated noise, so the designer must make this trade-off.
Radiated noise can be decreased by choosing a shielded inductor. The remaining components should also be
placed as close as possible to the IC. Please see Application Note AN-1229 SNVA054 for further considerations
and the LMR62421 demo board as an example of a good layout.
SEPIC Converter
The LMR62421 can easily be converted into a SEPIC converter. A SEPIC converter has the ability to regulate an
output voltage that is either larger or smaller in magnitude than the input voltage. Other converters have this
ability as well (CUK and Buck-Boost), but usually create an output voltage that is opposite in polarity to the input
voltage. This topology is a perfect fit for Lithium Ion battery applications where the input voltage for a single cell
Li-Ion battery will vary between 3V & 4.5V and the output voltage is somewhere in between. Most of the analysis
of the LMR62421 Boost Converter is applicable to the LMR62421 SEPIC Converter.
SEPIC Design Guide:
SEPIC Conversion ratio without loss elements:
(17)
Therefore:
(18)
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D
D'
=( )
Vo
VIN
D
D
V'
C1 =( )
Vo
2
AREA
1
AREA
S
T
S
DT
( )
tL
V
(s)
t
IR
VO
L2 =
x
=R¸
¹
·
VO
¨
©
§
¨
©
§D
D'¸
¹
·
IL1
=
and
L2
IxL1
I
D¸
¹
·
¨
©
§
'
D
LMR62421
www.ti.com
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
Small ripple approximation:
In a well-designed SEPIC converter, the output voltage, and input voltage ripple, the inductor ripple and is small
in comparison to the DC magnitude. Therefore it is a safe approximation to assume a DC value for these
components. The main objective of the Steady State Analysis is to determine the steady state duty-cycle, voltage
and current stresses on all components, and proper values for all components.
In a steady-state converter, the net volt-seconds across an inductor after one cycle will equal zero. Also, the
charge into a capacitor will equal the charge out of a capacitor in one cycle.
Therefore:
(19)
Substituting IL1 into IL2
(20)
The average inductor current of L2 is the average output load.
Figure 20. Inductor Volt-Sec Balance Waveform
Applying Charge balance on C1:
(21)
Since there are no DC voltages across either inductor, and capacitor C6 is connected to Vin through L1 at one
end, or to ground through L2 on the other end, we can say that
VC1 = VIN (22)
Therefore:
(23)
This verifies the original conversion ratio equation.
It is important to remember that the internal switch current is equal to IL1 and IL2. During the D interval. Design
the converter so that the minimum ensured peak switch current limit (2.1A) is not exceeded.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LMR62421
+
+-
-
sw
i
i)t(
1L
1L
R
vL1( )
t
IN
V
2L
R
i)t(
2L
i)t(
1D
+-
vC1( )
t
vD1( )
t
vL2( )
t
on
R
i)t(
2C
+
-
vC2( )
t
+
-
vO( )
t
i)t(
1C
VO
VIN L1D1
C1C2
R2
R1
C3
R3
C5C4
L2
C6
1
2
3
6
5
4
LMR62421
LMR62421
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
www.ti.com
Figure 21. SEPIC CONVERTER Schematic
Steady State Analysis with Loss Elements
18 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMR62421
VO
=
D¸
¹
·
¨
©
§(VIN x K)+VO
VO
VIN =1 - D
Dx K
¸
¹
·
¨
©
§
1
+ + ¸
¹
·
¨
©
§R
RL1
¸
¸
¹
·
¨
¨
©
§D2
D2
'
¨
©
§R
RON¸
¹
·
¸
¸
¹
·
¨
¨
©
§D
D2
'
1+ +¸
¸
¹
·
R
RL2
VD
VO
¨
¨
©
§
¨
¨
¨
¨
¨
¨
©
§
¸
¸
¸
¸
¸
¸
¹
·
K=
1
+ + ¸
¹
·
¨
©
§
R
RL1
¸
¸
¹
·
¨
¨
©
§D2
D2
'
¨
©
§
R
RON¸
¹
·
¸
¸
¹
·
¨
¨
©
§D
D2
'
1+ +¸
¸
¹
·
R
RL2
VD
VO
¨
¨
©
§
¸
¸
¹
·
¨
¨
©
§D
=
Vo
VIN D'
¨
¨
¨
¨
¨
¨
©
§
¸
¸
¸
¸
¸
¸
¹
·
x
=
IL1
and
D¸
¹
·
¨
©
§
'
D
R¸
¹
·
VO
¨
©
§
=
L2
IR¸
¹
·
VO
¨
©
§
LMR62421
www.ti.com
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
Using inductor volt-second balance & capacitor charge balance, the following equations are derived:
(24)
(25)
Therefore:
(26)
One can see that all variables are known except for the duty cycle (D). A quadratic equation is needed to solve
for D. A less accurate method of determining the duty cycle is to assume efficiency, and calculate the duty cycle.
(27)
(28)
Table 1. Efficiencies for Typical SEPIC Application
Vin 2.7V Vin 3.3V Vin 5V5V
Vo 3.1V Vo 3.1V Vo 3.1V
lin 770 mA lin 600mA lin 375 mA
lo 500 mA lo 500mA lo 500 mA
η75% η80% η83%
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMR62421
4
FB
VIN
EN
PGND
AGND
SW
5
6
3
2
1
VIN
VO
PCB
PGND
COUT
CIN
L1
D1
CIN
L2
C6
LMR62421
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
www.ti.com
SEPIC Converter PCB Layout
The layout guidelines described for the LMR62421 Boost-Converter are applicable to the SEPIC Converter.
Below is a proper PCB layout for a SEPIC Converter.
Figure 22. SEPIC PCB Layout
WSON Package
The LMR62421 packaged in the 6–pin WSON:
Figure 23. Internal WSON Connection
20 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMR62421
GND
FB
Vin SW
EN
1
C
12V
3
2
1
4
5
3
R
1
L
1
D
2
C
2
R
1
RLOAD
R
3
C
VIN 1 M:
10 PF
10V
6.8 PH
2.9A
2A 20V
86.6k 220 pF
25V
10.2k
10 PF
25V
FB
SW
Vin
EN
AGND
PGND
3
COPPER
1
2
COPPER
6
5
4
LMR62421
www.ti.com
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
For certain high power applications, the PCB land may be modified to a "dog bone" shape (see Figure 24).
Increasing the size of ground plane, and adding thermal vias can reduce the RθJA for the application.
Figure 24. PCB Dog Bone Layout
LMR62421 Design Example 1
Figure 25. Vin = 3V - 5V, Vout = 12V @ 500 mA
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LMR62421
GND
FB
Vin SW
1
C
20V
3
2
1
4
5
3
R
1
L
1
D
2
C
2
R
1
RLOAD
R
3
C
VIN
SHDN
1 M:
22 PF
6.3V
10 PH
1.2A
500 mA 30V
470 pF
50V
10k
4.7 PF
50V
150k
GND
FB
Vin SW
1
C
5V
3
2
1
4
5
3
R
1
L
1
D
2
C
2
R
1
R
LOAD
R
3
C
VIN
SHDN
1 M:
10 PF
6.3V
10 PH
1.2A
1A 20V
1 nF
30.1k
10 PF
10V 10k
LMR62421
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
www.ti.com
LMR62421 Design Example 2
Figure 26. Vin = 3V, Vout = 5V @ 500 mA
LMR62421 Design Example 3
Figure 27. Vin = 3.3V, Vout = 20V @ 100 mA
22 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMR62421
VO
VIN L1D1
C1C2
R2
R1
C3
R3
C5C4
L2
C6
1
2
3
6
5
4
LMR62421
10 PF
10V
6.8 PH
1.2A
1A 20V
2.2 nF
16.5k
2.2 PF
16V
10.2k
6.8 PH
1.2A
100k
22 PF
10V (opt)
(opt)
LMR62421
www.ti.com
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
LMR62421 SEPIC Design Example 4
Figure 28. Vin = 2.7V - 5V, Vout = 3.3V @ 500mA
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LMR62421
LMR62421
SNVS734B –OCTOBER 2011–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (April 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 23
24 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMR62421
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LMR62421XMF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SH8B
LMR62421XMFE/NOPB ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SH8B
LMR62421XMFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SH8B
LMR62421XSD/NOPB ACTIVE WSON NGG 6 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L270B
LMR62421XSDE/NOPB ACTIVE WSON NGG 6 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L270B
LMR62421XSDX/NOPB ACTIVE WSON NGG 6 4500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L270B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMR62421XMF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMR62421XMFE/NOPB SOT-23 DBV 5 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMR62421XMFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMR62421XSD/NOPB WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LMR62421XSDE/NOPB WSON NGG 6 250 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LMR62421XSDX/NOPB WSON NGG 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMR62421XMF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMR62421XMFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0
LMR62421XMFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMR62421XSD/NOPB WSON NGG 6 1000 210.0 185.0 35.0
LMR62421XSDE/NOPB WSON NGG 6 250 210.0 185.0 35.0
LMR62421XSDX/NOPB WSON NGG 6 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
MECHANICAL DATA
NGG0006A
www.ti.com
SDE06A (Rev A)
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