Datasheet RL78/G1C R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 RENESAS MCU Integrated USB Controller, True Low Power Platform (as low as 112.5 A/MHz, and 0.61 A for RTC + LVD), 2.4 V to 5.5 V Operation, 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All USB Based Applications 1. OUTLINE 1.1 Features Ultra-Low Power Technology * 2.4 V to 5.5 V operation from a single supply * Stop (RAM retained): 0.23 A, (LVD enabled): 0.31 A * Halt (RTC + LVD): 0.57 A * Supports snooze * Operating: 71 A/MHz 16-bit RL78 CPU Core * Delivers 31 DMIPS at maximum operating frequency of 24 MHz * Instruction Execution: 86% of instructions can be executed in 1 to 2 clock cycles * CISC Architecture (Harvard) with 3-stage pipeline * Multiply Signed & Unsigned: 16 x 16 to 32-bit result in 1 clock cycle * MAC: 16 x 16 to 32-bit result in 2 clock cycles * 16-bit barrel shifter for shift & rotate in 1 clock cycle * 1-wire on-chip debug function Code Flash Memory * Density: 32 KB * Block size: 1 KB * On-chip single voltage flash memory with protection from block erase/writing * Self-programming with secure boot swap function and flash shield window function Data Flash Memory * Data Flash with background operation * Data flash size: 2 KB * Erase Cycles: 1 Million (typ.) * Erase/programming voltage: 2.4 V to 5.5 V RAM * 5.5 KB size options * Supports operands or instructions * Back-up retention in all modes High-speed On-chip Oscillator * 24 MHz with +/- 1% accuracy over voltage (2.4 V to 5.5 V) and temperature (-20C to +85C) * Pre-configured settings: 48 MHz, 24 MHz (TYP.) Reset and Supply Management * Power-on reset (POR) monitor/generator * Low voltage detection (LVD) with 9 setting options (Interrupt and/or reset function) USB * Complying with USB version 2.0, incorporating host/function controller * Corresponding to full-speed transfer (12 Mbps) and low-speed (1.5 Mbps) * Complying with Battery Charging Specification Revision 1.2 * Compliant with the 2.1A/1.0A charging mode prescribed in the Apple Inc. MFi specification in the Note USB power supply component specification R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Direct Memory Access (DMA) Controller * Up to 2 fully programmable channels * Transfer unit: 8- or 16-bit Multiple Communication Interfaces 2 * Up to 2 x I C master 2 * Up to 1 x I C multi-master * Up to 2 x CSI (7-, 8-bit) * Up to 1 x UART (7-, 8-, 9-bit) Extended-Function Timers * Multi-function 16-bit timer TAU: Up to 4 channels (remote control output available) * Real-time clock (RTC): 1 channel (full calendar and alarm function with watch correction function) * 12-bit interval timer: 1 channel * 15 kHz watchdog timer: 1 channel (window function) Rich Analog * ADC: Up to 9 channels, 8/10-bit resolution, 2.1 s minimum conversion time * Internal voltage reference (1.45 V) * On-chip temperature sensor Safety Features (IEC or UL 60730 compliance) * Flash memory CRC calculation * RAM parity error check * RAM write protection * SFR write protection * Illegal memory access detection * Clock stop/frequency detection * ADC self-test * I/O port read back function (echo) General Purpose I/O * 5 V tolerant, high-current (up to 20 mA per pin) * Open-Drain, Internal Pull-up support Operating Ambient Temperature * Standard: -40C to + 85C * Extended: -40C to + 105C Package Type and Pin Count * 32-pin plastic HWQFN (5 x 5) * 32-pin plastic LQFP (7 x 7) * 48-pin plastic LFQFP (7 x 7) * 48-pin plastic HWQFN (7 x 7) Note To use the Apple Inc. battery charging mode, you must join in Apple's Made for iPod/iPhone/iPad (MFi) licensing program. Before requesting this specification from Renesas Electronics, please join in the Apple's MFi licensing program. Page 1 of 134 RL78/G1C 1. OUTLINE ROM, RAM capacities Flash ROM Data flash 32 KB 2 KB RAM 5.5 KB RL78/G1C Note 32-pin 48-pin R5F10JBC, R5F10KBC R5F10JGC, R5F10KGC Note This is about 4.5 KB when the self-programming function is used. Remark 1.2 The functions mounted depend on the product. See 1.6 Outline of Functions. List of Part Numbers Pin count Package USB Function Fields of Application 32 pins 32-pin plastic HWQFN Host/Function controller (5 x 5 , 0.5 mm pitch) Function controller only 32-pin plastic LQFP Host/Function controller (7 x 7 , 0.8 mm pitch) Function controller only 48 pins 48-pin plastic LFQFP Host/Function controller (7 x 7 , 0.5 mm pitch) Function controller only 48-pin plastic HWQFN Host/Function controller (7 x 7 , 0.5 mm pitch) Function controller only Note For the fields of application, refer to Figure 1-1 Part Number Note A R5F10JBCANA#U0, R5F10JBCANA#W0 G R5F10JBCGNA#U0, R5F10JBCGNA#W0 A R5F10KBCANA#U0, R5F10KBCANA#W0 G R5F10KBCGNA#U0, R5F10KBCGNA#W0 A R5F10JBCAFP#V0, R5F10JBCAFP#X0 G R5F10JBCGFP#V0, R5F10JBCGFP#X0 A R5F10KBCAFP#V0, R5F10KBCAFP#X0 G R5F10KBCGFP#V0, R5F10KBCGFP#X0 A R5F10JGCAFB#V0, R5F10JGCAFB#X0 G R5F10JGCGFB#V0, R5F10JGCGFB#X0 A R5F10KGCAFB#V0, R5F10KGCAFB#X0s G R5F10JGCANA#U0, R5F10JGCANA#W0 A R5F10JGCANA#U0, R5F10JGCANA#W0 G R5F10JGCGNA#U0, R5F10JGCGNA#W0 A R5F10KGCANA#U0, R5F10KGCANA#W0 G R5F10KGCGNA#U0, R5F10KGCGNA#W0 Part Number, Memory Size, and Package of RL78/G1C. Caution The part number above is valid as of when this manual was issued. For the latest part number, see the web page of the target product on the Renesas Electronics website. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 2 of 134 RL78/G1C 1. OUTLINE Figure 1-1. Part Number, Memory Size, and Package of RL78/G1C Part No. R5F10JGCAxxxFB#V0 Packing #U0 : Tray (HWQFN) #V0 : Tray (LQFP, LFQFP) #W0 : Embossed Tape (HWQFN) #X0 : Embossed Tape (LQFP, LFQFP) Package FP : LQFP, 0.80 mm pitch FB : LFQFP, 0.50 mm pitch NA : HWQFN, 0.50 mm pitch ROM Number (Blank product is omitted) Classification A : Consumer use, operating ambient temperature: - 40 C to +85 C G : Industrial use, operating ambient temperature: - 40 C to +105 C ROM Capacity C : 32 KB Pin count B : 32-pin G : 48-pin RL78/G1C group 10J : USB host / function controller mounted 10K : USB function controller mounted Type of Memory F : Flash data memory Renesas Microcontroller Renesas Semiconductor R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 3 of 134 RL78/G1C 1.3 1.3.1 1. OUTLINE Pin Configuration (Top View) 32-pin products * 32-pin plastic HWQFN (5 x 5 mm, 0.5 mm pitch) (1) USB function: Host/Function controller (R5F10JBC) UDP0 UDM0 UVBUS UVDD UDP1 UDM1 P16/TI01/TO01/INTP5/UOVRCUR1 P17/TI02/TO02/UVBUSEN1 <R> exposed die pad INDEX MARK 24 23 22 21 20 19 18 17 25 16 26 15 27 14 RL78/G1C 13 28 (Top View) 12 29 30 11 31 10 32 9 1 2 3 4 5 6 7 8 P51/INTP2/SO00/TxD0/TOOLTxD/(TI01)/(TO01) P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/(TI02)/(TO02) P30/INTP3/SCK00/SCL00/(TI03)/(TO03)/(PCLBUZ0) P70/PCLBUZ1/UOVRCUR0 P31/TI03/TO03/INTP4/PCLBUZ0/UVBUSEN0 P62 P61/SDAA0 P60/SCLA0 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P01/ANI16/TO00/INTP9/SCK01/SCL01/(SCLA0) P00/ANI17/TI00/INTP8/SI01/SDA01/(SDAA0) P120/ANI19/SO01/(PCLBUZ1) Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). 3. It is recommended to connect an exposed die pad to VSS. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 4 of 134 RL78/G1C 1. OUTLINE (2) USB function: Function controller only (R5F10KBC) UDP0 UDM0 UVBUS UVDD IC Note IC Note P16/TI01/TO01/INTP5 P17/TI02/TO02 <R> exposed die pad INDEX MARK 24 23 22 21 20 19 18 17 25 16 26 15 27 14 28 RL78/G1C 13 29 (Top View) 12 30 11 31 10 32 9 1 2 3 4 5 6 7 8 P51/INTP2/SO00/TxD0/TOOLTxD/(TI01)/(TO01) P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/(TI02)/(TO02) P30/INTP3/SCK00/SCL00/(TI03)/(TO03)/(PCLBUZ0) P70/PCLBUZ1 P31/TI03/TO03/INTP4/PCLBUZ0 P62 P61/SDAA0 P60/SCLA0 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P01/ANI16/TO00/INTP9/SCK01/SCL01/(SCLA0) P00/ANI17/TI00/INTP8/SI01/SDA01/(SDAA0) P120/ANI19/SO01/(PCLBUZ1) Note IC: Internal Connection Pin. Leave open. Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). 3. It is recommended to connect an exposed die pad to VSS. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 5 of 134 RL78/G1C 1. OUTLINE * 32-pin plastic LQFP (7 x 7 mm, 0.8 mm pitch) (1) USB function: Host/Function controller (R5F10JBC) UDP0 UDM0 UVBUS UVDD UDP1 UDM1 P16/TI01/TO01/INTP5/UOVRCUR1 P17/TI02/TO02/UVBUSEN1 <R> INDEX MARK 24 23 22 21 20 19 18 17 25 16 26 15 27 14 RL78/G1C 28 13 29 12 (Top View) 30 11 31 10 32 9 1 2 3 4 5 6 7 8 P51/INTP2/SO00/TxD0/TOOLTxD/(TI01)/(TO01) P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/(TI02)/(TO02) P30/INTP3/SCK00/SCL00/(TI03)/(TO03)/(PCLBUZ0) P70/PCLBUZ1/UOVRCUR0 P31/TI03/TO03/INTP4/PCLBUZ0/UVBUSEN0 P62 P61/SDAA0 P60/SCLA0 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P01/ANI16/TO00/INTP9/SCK01/SCL01/(SCLA0) P00/ANI17/TI00/INTP8/SI01/SDA01/(SDAA0) P120/ANI19/SO01/(PCLBUZ1) Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 6 of 134 RL78/G1C 1. OUTLINE (2) USB function: Function controller only (R5F10KBC) UDP0 UDM0 UVBUS UVDD ICNote ICNote P16/TI01/TO01/INTP5 P17/TI02/TO02 <R> INDEX MARK 24 23 22 21 20 19 18 17 25 16 26 15 27 14 28 RL78/G1C 13 29 (Top View) 12 30 11 31 10 32 9 1 2 3 4 5 6 7 8 P51/INTP2/SO00/TxD0/TOOLTxD/(TI01)/(TO01) P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/(TI02)/(TO02) P30/INTP3/SCK00/SCL00/(TI03)/(TO03)/(PCLBUZ0) P70/PCLBUZ1 P31/TI03/TO03/INTP4/PCLBUZ0 P62 P61/SDAA0 P60/SCLA0 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P01/ANI16/TO00/INTP9/SCK01/SCL01/(SCLA0) P00/ANI17/TI00/INTP8/SI01/SDA01/(SDAA0) P120/ANI19/SO01/(PCLBUZ1) Note IC: Internal Connection Pin Leave open. Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 7 of 134 RL78/G1C 1.3.2 1. OUTLINE 48-pin products * 48-pin plastic LFQFP (fine pitch) (7 x 7 , 0.5 mm pitch) (1) USB function: Host/Function controller (R5F10JGC) P140/PCLBUZ0/INTP6 P00/TI00/(SDAA0) P01/TO00/(SCLA0) P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 <R> 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 41 20 42 19 RL78/G1C 43 18 (Top View) 44 17 45 16 46 15 47 14 48 13 1 2 3 4 5 6 7 8 9 10 11 12 INDEX MARK UDP0 UDM0 UVBUS UVDD UDP1 UDM1 P14/UOVRCUR0 P15/PCLBUZ1/UVBUSEN0 P16/TI01/TO01/INTP5/UOVRCUR1 P17/TI02/TO02/UVBUSEN1 P51/INTP2/SO00/TxD0/TOOLTxD P50/INTP1/SI00/RxD0/TOOLRxD/SDA00 P60/SCLA0 P61/SDAA0 P62 P63 P31/TI03/TO03/INTP4 P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/(TI02)/(TO02) P71/KR1/(TI01)/(TO01)/(INTP5) P70/KR0 P30/INTP3/RTC1HZ/SCK00/SCL00 P120/ANI19 P41/(TI03)/(TO03)/(INTP4)/(PCLBUZ1) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 8 of 134 RL78/G1C 1. OUTLINE (2) USB function: Function controller only (R5F10KGC) P140/PCLBUZ0/INTP6 P00/TI00/(SDAA0) P01/TO00/(SCLA0) P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 <R> 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 41 20 42 19 RL78/G1C 43 18 (Top View) 44 17 45 16 46 15 47 14 48 13 1 2 3 4 5 6 7 8 9 10 11 12 INDEX MARK UDP0 UDM0 UVBUS UVDD IC Note IC Note P14 P15/PCLBUZ1 P16/TI01/TO01/INTP5 P17/TI02/TO02 P51/INTP2/SO00/TxD0/TOOLTxD P50/INTP1/SI00/RxD0/TOOLRxD/SDA00 P60/SCLA0 P61/SDAA0 P62 P63 P31/TI03/TO03/INTP4 P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/(TI02)/(TO02) P71/KR1/(TI01)/(TO01)/(INTP5) P70/KR0 P30/INTP3/RTC1HZ/SCK00/SCL00 P120/ANI19 P41/(TI03)/(TO03)/(INTP4)/(PCLBUZ1) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Note IC: Internal Connection Pin Leave open. Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 9 of 134 RL78/G1C 1. OUTLINE * 48-pin plastic WHQFN (7 x 7 , 0.5 mm pitch) (1) USB function: Host/Function controller (R5F10JGC) P140/PCLBUZ0/INTP6 P00/TI00/(SDAA0) P01/TO00/(SCLA0) P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 <R> 36 35 34 33 32 31 30 29 28 27 26 25 24 37 23 38 exposed die pad 22 39 21 40 20 41 19 42 RL78/G1C 18 43 (Top View) 17 44 16 45 15 46 14 47 13 48 1 2 3 4 5 6 7 8 9 10 11 12 INDEX MARK UDP0 UDM0 UVBUS UVDD UDP1 UDM1 P14/UOVRCUR0 P15/PCLBUZ1/UVBUSEN0 P16/TI01/TO01/INTP5/UOVRCUR1 P17/TI02/TO02/UVBUSEN1 P51/INTP2/SO00/TxD0/TOOLTxD P50/INTP1/SI00/RxD0/TOOLRxD/SDA00 P60/SCLA0 P61/SDAA0 P62 P63 P31/TI03/TO03/INTP4 P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/(TI02)/(TO02) P71/KR1/(TI01)/(TO01)/(INTP5) P70/KR0 P30/INTP3/RTC1HZ/SCK00/SCL00 P120/ANI19 P41/(TI03)/(TO03)/(INTP4)/(PCLBUZ1) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). 3. It is recommended to connect an exposed die pad to VSS. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 10 of 134 RL78/G1C 1. OUTLINE (2) USB function: Function controller only (R5F10KGC) P140/PCLBUZ0/INTP6 P00/TI00/(SDAA0) P01/TO00/(SCLA0) P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 <R> 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 exposed die pad 39 22 40 21 41 20 42 19 RL78/G1C 43 18 (Top View) 44 17 45 16 46 15 47 14 48 13 1 2 3 4 5 6 7 8 9 10 11 12 INDEX MARK UDP0 UDM0 UVBUS UVDD IC Note IC Note P14 P15/PCLBUZ1 P16/TI01/TO01/INTP5 P17/TI02/TO02 P51/INTP2/SO00/TxD0/TOOLTxD P50/INTP1/SI00/RxD0/TOOLRxD/SDA00 P60/SCLA0 P61/SDAA0 P62 P63 P31/TI03/TO03/INTP4 P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/(TI02)/(TO02) P71/KR1/(TI01)/(TO01)/(INTP5) P70/KR0 P30/INTP3/RTC1HZ/SCK00/SCL00 P120/ANI19 P41/(TI03)/(TO03)/(INTP4)/(PCLBUZ1) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Note IC: Internal Connection Pin Leave open. Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). 3. It is recommended to connect an exposed die pad to VSS. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 11 of 134 RL78/G1C 1.4 1. OUTLINE Pin Identification ANI0 to ANI7, ANI16, ANI17, ANI19: Analog Input AVREFM: Analog Reference Voltage Minus AVREFP: Analog Reference Voltage Plus EXCLK: External Clock Input (Main System Clock) EXCLKS: External Clock Input (Sub System Clock) INTP0 to INTP6, INTP8, INTP9: External Interrupt Input KR0 to KR5: Key Return P00, P01: Port 0 P14 to P17: Port 1 P20 to P27: Port 2 P30, P31: Port 3 P40, P41: Port 4 P50, P51: Port 5 P60 to P63: Port 6 P70 to P75: Port 7 P120 to P124: Port 12 P130, P137: Port 13 P140: Port 14 PCLBUZ0, PCLBUZ1: Programmable Clock Output/Buzzer Output REGC: Regulator Capacitance RESET: Reset RTC1HZ: Real-time Clock Correction Clock (1 Hz) Output RxD0: Receive Data SCK00, SCK01: Serial Clock Input/Output SCLA0, SCL00, SCL01: Serial Clock Input/Output SDAA0, SDA00, SDA01: Serial Data Input/Output SI00, SI01: Serial Data Input SO00, SO01: Serial Data Output TI00 to TI03: Timer Input TO00 to TO03: Timer Output TOOL0: Data Input/Output for Tool TOOLRxD, TOOLTxD: Data Input/Output for External Device TxD0: Transmit Data UDM0, UDM1, UDP0, UDP1: USB Input/Output UOVRCUR0, UOVRCUR1: USB Input UVBUSEN0, UVBUSEN1: USB Output UVDD: USB Power Supply/USB Regulator Capacitance UVBUS: USB Input/USB Power Supply (USB Optional BC) VDD: Power Supply VSS: Ground X1, X2: Crystal Oscillator (Main System Clock) XT1, XT2: Crystal Oscillator (Subsystem Clock) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 12 of 134 RL78/G1C 1.5 1. OUTLINE Block Diagram 1.5.1 32-pin products TIMER ARRAY UNIT (4ch) PORT 0 2 P00, P01 TI00/P00 TO00/P01 ch0 PORT 1 2 P16, P17 TI01/TO01/P16 ch1 PORT 2 5 P20 to P24 TI02/TO02/P17 ch2 PORT 3 2 P30, P31 TI03/TO03/P31 ch3 PORT 4 12-BIT INTERVAL TIMER P40 PORT 5 2 P50, P51 PORT 6 3 P60 to P62 PORT 7 WINDOW WATCHDOG TIMER PORT 12 SERIAL ARRAY UNIT0 (2ch) RxD0/P50 TxD0/P51 SCK00/P30 SI00/P50 SO00/P51 SCK01/P01 SI01/P00 SO01/P120 P121, P122 P137 CODE FLASH MEMORY RL78 CPU CORE DATA FLASH MEMORY A/D CONVERTER 5 ANI0/P20 to ANI4/P24 3 ANI16/P01, ANI17/P00, ANI19/P120 AVREFP/P20 AVREFM/P21 UART0 CSI00 RAM POWER ON RESET/ VOLTAGE DETECTOR CSI01 VDD SCL00/P30 SDA00/P50 IIC00 SCL01/P01 SDA01/P00 IIC01 VSS TOOLRxD/P50, TOOLTxD/P51 POR/LVD CONTROL RESET CONTROL TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL SCLA0/P60 HIGH-SPEED ON-CHIP OSCILLATOR PLL BUZZER OUTPUT 2 CLOCK OUTPUT CONTROL PCLBUZ0/P31, PCLBUZ1/P70 VOLTAGE REGULATOR MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT RESET X1/P121 X2/EXCLK/P122 SDAA0/P61 SERIAL INTERFACE IICA0 UDP0 UDM0 UDP1 UDM1 UVBUS P120 2 PORT 13 LOW-SPEED ON-CHIP OSCILLATOR REAL-TIME CLOCK P70 REGC INTP0/P137 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 2 INTP8/P00, INTP9/P01 INTP5/P16 USB UOVRCUR0 UVBUSEN0 UOVRCUR1 UVBUSEN1 R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 USB VOLTAGE REGULATOR UVDD Page 13 of 134 RL78/G1C 1.5.2 1. OUTLINE 48-pin products TIMER ARRAY UNIT (4ch) PORT 0 2 P00, P01 TI00/P00 TO00/P01 ch0 PORT 1 4 P14 to P17 TI01/TO01/P16 ch1 PORT 2 8 P20 to P27 TI02/TO02/P17 ch2 PORT 3 2 P30, P31 TI03/TO03/P31 ch3 PORT 4 2 P40, P41 PORT 5 2 P50, P51 PORT 6 4 P60 to P63 PORT 7 6 P70 to P75 4 P121 to P124 12-BIT INTERVAL TIMER WINDOW WATCHDOG TIMER PORT 12 LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 REAL-TIME CLOCK SERIAL ARRAY UNIT0 (2ch) RxD0/P50 TxD0/P51 PORT 13 P130 P137 PORT 14 P140 CODE FLASH MEMORY RL78 CPU CORE DATA FLASH MEMORY A/D CONVERTER ANI19/P120 AVREFP/P20 AVREFM/P21 UART0 KR0/P70 to KR5/P75 6 CSI00 RAM POWER ON RESET/ VOLTAGE DETECTOR CSI01 VDD SCL00/P30 SDA00/P50 IIC00 SCL01/P75 SDA01/P74 IIC01 VSS TOOLRxD/P50, TOOLTxD/P51 POR/LVD CONTROL RESET CONTROL TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL SCLA0/P60 HIGH-SPEED ON-CHIP OSCILLATOR 2 XT2/EXCLKS/P124 PCLBUZ0/P140, PCLBUZ1/P15 VOLTAGE REGULATOR MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR DIRECT MEMORY ACCESS CONTROL XT1/P123 PLL BUZZER OUTPUT CLOCK OUTPUT CONTROL RESET X1/P121 X2/EXCLK/P122 SDAA0/P61 SERIAL INTERFACE IICA0 UDP0 UDM0 UDP1 UDM1 UVBUS ANI0/P20 to ANI7/P27 8 KEY RETURN SCK00/P30 SI00/P50 SO00/P51 SCK01/P75 SI01/P74 SO01/P73 P120 REGC INTP0/P137 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 INTP5/P16 INTP6/P140 BCD ADJUSTMENT 2 INTP8/P74, INTP9/P75 USB UOVRCUR0 UVBUSEN0 UOVRCUR1 UVBUSEN1 R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 USB VOLTAGE REGULATOR UVDD Page 14 of 134 RL78/G1C 1.6 1. OUTLINE Outline of Functions [32-pin, 48-pin products] (1/2) Item 32-pin R5F10JBC Code flash memory (KB) 32 KB Data flash memory (KB) 2 KB RAM (KB) <R> 5.5 KB 48-pin R5F10KBC R5F10JGC 2 KB Note 1 5.5 KB Note 1 Memory space 1 MB Main system clock High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V), HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V) High-speed on-chip oscillator 1 to 24 MHz (VDD = 2.7 to 5.5 V), 1 to 16 MHz (VDD = 2.4 to 5.5 V) PLL clock 6, 12, 24 MHz Note 2 : VDD = 2.4 to 5.5 V - Subsystem clock Low-speed on-chip oscillator R5F10KGC 32 KB XT1 (crystal) oscillation 32.768 kHz (TYP.): VDD = 2.4 to 5.5 V On-chip oscillation (Watchdog timer/Real-time clock/12-bit interval timer clock) 15 kHz (TYP.): VDD = 2.4 to 5.5 V General-purpose register 8 bits x 32 registers (8 bits x 8 registers x 4 banks) Minimum instruction execution time 0.04167 s (High-speed on-chip oscillator: fHOCO = 48 MHz /fIH = 24 MHz operation) 0.04167 s (PLL clock: fPLL = 48 MHz /fIH = 24 MHz Note 2 operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) - * * * * Instruction set I/O port Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits x 8 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. Total 22 38 CMOS I/O 16 (N-ch O.D. I/O [VDD withstand voltage]: 5) 28 (N-ch O.D. I/O [VDD withstand voltage]: 6) CMOS input 3 5 - CMOS output Timer N-ch open-drain I/O (6 V tolerance) 3 16-bit timer 4 channel Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit Interval timer (IT) 1 channel Timer output 4 channels (PWM output: 3) RTC output - 1 4 Note 3 Note 4 1 * 1 Hz (subsystem clock: fSUB = 32.768 kHz) Notes 1. In the case of the 5.5 KB, this is about 4.5 KB when the self-programming function is used. 2. In the PLL clock 48 MHz operation, the system clock is 2/4/8 dividing ratio. 3. In 32-pin products, this channel can only be used for the constant-period interrupt function based on the low-speed on-chip oscillator clock (fIL). 4. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves). Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 15 of 134 RL78/G1C 1. OUTLINE (2/2) Item 32-pin R5F10JBC Clock output/buzzer output 48-pin R5F10KBC R5F10JGC 2 R5F10KGC 2 * 2.93 kHz, 5.86 kHz, 11.7 kHz, 1.5 MHz, 3 MHz, 6 MHz, 12 MHz (Main system clock: fMAIN = 24 MHz operation) * 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 9 channels 2 Serial interface CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels 2 USB 8 channels I C bus 1 channel Host controller 2 channels Function controller 1 channel Multiplier and * Multiplier: divider/multiply-accumulator * Divider: - - 2 channels 16 bits x 16 bits = 32 bits (Unsigned or signed) 32 bits / 32 bits = 32 bits (Unsigned) * Multiply-accumulator:16 bits x 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller Vectored interrupt sources 2 channels Internal 20 20 External 8 10 - Key interrupt Reset Power-on-reset circuit 6 * Reset by RESET pin * Internal reset by watchdog timer * Internal reset by power-on-reset * Internal reset by voltage detector * Internal reset by illegal instruction execution * Internal reset by RAM parity error * Internal reset by illegal-memory access * Power-on-reset: * Power-down-reset: Note 1.51 V (TYP.) 1.50 V (TYP.) Voltage detector 2.45 V to 4.06 V (9 stages) On-chip debug function Provided Power supply voltage VDD = 2.4 to 5.5 V Operating ambient temperature TA = -40 to +85 C (A: Consumer applications), TA = -40 to +105C (G: Industrial applications) Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 16 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) This chapter describes the electrical specifications for the products "A: Consumer applications (TA = -40 to +85C)". The target products A: Consumer applications ; TA = -40 to +85C R5F10JBCANA, R5F10JBCAFP, R5F10JGCANA, R5F10JGCAFB, R5F10KBCANA, R5F10KBCAFP, R5F10KGCANA, R5F10KGCAFB G: Industrial applications ; when using TA = -40 to +105C specification products at TA = -40 to +85C. R5F10JBCGNA, R5F10JBCGFP, R5F10JGCGNA, R5F10JGCGFB, R5F10KBCGNA, R5F10KBCGFP, R5F10KGCGNA, R5F10KGCGFB Cautions 1. The RL78 microcontrollers has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. The pins mounted depend on the product. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 17 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbols Conditions VDD REGC pin input voltage VIREGC Ratings Unit -0.5 to +6.5 V -0.3 to +2.8 REGC V and -0.3 to VDD +0.3 UVDD pin input voltage Input voltage VIUVDD VI1 Note 1 -0.3 to VDD +0.3 UVDD -0.3 to VDD +0.3 P00, P01, P14 to P17, P20 to P27, P30, P31, P40, V Note 2 V P41, P50, P51, P70 to P75, P120 to P124, P137, P140, EXCLK, EXCLKS, RESET Output voltage VI2 P60 to P63 (N-ch open-drain) -0.3 to +6.5 V VI3 UDP0, UDM0, UDP1, UDM1 -0.3 to +6.5 V VI4 UVBUS -0.3 to +6.5 VO1 -0.3 to VDD +0.3 P00, P01, P14 to P17, P20 to P27, P30, P31, P40, V Note 2 V P41, P50, P51, P60 to P63, P70 to P75, P120, P130, P140 Analog input voltage VO2 UDP0, UDM0, UDP1, UDM1 VAI1 ANI16, ANI17, ANI19 -0.3 to +6.5 V -0.3 to VDD +0.3 V and -0.3 to AVREF (+) +0.3 Notes 2, 3 VAI2 -0.3 to VDD +0.3 ANI0 to ANI7 V and -0.3 to AVREF (+) +0.3 Notes 2, 3 Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). maximum rating of the REGC pin. 2. 3. This value regulates the absolute Do not use this pin with voltage applied to it. Must be 6.5 V or lower. Do not exceed AV REF (+) + 0.3 V in case of A/D conversion target pin Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. AVREF (+) : The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal reference voltage (1.45 V), and VDD. 3. VSS : Reference voltage R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 18 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, high Symbols IOH1 Conditions Per pin P00, P01, P14 to P17, P30, P31, Ratings Unit -40 P40, P41, P50, P51, P70 to P75, P120, P130, P140 Total of all pins P00, P01, P40, P41, P120, -170 mA P130, P140 P14 to P17, P30, P31, -70 mA -100 mA P50, P51, P70 to P75 IOH2 Per pin P20 to P27 Total of all pins Output current, low IOL1 Per pin P00, P01, P14 to P17, P30, P31, -0.5 mA -2 mA 40 mA 70 mA 100 mA 1 mA 5 mA -40 to +85 C -65 to +150 C P40, P41, P50, P51, P60 to P63, P70 to P75, P120, P130, P140 Total of all pins P00, P01, P40, P41, P120, 170 mA P130, P140 P14 to P17, P30, P31, P50, P51, P60 to P63, P70 to P75 IOL2 Per pin P20 to P27 Total of all pins Operating ambient TA temperature Storage temperature In normal operation mode In flash memory programming mode Tstg Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 19 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2.2 2.2.1 Oscillator Characteristics X1, XT1 oscillator characteristics (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter X1 clock oscillation Note frequency (fX) XT1 clock oscillation Resonator Conditions MIN. TYP. MAX. Unit Ceramic resonator/ 2.7 V VDD 5.5 V 1.0 20.0 MHz crystal resonator 2.4 V VDD < 2.7 V 1.0 16.0 MHz 35 kHz Crystal resonator 32 32.768 Note frequency (fXT) Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. 2.2.2 On-chip oscillator characteristics (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Oscillators High-speed on-chip oscillator clock frequency Parameters Conditions fHOCO MIN. TYP. MAX. Unit 1 48 MHz Notes 1, 2 High-speed on-chip oscillator -20 to +85 C -1.0 +1.0 % clock frequency accuracy -40 to -20 C -1.5 +1.5 % Low-speed on-chip oscillator fIL 15 kHz clock frequency Low-speed on-chip oscillator -15 +15 % clock frequency accuracy Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and bits 0 to 2 of HOCODIV register. 2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution time. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 20 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2.2.3 PLL oscillator characteristics (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Oscillators PLL input frequency Parameters Note PLL output frequency Note fPLLIN Conditions High-speed system clock MIN. 6.00 fPLL Lock up time TYP. MAX. Unit 16.00 MHz 48.00 From PLL output enable to stabilization of the MHz 40.00 s 4.00 s 1.00 s output frequency Interval time From PLL stop to PLL re-operation setteing Wait time Setting wait time From after PLL input clock stabilization and PLL setting is fixed to start setting Wait time required Note Indicates only oscillator characteristics. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Refer to AC Characteristics for instruction execution time. Page 21 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2.3 DC Characteristics 2.3.1 Pin characteristics (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Items Symbol Output current, high Conditions Per pin for P00, P01, P14 to P17, IOH1 Note 1 MIN. TYP. 2.4 V VDD 5.5 V MAX. Unit -10.0 mA Note 2 P30, P31, P40, P41, P50, P51, P70 to P75, P120, P130, P140 Total of P00, P01, P40, P41, P120, 4.0 V VDD 5.5 V -55.0 mA P130, P140 2.7 V VDD < 4.0 V -10.0 mA 2.4 V VDD < 2.7 V -5.0 mA Total of P14 to P17, P30, P31, 4.0 V VDD 5.5 V -80.0 mA P50, P51, P70 to P75 2.7 V VDD < 4.0 V -19.0 mA 2.4 V VDD < 2.7 V -10.0 mA 2.4 V VDD 5.5 V -135.0 mA 2.4 V VDD 5.5 V -0.1 Not mA (When duty 70% (When duty 70% Note 3 Note 3 ) ) Total of all pins Note 3 (When duty 70% IOH2 ) Per pin for P20 to P27 e2 2.4 V VDD 5.5 V Total of all pins Note 3 (When duty 70% Notes 1. -1.5 mA ) Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin. 2. However, do not exceed the total current value. 3. Specification under conditions where the duty factor 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty ratio to n%). * Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where n = 80% and IOH = -10.0 mA Total output current of pins = (-10.0 x 0.7)/(80 x 0.01) -8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P00, P01, P30, and P74 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 22 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Items Symbol Output current, Conditions Per pin for P00, P01, P14 to P17, IOL1 Note 1 MIN. 2.4V VDD 5.5 V TYP. MAX. 20.0 mA Note mA 2 P30, P31, P40, P41, P50, P51, low Unit Note P70 to P75, P120, P130, P140 2.4V VDD 5.5 V Per pin for P60 to P63 20.0 2 Total of P00, P01, P40, P41, P120, 4.0 V VDD 5.5 V 70.0 mA P130, P140 2.7 V VDD < 4.0 V 15.0 mA 2.4 V VDD < 2.7 V 9.0 mA Total of P14 to P17, P30, P31, P50, 4.0 V VDD 5.5 V 80.0 mA P51, P60 to P63, P70 to P75 2.7 V VDD < 4.0 V 35.0 mA 2.4 V VDD < 2.7 V 20.0 mA 2.4V VDD 5.5 V 150.0 mA (When duty 70% (When duty 70% Note 3 Note 3 ) ) Total of all pins (When duty 70% IOL2 Note 3 Per pin for P20 to P27 2.4V VDD 5.5 V Total of all pins 2.4V VDD 5.5 V Note 3 (When duty 70% Notes 1. ) 0.4 Note 2 5.0 mA mA ) Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin. 2. 3. However, do not exceed the total current value. Specification under conditions where the duty factor 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty ratio to n%). * Total output current of pins = (IOL x 0.7)/(n x 0.01) <Example> Where n = 80% and IOL = 10.0 mA Total output current of pins = (10.0 x 0.7)/(80 x 0.01) 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 23 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Items Input voltage, Symbol VIH1 Conditions P00, P01, P14 to P17, MIN. Normal input buffer TYP. MAX. Unit 0.8VDD VDD V 2.2 VDD V 2.0 VDD V 1.5 VDD V P30, P31, P40, P41, P50, P51, P70 high to P75, P120, P140 VIH2 P00, P01, P30, P50 TTL input buffer 4.0 V VDD 5.5 V TTL input buffer 3.3 V VDD < 4.0 V TTL input buffer 2.4 V VDD < 3.3 V Input voltage, VIH3 P20 to P27 0.7VDD VDD V VIH4 P60 to P63 0.7VDD 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD VDD V VIL1 P00, P01, P14 to P17, P30, P31, Normal input buffer 0 0.2VDD V TTL input buffer 0 0.8 V 0 0.5 V 0 0.32 V P40, P41, P50, P51, P70 to P75, low P120, P140 VIL2 P00, P01, P30, P50 4.0 V VDD 5.5 V TTL input buffer 3.3 V VDD < 4.0 V TTL input buffer 2.4 V VDD < 3.3 V VIL3 P20 to P27 0 0.3VDD V VIL4 P60 to P63 0 0.3VDD V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2VDD V Caution The maximum value of VIH of pins P00, P01, P30, and P74 is VDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 24 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Items Symbol Output voltage, VOH1 high Conditions MIN. P00, P01, P14 to P17, P30, P31, 4.0 V VDD 5.5 V, P40, P41, P50, P51, P70 to P75, IOH1 = -10.0 mA P120, P130, P140 4.0 V VDD 5.5 V, IOH1 = -3.0 mA 2.7 V VDD 5.5 V, IOH1 = -2.0 mA 2.4 V VDD 5.5 V, IOH1 = -1.5 mA VOH2 P20 to P27 2.4 V VDD 5.5 V, IOH2 = -100 A Output voltage, VOL1 low P00, P01, P14 to P17, P30, P31, 4.0 V VDD 5.5 V, P40, P41, P50, P51, P70 to P75, IOL1 = 20.0 mA P120, P130, P140 TYP. MAX. VDD - Unit V 1.5 VDD - V 0.7 VDD - V 0.6 VDD - V 0.5 VDD - V 0.5 4.0 V VDD 5.5 V, 1.3 V 0.7 V 0.6 V 0.4 V 0.4 V 0.4 V 2.0 V 0.4 V 0.4 V 0.4 V IOL1 = 8.5 mA 2.7 V VDD 5.5 V, IOL1 = 3.0 mA 2.7 V VDD 5.5 V, IOL1 = 1.5 mA 2.4 V VDD 5.5 V, IOL1 = 0.6 mA VOL2 P20 to P27 2.4 V VDD 5.5 V, IOL2 = 400 A VOL3 P60 to P63 4.0 V VDD 5.5 V, IOL1 = 20.0 mA 4.0 V VDD 5.5 V, IOL1 = 5.0 mA 2.7 V VDD 5.5 V, IOL1 = 3.0 mA 2.4 V VDD 5.5 V, IOL1 = 2.0 mA Caution P00, P01, P30, and P74 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 25 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Items Input leakage Symbol ILIH1 Conditions P00, P01, P14 to P17, MIN. TYP. VI = VDD MAX. Unit 1 A 1 A 10 A -1 A -1 A -10 A 100 k P20 to P27, P30, P31, current, high P40, P41, P50, P51, P60 to P63, P70 to P75, P120, P137, P140, RESET ILIH2 P121 to P124 VI = VDD In input port (X1, X2, XT1, XT2, EXCLK, or external EXCLKS) clock input In resonator connection Input leakage ILIL1 P00, P01, P14 to P17, VI = VSS P20 to P27, P30, P31, P40, current, low P41, P50, P51, P60 to P63, P70 to P75, P120, P137, P140, RESET ILIL2 P121 to P124 VI = VSS In input port (X1, X2, XT1, XT2, EXCLK, or external EXCLKS) clock input In resonator connection On-chip pll-up RU P00, P01, P14 to P17, VI = VSS, In input port 10 20 P30, P31, P40, P41, resistance P50, P51, P70 to P75, P120, P140 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 26 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2.3.2 Supply current characteristics (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Supply current IDD1 Note 1 (1/2) Conditions Operating mode MIN. fHOCO = 48 MHz HS (High-speed fIH = 24 MHz Note 3 main) mode Note 6 fHOCO = 24 MHz fIH = 12 MHz Note 3 fHOCO = 12 MHz fIH = 6 MHz Note 5 Note 5 Note 3 Note fHOCO = 6 MHz 5 fIH = 3 MHz Note 2 VDD = 3.0 V fMX = 10 MHz Note 2 , VDD = 5.0 V fMX = 10 MHz Note 2 , VDD = 3.0 V HS (High-speed main) mode (PLL operation) Note 6 fPLL = 48 MHz, fCLK = 24 MHz fPLL = 48 MHz, fCLK = 12 MHz Note 2 fPLL = 48 MHz, fCLK = 6 MHz Subsystem clock operation Note 2 Note 2 fSUB = 32.768 kHz Note 4 MAX. 1.7 mA VDD = 3.0 V 1.7 Normal operation VDD = 5.0 V 3.7 VDD = 3.0 V 3.7 5.5 mA Normal operation VDD = 5.0 V 2.3 3.2 mA VDD = 3.0 V 2.3 3.2 mA Normal operation VDD = 5.0 V 1.6 2.0 mA VDD = 3.0 V 1.6 2.0 mA Normal operation VDD = 5.0 V 1.2 1.5 mA VDD = 3.0 V 1.2 1.5 mA Normal operation Square wave input 3.0 4.6 mA Resonator connection 3.2 4.8 mA Normal operation Square wave input 3.0 4.6 mA Resonator connection 3.2 4.8 mA Normal operation Square wave input 1.9 2.7 mA Resonator connection 1.9 2.7 mA Normal operation Square wave input 1.9 2.7 mA Resonator connection 1.9 2.7 mA Normal operation VDD = 5.0 V 4.0 5.9 mA VDD = 3.0 V 4.0 5.9 mA Normal operation VDD = 5.0 V 2.6 3.6 mA VDD = 3.0 V 2.6 3.6 mA Normal operation VDD = 5.0 V 1.9 2.4 mA VDD = 3.0 V 1.9 2.4 mA Normal operation Resonator connection 4.1 4.9 A Square wave input 4.2 5.0 A Normal operation Square wave input 4.1 4.9 A Resonator connection 4.2 5.0 A Normal operation Square wave input 4.2 5.5 A Resonator connection 4.3 5.6 A Normal operation Square wave input 4.2 6.3 A Resonator connection 4.3 6.4 A Normal operation Square wave input 4.8 7.7 A Resonator connection 4.9 7.8 A mA 5.5 TA = -40C f = 32.768 kHz SUB Note 4 TA = +25C fSUB = 32.768 kHz Note 4 Unit VDD = 5.0 V Note 3 HS fMX = 20 MHz , (High-speed VDD = 5.0 V main) mode Note 2 Note 6 fMX = 20 MHz , TYP. Basic operation mA TA = +50C fSUB = 32.768 kHz Note 4 TA = +70C fSUB = 32.768 kHz Note 4 TA = +85C (Notes and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 27 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 5. When Operating frequency setting of option byte = 48 MHz. When fHOCO is divided by HOCODIV. When RDIV[1:0] = 00 (divided by 2: default). 6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 24 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz Remarks 1. fHOCO: High-speed on-chip oscillator clock frequency (Max. 48 MHz) 2. fIH: Main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock by 2, 4, or 8 (Max. 24 MHz) 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 4. fPLL: PLL oscillation frequency 5. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 6. fCLK: CPU/peripheral hardware clock frequency 7. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 28 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol (2/2) Conditions MIN. fHOCO = 48 MHz Supply IDD2 HALT HS current Note 2 mode (High-speed fIH = 24 MHz Note 4 main) mode Note 7 fHOCO = 24 MHz Note 9 Note 1 fIH = 12 MHz Note 4 fHOCO = 12 MHz fIH = 6 MHz Note 4 fHOCO = 6 MHz fIH = 3 MHz HS Note 7 Note 7 Note 4 fMX = 20 MHz Note 3 , (High-speed VDD = 5.0 V main) mode Note 3 fMX = 20 MHz , Note 9 VDD = 3.0 V fMX = 10 MHz Note 3 , VDD = 5.0 V fMX = 10 MHz Note 3 , VDD = 3.0 V HS fPLL = 48 MHz, (High-speed fCLK = 24 MHz main) mode (PLL operation) Note 9 Unit VDD = 5.0 V 0.67 1.25 mA VDD = 3.0 V 0.67 1.25 mA VDD = 5.0 V 0.50 0.86 mA VDD = 3.0 V 0.50 0.86 mA VDD = 5.0 V 0.41 0.67 mA VDD = 3.0 V 0.41 0.67 mA VDD = 5.0 V 0.37 0.58 mA VDD = 3.0 V 0.37 0.58 mA Square wave input 0.28 1.00 mA Resonator connection 0.45 1.17 mA Square wave input 0.28 1.00 mA Resonator connection 0.45 1.17 mA Square wave input 0.19 0.60 mA Resonator connection 0.26 0.67 mA Square wave input 0.19 0.60 mA Resonator connection 0.26 0.67 mA VDD = 5.0 V 0.91 1.52 mA VDD = 3.0 V 0.91 1.52 mA VDD = 5.0 V 0.85 1.28 mA VDD = 3.0 V 0.85 1.28 mA VDD = 5.0 V 0.82 1.15 mA Note 3 fPLL = 48 MHz, fCLK = 6 MHz MAX. Note 3 fPLL = 48 MHz, fCLK = 12 MHz TYP. Note 3 VDD = 3.0 V 0.82 1.15 mA Square wave input 0.25 0.57 A Resonator 0.44 0.76 A Square wave input 0.30 0.57 A Resonator 0.49 0.76 A Square wave input 0.33 1.17 A Resonator 0.63 1.36 A Square wave input 0.46 1.97 A Resonator 0.76 2.16 A Square wave input 0.97 3.37 A Resonator 1.16 3.56 A TA = -40C 0.18 0.50 A TA = +25C 0.23 0.50 A TA = +50C 0.26 1.10 A TA = +70C 0.29 1.90 A TA = +85C 0.90 3.30 A Subsystem fSUB = 32.768 kHz clock TA = -40C operation Note 5 connection fSUB = 32.768 kHz Note 5 TA = +25C connection fSUB = 32.768 kHz Note 5 TA = +50C connection fSUB = 32.768 kHz Note 5 TA = +70C connection fSUB = 32.768 kHz TA = +85C Note 5 connection Note 6 IDD3 STOP mode Note 8 (Notes and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 29 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, USB 2.0 host/function module, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 7. When Operating frequency setting of option byte = 48 MHz. When fHOCO is divided by HOCODIV. When RDIV[1:0] = 00 (divided by 2: default). 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. 9. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 24 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz Remarks 1. fHOCO: High-speed on-chip oscillator clock frequency (Max. 48 MHz) 2. fIH: Main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock by 2, 4, or 8 (Max. 24 MHz) 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 4. fPLL: PLL oscillation frequency 5. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 6. fCLK: CPU/peripheral hardware clock frequency 7. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 30 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) (1/2) Parameter Low-speed on-chip Symbol I Conditions MIN. Note 1 FIL TYP. MAX. Unit 0.20 A 0.02 A 0.02 A 0.22 A oscillator operating current RTC operating current IRTC Notes 1, 2, 3 12-bit interval timer IIT Notes 1, 2, 4 operating current Watchdog timer operating current IWDT A/D converter operating current IADC fIL = 15 kHz Notes 1, 2, 5 Notes 1, 6 When conversion at maximum speed Normal mode, AVREFP = VDD = 5.0 V Low voltage mode, AVREFP = VDD = 3.0 V 1.3 1.7 mA 0.5 0.7 mA Note 75.0 A Note 1 75.0 A Notes 1, 0.08 A Notes 1, 2.00 12.20 mA Notes 1, 2.00 12.20 mA 0.50 1.06 mA 1.20 1.62 mA 0.70 0.84 mA A/D converter reference IADREF 1 voltage current Temperature sensor operating current ITMPS LVD operating current ILVD 7 Self-programming IFSP operating current 9 BGO operating current IBGO 8 SNOOZE operating current ISNOZ Note 1 ADC operation The mode is performed Note 10 The A/D conversion operations are performed, Low voltage mode, AVREFP = VDD = 3.0 V CSI operation (Notes and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 31 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) (2/2) Parameter USB operating current Symbol IUSBH Note 11 IUSBF Note 11 ISUSP Note 12 Conditions MIN. TYP. MAX. Unit During USB communication operation under the following settings and conditions (VDD = 5.0 V, TA = +25C): * The internal power supply for the USB is used. * X1 oscillation frequency (fX) = 12 MHz, PLL oscillation frequency (fPLL) = 48 MHz * The host controller (via two ports) is set to operate in full-speed mode with four pipes (end points) used simultaneously. (PIPE4: Bulk OUT transfer (64 bytes), PIPE5: Bulk IN transfer (64 bytes), PIPE6: Interrupt OUT transfer, PIPE7: Interrupt IN transfer). * The USB ports (two ports) are individually connected to a peripheral function via a 0.5 m USB cable. 9.0 mA During USB communication operation under the following settings and conditions (VDD = 5.0 V, TA = +25C): * The internal power supply for the USB is used. * X1 oscillation frequency (fX) = 12 MHz, PLL oscillation frequency (fPLL) = 48 MHz * The function controller is set to operate in full-speed mode with four pipes (end points) used simultaneously. (PIPE4: Bulk OUT transfer (64 bytes), PIPE5: Bulk IN transfer (64 bytes), PIPE6: Interrupt OUT transfer, PIPE7: Interrupt IN transfer). * The USB port (one port) is connected to the host device via a 0.5 m USB cable. 2.5 mA During suspended state under the following settings and conditions (VDD = 5.0 V, TA = +25C): * The function controller is set to full-speed mode (the UDP0 pin is pulled up). * The internal power supply for the USB is used. * The system is set to STOP mode (When the high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When the watchdog timer is stopped.). * The USB port (one port) is connected to the host device via a 0.5 m USB cable. 240 A (Notes and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 32 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C Notes 1. Current flowing to VDD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock. 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in operation. 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 7. Current flowing only to the LVD circuit. The current value of the RL78/G1C is the sum of IDD1, IDD2 or IDD3 and ILVI when the LVD circuit operates in the Operating, HALT or STOP mode. 8. Current flowing only during data flash rewrite. 9. Current flowing only during self programming. 10. For shift time to the SNOOZE mode. 11. Current consumed only by the USB module and the internal power supply for the USB. 12. Includes the current supplied from the pull-up resistor of the UDP0 pin to the pull-down resistor of the host device, in addition to the current consumed by this MCU during the suspended state. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 3. fCLK: CPU/peripheral hardware clock frequency 4. Temperature condition of the TYP. value is TA = 25C R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 33 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2.4 2.4.1 AC Characteristics Basic operation (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Items Instruction cycle (minimum Symbol TCY instruction execution time) Conditions MIN. MAX. Unit 0.04167 1 s 0.0625 1 s 31.3 s 0.04167 1 s 0.0625 1 s 2.7 V VDD 5.5 V 1.0 20.0 MHz 2.4 V VDD < 2.7 V 1.0 16.0 MHz 32 35 kHz 2.7 V VDD Main HS system (High-speed 5.5 V clock (fMAIN) main) mode 2.4 V VDD < operation 2.7 V Subsystem clock (fSUB) 2.4 V VDD operation 5.5 V In the self TYP. HS 2.7 V VDD 28.5 30.5 programmin (High-speed 5.5 V g mode main) mode 2.4 V VDD < 2.7 V External system clock frequency fEX fEXS External system clock input tEXH, tEXL high-level width, low-level width 2.7 V VDD 5.5 V 24 ns 2.4 V VDD < 2.7 V 30 ns 13.7 s 1/fMCK+10 ns tEXHS, tEXLS TI00 to TI03 input high-level tTIH, width, low-level width tTIL TO00 to TO03 output frequency fTO PCLBUZ0, PCLBUZ1 output fPCL frequency High-speed main 4.0 V VDD 5.5 V 12 MHz mode 2.7 V VDD < 4.0 V 8 MHz 2.4 V VDD < 2.7 V 4 MHz High-speed main 4.0 V VDD 5.5 V 16 MHz mode 2.7 V VDD < 4.0 V 8 MHz 2.4 V VDD < 2.7 V 4 MHz Interrupt input high-level width, tINTH, INTP0 to INTP6, low-level width tINTL INTP8, INTP9 Key interrupt input low-level width tKR RESET low-level width KR0 to KR5 tRSL 2.4 V VDD 5.5 V 1 s 2.4 V VDD 5.5 V 250 ns 10 s Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 3)) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 34 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 10 1.0 Cycle time TCY [s] When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.1 0.0625 0.05 0.04167 0.01 0 1.0 2.0 3.0 2.4 2.7 4.0 5.0 5.5 6.0 Supply voltage VDD [V] AC Timing Test Points VIH/VOH VIL/VOL Test points VIH/VOH VIL/VOL External System Clock Timing 1/fEX/ 1/fEXS tEXL/ tEXLS tEXH/ tEXHS EXCLK/EXCLKS R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 35 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C TI/TO Timing tTIH tTIL TI00 to TI03 1/fTO TO00 to TO03 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP6, INTP8, INTP9 Key Interrupt Input Timing tKR KR0 to KR5 RESET Input Timing tRSL RESET R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 36 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2.5 Peripheral Functions Characteristics 2.5.1 Serial array unit (1) During communication at same potential (UART mode) (dedicated baud rate generator output) (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. Transfer rate Theoretical value of the MAX. Unit fMCK/6 bps 4.0 Mbps maximum transfer rate fMCK = fCLK Note Note The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) Rx TxDq User's device RL78 microcontroller Tx RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remarks 1. 2. q: UART number (q = 0), g: PIM and POM number (g = 5) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 37 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = -40 to +85C, 2.7 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions SCKp cycle time tKCY1 tKCY1 2/fCLK SCKp high-/low-level width tKH1, tKL1 SIp setup time (to SCKp) Note 1 SIp hold time (from SCKp) Note 2 Delay time from SCKp to SOp output tSIK1 tKSI1 tKSO1 2.7 V VDD 5.5 V MIN. TYP. MAX. Unit 83.3 ns 4.0 V VDD 5.5 V tKCY1/2 - 7 ns 2.7 V VDD 5.5 V tKCY1/2 - 10 ns 4.0 V VDD 5.5 V 23 ns 2.7 V VDD 5.5 V 33 ns 2.7 V VDD 5.5 V 10 ns Note 3 C = 20 pF 10 ns Note 3 Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. 2. This specification is valid only when CSI00's peripheral I/O redirect function is not used. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 3, 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 38 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol SCKp cycle time tKCY1 SCKp high-/low-level width SIp setup time (to SCKp) Note 1 SIp hold time (from SCKp) Note 2 Delay time from SCKp to SOp output Conditions tKCY1 4/fCLK MIN. TYP. MAX. Unit 2.7 V VDD 5.5 V 167 ns 2.4 V VDD 5.5 V 250 ns tKH1, 4.0 V VDD 5.5 V tKCY1/2 - 12 ns tKL1 2.7 V VDD 5.5 V tKCY1/2 - 18 ns 2.4 V VDD 5.5 V tKCY1/2 - 38 ns 4.0 V VDD 5.5 V 44 ns 2.7 V VDD 5.5 V 44 ns 2.4 V VDD 5.5 V 75 ns 19 ns tSIK1 tKSI1 tKSO1 Note 4 C = 30 pF 25 ns Note 3 Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 0, 3, 5, 7) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 39 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter SCKp cycle time Note 5 Symbol tKCY2 Conditions 4.0 V VDD 5.5 V 2.7 V VDD 5.5 V MIN. TYP. MAX. Unit 20 MHz < fMCK 8/fMCK ns fMCK 20 MHz 6/fMCK ns 16 MHz < fMCK 8/fMCK ns fMCK 16 MHz 6/fMCK ns 6/fMCK ns 2.4 V VDD 5.5 V and 500 SCKp high-/low-level width tKH2, 4.0 V VDD 5.5 V tKCY2/2 - 7 ns tKL2 2.7 V VDD 5.5 V tKCY2/2 - 8 ns 2.4 V VDD 5.5 V tKCY2/2 - ns 18 SIp setup time (to SCKp) tSIK2 Note 1 SIp hold time (from SCKp) tKSI2 Note 2 Delay time from SCKp to SOp output tKSO2 2.7 V VDD 5.5 V 1/fMCK+20 ns 2.4 V VDD 5.5 V 1/fMCK+30 ns 2.7 V VDD 5.5 V 1/fMCK+31 ns 2.4 V VDD 5.5 V 1/fMCK+31 ns C = 30 pF Note 4 Note 3 2.7 V VDD 5.5 V 2/fMCK+44 ns 2.4 V VDD 5.5 V 2/fMCK+75 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM number (g = 0, 3, 5, 7) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 40 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C CSI mode connection diagram (during communication at same potential) SCK SCKp RL78 microcontroller SIp SO User's device SI SOp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 Output data SOp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Remarks 1. 2. Output data p: CSI number (p = 00, 01) m: Unit number, n: Channel number (mn = 00, 01) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 41 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2 (5) During communication at same potential (simplified I C mode) (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter SCLr clock frequency Symbol fSCL Conditions MIN. MAX. 1000 2.7 V VDD 5.5 V, Note 1 Unit kHz Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, 400 Note 1 kHz 300 Note 1 kHz Cb = 100 pF, Rb = 3 k 2.4 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Hold time when SCLr = "L" tLOW 2.7 V VDD 5.5 V, 475 ns 1150 ns 1550 ns 475 ns 1150 ns 1550 ns 1/fMCK + 85 ns 1/fMCK + 145 ns 1/fMCK + 230 ns Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k 2.4 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Hold time when SCLr = "H" tHIGH 2.7 V VDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k 2.4 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Data setup time (reception) tSU:DAT 2.7 V VDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k 2.4 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Data hold time (transmission) tHD:DAT 2.7 V VDD 5.5 V, Note 2 Note 2 Note 2 0 305 ns 0 355 ns 0 405 ns Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k 2.4 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Notes 1. The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). (Caution and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 42 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2 Simplified I C mode mode connection diagram (during communication at same potential) VDD Rb SDA SDAr User's device RL78 microcontroller SCL SCLr 2 Simplified I C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT tSU:DAT Remarks 1. Rb[]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2. r: IIC number (r = 00, 01), g: PIM number (g = 5), h: POM number (h = 3, 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 43 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (6) Communication at different potential (2.5 V, 3 V) (UART mode) (1/2) (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Transfer rate Conditions reception MIN. TYP. Note 1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V MAX. fMCK/6 Theoretical value of the 4.0 Unit bps Mbps maximum transfer rate fMCK = fCLK Note 2 Note 1 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V fMCK/6 Theoretical value of the 4.0 bps Mbps maximum transfer rate fMCK = fCLK Note 2 Note 1 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V fMCK/6 Theoretical value of the 4.0 bps Mbps maximum transfer rate fMCK = fCLK Note 2 Notes 1. Use it with VDDVb. 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. For VIH and VIL, see the DC characteristics with TTL input buffer selected. Vb[V]: Communication line voltage 2. q: UART number (q = 0), g: PIM and POM number (g = 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 44 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (6) Communication at different potential (2.5 V, 3 V) (UART mode) (2/2) (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Transfer rate Symbol Conditions transmission MIN. TYP. 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V Theoretical value of the MAX. Unit Note 1 bps 2.8 Note 2 Mbps maximum transfer rate Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V 2.7 V VDD < 4.0 V Note 3 2.3 V Vb 2.7 V Theoretical value of the 1.2 Note 4 bps Mbps maximum transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V 2.4 V VDD < 3.3 V Notes bps 5, 6 1.6 V Vb 2.0 V Theoretical value of the 0.43 maximum transfer rate Note 7 Mbps Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V VDD 5.5 V and 2.7 V Vb 4.0 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 2.2 Vb )} x 3 [bps] 1 - {-Cb x Rb x ln (1 - Transfer rate x 2 2.2 Vb )} 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 2. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. 3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V VDD < 4.0 V and 2.3 V Vb 2.7 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 2.0 Vb )} x 3 [bps] 1 - {-Cb x Rb x ln Transfer rate x 2 2.0 (1 - Vb )} 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 4. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. 5. Use it with VDD Vb. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 45 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C Notes 6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.4 V VDD < 3.3 V and 1.6 V Vb 2.0 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 1.5 Vb )} x 3 [bps] 1.5 1 - {-Cb x Rb x ln (1 - Vb )} Transfer rate x 2 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 7. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. UART mode connection diagram (during communication at different potential) Vb Rb TxDq Rx User's device RL78 microcontroller RxDq R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Tx Page 46 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1. Rb[]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0), g: PIM and POM number (g = 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 47 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter SCKp cycle time Symbol tKCY1 tKCY1 2/fCLK Conditions MIN. TYP. MAX. Unit 4.0 V VDD 5.5 V, 200 ns 300 ns tKCY1/2 - 50 ns tKCY1/2 - ns 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCKp high-level width tKH1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCKp low-level width tKL1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 120 tKCY1/2 - 7 ns tKCY1/2 - 10 ns 58 ns 121 ns 10 ns 10 ns Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp setup time (to SCKp) tSIK1 Note 1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp hold time (from SCKp) tKSI1 Note 1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Delay time from SCKp to SOp output tKSO1 Note 1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 60 ns 130 ns Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp setup time (to SCKp) tSIK1 Note 2 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 23 ns 33 ns 10 ns 10 ns Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp hold time (from SCKp) tKSI1 Note 2 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Delay time from SCKp to SOp output Note 2 tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 10 ns 10 ns Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. (Caution and Remark are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 48 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Rb[]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 3, 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00) 4. This value is valid only when CSI00's peripheral I/O redirect function is not used. (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/2) (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter SCKp cycle time Symbol tKCY1 Conditions tKCY1 4/fCLK 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, MIN. TYP. MAX. Unit 300 ns 500 ns 1150 ns tKCY1/2 - 75 ns tKCY1/2 - ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 2.4 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SCKp high-level width tKH1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, C = 30 pF, Rb = 5.5 k b SCKp low-level width tKL1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 170 tKCY1/2 - ns 458 tKCY1/2 - 12 ns tKCY1/2 - 18 ns tKCY1/2 - 50 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. Use it with VDD Vb. (Remarks are listed two pages after the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 49 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/2) (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter SIp setup time Note 1 (to SCKp) Symbol tSIK1 Conditions MIN. 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, TYP. MAX. Unit 81 ns 177 ns 479 ns 19 ns 19 ns 19 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 3 , Cb = 30 pF, Rb = 5.5 k SIp hold time Note 1 (from SCKp) tKSI1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 3 , Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to Note 1 SOp output tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 100 ns 195 ns 483 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 3 , Cb = 30 pF, Rb = 5.5 k SIp setup time Note 2 (to SCKp) tSIK1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 44 ns 44 ns 110 ns 19 ns 19 ns 19 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 3 , Cb = 30 pF, Rb = 5.5 k SIp hold time Note 2 (from SCKp) tKSI1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 3 , Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to Note 2 SOp output tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 25 ns 25 ns 25 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 3 , Cb = 30 pF, Rb = 5.5 k (Notes, Cautions and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 50 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3 Use it with VDD Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) Vb <Master> Vb Rb Rb SCK SCKp RL78 microcontroller SIp SO User's device SI SOp Remarks 1. Rb[]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g = 0, 3, 5, 7) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) 4. CSI01 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 51 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data Remarks 1. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g = 0, 3, 5, 7) 2. CSI01 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 52 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter SCKp cycle time Note 1 Symbol tKCY2 Conditions tKH2, Unit 12/fMCK ns 2.7 V Vb 4.0 V 8 MHz < fMCK 20 MHz 10/fMCK ns 4 MHz < fMCK 8 MHz 8/fMCK ns fMCK 4 MHz 6/fMCK ns 2.7 V VDD < 4.0 V, 20 MHz < fMCK 24 MHz 16/fMCK ns 2.3 V Vb 2.7 V 16 MHz < fMCK 20 MHz 14/fMCK ns 8 MHz < fMCK 16 MHz 12/fMCK ns 4 MHz < fMCK 8 MHz 8/fMCK ns fMCK 4 MHz 6/fMCK ns 20 MHz < fMCK 24 MHz 36/fMCK ns 16 MHz < fMCK 20 MHz 32/fMCK ns 8 MHz < fMCK 16 MHz 26/fMCK ns 4 MHz < fMCK 8 MHz 16/fMCK ns fMCK 4 MHz 10/fMCK ns tKCY2/2 - ns Note 2 tKL2 MAX. 20 MHz < fMCK 24 MHz 1.6 V Vb 2.0 V width TYP. 4.0 V VDD 5.5 V, 2.4 V VDD < 3.3 V, SCKp high-/low-level MIN. 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V 12 tKCY2/2 - 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V ns 18 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 tKCY2/2 - ns 50 SIp setup time (to SCKp) tSIK2 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V 1/fMCK + Note 3 ns 20 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V 1/fMCK + ns 20 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 1/fMCK + ns 30 SIp hold time (from SCKp) tKSI2 Delay time from SCKp to SOp output 1/fMCK + 31 ns Note 4 tKSO2 Note 5 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 2/fMCK + Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, 2/fMCK + ns 214 Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V ns 120 Note 2 , Cb = 30 pF, Rb = 5.5 k 2/fMCK + ns 573 Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps 2. Use it with VDD Vb. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. (Caution and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 53 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) Vb <Slave> Rb SCKp RL78 microcontroller SIp SOp Remarks 1. SCK SO User's device SI Rb[]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g = 0, 3, 5, 7) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) 4. CSI01 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 54 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 Output data SOp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 SOp Output data Remarks 1. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g = 0, 3, 5, 7) 2. CSI01 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 55 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (1/2) (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter SCLr clock frequency Symbol fSCL Conditions MIN. 4.0 V VDD 5.5 V, MAX. Unit 1000 Note 1 kHz 1000 Note 1 kHz 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V VDD 5.5 V, 400 Note 1 kHz 400 Note 1 kHz 300 Note 1 kHz 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 , Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "L" tLOW 4.0 V VDD 5.5 V, 475 ns 475 ns 1150 ns 1150 ns 1550 ns 245 ns 200 ns 675 ns 600 ns 610 ns 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 , Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "H" tHIGH 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 , Cb = 100 pF, Rb = 5.5 k (Notes, Caution and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 56 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (2/2) (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Data setup time (reception) Data hold time (transmission) Symbol tSU:DAT tHD:DAT Conditions MIN. 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 135 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 135 MAX. Unit ns Note 3 ns Note 3 1/fMCK + 190 4.0 V VDD 5.5 V, Note 3 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k ns 2.7 V VDD < 4.0 V, 1/fMCK + 190 Note 3 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k ns 1/fMCK + 190 2.4 V VDD < 3.3 V, Notes 2 Note 3 , 1.6 V Vb 2.0 V Cb = 100 pF, Rb = 5.5 k ns 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 0 305 ns 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 0 305 ns 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 0 355 ns 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 0 355 ns 2.4 V VDD < 3.3 V, Note 2 , 1.6 V Vb 2.0 V Cb = 100 pF, Rb = 5.5 k 0 405 ns Notes 1. The value must also be equal to or less than fMCK/4. 2. Use it with VDD Vb. 3. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 57 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2 Simplified I C mode connection diagram (during communication at different potential) Vb Vb Rb Rb SDA SDAr User's device RL78 microcontroller SCL SCLr 2 Simplified I C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT tSU:DAT Remarks 1. Rb[]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage 2. r: IIC number (r = 00), g: PIM, POM number (g = 0, 3, 5, 7) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 58 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2.5.2 Serial interface IICA 2 (1) I C standard mode (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter SCLA0 clock frequency Symbol fSCL Setup time of restart condition tSU:STA Hold time Note 1 tHD:STA Hold time when SCLA0 = "L" Hold time when SCLA0 = "H" Data setup time (reception) Data hold time tLOW tHIGH tSU:DAT tHD:DAT Note 2 (transmission) Setup time of stop condition Bus-free time Notes 1. 2. tSU:STO tBUF Conditions HS (high-speed main) mode MIN. MAX. Unit Standard mode: fCLK 1 2.7 V VDD 5.5 V 0 100 kHz MHz 2.4 V VDD 5.5 V 0 100 kHz 2.7 V VDD 5.5 V 4.7 s 2.4 V VDD 5.5 V 4.7 s 2.7 V VDD 5.5 V 4.0 s 2.4 V VDD 5.5 V 4.0 s 2.7 V VDD 5.5 V 4.7 s 2.4 V VDD 5.5 V 4.7 s 2.7 V VDD 5.5 V 4.0 s 2.4 V VDD 5.5 V 4.0 s 2.7 V VDD 5.5 V 250 s 2.4 V VDD 5.5 V 250 s 2.7 V VDD 5.5 V 0 3.45 s 2.4 V VDD 5.5 V 0 3.45 s 2.7 V VDD 5.5 V 4.0 s 2.4 V VDD 5.5 V 4.0 s 2.7 V VDD 5.5 V 4.7 s 2.4 V VDD 5.5 V 4.7 s The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 1 (PIOR1) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 k R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 59 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2 (2) I C fast mode (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol SCLA0 clock frequency fSCL Setup time of restart condition tSU:STA Hold time Note 1 tHD:STA Hold time when SCLA0 = "L" tLOW Hold time when SCLA0 = "H" tHIGH Data setup time (reception) tSU:DAT Data hold time tHD:DAT Note 2 (transmission) Setup time of stop condition tSU:STO Bus-free time Notes 1. 2. tBUF Conditions HS (high-speed main) Mode MIN. MAX. Unit Fast mode: fCLK 3.5 2.7 V VDD 5.5 V 0 400 kHz MHz 2.4 V VDD 5.5 V 0 400 kHz 2.7 V VDD 5.5 V 0.6 s 2.4 V VDD 5.5 V 0.6 s 2.7 V VDD 5.5 V 0.6 s 2.4 V VDD 5.5 V 0.6 s 2.7 V VDD 5.5 V 1.3 s 2.4 V VDD 5.5 V 1.3 s 2.7 V VDD 5.5 V 0.6 s 2.4 V VDD 5.5 V 0.6 s 2.7 V VDD 5.5 V 100 ns 2.4 V VDD 5.5 V 100 ns 2.7 V VDD 5.5 V 0 0.9 s 2.4 V VDD 5.5 V 0 0.9 s 2.7 V VDD 5.5 V 0.6 s 2.4 V VDD 5.5 V 0.6 s 2.7 V VDD 5.5 V 1.3 s 2.4 V VDD 5.5 V 1.3 s The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 1 (PIOR1) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode: Cb = 320 pF, Rb = 1.1 k R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 60 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2 (3) I C fast mode plus (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol SCLA0 clock frequency fSCL Conditions Fast mode plus: HS (high-speed main) Mode 2.7 V VDD 5.5 V MIN. MAX. 0 1000 Unit kHz fCLK 10 MHz 2.7 V VDD 5.5 V 0.26 s tHD:STA 2.7 V VDD 5.5 V 0.26 s tLOW 2.7 V VDD 5.5 V 0.5 s Setup time of restart condition tSU:STA Hold time Note 1 Hold time when SCLA0 = "L" Hold time when SCLA0 = "H" tHIGH 2.7 V VDD 5.5 V 0.26 s Data setup time (reception) tSU:DAT 2.7 V VDD 5.5 V 50 ns Data hold time tHD:DAT 2.7 V VDD 5.5 V 0 Setup time of stop condition tSU:STO 2.7 V VDD 5.5 V 0.26 s Bus-free time tBUF 2.7 V VDD 5.5 V 0.5 s s 0.45 Note 2 (transmission) Notes 1. 2. The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 1 (PIOR1) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode plus: Cb = 120 pF, Rb = 1.1 k IICA serial transfer timing tLOW SCLA0 tHD:DAT tHD:STA tHIGH tSU:STA tHD:STA tSU:STO tSU:DAT SDAA0 tLOW Stop condition Start condition R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Restart condition Stop condition Page 61 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2.5.3 USB (1) Electrical specifications (TA = -40 to +85C, 3.0 V UVDD 3.6 V, 3.0 V VDD 5.5 V, VSS = 0 V) Parameter UVDD UVBUS MIN. TYP. MAX. Unit UVDD input voltage characteristic UVDD Symbol VDD = 3.0 to 5.5 V, PXXCON = 1, VDDUSEB = 0 (UVDD VDD) Conditions 3.0 3.3 3.6 V UVDD output voltage characteristic UVDD VDD = 4.0 to 5.5 V, PXXCON = VDDUSEB = 1 3.0 3.3 3.6 V UVBUS input voltage characteristic UVBUS Function 4.35 Note (4.02 ) 5.00 5.25 V 4.75 5.00 5.25 V MIN. TYP. MAX. Unit 0.8 V Host Note Value of instantaneous voltage (TA = -40 to +85C, 3.0 V UVDD 3.6 V, 3.0 V VDD 5.5 V, VSS = 0 V) Parameter UDPi/UDMi pins input characteristic (FS/LS receiver) UDPi/UDMi pins output characteristic (FS driver) Symbol Input voltage Conditions 2.0 VIH | UDP voltage - UDM voltage | Difference input sensitivity VDI Difference common mode range VCM Output voltage VOH IOH = -200 A VOL IOL = 2.4 mA tFR Rising: From 10% to 90 % of amplitude, Falling: From 90% to 10 % of amplitude, CL = 50 pF Transi-ti Rising on time Falling Matching (TFR/TFF) tFF VFRFM Crossover voltage VFCRS UDPi/UDMi pins output characteristic (LS driver) Output Impedance ZDRV Output voltage VOH Transi-ti Rising on time Falling tLR tLF VLTFM Crossover voltage VLCRS Note UVBUS UVDD voltage = 3.3 V, Pin voltage = 1.65 V VOL Matching Note (TFR/TFF) UDPi/UDMi pins pull-up, pull-down V VIL Rising: From 10% to 90 % of amplitude, Falling: From 90% to 10 % of amplitude, CL = 200 to 600 pF When the host controller function is selected: The UDMi pin (i = 0, 1) is pulled up via 1.5 k. When the function controller function is selected: The UDP0 and UDM0 pins are individually pulled down via 15 k Pull-down resistor RPD Pull-up resistor (i = 0 only) Idle RPUI Recep-t RPUA ion UVBUS pull-down resistor RVBUS UVBUS input voltage VIH 0.2 0.8 2.5 V 2.8 3.6 V 0 0.3 V 4 20 ns 4 20 ns 90 111.1 % 1.3 2.0 V 28 44 2.8 3.6 V 0 0.3 V 75 300 ns 75 300 ns 80 125 % 1.3 2.0 V 14.25 24.80 k 0.9 1.575 k 1.425 3.09 k UVBUS voltage = 5.5 V VIL V 1000 k 3.20 V 0.8 V Note Excludes the first signal transition from the idle state. Remark i = 0, 1 R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 62 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C Timing of UDPi and UDMi UDPi 90 % 90 % VCRS (Crossover voltage) 10 % 10 % UDMi tR tF (2) BC standard (TA = -40 to +85C, 3.0 V UVDD 3.6 V, 3.0 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit USB UDPi sink current IDP_SINK 25 175 A standard UDMi sink current IDM_SINK 25 175 A DCD source current IDP_SRC 7 13 A Dedicated charging RDCP_DAT 200 0.25 0.4 V BC1.2 0 V < UDP/UDM voltage < 1.0 V port resistor Data detection voltage VDAT_REF UDPi source voltage VDP_SRC Output current 250 A 0.5 0.7 V UDMi source voltage VDM_SRC Output current 250 A 0.5 0.7 V Remark i = 0, 1 R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 63 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (3) BC option standard (Host) (TA = -40 to +85C, 4.75 V UVBUS 5.25 V, 3.0 V UVDD 3.6 V, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit UDPi output VDSELi 1000 VP20 38 40 42 % UVBUS voltage [3:0] 1001 VP27 51.6 53.6 55.6 % UVBUS 1010 VP20 38 40 42 % UVBUS 1100 VP33 60 66 72 % UVBUS (UVBUS divider (i = 0, 1) ratio) * VDOUEi = 1 UDMi output VDSELi 1000 VM20 38 40 42 % UVBUS voltage [3:0] 1001 VM20 38 40 42 % UVBUS 1010 VM27 51.6 53.6 55.6 % UVBUS 1100 VM33 60 66 72 % UVBUS 1000 VHDETP_UP0 (UVBUS divider (i = 0, 1) ratio) * VDOUEi = 1 UDPi VDSELi comparing Note 1 voltage [3:0] (i = 0, 1) (UVBUS divider The rise of pin voltage detection voltage 56.2 VHDETP_DWN0 The fall of pin voltage detection voltage 1001 VHDETP_UP1 1010 VHDETP_UP2 The rise of pin voltage detection voltage 29.4 60.5 VHDETP_DWN1 The fall of pin voltage detection voltage ratio) * VDOUEi = 1 The rise of pin voltage detection voltage UDMi VDSELi comparing Note 1 voltage [3:0] (i = 0, 1) (UVBUS divider 1000 VHDETM_UP0 The rise of pin voltage detection voltage 45.0 1001 VHDETM_UP1 The rise of pin voltage detection voltage 56.2 * VDOUEi = 1 1010 56.2 Note 2 Connect detection with the full speed function The rise of pin voltage detection voltage 1000 RHDET_PULL 60.5 In full-speed mode, the power supply % UVBUS % UVBUS 29.4 VHDETM_DWN2 The fall of pin voltage detection voltage * CUSDETEi = 1 UDPi pull-up detection VHDETM_UP2 % UVBUS % UVBUS 29.4 VHDETM_DWN1 The fall of pin voltage detection voltage ratio) % UVBUS % UVBUS 29.4 VHDETM_DWN0 The fall of pin voltage detection voltage % UVBUS % UVBUS 56.2 VHDETP_DWN2 The fall of pin voltage detection voltage * CUSDETEi = 1 % UVBUS % UVBUS % UVBUS 45.0 % UVBUS 1.575 k 1.575 k voltage range of pull-up resistors 1001 connected to the USB function 1010 module is between 3.0 V and 3.6 V. (pull-up resistor) UDMi pull-up detection Note 2 Connect detection with the low-speed (pull-up 1000 RHDET_PULL In low-speed mode, the power supply voltage range of pull-up resistors 1001 connected to the USB function 1010 module is between 3.0 V and 3.6 V. resistor) UDMi sink current Note 2 detection Connect detection with the BC1.2 portable 1000 IHDET_SINK 25 A 1001 1010 device (sink resistor) Notes 1. If the voltage output from UDPi or UDMi (i = 0, 1) exceeds the range of the MAX and MIN values prescribed in this specification, DPCUSDETi (bit 8) and DMCUSDETi (bit 9) of the USBBCOPTi register are set to 1. 2. If the pull-up resistance or sink current prescribed in this specification is applied to UDPi or UDMi (i = 0, 1), DPCUSDETi (bit 8) and DMCUSDETi (bit 9) of the USBBCOPTi register are set to 1. Remark i = 0, 1 R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 64 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (4) BC option standard (Function) (TA = -40 to +85C, 4.35 V UVBUS 5.25 V, 3.0 V UVDD 3.6 V, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit UDPi/UDMi VDSELi 0000 VDDET0 27 32 37 % UVBUS input [3:0] reference (i = 0) 0001 VDDET1 29 34 39 % UVBUS 0010 VDDET2 32 37 42 % UVBUS (UVBUS divider 0011 VDDET3 35 40 45 % UVBUS ratio) 0100 VDDET4 38 43 48 % UVBUS * VDOUEi = 0 0101 VDDET5 41 46 51 % UVBUS 0110 VDDET6 44 49 54 % UVBUS 0111 VDDET7 47 52 57 % UVBUS 1000 VDDET8 51 56 61 % UVBUS 1001 VDDET9 55 60 65 % UVBUS 1010 VDDET10 59 64 69 % UVBUS 1011 VDDET11 63 68 73 % UVBUS 1100 VDDET12 67 72 77 % UVBUS 1101 VDDET13 71 76 81 % UVBUS 1110 VDDET14 75 80 85 % UVBUS 1111 VDDET15 79 84 89 % UVBUS voltage (i = 0)) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 65 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2.6 Analog Characteristics 2.6.1 A/D converter characteristics Classification of A/D converter characteristics Input channel Reference Voltage Reference voltage (+) = Reference voltage (+) = AVREFP VBGR Reference voltage (-) = Reference voltage (+) = VDD Reference voltage (-) = AVREFM Reference voltage (-) = VSS AVREFM ANI0 to ANI7 Refer to 2.6.1 (1). ANI16, ANI17, ANI19 Refer to 2.6.1 (2). Internal reference voltage Refer to 2.6.1 (1). Refer to 2.6.1 (3). Refer to 2.6.1 (4). - Temperature sensor output voltage (1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI2 to ANI7, internal reference voltage, and temperature sensor output voltage (TA = -40 to +85C, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Resolution Conditions RES Note 1 Overall error AINL tCONV TYP. 8 10-bit resolution AVREFP = VDD Conversion time MIN. 2.4 V VDD 5.5 V 1.2 MAX. Unit 10 bit 3.5 LSB Note 3 10-bit resolution Target pin: ANI2 to ANI7 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 2.4 V VDD 5.5 V 17 39 s 10-bit resolution 3.6 V VDD 5.5 V 2.375 39 s Target pin: Internal 2.7 V VDD 5.5 V 3.5625 39 s 2.4 V VDD 5.5 V 17 39 s reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) Notes 1, 2 Zero-scale error Notes 1, 2 Full-scale error Integral linearity error Note 1 EZS 10-bit resolution Note 3 AVREFP = VDD 2.4 V VDD 5.5 V 0.25 %FSR EFS 10-bit resolution Note 3 AVREFP = VDD 2.4 V VDD 5.5 V 0.25 %FSR ILE 10-bit resolution 2.4 V VDD 5.5 V 2.5 LSB 2.4 V VDD 5.5 V 1.5 LSB AVREFP V AVREFP = VDD Differential linearity error Note 1 DLE 10-bit resolution AVREFP = VDD Analog input voltage VAIN Note 3 Note 3 ANI2 to ANI7 0 Note 4 Internal reference voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode) VBGR Temperature sensor output voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode) VTMPS25 Note 4 V V (Notes are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 66 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD. 4. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 67 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI16, ANI17, ANI19 (TA = -40 to +85C, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Resolution Conditions RES Note 1 Overall error AINL tCONV 10-bit resolution Notes 1, 2 Notes 1, 2 Full-scale error Integral linearity error Note 1 Note 1 10 bit 5.0 LSB 3.6 V VDD 5.5 V 2.125 39 s Target ANI pin : 2.7 V VDD 5.5 V 3.1875 39 s 2.4 V VDD 5.5 V 17 39 s EZS 10-bit resolution Note 3 AVREFP = VDD 2.4 V VDD 5.5 V 0.35 %FSR EFS 10-bit resolution Note 3 AVREFP = VDD 2.4 V VDD 5.5 V 0.35 %FSR ILE 10-bit resolution 2.4 V VDD 5.5 V 3.5 LSB 2.4 V VDD 5.5 V 2.00 LSB AVREFP V DLE VAIN Note 3 10-bit resolution AVREFP = VDD Analog input voltage 1.2 Unit 10-bit resolution AVREFP = VDD Differential linearity error 2.4 V VDD 5.5 V MAX. Note 3 ANI16, ANI17, ANI19 Zero-scale error TYP. 8 AVREFP = VDD Conversion time MIN. Note 3 ANI16, ANI17, ANI19 0 and VDD Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add 4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 2.0 LSB to the MAX. value when AVREFP = VDD. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 68 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (3) Reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), Reference voltage (-) = VSS (ADREFM = 0), target ANI pin : ANI0 to ANI7, ANI16, ANI17, ANI19, internal reference voltage, and temperature sensor output voltage (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (-) = VSS) Parameter Symbol Resolution Conditions RES Notes 1, 2 MIN. TYP. 8 MAX. Unit 10 bit 7.0 LSB Overall error AINL 10-bit resolution 2.4 V VDD 5.5 V Conversion time tCONV 10-bit resolution 3.6 V VDD 5.5 V 2.125 39 s Target ANI pin : 2.7 V VDD 5.5 V 3.1875 39 s ANI17, ANI19 2.4 V VDD 5.5 V 17 39 s 10-bit resolution 3.6 V VDD 5.5 V 2.375 39 s Target ANI pin : Internal 2.7 V VDD 5.5 V 3.5625 39 s 2.4 V VDD 5.5 V 17 39 s ANI0 to ANI7, ANI16, reference voltage, and temperature sensor 1.2 output voltage (HS (high-speed main) mode) Notes 1, 2 Zero-scale error Notes 1, 2 Full-scale error Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage EZS 10-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR EFS 10-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR ILE 10-bit resolution 2.4 V VDD 5.5 V 4.0 LSB DLE 10-bit resolution 2.4 V VDD 5.5 V 2.0 LSB VAIN ANI0 to ANI7, ANI16, ANI17, ANI19 VDD V Internal reference voltage 0 VBGR Note 3 V (2.4 V VDD 5.5 V, HS (high-speed main) mode) Temperature sensor output voltage VTMPS25 Note 3 V (2.4 V VDD 5.5 V, HS (high-speed main) mode) Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 69 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C (4) When Reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), Reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0 to ANI7, ANI16, ANI17, ANI19 (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VBGR AVREFM Note 4 Note 3 , Reference voltage (-) = = 0 V, HS (high-speed main) mode) Parameter Symbol Resolution Conditions MIN. TYP. RES Conversion time Notes 1, 2 Zero-scale error Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage MAX. 8 Unit Bit 39 s 2.4 V VDD 5.5 V 0.60 %FSR 8-bit resolution 2.4 V VDD 5.5 V 2.0 LSB 8-bit resolution 2.4 V VDD 5.5 V 1.0 LSB tCONV 8-bit resolution 2.4 V VDD 5.5 V EZS 8-bit resolution ILE DLE VAIN 17 0 VBGR Note 3 V Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics. 4. When reference voltage (-) = VSS, the MAX. values are as follows. Zero-scale error: Add 0.35%FSR to the MAX. value when reference voltage (-) = AVREFM. Integral linearity error: Add 0.5 LSB to the MAX. value when reference voltage (-) = AVREFM. Differential linearity error: Add 0.2 LSB to the MAX. value when reference voltage (-) = AVREFM. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 70 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2.6.2 Temperature sensor/internal reference voltage characteristics (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25C Internal reference voltage VBGR Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the TYP. MAX. 1.05 1.38 Unit V 1.45 1.5 -3.6 V mV/C temperature Operation stabilization wait time 2.6.3 tAMP s 5 POR circuit characteristics (TA = -40 to +85C, VSS = 0 V) Parameter Detection voltage Minimum pulse width Note Symbol Conditions MIN. TYP. MAX. Unit VPOR Power supply rise time 1.47 1.51 1.55 V VPDR Power supply fall time 1.46 1.50 1.54 V TPW s 300 Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock (fMAIN) is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW Supply voltage (VDD) VPOR VPDR or 0.7 V R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 71 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2.6.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = -40 to +85C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Detection Supply voltage level Symbol VLVD0 voltage VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VLVD8 Minimum pulse width tLW Detection delay time tLD R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Conditions MIN. TYP. MAX. Unit Power supply rise time 3.98 4.06 4.14 V Power supply fall time 3.90 3.98 4.06 V Power supply rise time 3.68 3.75 3.82 V Power supply fall time 3.60 3.67 3.74 V Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.02 V Power supply rise time 2.86 2.92 2.97 V Power supply fall time 2.80 2.86 2.91 V Power supply rise time 2.76 2.81 2.87 V Power supply fall time 2.70 2.75 2.81 V Power supply rise time 2.66 2.71 2.76 V Power supply fall time 2.60 2.65 2.70 V Power supply rise time 2.56 2.61 2.66 V Power supply fall time 2.50 2.55 2.60 V Power supply rise time 2.45 2.50 2.55 V Power supply fall time 2.40 2.45 2.50 V s 300 300 s Page 72 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +85C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Symbol Interrupt and reset VLVDC0 mode Conditions MIN. TYP. MAX. Unit VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 V 2.56 2.61 2.66 V 2.50 2.55 2.60 V 2.66 2.71 2.76 V 2.60 2.65 2.70 V 3.68 3.75 3.82 V 3.60 3.67 3.74 V 2.70 2.75 2.81 V 2.86 2.92 2.97 V 2.80 2.86 2.91 V 2.96 3.02 3.08 V VLVDC1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage LVIS1, LVIS0 = 0, 1 Rising release reset voltage VLVDC2 Falling interrupt voltage LVIS1, LVIS0 = 0, 0 Rising release reset voltage VLVDC3 Falling interrupt voltage VLVDD0 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage VLVDD1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage VLVDD2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage Falling interrupt voltage VLVDD3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage Falling interrupt voltage 2.6.5 2.90 2.96 3.02 V 3.98 4.06 4.14 V 3.90 3.98 4.06 V Power supply voltage rising slope characteristics (TA = -40 to +85C, VSS = 0 V) Parameter Power supply voltage rising slope Caution Symbol Conditions MIN. SVDD TYP. MAX. Unit 54 V/ms Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 30.4 R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 AC Characteristics. Page 73 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2.7 <R> RAM Data Retention Characteristics (TA = -40 to +85C, VSS = 0 V) Parameter Data retention supply voltage Symbol Conditions VDDDR MIN. 1.46 TYP. Note MAX. Unit 5.5 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected. Operation mode STOP mode RAM data retention <R> VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 2.8 Flash Memory Programming Characteristics (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter CPU/peripheral hardware clock Symbol Conditions fCLK 2.4 V VDD 5.5 V Cerwr Retaining years: 20 years MIN. TYP. 1 MAX. Unit 24 MHz frequency <R> Number of code flash rewrites 1,000 Times TA = +85C <R> Number of data flash rewrites Retaining years: 1 year 1,000,000 TA = +25C Notes 1, 2, 3 <R> Retaining years: 5 years 100,000 TA = +85C <R> Retaining years: 20 years 10,000 TA = +85C Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library. 3. These specifications show the characteristics of the flash memory and the results obtained from Renesas Electronics reliability testing. 2.9 Dedicated Flash Memory Programmer Communication (UART) (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Transfer rate R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Symbol Conditions During serial programming MIN. 115,200 TYP. MAX. Unit 1,000,000 bps Page 74 of 134 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85C) RL78/G1C 2.10 Timing Specs for Switching Flash Memory Programming Modes (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol How long from when an external tSUINIT Conditions MIN. POR and LVD reset must end before the TYP. MAX. Unit 100 ms external reset ends. reset ends until the initial communication settings are specified How long from when the TOOL0 tSU POR and LVD reset must end before the 10 s 1 ms external reset ends. pin is placed at the low level until an external reset ends How long the TOOL0 pin must be tHD POR and LVD reset must end before the external reset ends. kept at the low level after an external reset ends (excluding the processing time of the firmware to control the flash memory) <1> <2> <4> <3> RESET 723 s + tHD processing time 00H reception (TOOLRxD, TOOLTxD mode) TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset ends (POR and LVD reset must end before the external reset ends.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. tSU: How long from when the TOOL0 pin is placed at the low level until an external reset ends tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end (excluding the processing time of the firmware to control the flash memory) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 75 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) This chapter describes the electrical specifications for the products "G: Industrial applications (TA = -40 to +105C)". The target products G: Industrial applications ; TA = -40 to +105C R5F10JBCGNA, R5F10JBCGFP, R5F10JGCGNA, R5F10JGCGFB, R5F10KBCGNA, R5F10KBCGFP, R5F10KGCGNA, R5F10KGCGFB Cautions 1. The RL78 microcontrollers has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. The pins mounted depend on the product. 3. Please contact Renesas Electronics sales office for derating of operation under TA = +85C to +105C. Derating is the systematic reduction of load for the sake of improved reliability. There are following differences between the products "G: Industrial applications (TA = -40 to +105C)" and the products "A: Consumer applications". Parameter Application A: Consumer applications Operating ambient temperature TA = -40 to +85C G: Industrial applications TA = -40 to +105C High-speed on-chip oscillator clock 2.4 V VDD 5.5 V 2.4 V VDD 5.5 V accuracy 1.0%@ TA = -20 to +85C 2.0%@ TA = +85 to +105C 1.5%@ TA = -40 to -20C 1.0%@ TA = -20 to +85C 1.5%@ TA = -40 to -20C Serial array unit UART UART CSI: fCLK/2 (supporting 16 Mbps), fCLK/4 2 IICA CSI: fCLK/4 2 Simplified I C communication Simplified I C communication Normal mode Normal mode Fast mode Fast mode Fast mode plus Remark The electrical characteristics of the products G: Industrial applications (TA = -40 to +105C) are different from those of the products "A: Consumer applications". For details, refer to 3.1 to 3.10. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 76 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbols Conditions VDD REGC pin input voltage VIREGC Ratings Unit -0.5 to +6.5 V -0.3 to +2.8 REGC V and -0.3 to VDD +0.3 UVDD pin input voltage Input voltage VIUVDD VI1 Note 1 -0.3 to VDD +0.3 UVDD -0.3 to VDD +0.3 P00, P01, P14 to P17, P20 to P27, P30, P31, P40, V Note 2 V P41, P50, P51, P70 to P75, P120 to P124, P137, P140, EXCLK, EXCLKS, RESET Output voltage VI2 P60 to P63 (N-ch open-drain) -0.3 to +6.5 V VI3 UDP0, UDM0, UDP1, UDM1 -0.3 to +6.5 V VI4 UVBUS -0.3 to +6.5 VO1 -0.3 to VDD +0.3 P00, P01, P14 to P17, P20 to P27, P30, P31, P40, V Note 2 V P41, P50, P51, P60 to P63, P70 to P75, P120, P130, P140 Analog input voltage VO2 UDP0, UDM0, UDP1, UDM1 VAI1 ANI16, ANI17, ANI19 -0.3 to +6.5 V -0.3 to VDD +0.3 V and -0.3 to AVREF (+) +0.3 Notes 2, 3 VAI2 -0.3 to VDD +0.3 ANI0 to ANI7 V and -0.3 to AVREF (+) +0.3 Notes 2, 3 Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). maximum rating of the REGC pin. 2. 3. This value regulates the absolute Do not use this pin with voltage applied to it. Must be 6.5 V or lower. Do not exceed AV REF (+) + 0.3 V in case of A/D conversion target pin Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. AVREF (+) : The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal reference voltage (1.45 V), and VDD. 3. VSS : Reference voltage R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 77 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, high Symbols IOH1 Conditions Per pin P00, P01, P14 to P17, P30, P31, Ratings Unit -40 mA -70 mA -100 mA -0.5 mA -2 mA 40 mA 70 mA 100 mA 1 mA 5 mA -40 to +105 C -65 to +150 C P40, P41, P50, P51, P70 to P75, P120, P130, P140 Total of all pins P00, P01, P40, P41, P120, -170 mA P130, P140 P14 to P17, P30, P31, P50, P51, P70 to P75 IOH2 Per pin P20 to P27 Total of all pins Output current, low IOL1 Per pin P00, P01, P14 to P17, P30, P31, P40, P41, P50, P51, P60 to P63, P70 to P75, P120, P130, P140 Total of all pins P00, P01, P40, P41, P120, 170 mA P130, P140 P14 to P17, P30, P31, P50, P51, P60 to P63, P70 to P75 IOL2 Per pin P20 to P27 Total of all pins Operating ambient TA temperature Storage temperature In normal operation mode In flash memory programming mode Tstg Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 78 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3.2 Oscillator Characteristics 3.2.1 X1, XT1 oscillator characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Resonator X1 clock oscillation Note frequency (fX) XT1 clock oscillation Conditions MIN. TYP. MAX. Unit Ceramic resonator/ 2.7 V VDD 5.5 V 1.0 20.0 MHz crystal resonator 2.4 V VDD < 2.7 V 1.0 16.0 MHz 35 kHz Crystal resonator 32 32.768 Note frequency (fXT) Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. 3.2.2 On-chip oscillator characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Oscillators High-speed on-chip oscillator clock frequency Parameters Conditions fHOCO MIN. TYP. MAX. Unit 1 48 MHz Notes 1, 2 High-speed on-chip oscillator -20 to +85 C -1.0 +1.0 % clock frequency accuracy -40 to -20 C -1.5 +1.5 % +85 to +105 C -2.0 +2.0 % Low-speed on-chip oscillator fIL 15 kHz clock frequency Low-speed on-chip oscillator -15 +15 % clock frequency accuracy Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and bits 0 to 2 of HOCODIV register. 2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution time. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 79 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3.2.3 PLL oscillator characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Oscillators PLL input frequency Parameters Note PLL output frequency Note fPLLIN Conditions High-speed system clock MIN. 6.00 fPLL Lock up time TYP. MAX. Unit 16.00 MHz 48.00 From PLL output enable to stabilization of the MHz 40.00 s 4.00 s 1.00 s output frequency Interval time From PLL stop to PLL re-operation setteing Wait time Setting wait time From after PLL input clock stabilization and PLL setting is fixed to start setting Wait time required Note Indicates only oscillator characteristics. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Refer to AC Characteristics for instruction execution time. Page 80 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3.3 DC Characteristics 3.3.1 Pin characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Items Symbol Output current, high Conditions Per pin for P00, P01, P14 to P17, IOH1 Note 1 MIN. TYP. 2.4 V VDD 5.5 V P30, P31, P40, P41, P50, P51, P70 to MAX. -3.0 Note Unit mA 2 P75, P120, P130, P140 Total of P00, P01, P40, P41, P120, 4.0 V VDD 5.5 V -30.0 mA P130, P140 2.7 V VDD < 4.0 V -10.0 mA 2.4 V VDD < 2.7 V -5.0 mA Total of P14 to P17, P30, P31, 4.0 V VDD 5.5 V -30.0 mA P50, P51, P70 to P75 2.7 V VDD < 4.0 V -19.0 mA 2.4 V VDD < 2.7 V -10.0 mA 2.4 V VDD 5.5 V -60.0 mA (When duty 70% (When duty 70% Note 3 Note 3 ) ) Total of all pins Note 3 (When duty 70% IOH2 ) 2.4 V VDD 5.5 V Per pin for P20 to P27 2.4 V VDD 5.5 V Total of all pins Note 3 (When duty 70% Notes 1. -0.1 Note mA 2 -1.5 mA ) Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin. 2. 3. However, do not exceed the total current value. Specification under conditions where the duty factor 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty ratio to n%). * Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where n = 80% and IOH = -10.0 mA Total output current of pins = (-10.0 x 0.7)/(80 x 0.01) -8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P00, P01, P30, and P74 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 81 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Items Symbol Output current, Conditions TYP. MAX. Note 2 Unit 2.4V VDD 5.5 V 8.5 Per pin for P60 to P63 2.4V VDD 5.5 V 15.0 Total of P00, P01, P40, P41, P120, 4.0 V VDD 5.5 V 40.0 P130, P140 2.7 V VDD < 4.0 V 15.0 mA 2.4 V VDD < 2.7 V 9.0 mA Total of P14 to P17, P30, P31, P50, 4.0 V VDD 5.5 V 40.0 mA P51, P60 to P63, P70 to P75 2.7 V VDD < 4.0 V 35.0 mA 2.4 V VDD < 2.7 V 20.0 mA 2.4V VDD 5.5 V 80.0 mA Per pin for P00, P01, P14 to P17, IOL1 Note 1 MIN. mA P30, P31, P40, P41, P50, P51, low P70 to P75, P120, P130, P140 (When duty 70% (When duty 70% Note 3 Note 3 ) ) Total of all pins (When duty 70% IOL2 Note 3 2.4V VDD 5.5 V 2.4V VDD 5.5 V Total of all pins Note 3 Notes 1. mA mA ) Per pin for P20 to P27 (When duty 70% Note 2 0.4 Note 2 5.0 mA mA ) Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin. 2. 3. However, do not exceed the total current value. Specification under conditions where the duty factor 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty ratio to n%). * Total output current of pins = (IOL x 0.7)/(n x 0.01) <Example> Where n = 80% and IOL = 10.0 mA Total output current of pins = (10.0 x 0.7)/(80 x 0.01) 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 82 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Items Input voltage, Symbol VIH1 Conditions P00, P01, P14 to P17, MIN. Normal input buffer TYP. MAX. Unit 0.8VDD VDD V 2.2 VDD V 2.0 VDD V 1.5 VDD V P30, P31, P40, P41, P50, P51, P70 high to P75, P120, P140 VIH2 P00, P01, P30, P50 TTL input buffer 4.0 V VDD 5.5 V TTL input buffer 3.3 V VDD < 4.0 V TTL input buffer 2.4 V VDD < 3.3 V Input voltage, VIH3 P20 to P27 0.7VDD VDD V VIH4 P60 to P63 0.7VDD 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD VDD V VIL1 P00, P01, P14 to P17, P30, P31, Normal input buffer 0 0.2VDD V TTL input buffer 0 0.8 V 0 0.5 V 0 0.32 V P40, P41, P50, P51, P70 to P75, low P120, P140 VIL2 P00, P01, P30, P50 4.0 V VDD 5.5 V TTL input buffer 3.3 V VDD < 4.0 V TTL input buffer 2.4 V VDD < 3.3 V VIL3 P20 to P27 0 0.3VDD V VIL4 P60 to P63 0 0.3VDD V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2VDD V Caution The maximum value of VIH of pins P00, P01, P30, and P74 is VDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 83 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Items Symbol Output voltage, VOH1 high Conditions MIN. P00, P01, P14 to P17, P30, P31, 4.0 V VDD 5.5 V, P40, P41, P50, P51, P70 to P75, IOH1 = -3.0 mA P120, P130, P140 2.7 V VDD 5.5 V, TYP. MAX. Unit VDD - 0.7 V VDD - 0.6 V VDD - 0.5 V VDD - 0.5 V IOH1 = -2.0 mA 2.4 V VDD 5.5 V, IOH1 = -1.5 mA VOH2 P20 to P27 2.4 V VDD 5.5 V, IOH2 = -100 A Output voltage, VOL1 low P00, P01, P14 to P17, P30, P31, 4.0 V VDD 5.5 V, P40, P41, P50, P51, P70 to P75, IOL1 = 8.5 mA P120, P130, P140 2.7 V VDD 5.5 V, 0.7 V 0.6 V 0.4 V 0.4 V 0.4 V 2.0 V 0.4 V 0.4 V 0.4 V IOL1 = 3.0 mA 2.7 V VDD 5.5 V, IOL1 = 1.5 mA 2.4 V VDD 5.5 V, IOL1 = 0.6 mA VOL2 P20 to P27 2.4 V VDD 5.5 V, IOL2 = 400 A VOL3 P60 to P63 4.0 V VDD 5.5 V, IOL1 = 15.0 mA 4.0 V VDD 5.5 V, IOL1 = 5.0 mA 2.7 V VDD 5.5 V, IOL1 = 3.0 mA 2.4 V VDD 5.5 V, IOL1 = 2.0 mA Caution P00, P01, P30, and P74 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 84 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Items Input leakage Symbol ILIH1 Conditions P00, P01, P14 to P17, MIN. TYP. VI = VDD MAX. Unit 1 A 1 A 10 A -1 A -1 A -10 A 100 k P20 to P27, P30, P31, current, high P40, P41, P50, P51, P60 to P63, P70 to P75, P120, P137, P140, RESET ILIH2 P121 to P124 VI = VDD In input port (X1, X2, XT1, XT2, EXCLK, or external EXCLKS) clock input In resonator connection Input leakage ILIL1 P00, P01, P14 to P17, VI = VSS P20 to P27, P30, P31, P40, current, low P41, P50, P51, P60 to P63, P70 to P75, P120, P137, P140, RESET ILIL2 P121 to P124 VI = VSS In input port (X1, X2, XT1, XT2, EXCLK, or external EXCLKS) clock input In resonator connection On-chip pll-up RU P00, P01, P14 to P17, VI = VSS, In input port 10 20 P30, P31, P40, P41, resistance P50, P51, P70 to P75, P120, P140 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 85 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3.3.2 Supply current characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Supply current IDD1 Note 1 (1/2) Conditions Operating mode MIN. fHOCO = 48 MHz HS (High-speed fIH = 24 MHz Note 3 main) Note 6 modffe fHOCO = 24 MHz fIH = 12 MHz Note 3 fHOCO = 12 MHz fIH = 6 MHz Note 5 Note 5 Note 3 Note fHOCO = 6 MHz 5 fIH = 3 MHz Note 2 VDD = 3.0 V fMX = 10 MHz Note 2 , VDD = 5.0 V fMX = 10 MHz Note 2 , VDD = 3.0 V HS (High-speed main) mode (PLL operation) Note 6 fPLL = 48 MHz, fCLK = 24 MHz fPLL = 48 MHz, fCLK = 12 MHz Note 2 fPLL = 48 MHz, fCLK = 6 MHz Subsystem clock operation Note 2 Note 2 fSUB = 32.768 kHz Note 4 MAX. 1.7 mA VDD = 3.0 V 1.7 Normal operation VDD = 5.0 V 3.7 5.8 mA VDD = 3.0 V 3.7 5.8 mA Normal operation VDD = 5.0 V 2.3 3.4 mA VDD = 3.0 V 2.3 3.4 mA Normal operation VDD = 5.0 V 1.6 2.2 mA VDD = 3.0 V 1.6 2.2 mA Normal operation VDD = 5.0 V 1.2 1.6 mA VDD = 3.0 V 1.2 1.6 mA Normal operation Square wave input 3.0 4.9 mA Resonator connection 3.2 5.0 mA Normal operation Square wave input 3.0 4.9 mA Resonator connection 3.2 5.0 mA Normal operation Square wave input 1.9 2.9 mA Resonator connection 1.9 2.9 mA Normal operation Square wave input 1.9 2.9 mA Resonator connection 1.9 2.9 mA Normal operation VDD = 5.0 V 4.0 6.3 mA VDD = 3.0 V 4.0 6.3 mA Normal operation VDD = 5.0 V 2.6 3.9 mA VDD = 3.0 V 2.6 3.9 mA Normal operation VDD = 5.0 V 1.9 2.7 mA VDD = 3.0 V 1.9 2.7 mA Normal operation Resonator connection 4.1 4.9 A Square wave input 4.2 5.0 A Normal operation Square wave input 4.1 4.9 A Resonator connection 4.2 5.0 A Normal operation Square wave input 4.2 5.5 A Resonator connection 4.3 5.6 A Normal operation Square wave input 4.2 6.3 A Resonator connection 4.3 6.4 A Normal operation Square wave input 4.8 7.7 A Resonator connection 4.9 7.8 A Normal operation Square wave input 6.9 19.7 A Resonator connection 7.0 19.8 A mA TA = -40C f = 32.768 kHz SUB Note 4 TA = +25C fSUB = 32.768 kHz Note 4 Unit VDD = 5.0 V Note 3 HS fMX = 20 MHz , (High-speed VDD = 5.0 V main) mode Note 2 Note 6 fMX = 20 MHz , TYP. Basic operation TA = +50C fSUB = 32.768 kHz Note 4 TA = +70C fSUB = 32.768 kHz Note 4 TA = +85C fSUB = 32.768 kHz Note 4 TA = +105C (Notes and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 86 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 5. When Operating frequency setting of option byte = 48 MHz. When fHOCO is divided by HOCODIV. When RDIV[1:0] = 00 (divided by 2: default). 6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 24 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz Remarks 1. fHOCO: High-speed on-chip oscillator clock frequency (Max. 48 MHz) 2. fIH: Main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock by 2, 4, or 8 (Max. 24 MHz) 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 4. fPLL: PLL oscillation frequency 5. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 6. fCLK: CPU/peripheral hardware clock frequency 7. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 87 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol (2/2) Conditions MIN. fHOCO = 48 MHz Supply IDD2 HALT HS current Note 2 mode (High-speed fIH = 24 MHz Note 4 main) mode Note 7 fHOCO = 24 MHz Note 9 Note 1 fIH = 12 MHz Note 4 fHOCO = 12 MHz fIH = 6 MHz Note 4 fHOCO = 6 MHz fIH = 3 MHz Note 7 Note 7 Note 4 2.25 mA VDD = 3.0 V 0.67 2.25 mA VDD = 5.0 V 0.50 1.55 mA VDD = 3.0 V 0.50 1.55 mA VDD = 5.0 V 0.41 1.21 mA VDD = 3.0 V 0.41 1.21 mA VDD = 5.0 V 0.37 1.05 mA 1.05 mA 1.90 mA Resonator connection 0.45 2.00 mA Square wave input 0.28 1.90 mA Resonator connection 0.45 2.00 mA Square wave input 0.19 1.02 mA Resonator connection 0.26 1.10 mA Square wave input 0.19 1.02 mA VDD = 3.0 V Resonator connection 0.26 1.10 mA fPLL = 48 MHz, VDD = 5.0 V 0.91 2.74 mA VDD = 3.0 V 0.91 2.74 mA VDD = 5.0 V 0.85 2.31 mA VDD = 3.0 V 0.85 2.31 mA VDD = 5.0 V 0.82 2.07 mA VDD = 3.0 V 0.82 2.07 mA Square wave input 0.25 0.57 A Resonator connection 0.44 0.76 A Square wave input 0.30 0.57 A Resonator connection 0.49 0.76 A Square wave input 0.33 1.17 A Resonator connection 0.63 1.36 A Square wave input 0.46 1.97 A Resonator connection 0.76 2.16 A Square wave input 0.97 3.37 A Resonator connection 1.16 3.56 A Square wave input 3.01 15.37 A Resonator connection 3.20 15.56 A TA = -40C 0.18 0.50 A TA = +25C 0.23 0.50 A TA = +50C 0.26 1.10 A TA = +70C 0.29 1.90 A TA = +85C 0.90 3.30 A TA = +105C 2.94 15.30 A , Note 3 , VDD = 5.0 V fMX = 10 MHz HS Note 3 (High-speed fCLK = 24 MHz main) mode (PLL operation) Note 9 Subsystem clock operation , Note 3 fPLL = 48 MHz, fCLK = 12 MHz Note 3 fPLL = 48 MHz, fCLK = 6 MHz Note 3 fSUB = 32.768 kHz Note 5 TA = -40C fSUB = 32.768 kHz Note 5 TA = +25C fSUB = 32.768 kHz Note 5 TA = +50C fSUB = 32.768 kHz Note 5 TA = +70C fSUB = 32.768 kHz Note 5 TA = +85C fSUB = 32.768 kHz TA = +105C Note 8 0.67 0.37 fMX = 10 MHz mode VDD = 5.0 V 0.28 Note 3 VDD = 3.0 V STOP Unit Square wave input fMX = 20 MHz (High-speed VDD = 5.0 V main) mode Note 3 fMX = 20 MHz , Note 9 I MAX. VDD = 3.0 V HS Note 6 DD3 TYP. Note 5 (Notes and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 88 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, USB2.0 host/function module, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 7. When Operating frequency setting of option byte = 48 MHz. When fHOCO is divided by HOCODIV. When RDIV[1:0] = 00 (divided by 2: default). 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. 9. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 24 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz Remarks 1. fHOCO: High-speed on-chip oscillator clock frequency (Max. 48 MHz) 2. fIH: Main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock by 2, 4, or 8 (Max. 24 MHz) 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 4. fPLL: PLL oscillation frequency 5. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 6. fCLK: CPU/peripheral hardware clock frequency 7. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 89 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) (1/2) Parameter Low-speed on-chip Symbol I Conditions MIN. Note 1 FIL TYP. MAX. Unit 0.20 A 0.02 A 0.02 A 0.22 A oscillator operating current RTC operating current IRTC Notes 1, 2, 3 12-bit interval timer IIT Notes 1, 2, 4 operating current Watchdog timer operating current IWDT A/D converter operating current IADC fIL = 15 kHz Notes 1, 2, 5 Notes 1, 6 When conversion at maximum speed Normal mode, AVREFP = VDD = 5.0 V Low voltage mode, AVREFP = VDD = 3.0 V 1.3 1.8 mA 0.5 0.8 mA Note 75.0 A Note 1 75.0 A Notes 1, 0.08 A Notes 1, 2.00 12.30 mA Notes 1, 2.00 12.30 mA 0.80 1.97 mA 1.20 3.00 mA 0.70 1.56 mA A/D converter reference IADREF 1 voltage current Temperature sensor operating current ITMPS LVD operating current ILVD 7 Self-programming IFSP operating current 9 BGO operating current IBGO 8 SNOOZE operating current ISNOZ Note 1 ADC operation The mode is performed Note 10 The A/D conversion operations are performed, Low voltage mode, AVREFP = VDD = 3.0 V CSI operation (Notes and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 90 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) (2/2) Parameter USB operating current Symbol IUSBH Note 11 IUSBF Note 11 ISUSP Note 12 Conditions MIN. TYP. MAX. Unit During USB communication operation under the following settings and conditions (VDD = 5.0 V, TA = +25C): * The internal power supply for the USB is used. * X1 oscillation frequency (fX) = 12 MHz, PLL oscillation frequency (fPLL) = 48 MHz * The host controller (via two ports) is set to operate in full-speed mode with four pipes (end points) used simultaneously. (PIPE4: Bulk OUT transfer (64 bytes), PIPE5: Bulk IN transfer (64 bytes), PIPE6: Interrupt OUT transfer, PIPE7: Interrupt IN transfer). * The USB ports (two ports) are individually connected to a peripheral function via a 0.5 m USB cable. 9.0 mA During USB communication operation under the following settings and conditions (VDD = 5.0 V, TA = +25C): * The internal power supply for the USB is used. * X1 oscillation frequency (fX) = 12 MHz, PLL oscillation frequency (fPLL) = 48 MHz * The function controller is set to operate in full-speed mode with four pipes (end points) used simultaneously. (PIPE4: Bulk OUT transfer (64 bytes), PIPE5: Bulk IN transfer (64 bytes), PIPE6: Interrupt OUT transfer, PIPE7: Interrupt IN transfer). * The USB port (one port) is connected to the host device via a 0.5 m USB cable. 2.5 mA During suspended state under the following settings and conditions (VDD = 5.0 V, TA = +25C): * The function controller is set to full-speed mode (the UDP0 pin is pulled up). * The internal power supply for the USB is used. * The system is set to STOP mode (When the high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When the watchdog timer is stopped.). * The USB port (one port) is connected to the host device via a 0.5 m USB cable. 240 A (Notes and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 91 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C Notes 1. Current flowing to VDD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock. 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in operation. 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 7. Current flowing only to the LVD circuit. The current value of the RL78/G1C is the sum of IDD1, IDD2 or IDD3 and ILVI when the LVD circuit operates in the Operating, HALT or STOP mode. 8. Current flowing only during data flash rewrite. 9. Current flowing only during self programming. 10. For shift time to the SNOOZE mode. 11. Current consumed only by the USB module and the internal power supply for the USB. 12. Includes the current supplied from the pull-up resistor of the UDP0 pin to the pull-down resistor of the host device, in addition to the current consumed by this MCU during the suspended state. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 3. fCLK: CPU/peripheral hardware clock frequency 4. Temperature condition of the TYP. value is TA = 25C R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 92 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3.4 3.4.1 AC Characteristics Basic operation (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Items Instruction cycle (minimum Symbol TCY instruction execution time) Conditions MIN. MAX. Unit 0.04167 1 s 0.0625 1 s 31.3 s 0.04167 1 s 0.0625 1 s 2.7 V VDD 5.5 V 1.0 20.0 MHz 2.4 V VDD < 2.7 V 1.0 16.0 MHz 32 35 kHz 2.7 V VDD Main HS system (High-speed 5.5 V clock (fMAIN) main) mode 2.4 V VDD < operation 2.7 V Subsystem clock (fSUB) 2.4 V VDD operation 5.5 V In the self TYP. HS 2.7 V VDD 28.5 30.5 programmin (High-speed 5.5 V g mode main) mode 2.4 V VDD < 2.7 V External system clock frequency fEX fEXS External system clock input tEXH, tEXL high-level width, low-level width 2.7 V VDD 5.5 V 24 ns 2.4 V VDD < 2.7 V 30 ns 13.7 s 1/fMCK+10 ns tEXHS, tEXLS TI00 to TI03 input high-level tTIH, width, low-level width tTIL TO00 to TO03 output frequency fTO PCLBUZ0, PCLBUZ1 output fPCL frequency High-speed main 4.0 V VDD 5.5 V 12 MHz mode 2.7 V VDD < 4.0 V 8 MHz 2.4 V VDD < 2.7 V 4 MHz High-speed main 4.0 V VDD 5.5 V 16 MHz mode 2.7 V VDD < 4.0 V 8 MHz 2.4 V VDD < 2.7 V 4 MHz Interrupt input high-level width, tINTH, INTP0 to INTP6, low-level width tINTL INTP8, INTP9 Key interrupt input low-level width tKR RESET low-level width KR0 to KR5 tRSL 2.4 V VDD 5.5 V 1 s 2.4 V VDD 5.5 V 250 ns 10 s Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 3)) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 93 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 10 1.0 Cycle time TCY [s] When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.1 0.0625 0.05 0.04167 0.01 0 1.0 2.0 3.0 2.4 2.7 4.0 5.0 5.5 6.0 Supply voltage VDD [V] AC Timing Test Points VIH/VOH VIL/VOL Test points VIH/VOH VIL/VOL External System Clock Timing 1/fEX/ 1/fEXS tEXL/ tEXLS tEXH/ tEXHS EXCLK/EXCLKS R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 94 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C TI/TO Timing tTIH tTIL TI00 to TI03 1/fTO TO00 to TO03 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP6, INTP8, INTP9 Key Interrupt Input Timing tKR KR0 to KR5 RESET Input Timing tRSL RESET R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 95 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3.5 Peripheral Functions Characteristics 3.5.1 Serial array unit (1) During communication at same potential (UART mode) (dedicated baud rate generator output) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. Transfer rate Theoretical value of the MAX. Unit fMCK/12 bps 2.0 Mbps maximum transfer rate fMCK = fCLK Note Note The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) Rx TxDq User's device RL78 microcontroller Tx RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remarks 1. 2. q: UART number (q = 0), g: PIM and POM number (g = 5) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 96 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol SCKp cycle time tKCY1 SCKp high-/low-level width SIp setup time (to SCKp) Note 1 SIp hold time (from SCKp) Note 2 Delay time from SCKp to SOp output Conditions tKCY1 4/fCLK MIN. TYP. MAX. Unit 2.7 V VDD 5.5 V 250 ns 2.4 V VDD 5.5 V 500 ns tKH1, 4.0 V VDD 5.5 V tKCY1/2 - 24 ns tKL1 2.7 V VDD 5.5 V tKCY1/2 - 36 ns 2.4 V VDD 5.5 V tKCY1/2 - 76 ns 4.0 V VDD 5.5 V 66 ns 2.7 V VDD 5.5 V 66 ns 2.4 V VDD 5.5 V 113 ns 38 ns tSIK1 tKSI1 tKSO1 Note 4 C = 30 pF 50 ns Note 3 Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 0, 3, 5, 7) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 97 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter SCKp cycle time Note 5 Symbol tKCY2 Conditions 4.0 V VDD 5.5 V 2.7 V VDD 5.5 V MIN. TYP. MAX. Unit 20 MHz < fMCK 16/fMCK ns fMCK 20 MHz 12/fMCK ns 16 MHz < fMCK 16/fMCK ns fMCK 16 MHz 12/fMCK ns 12/fMCK ns 2.4 V VDD 5.5 V and 1000 SCKp high-/low-level width tKH2, tKCY2/2 - 4.0 V EVDD0 5.5 V tKL2 ns 14 tKCY2/2 - 2.7 V EVDD0 5.5 V ns 16 tKCY2/2 - 2.4 V VDD 5.5 V ns 36 SIp setup time (to SCKp) tSIK2 Note 1 SIp hold time (from SCKp) tKSI2 Note 2 Delay time from SCKp to SOp output tKSO2 2.7 V VDD 5.5 V 1/fMCK+40 ns 2.4 V VDD 5.5 V 1/fMCK+60 ns 2.7 V VDD 5.5 V 1/fMCK+62 ns 2.4 V VDD 5.5 V 1/fMCK+62 ns C = 30 pF Note 4 Note 3 2.7 V VDD 5.5 V 2/fMCK+66 ns 2.4 V VDD 5.5 V 2/fMCK+113 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM number (g = 0, 3, 5, 7) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 98 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C CSI mode connection diagram (during communication at same potential) SCK SCKp RL78 microcontroller SIp SO User's device SI SOp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 Output data SOp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Remarks 1. 2. Output data p: CSI number (p = 00, 01) m: Unit number, n: Channel number (mn = 00, 01) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 99 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 2 (4) During communication at same potential (simplified I C mode) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter SCLr clock frequency Symbol fSCL Conditions MIN. 2.7 V VDD 5.5 V, MAX. Unit 400 Note 1 kHz 100 Note 1 kHz Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k Hold time when SCLr = "L" tLOW 2.7 V VDD 5.5 V, 1200 ns 4600 ns 1200 ns 4600 ns 1/fMCK + 220 ns 1/fMCK + 580 ns Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k Hold time when SCLr = "H" tHIGH 2.7 V VDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k Data setup time (reception) tSU:DAT 2.7 V VDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k Data hold time (transmission) tHD:DAT 2.7 V VDD 5.5 V, Note 2 Note 2 0 770 ns 0 1420 ns Cb = 50 pF, Rb = 2.7 k 2.4 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k Notes 1. The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). (Caution and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 100 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 2 Simplified I C mode mode connection diagram (during communication at same potential) VDD Rb SDA SDAr User's device RL78 microcontroller SCL SCLr 2 Simplified I C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT tSU:DAT Remarks 1. Rb[]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2. r: IIC number (r = 00, 01), g: PIM number (g = 5), h: POM number (h = 3, 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 101 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (5) Communication at different potential (2.5 V, 3 V) (UART mode) (1/2) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Transfer rate Conditions reception MIN. TYP. 4.0 V VDD 5.5 V, MAX. Unit fMCK/12 bps Note 1 2.7 V Vb 4.0 V Theoretical value of the 2.0 Mbps fMCK/12 bps maximum transfer rate fCLK = 24 MHz, fMCK = fCLK Note 2 2.7 V VDD < 4.0 V, Note 1 2.3 V Vb 2.7 V Theoretical value of the 2.0 Mbps fMCK/12 bps maximum transfer rate fCLK = 24 MHz, fMCK = fCLK Note 2 2.4 V VDD < 3.3 V, Note 1 1.6 V Vb 2.0 V Theoretical value of the 2.0 Mbps maximum transfer rate fCLK = 24 MHz, fMCK = fCLK Note 2 Notes 1. Use it with VDDVb. 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. For VIH and VIL, see the DC characteristics with TTL input buffer selected Vb[V]: Communication line voltage 2. q: UART number (q = 0), g: PIM and POM number (g = 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 102 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (5) Communication at different potential (2.5 V, 3 V) (UART mode) (2/2) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Transfer rate Symbol Conditions MIN. TYP. transmission 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V Theoretical value of the MAX. Unit Note 1 bps 2.6 Note 2 Mbps maximum transfer rate Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V 2.7 V VDD < 4.0 V, Note 3 2.3 V Vb 2.7 V Theoretical value of the 1.2 Note 4 bps Mbps maximum transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V 2.4 V VDD < 3.3 V, Notes 1.6 V Vb 2.0 V 5, 6 Theoretical value of the 0.43 maximum transfer rate Note 7 bps Mbps Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V Notes 1. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V VDD 5.5 V and 2.7 V Vb 4.0 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 2.2 Vb )} x 3 [bps] 1 - {-Cb x Rb x ln (1 - Transfer rate x 2 2.2 Vb )} 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 2. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. 3. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V VDD < 4.0 V and 2.3 V Vb 2.7 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 2.0 Vb )} x 3 [bps] 1 - {-Cb x Rb x ln Transfer rate x 2 2.0 (1 - Vb )} 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 4. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. 5. Use it with VDD Vb. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 103 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C Notes 6. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.4 V VDD < 3.3 V and 1.6 V Vb 2.0 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 1.5 Vb )} x 3 [bps] 1.5 1 - {-Cb x Rb x ln (1 - Vb )} Transfer rate x 2 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 7. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected UART mode connection diagram (during communication at different potential) Vb Rb TxDq Rx User's device RL78 microcontroller RxDq R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Tx Page 104 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1. Rb[]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0), g: PIM and POM number (g = 5) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 105 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/2) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter SCKp cycle time Symbol tKCY1 Conditions tKCY1 4/fCLK 4.0 V VDD 5.5 V, MIN. TYP. MAX. Unit 600 ns 1000 ns 2300 ns tKCY1/2 - ns 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 2.4 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SCKp high-level width tKH1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SCKp low-level width tKL1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 150 tKCY1/2 - ns 340 tKCY1/2 - ns 916 tKCY1/2 - 24 ns tKCY1/2 - 36 ns tKCY1/2 - ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k 100 Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. Use it with VDD Vb. (Remarks are listed two pages after the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 106 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/2) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter SIp setup time Note 1 (to SCKp) Symbol tSIK1 Conditions MIN. 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, TYP. MAX. Unit 162 ns 354 ns 958 ns 38 ns 38 ns 38 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 3 , Cb = 30 pF, Rb = 5.5 k SIp hold time Note 1 (from SCKp) tKSI1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 3 , Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to Note 1 SOp output tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 200 ns 390 ns 966 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 3 , Cb = 30 pF, Rb = 5.5 k SIp setup time Note 2 (to SCKp) tSIK1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 88 ns 88 ns 220 ns 38 ns 38 ns 38 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 3 , Cb = 30 pF, Rb = 5.5 k SIp hold time Note 2 (from SCKp) tKSI1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 3 , Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to Note 2 SOp output tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 50 ns 50 ns 50 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 3 , Cb = 30 pF, Rb = 5.5 k (Notes, Cautions and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 107 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3 Use it with VDD Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) Vb <Master> Vb Rb Rb SCK SCKp RL78 microcontroller SIp SO User's device SI SOp Remarks 1. Rb[]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00), m: Unit number , n: Channel number (mn = 00), g: PIM and POM number (g = 0, 3, 5, 7) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) 4. CSI01 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 108 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data Remarks 1. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g = 0, 3, 5, 7) 2. CSI01 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 109 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter SCKp cycle time Note 1 Symbol tKCY2 Conditions tKH2, Unit 24/fMCK ns 2.7 V Vb 4.0 V 8 MHz < fMCK 20 MHz 20/fMCK ns 4 MHz < fMCK 8 MHz 16/fMCK ns fMCK 4 MHz 12/fMCK ns 2.7 V VDD < 4.0 V, 20 MHz < fMCK 24 MHz 32/fMCK ns 2.3 V Vb 2.7 V 16 MHz < fMCK 20 MHz 28/fMCK ns 8 MHz < fMCK 16 MHz 24/fMCK ns 4 MHz < fMCK 8 MHz 16/fMCK ns fMCK 4 MHz 12/fMCK ns 20 MHz < fMCK 24 MHz 72/fMCK ns 16 MHz < fMCK 20 MHz 64/fMCK ns 8 MHz < fMCK 16 MHz 52/fMCK ns 4 MHz < fMCK 8 MHz 32/fMCK ns fMCK 4 MHz 20/fMCK ns tKCY2/2 - ns Note 2 tKL2 MAX. 20 MHz < fMCK 24 MHz 1.6 V Vb 2.0 V width TYP. 4.0 V VDD 5.5 V, 2.4 V VDD < 3.3 V, SCKp high-/low-level MIN. 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V 24 tKCY2/2 - 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V ns 36 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 tKCY2/2 - ns 100 SIp setup time (to SCKp) tSIK2 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V 1/fMCK + Note 3 ns 40 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V 1/fMCK + ns 40 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 1/fMCK + ns 60 SIp hold time (from SCKp) tKSI2 Delay time from SCKp to SOp output 1/fMCK + 62 ns Note 4 tKSO2 Note 5 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 2/fMCK + Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, 2/fMCK + ns 428 Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V ns 240 Note 2 , Cb = 30 pF, Rb = 5.5 k 2/fMCK + ns 1146 Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps 2. Use it with VDD Vb. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. (Caution and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 110 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) Vb <Slave> Rb SCKp RL78 microcontroller SIp SOp Remarks 1. SCK SO User's device SI Rb[]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g = 0, 3, 5, 7) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) 4. CSI01 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 111 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 Output data SOp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 SOp Output data Remarks 1. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g = 0, 3, 5, 7) 2. CSI01 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 112 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 2 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (1/2) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter SCLr clock frequency Symbol fSCL Conditions MIN. 4.0 V VDD 5.5 V, MAX. Unit 400 Note 1 kHz 400 Note 1 kHz 100 Note 1 kHz 100 Note 1 kHz 100 Note 1 kHz 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 , Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "L" tLOW 4.0 V VDD 5.5 V, 1200 ns 1200 ns 4600 ns 4600 ns 4650 ns 620 ns 500 ns 2700 ns 2400 ns 1830 ns 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 , Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "H" tHIGH 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 , Cb = 100 pF, Rb = 5.5 k (Notes, Caution and Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 113 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 2 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (2/2) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Data setup time (reception) Data hold time (transmission) Symbol tSU:DAT tHD:DAT Conditions MIN. 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 340 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + Note 3 340 MAX. Unit ns Note 3 ns 1/fMCK + 760 4.0 V VDD 5.5 V, Note 3 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k ns 2.7 V VDD < 4.0 V, 1/fMCK + 760 Note 3 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k ns 1/fMCK + 570 2.4 V VDD < 3.3 V, Notes 2 Note 3 , 1.6 V Vb 2.0 V Cb = 100 pF, Rb = 5.5 k ns 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 0 770 ns 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 0 770 ns 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 0 1420 ns 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 0 1420 ns 2.4 V VDD < 3.3 V, Note 2 , 1.6 V Vb 2.0 V Cb = 100 pF, Rb = 5.5 k 0 1215 ns Notes 1. The value must also be equal to or less than fMCK/4. 2. Use it with VDD Vb. 3. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 114 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 2 Simplified I C mode connection diagram (during communication at different potential) Vb Vb Rb Rb SDA SDAr User's device RL78 microcontroller SCL SCLr 2 Simplified I C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT tSU:DAT Remarks 1. Rb[]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage 2. r: IIC number (r = 00), g: PIM, POM number (g = 0, 3, 5, 7) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 115 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3.5.2 Serial interface IICA (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Standard Unit Fast Mode Mode SCLA0 clock frequency fSCL Setup time of restart condition Note 1 MIN. MAX. MIN. MAX. Fast mode: fCLK 3.5 MHz - - 0 400 kHz Standard mode: fCLK 1 MHz 0 100 - - kHz tSU:STA 4.7 0.6 s tHD:STA 4.0 0.6 s Hold time when SCLA0 = "L" tLOW 4.7 1.3 s Hold time when SCLA0 = "H" tHIGH 4.0 0.6 s tSU:DAT 250 100 ns tHD:DAT 0 Setup time of stop condition tSU:STO 4.0 0.6 s Bus-free time tBUF 4.7 1.3 s Hold time Data setup time (reception) Data hold time (transmission) Notes 1. 2. Note 2 3.45 0 0.9 s The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 1 (PIOR1) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 k Fast mode: Cb = 320 pF, Rb = 1.1 k IICA serial transfer timing tLOW SCLA0 tHD:DAT tHD:STA tHIGH tSU:STA tHD:STA tSU:STO tSU:DAT SDAA0 tBUF Stop condition Start condition R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Restart condition Stop condition Page 116 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3.5.3 USB (1) Electrical specifications (TA = -40 to +105C, 3.0 V UVDD 3.6 V, 3.0 V VDD 5.5 V, VSS = 0 V) Parameter UVDD UVBUS MIN. TYP. MAX. Unit UVDD input voltage characteristic UVDD Symbol VDD = 3.0 to 5.5 V, PXXCON = 1, VDDUSEB = 0 (UVDD VDD) Conditions 3.0 3.3 3.6 V UVDD output voltage characteristic UVDD VDD = 4.0 to 5.5 V, PXXCON = VDDUSEB = 1 3.0 3.3 3.6 V UVBUS input voltage characteristic UVBUS Function 4.35 Note (4.02 ) 5.00 5.25 V 4.75 5.00 5.25 V MIN. TYP. MAX. Unit 0.8 V Host Note Value of instantaneous voltage (TA = -40 to +105C, 3.0 V UVDD 3.6 V, 3.0 V VDD 5.5 V, VSS = 0 V) Parameter UDPi/UDMi pins input characteristic (FS/LS receiver) UDPi/UDMi pins output characteristic (FS driver) Symbol Input voltage Conditions 2.0 VIH | UDP voltage - UDM voltage | Difference input sensitivity VDI Difference common mode range VCM Output voltage VOH IOH = -200 A VOL IOL = 2.4 mA tFR Rising: From 10% to 90 % of amplitude, Falling: From 90% to 10 % of amplitude, CL = 50 pF Transi-ti Rising on time Falling Matching (TFR/TFF) tFF VFRFM Crossover voltage VFCRS UDPi/UDMi pins output characteristic (LS driver) Output Impedance ZDRV Output voltage VOH Transi-ti Rising on time Falling tLR tLF VLTFM Crossover voltage VLCRS Note UVBUS UVDD voltage = 3.3 V, Pin voltage = 1.65 V VOL Matching Note (TFR/TFF) UDPi/UDMi pins pull-up, pull-down V VIL Rising: From 10% to 90 % of amplitude, Falling: From 90% to 10 % of amplitude, CL = 200 to 600 pF When the host controller function is selected: The UDMi pin (i = 0, 1) is pulled up via 1.5 k. When the function controller function is selected: The UDP0 and UDM0 pins are individually pulled down via 15 k Pull-down resistor RPD Pull-up resistor (i = 0 only) Idle RPUI Recep-t RPUA ion UVBUS pull-down resistor RVBUS UVBUS input voltage VIH 0.2 0.8 2.5 V 2.8 3.6 V 0 0.3 V 4 20 ns 4 20 ns 90 111.1 % 1.3 2.0 V 28 44 2.8 3.6 V 0 0.3 V 75 300 ns 75 300 ns 80 125 % 1.3 2.0 V 14.25 24.80 k 0.9 1.575 k 1.425 3.09 k UVBUS voltage = 5.5 V VIL V 1000 k 3.20 V 0.8 V Note Excludes the first signal transition from the idle state. Remark i = 0, 1 R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 117 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C Timing of UDPi and UDMi UDPi 90 % 90 % VCRS (Crossover voltage) 10 % 10 % UDMi tR tF (2) BC standard (TA = -40 to +105C, 3.0 V UVDD 3.6 V, 3.0 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit USB UDPi sink current IDP_SINK 25 175 A standard UDMi sink current IDM_SINK 25 175 A DCD source current IDP_SRC 7 13 A Dedicated charging RDCP_DAT 200 0.25 0.4 V BC1.2 0 V < UDP/UDM voltage < 1.0 V port resistor Data detection voltage VDAT_REF UDPi source voltage VDP_SRC Output current 250 A 0.5 0.7 V UDMi source voltage VDM_SRC Output current 250 A 0.5 0.7 V Remark i = 0, 1 R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 118 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (3) BC option standard (Host) (TA = -40 to +105C, 4.75 V UVBUS 5.25 V, 3.0 V UVDD 3.6 V, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit UDPi output VDSELi 1000 VP20 38 40 42 % UVBUS voltage [3:0] 1001 VP27 51.6 53.6 55.6 % UVBUS 1010 VP20 38 40 42 % UVBUS 1100 VP33 60 66 72 % UVBUS (UVBUS divider (i = 0, 1) ratio) * VDOUEi = 1 UDMi output VDSELi 1000 VM20 38 40 42 % UVBUS voltage [3:0] 1001 VM20 38 40 42 % UVBUS 1010 VM27 51.6 53.6 55.6 % UVBUS 1100 VM33 60 66 72 % UVBUS 1000 VHDETP_UP0 (UVBUS divider (i = 0, 1) ratio) * VDOUEi = 1 UDPi VDSELi comparing Note 1 voltage [3:0] (i = 0, 1) (UVBUS divider The rise of pin voltage detection voltage 56.2 VHDETP_DWN0 The fall of pin voltage detection voltage 1001 VHDETP_UP1 1010 VHDETP_UP2 The rise of pin voltage detection voltage 29.4 60.5 VHDETP_DWN1 The fall of pin voltage detection voltage ratio) * VDOUEi = 1 The rise of pin voltage detection voltage UDMi VDSELi comparing Note 1 voltage [3:0] (i = 0, 1) (UVBUS divider 1000 VHDETM_UP0 The rise of pin voltage detection voltage 45.0 1001 VHDETM_UP1 The rise of pin voltage detection voltage 56.2 * VDOUEi = 1 1010 56.2 Note 2 Connect detection with the full speed function The rise of pin voltage detection voltage 1000 RHDET_PULL 60.5 In full-speed mode, the power supply % UVBUS % UVBUS 29.4 VHDETM_DWN2 The fall of pin voltage detection voltage * CUSDETEi = 1 UDPi pull-up detection VHDETM_UP2 % UVBUS % UVBUS 29.4 VHDETM_DWN1 The fall of pin voltage detection voltage ratio) % UVBUS % UVBUS 29.4 VHDETM_DWN0 The fall of pin voltage detection voltage % UVBUS % UVBUS 56.2 VHDETP_DWN2 The fall of pin voltage detection voltage * CUSDETEi = 1 % UVBUS % UVBUS % UVBUS 45.0 % UVBUS 1.575 k 1.575 k voltage range of pull-up resistors 1001 connected to the USB function 1010 module is between 3.0 V and 3.6 V. (pull-up resistor) UDMi pull-up detection Note 2 Connect detection with the low-speed (pull-up 1000 RHDET_PULL In low-speed mode, the power supply voltage range of pull-up resistors 1001 connected to the USB function 1010 module is between 3.0 V and 3.6 V. resistor) UDMi sink current Note 2 detection Connect detection with the BC1.2 portable 1000 IHDET_SINK 25 A 1001 1010 device (sink resistor) Notes 1. If the voltage output from UDPi or UDMi (i = 0, 1) exceeds the range of the MAX and MIN values prescribed in this specification, DPCUSDETi (bit 8) and DMCUSDETi (bit 9) of the USBBCOPTi register are set to 1. 2. If the pull-up resistance or sink current prescribed in this specification is applied to UDPi or UDMi (i = 0, 1), DPCUSDETi (bit 8) and DMCUSDETi (bit 9) of the USBBCOPTi register are set to 1. Remark i = 0, 1 R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 119 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (4) BC option standard (Function) (TA = -40 to +105C, 4.35 V UVBUS 5.25 V, 3.0 V UVDD 3.6 V, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit UDPi/UDMi VDSELi 0000 VDDET0 27 32 37 % UVBUS input [3:0] reference (i = 0) 0001 VDDET1 29 34 39 % UVBUS 0010 VDDET2 32 37 42 % UVBUS (UVBUS divider 0011 VDDET3 35 40 45 % UVBUS ratio) 0100 VDDET4 38 43 48 % UVBUS * VDOUEi = 0 0101 VDDET5 41 46 51 % UVBUS 0110 VDDET6 44 49 54 % UVBUS 0111 VDDET7 47 52 57 % UVBUS 1000 VDDET8 51 56 61 % UVBUS 1001 VDDET9 55 60 65 % UVBUS 1010 VDDET10 59 64 69 % UVBUS 1011 VDDET11 63 68 73 % UVBUS 1100 VDDET12 67 72 77 % UVBUS 1101 VDDET13 71 76 81 % UVBUS 1110 VDDET14 75 80 85 % UVBUS 1111 VDDET15 79 84 89 % UVBUS voltage (i = 0)) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 120 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3.6 Analog Characteristics 3.6.1 A/D converter characteristics Classification of A/D converter characteristics Input channel Reference Voltage Reference voltage (+) = Reference voltage (+) = VBGR AVREFP Reference voltage (-) = Reference voltage (+) = VDD Reference voltage (-) = AVREFM Reference voltage (-) = VSS AVREFM ANI0 to ANI7 Refer to 3.6.1 (1). ANI16, ANI17, ANI19 Refer to 3.6.1 (2). Internal reference voltage Refer to 3.6.1 (1). Refer to 3.6.1 (3). Refer to 3.6.1 (4). - Temperature sensor output voltage (1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI2 to ANI7, internal reference voltage, and temperature sensor output voltage (TA = -40 to +105C, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Resolution Conditions RES Note 1 Overall error AINL tCONV TYP. 8 10-bit resolution AVREFP = VDD Conversion time MIN. 2.4 V AVREFP 5.5 V 1.2 MAX. Unit 10 bit 3.5 LSB Note 3 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 2.4 V VDD 5.5 V 17 39 s 10-bit resolution 3.6 V VDD 5.5 V 2.375 39 s Target pin: Internal 2.7 V VDD 5.5 V 3.5625 39 s 2.4 V VDD 5.5 V 17 39 s 10-bit resolution Target pin: ANI2 to ANI7 reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) Notes 1, 2 Zero-scale error Notes 1, 2 Full-scale error Integral linearity error Note 1 EZS 10-bit resolution Note 3 AVREFP = VDD 2.4 V AVREFP 5.5 V 0.25 %FSR EFS 10-bit resolution Note 3 AVREFP = VDD 2.4 V AVREFP 5.5 V 0.25 %FSR ILE 10-bit resolution 2.4 V AVREFP 5.5 V 2.5 LSB 2.4 V AVREFP 5.5 V 1.5 LSB AVREFP V AVREFP = VDD Differential linearity error Note 1 DLE 10-bit resolution AVREFP = VDD Analog input voltage VAIN Note 3 Note 3 ANI2 to ANI7 0 Note 4 Internal reference voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode) VBGR Temperature sensor output voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode) VTMPS25 Note 4 V V (Notes are listed on the next page.) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 121 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD. 4. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 122 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI16, ANI17, ANI19 (TA = -40 to +105C, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Resolution Conditions RES Note 1 Overall error AINL tCONV 10-bit resolution Zero-scale error Notes 1, 2 Full-scale error Integral linearity error Note 1 Note 1 10 bit 5.0 LSB 3.6 V VDD 5.5 V 2.125 39 s Target ANI pin : 2.7 V VDD 5.5 V 3.1875 39 s 2.4 V VDD 5.5 V 17 39 s EZS 10-bit resolution Note 3 AVREFP = VDD 2.4 V AVREFP 5.5 V 0.35 %FSR EFS 10-bit resolution Note 3 AVREFP = VDD 2.4 V AVREFP 5.5 V 0.35 %FSR ILE 10-bit resolution 2.4 V AVREFP 5.5 V 3.5 LSB 2.4 V AVREFP 5.5 V 2.0 LSB AVREFP V DLE VAIN Note 3 10-bit resolution AVREFP = VDD Analog input voltage 1.2 Unit 10-bit resolution AVREFP = VDD Differential linearity error 2.4 V AVREFP 5.5 V MAX. Note 3 ANI16, ANI17, ANI19 Notes 1, 2 TYP. 8 AVREFP = VDD Conversion time MIN. Note 3 ANI16, ANI17, ANI19 0 and VDD Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add 4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 2.0 LSB to the MAX. value when AVREFP = VDD. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 123 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (3) Reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), Reference voltage (-) = VSS (ADREFM = 0), target ANI pin : ANI0 to ANI7, ANI16, ANI17, ANI19, internal reference voltage, and temperature sensor output voltage (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (-) = VSS) Parameter Symbol Resolution Conditions RES Notes 1, 2 MIN. TYP. 8 MAX. Unit 10 bit 7.0 LSB Overall error AINL 10-bit resolution 2.4 V VDD 5.5 V Conversion time tCONV 10-bit resolution 3.6 V VDD 5.5 V 2.125 39 s Target ANI pin : 2.7 V VDD 5.5 V 3.1875 39 s ANI17, ANI19 2.4 V VDD 5.5 V 17 39 s 10-bit resolution 3.6 V VDD 5.5 V 2.375 39 s Target ANI pin : Internal 2.7 V VDD 5.5 V 3.5625 39 s 2.4 V VDD 5.5 V 17 39 s ANI0 to ANI7, ANI16, reference voltage, and temperature sensor 1.2 output voltage (HS (high-speed main) mode) Notes 1, 2 Zero-scale error Notes 1, 2 Full-scale error Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage EZS 10-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR EFS 10-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR ILE 10-bit resolution 2.4 V VDD 5.5 V 4.0 LSB DLE 10-bit resolution 2.4 V VDD 5.5 V 2.0 LSB VAIN ANI0 to ANI7, ANI16, ANI17, ANI19 VDD V Internal reference voltage 0 VBGR Note 3 V (2.4 V VDD 5.5 V, HS (high-speed main) mode) Temperature sensor output voltage VTMPS25 Note 3 V (2.4 V VDD 5.5 V, HS (high-speed main) mode) Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 124 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C (4) When Reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), Reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0 to ANI7, ANI16, ANI17, ANI19 (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VBGR AVREFM Note 4 Note 3 , Reference voltage (-) = = 0 V, HS (high-speed main) mode) Parameter Symbol Resolution Conditions MIN. TYP. RES Conversion time Notes 1, 2 Zero-scale error Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage MAX. 8 Unit Bit 39 s 2.4 V VDD 5.5 V 0.60 %FSR 8-bit resolution 2.4 V VDD 5.5 V 2.0 LSB 8-bit resolution 2.4 V VDD 5.5 V 1.0 LSB tCONV 8-bit resolution 2.4 V VDD 5.5 V EZS 8-bit resolution ILE DLE VAIN 17 0 VBGR Note 3 V Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics. 4. When reference voltage (-) = VSS, the MAX. values are as follows. Zero-scale error: Add 0.35%FSR to the MAX. value when reference voltage (-) = AVREFM. Integral linearity error: Add 0.5 LSB to the MAX. value when reference voltage (-) = AVREFM. Differential linearity error: Add 0.2 LSB to the MAX. value when reference voltage (-) = AVREFM. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 125 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3.6.2 Temperature sensor/internal reference voltage characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25C Internal reference voltage VBGR Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the TYP. MAX. 1.05 1.38 Unit V 1.45 1.5 -3.6 V mV/C temperature Operation stabilization wait time 3.6.3 tAMP s 5 POR circuit characteristics (TA = -40 to +105C, VSS = 0 V) Parameter Detection voltage Minimum pulse width Note Symbol Conditions MIN. TYP. MAX. Unit VPOR Power supply rise time 1.45 1.51 1.57 V VPDR Power supply fall time 1.44 1.50 1.56 V TPW s 300 Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock (fMAIN) is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW Supply voltage (VDD) VPOR VPDR or 0.7 V R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 126 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3.6.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = -40 to +105C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Detection Supply voltage level Symbol VLVD0 voltage VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Minimum pulse width tLW Detection delay time tLD R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Conditions MIN. TYP. MAX. Unit Power supply rise time 3.90 4.06 4.22 V Power supply fall time 3.83 3.98 4.13 V Power supply rise time 3.60 3.75 3.90 V Power supply fall time 3.53 3.67 3.81 V Power supply rise time 3.01 3.13 3.25 V Power supply fall time 2.94 3.06 3.18 V Power supply rise time 2.90 3.02 3.14 V Power supply fall time 2.85 2.96 3.07 V Power supply rise time 2.81 2.92 3.03 V Power supply fall time 2.75 2.86 2.97 V Power supply rise time 2.70 2.81 2.92 V Power supply fall time 2.64 2.75 2.86 V Power supply rise time 2.61 2.71 2.81 V Power supply fall time 2.55 2.65 2.75 V Power supply rise time 2.51 2.61 2.71 V Power supply fall time 2.45 2.55 2.65 V s 300 300 s Page 127 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +105C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Symbol Interrupt and reset VLVDD0 mode Conditions MIN. TYP. MAX. Unit VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage 2.64 2.75 2.86 V 2.81 2.92 3.03 V 2.75 2.86 2.97 V 2.90 3.02 3.14 V 2.85 2.96 3.07 V 3.90 4.06 4.22 V 3.83 3.98 4.13 V VLVDD1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage VLVDD2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage Falling interrupt voltage VLVDD3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage Falling interrupt voltage 3.6.5 Power supply voltage rising slope characteristics (TA = -40 to +105C, VSS = 0 V) Parameter Power supply voltage rising slope Caution Symbol Conditions MIN. SVDD TYP. MAX. Unit 54 V/ms Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 3.4 R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 AC Characteristics. Page 128 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3.7 <R> RAM Data Retention Characteristics (TA = -40 to +105C, VSS = 0 V) Parameter Data retention supply voltage Symbol Conditions MIN. VDDDR 1.44 TYP. Note MAX. Unit 5.5 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected. Operation mode STOP mode RAM data retention <R> VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 3.8 Flash Memory Programming Characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter CPU/peripheral hardware clock Symbol Conditions fCLK 2.4 V VDD 5.5 V Cerwr Retaining years: 20 years MIN. TYP. 1 MAX. Unit 24 MHz frequency <R> Number of code flash rewrites TA = +85C <R> Number of data flash rewrites 1,000 Retaining years: 1 year TA = +25C Notes 1, 2, 3 <R> 1,000,000 Note 4 Retaining years: 5 years TA = +85C <R> 100,000 Note 4 Retaining years: 20 years TA = +85C Times Note 4 10,000 Note 4 Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library. 3. These specifications show the characteristics of the flash memory and the results obtained from Renesas Electronics reliability testing. 4. This temperature is the average value at which data are retained. <R> 3.9 Dedicated Flash Memory Programmer Communication (UART) (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Transfer rate R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Symbol Conditions During serial programming MIN. 115,200 TYP. MAX. Unit 1,000,000 bps Page 129 of 134 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) RL78/G1C 3.10 Timing Specs for Switching Flash Memory Programming Modes (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol How long from when an external tSUINIT Conditions MIN. POR and LVD reset must end before the TYP. MAX. Unit 100 ms external reset ends. reset ends until the initial communication settings are specified How long from when the TOOL0 tSU POR and LVD reset must end before the 10 s 1 ms external reset ends. pin is placed at the low level until an external reset ends How long the TOOL0 pin must be tHD POR and LVD reset must end before the external reset ends. kept at the low level after an external reset ends (excluding the processing time of the firmware to control the flash memory) <1> <2> <4> <3> RESET 723 s + tHD processing time 00H reception (TOOLRxD, TOOLTxD mode) TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset ends (POR and LVD reset must end before the external reset ends.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. tSU: How long from when the TOOL0 pin is placed at the low level until an external reset ends tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end (excluding the processing time of the firmware to control the flash memory) R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 130 of 134 RL78/G1C 4. 4. PACKAGE DRAWINGS PACKAGE 4.1 DRAWINGS 32-pin Products R5F10JBCAFP, R5F10KBCAFP R5F10JBCGFP, R5F10KBCGFP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP32-7x7-0.80 PLQP0032GB-A P32GA-80-GBT-1 0.2 HD 2 D 17 16 24 25 detail of lead end 1 E c HE 32 8 1 L 9 e (UNIT:mm) 3 b x M A A2 ITEM D DIMENSIONS 7.000.10 E 7.000.10 HD 9.000.20 HE 9.000.20 A 1.70 MAX. A1 0.100.10 A2 y A1 1.40 b 0.370.05 c 0.145 0.055 L 0.500.20 0 to 8 e 0.80 1.Dimensions " 1" and " 2" do not include mold flash. x 0.20 2.Dimension " 3" does not include trim offset. y 0.10 NOTE R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 131 of 134 RL78/G1C 4. PACKAGE DRAWINGS R5F10JBCANA, R5F10KBCANA R5F10JBCGNA, R5F10KBCGNA <R> JEITA Package code RENESAS code Previous code P-HWQFN32-5x5-0.50 PWQN0032KB-A P32K8-50-3B4-5 MASS (TYP.)[g] 0.06 D 17 24 DETAIL OF A PART 16 25 E A 9 32 A1 C2 8 1 INDEX AREA A S y S Referance Symbol D2 A Lp EXPOSED DIE PAD 1 8 9 32 Dimension in Millimeters Min Nom Max D 4.95 5.00 5.05 E 4.95 5.00 5.05 A 0.80 A1 0.00 b 0.18 e Lp B E2 ZE 16 25 17 24 ZD e b x M 0.25 0.30 0.50 0.30 0.40 0.50 x 0.05 y 0.05 ZD 0.75 ZE 0.75 c2 0.15 0.20 D2 3.50 E2 3.50 0.25 S AB 2013 Renesas Electronics Corporation. All rights reserved. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 132 of 134 RL78/G1C 4.2 4. PACKAGE DRAWINGS 48-pin Products R5F10JGCAFB, R5F10KGCAFB R5F10JGCGFB, R5F10KGCGFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP48-7x7-0.50 PLQP0048KF-A P48GA-50-8EU-1 0.16 HD D detail of lead end 36 25 37 A3 24 c E L Lp HE L1 (UNIT:mm) 13 48 12 1 ZE e ZD b x M S A ITEM D DIMENSIONS 7.000.20 E 7.000.20 HD 9.000.20 HE 9.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 b A2 c L S y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. A1 0.25 0.220.05 0.145 +0.055 -0.045 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.50 x 0.08 y 0.08 ZD 0.75 ZE 0.75 2012 Renesas Electronics Corporation. All rights reserved. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 133 of 134 RL78/G1C 4. PACKAGE DRAWINGS R5F10JGCANA, R5F10KGCANA R5F10JGCGNA, R5F10KGCGNA <R> JEITA Package Code P-HWQFN48-7x7-0.50 RENESAS Code Previous Code MASS (Typ) [g] PWQN0048KB-A 48PJN-A P48K8-50-5B4-7 0.13 Unit: mm D 25 36 DETAIL OF A PART 24 37 E A A1 13 48 c2 12 1 INDEX AREA A S y S D2 A Lp EXPOSED DIE PAD Reference Dimensions in millimeters Symbol Min Nom Max D 6.95 7.00 7.05 E 6.95 7.00 7.05 A -- -- 0.80 A1 0.00 -- -- b 0.18 0.25 0.30 e -- 0.50 -- Lp 0.30 -- 0.40 -- 0.50 -- -- -- 0.75 0.05 -- ZE -- 0.75 -- c2 0.15 0.20 0.25 D2 -- 5.50 -- E2 -- 5.50 -- 12 1 13 48 B E2 ZE 24 37 36 y 25 ZD ZD e b M x S AB x 0.05 (c) 2015 Renesas Electronics Corporation. All rights reserved. R01DS0348EJ0120 Rev.1.20 Sep 30, 2016 Page 134 of 134 Revision History RL78/G1A Data Sheet Description Rev. Date 0.01 Sep 20, 2012 - 1.00 Aug 08, 2013 Throughout Page Summary First Edition issued Deletion of the bar over SCK and SCKxx Renaming of fEXT to fEXS Renaming of interval timer (unit) to 12-bit interval timer Addition of products for G: Industrial applications (TA = -40 to +105 C ) 1 Change of 1.1 Features 2 Change of 1.2 List of Part Numbers 3 Modification of Figure 1-1. Part Number, Memory Size, and Package of RL78/G1C 4, 5 15, 16 1.10 1.20 Nov 15, 2013 Sep 30, 2016 Addition of remark to 1.3 Pin Configuration (Top View) Change of 1.6 Outline of Functions 17 to 76 Addition of a whole chapter 77 to 131 Addition of a whole chapter 132 Addition of products for G: Industrial applications (TA = -40 to +105 C ) 77 Caution 3 added. 79 Note for operating ambient temperature in 3.1 Absolute Maximum Ratings deleted. 4 to 7 Modification of pin configuration in 1.3.1 32-pin products 8 to 11 Modification of pin configuration in 1.3.2 48-pin products 15 Modification of description of main system clock in 1.6 Outline of Functions 74 Modification of title of 2.7 RAM Data Retention Characteristics and figure 74 Modification of table of 2.8 Flash Memory Programming Characteristics 129 Modification of title of 3.7 RAM Data Retention Characteristics and figure 129 Modification of table of 3.8 Flash Memory Programming Characteristics and addition of Note 4 132 Change of figure in 4.1 32-pin Products 134 Change of figure in 4.2 48-pin Products SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. All trademarks and registered trademarks are the property of their respective owners. C-1 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Notice 1. 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Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3 Tel: +1-905-237-2004 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-585-100, Fax: +44-1628-585-900 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Dusseldorf, Germany Tel: +49-211-6503-0, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. 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No.777C, 100 Feet Road, HAL II Stage, Indiranagar, Bangalore, India Tel: +91-80-67208700, Fax: +91-80-67208777 Renesas Electronics Korea Co., Ltd. 12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 (c) 2016 Renesas Electronics Corporation. All rights reserved. Colophon 5.0