Datasheet
RL78/G1C
RENESAS MCU
Integrated USB Controller, True Low Power Platform (as low as 112.5 µA/MHz, and 0.61 µA for RTC + LVD),
2.4 V to 5.5 V Operation, 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All USB Based Applications
Page 1 of 134
R01DS0348EJ0120
Rev.1.20
Sep 30, 2016
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
1. OUTLINE
1.1 Features
Ultra-Low Power Technology
• 2.4 V to 5.5 V operation from a single supply
• Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31 µA
• Halt (RTC + LVD): 0.57 µA
• Supports snooze
• Operating: 71 µA/MHz
16-bit RL78 CPU Core
• Delivers 31 DMIPS at maximum operating frequency
of 24 MHz
• Instruction Execution: 86% of instructions can be
executed in 1 to 2 clock cycles
• CISC Architecture (Harvard) with 3-stage pipeline
• Multiply Signed & Unsigned: 16 x 16 to 32-bit result in
1 clock cycle
• MAC: 16 x 16 to 32-bit result in 2 clock cycles
• 16-bit barrel shifter for shift & rotate in 1 clock cycle
• 1-wire on-chip debug function
Code Flash Memory
• Density: 32 KB
• Block size: 1 KB
• On-chip single voltage flash memory with protection
from block erase/writing
• Self-programming with secure boot swap function
and flash shield window function
Data Flash Memory
• Data Flash with background operation
• Data flash size: 2 KB
• Erase Cycles: 1 Million (typ.)
• Erase/programming voltage: 2.4 V to 5.5 V
RAM
• 5.5 KB size options
• Supports operands or instructions
• Back-up retention in all modes
High-speed On-chip Oscillator
• 24 MHz with +/− 1% accuracy over voltage (2.4 V to
5.5 V) and temperature (−20°C to +85°C)
• Pre-configured settings: 48 MHz, 24 MHz (TYP.)
Reset and Supply Management
• Power-on reset (POR) monitor/generator
• Low voltage detection (LVD) with 9 setting options
(Interrupt and/or reset function)
USB
• Complying with USB version 2.0, incorporating
host/function controller
• Corresponding to full-speed transfer (12 Mbps) and
low-speed (1.5 Mbps)
• Complying with Battery Charging Specification
Revision 1.2
• Compliant with the 2.1A/1.0A charging mode
prescribed in the Apple Inc. MFi specification in the
USB power supply component specification Note
Direct Memory Access (DMA) Controller
• Up to 2 fully programmable channels
• Transfer unit: 8- or 16-bit
Multiple Communication Interfaces
• Up to 2 x I2C master
• Up to 1 x I2C multi-master
• Up to 2 x CSI (7-, 8-bit)
• Up to 1 x UART (7-, 8-, 9-bit)
Extended-Function Timers
• Multi-function 16-bit timer TAU: Up to 4 channels
(remote control output available)
• Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
• 12-bit interval timer: 1 channel
• 15 kHz watchdog timer: 1 channel (window function)
Rich Analog
• ADC: Up to 9 channels, 8/10-bit resolution, 2.1 µs
minimum conversion time
• Internal voltage reference (1.45 V)
• On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
• Flash memory CRC calculation
• RAM parity error check
• RAM write protection
• SFR write protection
• Illegal memory access detection
• Clock stop/frequency detection
• ADC self-test
• I/O port read back function (echo)
General Purpose I/O
• 5 V tolerant, high-current (up to 20 mA per pin)
• Open-Drain, Internal Pull-up support
Operating Ambient Temperature
• Standard: −40°C to + 85°C
• Extended: −40°C to + 105°C
Package Type and Pin Count
• 32-pin plastic HWQFN (5 x 5)
• 32-pin plastic LQFP (7 x 7)
• 48-pin plastic LFQFP (7 x 7)
• 48-pin plastic HWQFN (7 x 7)
Note To use the Apple Inc. battery charging mode, you must
join in Apple's Made for iPod/iPhone/iPad (MFi)
licensing program. Before requesting this specification
from Renesas Electronics, please join in the Apple's
MFi licensing program.
RL78/G1C 1. OUTLINE
Page 2 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
ROM, RAM capacities
Flash ROM
Data flash
RAM RL78/G1C
32-pin 48-pin
32 KB 2 KB 5.5 KB Note R5F10JBC, R5F10KBC R5F10JGC, R5F10KGC
Note This is about 4.5 KB when the self-programming function is used.
Remark The functions mounted depend on the product. See 1.6 Outline of Functions.
1.2 List of Part Numbers
Pin count Package USB Function Fields of
Application Note
Part Number
32 pins 32-pin plastic HWQFN
(5 × 5 , 0.5 mm pitch)
Host/Function controller A R5F10JBCANA#U0, R5F10JBCANA#W0
G R5F10JBCGNA#U0, R5F10JBCGNA#W0
Function controller only A R5F10KBCANA#U0, R5F10KBCANA#W0
G R5F10KBCGNA#U0, R5F10KBCGNA#W0
32-pin plastic LQFP
(7 × 7 , 0.8 mm pitch)
Host/Function controller A R5F10JBCAFP#V0, R5F10JBCAFP#X0
G R5F10JBCGFP#V0, R5F10JBCGFP#X0
Function controller only A R5F10KBCAFP#V0, R5F10KBCAFP#X0
G R5F10KBCGFP#V0, R5F10KBCGFP#X0
48 pins 48-pin plastic LFQFP
(7 × 7 , 0.5 mm pitch)
Host/Function controller A R5F10JGCAFB#V0, R5F10JGCAFB#X0
G R5F10JGCGFB#V0, R5F10JGCGFB#X0
Function controller only A R5F10KGCAFB#V0, R5F10KGCAFB#X0s
G R5F10JGCANA#U0, R5F10JGCANA#W0
48-pin plastic HWQFN
(7 × 7 , 0.5 mm pitch)
Host/Function controller A R5F10JGCANA#U0, R5F10JGCANA#W0
G R5F10JGCGNA#U0, R5F10JGCGNA#W0
Function controller only A R5F10KGCANA#U0, R5F10KGCANA#W0
G R5F10KGCGNA#U0, R5F10KGCGNA#W0
Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of
RL78/G1C.
Caution The part number above is valid as of when this manual was issued. For the latest part number,
see the web page of the target product on the Renesas Electronics website.
RL78/G1C 1. OUTLINE
Page 3 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Figure 1-1. Part Number, Memory Size, and Package of RL78/G1C
Part No. R 5 F 1 0 J G C A x x x F B # V 0
Packing
#U0 : Tray (HWQFN)
#V0 : Tray (LQFP, LFQFP)
#W0 : Embossed Tape (HWQFN)
#X0 : Embossed Tape (LQFP, LFQFP)
Package
ROM Number (Blank product is omitted)
ROM Capacity
RL78/G1C group
Renesas Microcontroller
Renesas Semiconductor
FP : LQFP, 0.80 mm pitch
FB : LFQFP, 0.50 mm pitch
NA : HWQFN, 0.50 mm pitch
C
:
32 KB
Pin count
B : 32-pin
G : 48-pin
10J
: USB host / function controller mounted
10K : USB function controller mounted
Classification
A : Consumer use, operating ambient temperature: − 40 °C to +85 °C
G : Industrial use, operating ambient temperature: − 40 °C to +105 °C
Type of Memory
F : Flash data memory
RL78/G1C 1. OUTLINE
Page 4 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
1.3 Pin Configuration (Top View)
1.3.1 32-pin products
• 32-pin plastic HWQFN (5 × 5 mm, 0.5 mm pitch)
(1) USB function: Host/Function controller (R5F10JBC)
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32
24 23 22 21 20 19 18 17
123456 78
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/ANI16/TO00/INTP9/SCK01/SCL01/(SCLA0)
P00/ANI17/TI00/INTP8/SI01/SDA01/(SDAA0)
P120/ANI19/SO01/(PCLBUZ1)
P51/INTP2/SO00/TxD0/TOOLTxD/(TI01)/(TO01)
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/(TI02)/(TO02
)
P30/INTP3/SCK00/SCL00/(TI03)/(TO03)/(PCLBUZ0)
P70/PCLBUZ1/UOVRCUR0
P31/TI03/TO03/INTP4/PCLBUZ0/UVBUSEN0
P62
P61/SDAA0
P60/SCLA0
exposed die pad
UDP0
UDM0
UVBUS
UVDD
UDP1
UDM1
P16/TI01/TO01/INTP5/UOVRCUR1
P17/TI02/TO02/UVBUSEN1
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
INDEX MARK
RL78/G1C
(Top View)
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
3. It is recommended to connect an exposed die pad to VSS.
<R>
RL78/G1C 1. OUTLINE
Page 5 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(2) USB function: Function controller only (R5F10KBC)
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32
24 23 22 21 20 19 18 17
123456 78
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AV
REFM
P20/ANI0/AV
REFP
P01/ANI16/TO00/INTP9/SCK01/SCL01/(SCLA0)
P00/ANI17/TI00/INTP8/SI01/SDA01/(SDAA0)
P120/ANI19/SO01/(PCLBUZ1)
P51/INTP2/SO00/TxD0/TOOLTxD/(TI01)/(TO01)
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/(TI02)/(TO02
)
P30/INTP3/SCK00/SCL00/(TI03)/(TO03)/(PCLBUZ0)
P70/PCLBUZ1
P31/TI03/TO03/INTP4/PCLBUZ0
P62
P61/SDAA0
P60/SCLA0
exposed die pad
UDP0
UDM0
UV
BUS
UV
DD
IC
Note
IC
Note
P16/TI01/TO01/INTP
5
P17/TI02/TO02
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
V
DD
INDEX MARK
RL78/G1C
(Top View)
Note IC: Internal Connection Pin. Leave open.
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
3. It is recommended to connect an exposed die pad to VSS.
<R>
RL78/G1C 1. OUTLINE
Page 6 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
• 32-pin plastic LQFP (7 × 7 mm, 0.8 mm pitch)
(1) USB function: Host/Function controller (R5F10JBC)
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32
24 23 22 21 20 19 18 17
123456 78
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AV
REFM
P20/ANI0/AV
REFP
P01/ANI16/TO00/INTP9/SCK01/SCL01/(SCLA0)
P00/ANI17/TI00/INTP8/SI01/SDA01/(SDAA0)
P120/ANI19/SO01/(PCLBUZ1)
P51/INTP2/SO00/TxD0/TOOLTxD/(TI01)/(TO01)
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/(TI02)/(TO02
)
P30/INTP3/SCK00/SCL00/(TI03)/(TO03)/(PCLBUZ0)
P70/PCLBUZ1/UOVRCUR0
P31/TI03/TO03/INTP4/PCLBUZ0/UVBUSEN0
P62
P61/SDAA0
P60/SCLA0
UDP0
UDM0
UV
BUS
UV
DD
UDP1
UDM1
P16/TI01/TO01/INTP5/UOVRCUR1
P17/TI02/TO02/UVBUSEN1
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
V
DD
INDEX MARK
RL78/G1C
(Top View)
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
<R>
RL78/G1C 1. OUTLINE
Page 7 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(2) USB function: Function controller only (R5F10KBC)
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32
24 23 22 21 20 19 18 17
123456 78
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AV
REFM
P20/ANI0/AV
REFP
P01/ANI16/TO00/INTP9/SCK01/SCL01/(SCLA0)
P00/ANI17/TI00/INTP8/SI01/SDA01/(SDAA0)
P120/ANI19/SO01/(PCLBUZ1)
P51/INTP2/SO00/TxD0/TOOLTxD/(TI01)/(TO01)
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/(TI02)/(TO02
)
P30/INTP3/SCK00/SCL00/(TI03)/(TO03)/(PCLBUZ0)
P70/PCLBUZ1
P31/TI03/TO03/INTP4/PCLBUZ0
P62
P61/SDAA0
P60/SCLA0
UDP0
UDM0
UV
BUS
UV
DD
IC
Note
IC
Note
P16/TI01/TO01/INTP5
P17/TI02/TO02
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
V
DD
INDEX MARK
RL78/G1C
(Top View)
Note IC: Internal Connection Pin Leave open.
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
<R>
RL78/G1C 1. OUTLINE
Page 8 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
1.3.2 48-pin products
• 48-pin plastic LFQFP (fine pitch) (7 × 7 , 0.5 mm pitch)
(1) USB function: Host/Function controller (R5F10JGC)
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
36 35 34 33 32 31 30 29 28 27 26 25
12 345 6 789101112
UDP0
UDM0
UV
BUS
UV
DD
UDP1
UDM1
P14/UOVRCUR0
P15/PCLBUZ1/UVBUSEN0
P16/TI01/TO01/INTP5/UOVRCUR1
P17/TI02/TO02/UVBUSEN1
P51/INTP2/SO00/TxD0/TOOLTxD
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00
P120/ANI19
P41/(TI03)/(TO03)/(INTP4)/(PCLBUZ1)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
V
DD
P140/PCLBUZ0/INTP
6
P00/TI00/(SDAA0)
P01/TO00/(SCLA0)
P130
P20/ANI0/AV
REFP
P21/ANI1/AV
REFM
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P60/SCLA0
P61/SDAA0
P62
P63
P31/TI03/TO03/INTP4
P75/KR5/INTP9/SCK01/SCL01
P74/KR4/INTP8/SI01/SDA01
P73/KR3/SO01
P72/KR2/(TI02)/(TO02)
P71/KR1/(TI01)/(TO01)/(INTP5)
P70/KR0
P30/INTP3/RTC1HZ/SCK00/SCL00
INDEX MARK
RL78/G1C
(Top View)
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
<R>
RL78/G1C 1. OUTLINE
Page 9 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(2) USB function: Function controller only (R5F10KGC)
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
36 35 34 33 32 31 30 29 28 27 26 25
1 2 3 4 5 6 7 8 9101112
UDP0
UDM0
UV
BUS
UV
DD
IC
Note
IC
Note
P14
P15/PCLBUZ1
P16/TI01/TO01/INTP5
P17/TI02/TO02
P51/INTP2/SO00/TxD0/TOOLTxD
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00
P120/ANI19
P41/(TI03)/(TO03)/(INTP4)/(PCLBUZ1)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
V
DD
P140/PCLBUZ0/INTP
6
P00/TI00/(SDAA0)
P01/TO00/(SCLA0)
P130
P20/ANI0/AV
REFP
P21/ANI1/AV
REFM
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P60/SCLA0
P61/SDAA0
P62
P63
P31/TI03/TO03/INTP4
P75/KR5/INTP9/SCK01/SCL01
P74/KR4/INTP8/SI01/SDA01
P73/KR3/SO01
P72/KR2/(TI02)/(TO02)
P71/KR1/(TI01)/(TO01)/(INTP5)
P70/KR0
P30/INTP3/RTC1HZ/SCK00/SCL00
INDEX MARK
RL78/G1C
(Top View)
Note IC: Internal Connection Pin Leave open.
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
<R>
RL78/G1C 1. OUTLINE
Page 10 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
• 48-pin plastic WHQFN (7 × 7 , 0.5 mm pitch)
(1) USB function: Host/Function controller (R5F10JGC)
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
36 35 34 33 32 31 30 29 28 27 26 25
1 2 3 4 5 6 7 8 9101112
UDP0
UDM0
UV
BUS
UV
DD
UDP1
UDM1
P14/UOVRCUR0
P15/PCLBUZ1/UVBUSEN0
P16/TI01/TO01/INTP5/UOVRCUR1
P17/TI02/TO02/UVBUSEN1
P51/INTP2/SO00/TxD0/TOOLTxD
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00
P120/ANI19
P41/(TI03)/(TO03)/(INTP4)/(PCLBUZ1)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
V
DD
P140/PCLBUZ0/INTP
6
P00/TI00/(SDAA0)
P01/TO00/(SCLA0)
P130
P20/ANI0/AV
REFP
P21/ANI1/AV
REFM
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P60/SCLA0
P61/SDAA0
P62
P63
P31/TI03/TO03/INTP4
P75/KR5/INTP9/SCK01/SCL01
P74/KR4/INTP8/SI01/SDA01
P73/KR3/SO01
P72/KR2/(TI02)/(TO02)
P71/KR1/(TI01)/(TO01)/(INTP5)
P70/KR0
P30/INTP3/RTC1HZ/SCK00/SCL00
exposed die pad
INDEX MARK
RL78/G1C
(Top View)
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
3. It is recommended to connect an exposed die pad to VSS.
<R>
RL78/G1C 1. OUTLINE
Page 11 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(2) USB function: Function controller only (R5F10KGC)
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
36 35 34 33 32 31 30 29 28 27 26 25
12 345 6 789101112
UDP0
UDM0
UV
BUS
UV
DD
IC
Note
IC
Note
P14
P15/PCLBUZ1
P16/TI01/TO01/INTP5
P17/TI02/TO02
P51/INTP2/SO00/TxD0/TOOLTxD
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00
P120/ANI19
P41/(TI03)/(TO03)/(INTP4)/(PCLBUZ1)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
V
DD
P140/PCLBUZ0/INTP
6
P00/TI00/(SDAA0)
P01/TO00/(SCLA0)
P130
P20/ANI0/AV
REFP
P21/ANI1/AV
REFM
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P60/SCLA0
P61/SDAA0
P62
P63
P31/TI03/TO03/INTP4
P75/KR5/INTP9/SCK01/SCL01
P74/KR4/INTP8/SI01/SDA01
P73/KR3/SO01
P72/KR2/(TI02)/(TO02)
P71/KR1/(TI01)/(TO01)/(INTP5)
P70/KR0
P30/INTP3/RTC1HZ/SCK00/SCL00
exposed die pad
INDEX MARK
RL78/G1C
(Top View)
Note IC: Internal Connection Pin Leave open.
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
3. It is recommended to connect an exposed die pad to VSS.
<R>
RL78/G1C 1. OUTLINE
Page 12 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
1.4 Pin Identification
A
NI0 to ANI7, ANI16, ANI17, ANI19: Analog Input
A
VREFM: Analog Reference Voltage Minus
A
VREFP: Analog Reference Voltage Plus
EXCLK: External Clock Input (Main System Clock)
EXCLKS: External Clock Input (Sub System Clock)
INTP0 to INTP6, INTP8, INTP9: External Interrupt Input
KR0 to KR5: Key Return
P00, P01: Port 0
P14 to P17: Port 1
P20 to P27: Port 2
P30, P31: Port 3
P40, P41: Port 4
P50, P51: Port 5
P60 to P63: Port 6
P70 to P75: Port 7
P120 to P124: Port 12
P130, P137: Port 13
P140: Port 14
PCLBUZ0, PCLBUZ1: Programmable Clock Output/Buzzer Output
REGC: Regulator Capacitance
RESET: Reset
RTC1HZ: Real-time Clock Correction Clock (1 Hz) Output
RxD0: Receive Data
SCK00, SCK01: Serial Clock Input/Output
SCLA0, SCL00, SCL01: Serial Clock Input/Output
SDAA0, SDA00, SDA01: Serial Data Input/Output
SI00, SI01: Serial Data Input
SO00, SO01: Serial Data Output
TI00 to TI03: Timer Input
TO00 to TO03: Timer Output
TOOL0: Data Input/Output for Tool
TOOLRxD, TOOLTxD: Data Input/Output for External Device
TxD0: Transmit Data
UDM0, UDM1, UDP0, UDP1: USB Input/Output
UOVRCUR0, UOVRCUR1: USB Input
UVBUSEN0, UVBUSEN1: USB Output
UVDD: USB Power Supply/USB Regulator Capacitance
UVBUS: USB Input/USB Power Supply (USB Optional BC)
VDD: Power Supply
VSS: Ground
X1, X2: Crystal Oscillator (Main System Clock)
XT1, XT2: Crystal Oscillator (Subsystem Clock)
RL78/G1C 1. OUTLINE
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1.5 Block Diagram
1.5.1 32-pin products
PORT 1 P16, P17
PORT 2 P20 to P24
5
PORT 3 P30, P31
2
PORT 4
PORT 5
2
PORT 12 P121, P122
P40
P50, P51
2
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL
RAM
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
SYSTEM
CONTROL RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
PLL
ON-CHIP DEBUG
TOOL0/P40
SERIAL ARRAY
UNIT0 (2ch)
UART0
IIC00
RxD0/P50
TxD0/P51
TIMER ARRAY
UNIT (4ch)
ch2
TI02/TO02/P17
ch3
TI03/TO03/P31
ch0
ch1
2
INTP0/P137
INTP3/P30,
INTP4/P31
INTP1/P50,
INTP2/P51
A/D CONVERTER
5ANI0/P20 to
ANI4/P24
3ANI16/P01, ANI17/P00,
ANI19/P120
AV
REFP
/P20
AV
REFM
/P21
2P120
PORT 13 P137
SCL00/P30
SDA00/P50
IIC01
TI00/P00
TO00/P01
BCD
ADJUSTMENT
USB VOLTAGE
REGULATOR
SCK00/P30
SO00/P51
SI00/P50
CSI00
V
SS
TOOLRxD/P50,
TOOLTxD/P51
V
DD
UV
DD
SERIAL
INTERFACE IICA0
SDAA0/P61
SCLA0/P60
2
INTP5/P16
MULTIPLIER&
DIVIDER,
MULITIPLY-
ACCUMULATOR
PORT 0 P00, P01
2
BUZZER OUTPUT PCLBUZ0/P31,
PCLBUZ1/P70
CLOCK OUTPUT
CONTROL
CSI01
UOVRCUR0
UVBUSEN0
USB
UOVRCUR1
UVBUSEN1
UDM0
UDP0
UDP1
UV
BUS
UDM1
DIRECT MEMORY
ACCESS
CONTROL
PORT 6
PORT 7 P70
P60 to P62
3
2
TI01/TO01/P16
REAL-TIME
CLOCK
RL78
CPU
CORE
CODE FLASH MEMORY
DATA FLASH MEMORY
12-BIT INTERVAL
TIMER
2INTP8/P00,
INTP9/P01
SCL01/P01
SDA01/P00
SCK01/P01
SO01/P120
SI01/P00
RL78/G1C 1. OUTLINE
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1.5.2 48-pin products
PORT 1 P14 to P17
PORT 2 P20 to P27
8
PORT 3 P30, P31
2
PORT 4
PORT 5
4
PORT 12 P121 to P124
P40, P41
2
P50, P51
2
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL
RAM
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
SYSTEM
CONTROL RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
PLL
ON-CHIP DEBUG
TOOL0/P40
SERIAL ARRAY
UNIT0 (2ch)
UART0
IIC00
RxD0/P50
TxD0/P51
SCL00/P30
SDA00/P50
TIMER ARRAY
UNIT (4ch)
ch2
TI02/TO02/P17
ch3
TI03/TO03/P31
ch0
ch1
INTP8/P74,
INTP9/P75
2
INTP0/P137
INTP3/P30,
INTP4/P31
INTP6/P140
INTP1/P50,
INTP2/P51
A/D CONVERTER
8ANI0/P20 to
ANI7/P27
AV
REFP
/P20
AV
REFM
/P21
4P120
P140
PORT 13 P130
P137
ANI19/P120
IIC01
SCL01/P75
SDA01/P74
TI00/P00
TO00/P01
BCD
ADJUSTMENT
USB VOLTAGE
REGULATOR
SCK00/P30
SO00/P51
SI00/P50
CSI00
V
SS
TOOLRxD/P50,
TOOLTxD/P51
V
DD
UV
DD
SERIAL
INTERFACE IICA0
SDAA0/P61
SCLA0/P60
2
2
INTP5/P16
MULTIPLIER&
DIVIDER,
MULITIPLY-
ACCUMULATOR
XT1/P123
XT2/EXCLKS/P124
PORT 0 P00, P01
2
BUZZER OUTPUT PCLBUZ0/P140,
PCLBUZ1/P15
CLOCK OUTPUT
CONTROL
KEY RETURN
6KR0/P70 to
KR5/P75
SCK01/P75
SO01/P73
SI01/P74
CSI01
UOVRCUR0
UVBUSEN0
USB
UOVRCUR1
UVBUSEN1
UDM0
UDP0
UDP1
UV
BUS
UDM1
DIRECT MEMORY
ACCESS
CONTROL
PORT 6
PORT 7 P70 to P75
6
P60 to P63
4
PORT 14
2
TI01/TO01/P16
RTC1HZ/P30
REAL-TIME
CLOCK
RL78
CPU
CORE
CODE FLASH MEMORY
DATA FLASH MEMORY
12-BIT INTERVAL
TIMER
RL78/G1C 1. OUTLINE
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1.6 Outline of Functions
[32-pin, 48-pin products]
(1/2)
Item 32-pin 48-pin
R5F10JBC R5F10KBC R5F10JGC R5F10KGC
Code flash memory (KB) 32 KB 32 KB
Data flash memory (KB) 2 KB 2 KB
RAM (KB) 5.5 KB Note 1 5.5 KB Note 1
Memory space 1 MB
Main
system
clock
High-speed system
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V),
HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V)
High-speed on-chip
oscillator
1 to 24 MHz (VDD = 2.7 to 5.5 V), 1 to 16 MHz (VDD = 2.4 to 5.5 V)
PLL clock 6, 12, 24 MHz Note 2 : VDD = 2.4 to 5.5 V
Subsystem clock − XT1 (crystal) oscillation
32.768 kHz (TYP.): VDD = 2.4 to 5.5 V
Low-speed on-chip oscillator On-chip oscillation (Watchdog timer/Real-time clock/12-bit interval timer clock)
15 kHz (TYP.): VDD = 2.4 to 5.5 V
General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time 0.04167
μ
s (High-speed on-chip oscillator: fHOCO = 48 MHz /fIH = 24 MHz operation)
0.04167
μ
s (PLL clock: fPLL = 48 MHz /fIH = 24 MHz Note 2 operation)
0.05
μ
s (High-speed system clock: fMX = 20 MHz operation)
− 30.5
μ
s (Subsystem clock: fSUB = 32.768 kHz
operation)
Instruction set • Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits × 8 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port Total 22 38
CMOS I/O 16 (N-ch O.D. I/O [VDD withstand voltage]: 5) 28 (N-ch O.D. I/O [VDD withstand voltage]: 6)
CMOS input 3 5
CMOS output − 1
N-ch open-drain I/O
(6 V tolerance)
3 4
Timer 16-bit timer 4 channel
Watchdog timer 1 channel
Real-time clock (RTC) 1 channel Note 3
12-bit Interval timer (IT) 1 channel
Timer output
4 channels (PWM output: 3) Note 4
RTC output − 1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
Notes 1. In the case of the 5.5 KB, this is about 4.5 KB when the self-programming function is used.
2. In the PLL clock 48 MHz operation, the system clock is 2/4/8 dividing ratio.
3. In 32-pin products, this channel can only be used for the constant-period interrupt function based on
the low-speed on-chip oscillator clock (fIL).
4. The number of PWM outputs varies depending on the setting of channels in use (the number of
masters and slaves).
Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is
set to 00H.
<R>
RL78/G1C 1. OUTLINE
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(2/2)
Item 32-pin 48-pin
R5F10JBC R5F10KBC R5F10JGC R5F10KGC
Clock output/buzzer output 2 2
• 2.93 kHz, 5.86 kHz, 11.7 kHz, 1.5 MHz, 3 MHz, 6 MHz, 12 MHz
(Main system clock: fMAIN = 24 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768
kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter 8 channels 9 channels
Serial interface CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
I
2C bus 1 channel
USB Host controller 2 channels − 2 channels −
Function controller 1 channel
Multiplier and
divider/multiply-accumulator
• Multiplier: 16 bits × 16 bits = 32 bits (Unsigned or signed)
• Divider: 32 bits ÷ 32 bits = 32 bits (Unsigned)
• Multiply-accumulator:16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller 2 channels
Vectored
interrupt
sources
Internal 20 20
External 8 10
Key interrupt − 6
Reset • Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit • Power-on-reset: 1.51 V (TYP.)
• Power-down-reset: 1.50 V (TYP.)
Voltage detector 2.45 V to 4.06 V (9 stages)
On-chip debug function
Provided
Power supply voltage VDD = 2.4 to 5.5 V
Operating ambient temperature TA = −40 to +85 °C (A: Consumer applications), TA = −40 to +105°C (G: Industrial applications)
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
This chapter describes the electrical specifications for the products "A: Consumer applications (TA = -40 to
+85°C)".
The target products A: Consumer applications ; TA = -40 to +85°C
R5F10JBCANA, R5F10JBCAFP, R5F10JGCANA, R5F10JGCAFB,
R5F10KBCANA, R5F10KBCAFP, R5F10KGCANA, R5F10KGCAFB
G: Industrial applications ; when using TA = -40 to +105°C specification products
at TA = -40 to +85°C.
R5F10JBCGNA, R5F10JBCGFP, R5F10JGCGNA, R5F10JGCGFB,
R5F10KBCGNA, R5F10KBCGFP, R5F10KGCGNA, R5F10KGCGFB
Cautions 1. The RL78 microcontrollers has an on-chip debug function, which is provided for
development and evaluation. Do not use the on-chip debug function in products
designated for mass production, because the guaranteed number of rewritable times of the
flash memory may be exceeded when this function is used, and product reliability therefore
cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the
on-chip debug function is used.
2. The pins mounted depend on the product.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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2.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C) (1/2)
Parameter Symbols Conditions Ratings Unit
Supply voltage VDD −0.5 to +6.5 V
REGC pin input voltage VIREGC REGC −0.3 to +2.8
and −0.3 to VDD +0.3Note 1
V
UVDD pin input voltage VIUVDD UVDD −0.3 to VDD +0.3 V
Input voltage VI1 P00, P01, P14 to P17, P20 to P27, P30, P31, P40,
P41, P50, P51, P70 to P75, P120 to P124, P137,
P140, EXCLK, EXCLKS, RESET
−0.3 to VDD +0.3Note 2 V
VI2 P60 to P63 (N-ch open-drain) −0.3 to +6.5 V
VI3 UDP0, UDM0, UDP1, UDM1 −0.3 to +6.5 V
VI4 UVBUS −0.3 to +6.5 V
Output voltage VO1 P00, P01, P14 to P17, P20 to P27, P30, P31, P40,
P41, P50, P51, P60 to P63, P70 to P75, P120,
P130, P140
−0.3 to VDD +0.3 Note 2 V
VO2 UDP0, UDM0, UDP1, UDM1 −0.3 to +6.5 V
Analog input voltage VAI1 ANI16, ANI17, ANI19 −0.3 to VDD +0.3
and −0.3 to AVREF (+) +0.3
Notes 2, 3
V
VAI2 ANI0 to ANI7 −0.3 to VDD +0.3
and −0.3 to AVREF (+) +0.3
Notes 2, 3
V
Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F). This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2. Must be 6.5 V or lower.
3. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
2. AVREF (+) : The + side reference voltage of the A/D converter. This can be selected from AVREFP, the
internal reference voltage (1.45 V), and VDD.
3. V
SS : Reference voltage
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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Absolute Maximum Ratings (TA = 25°C) (2/2)
Parameter Symbols Conditions Ratings Unit
Output current, high IOH1 Per pin P00, P01, P14 to P17, P30, P31,
P40, P41, P50, P51, P70 to P75,
P120, P130, P140
−40
Total of all pins
−170 mA
P00, P01, P40, P41, P120,
P130, P140
−70 mA
P14 to P17, P30, P31,
P50, P51, P70 to P75
−100 mA
IOH2 Per pin P20 to P27 −0.5 mA
Total of all pins −2 mA
Output current, low IOL1 Per pin P00, P01, P14 to P17, P30, P31,
P40, P41, P50, P51, P60 to P63,
P70 to P75, P120, P130, P140
40 mA
Total of all pins
170 mA
P00, P01, P40, P41, P120,
P130, P140
70 mA
P14 to P17, P30, P31,
P50, P51, P60 to P63, P70 to P75
100 mA
IOL2 Per pin P20 to P27 1 mA
Total of all pins 5 mA
Operating ambient
temperature
TA In normal operation mode −40 to +85 °C
In flash memory programming mode
Storage temperature Tstg −65 to +150 °C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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2.2 Oscillator Characteristics
2.2.1 X1, XT1 oscillator characteristics
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Resonator Conditions MIN. TYP. MAX. Unit
X1 clock oscillation
frequency (fX)Note
Ceramic resonator/
crystal resonator
2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz
2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz
XT1 clock oscillation
frequency (fXT)Note
Crystal resonator 32 32.768 35 kHz
Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution
time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the
oscillator characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check
the X1 clock oscillation stabilization time using the oscillation stabilization time counter status
register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register
and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the
oscillation stabilization time with the resonator to be used.
2.2.2 On-chip oscillator characteristics
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Oscillators Parameters Conditions MIN. TYP. MAX. Unit
High-speed on-chip oscillator
clock frequency Notes 1, 2
fHOCO 1 48 MHz
High-speed on-chip oscillator
clock frequency accuracy
−20 to +85 °C −1.0 +1.0 %
−40 to −20 °C −1.5 +1.5 %
Low-speed on-chip oscillator
clock frequency
fIL 15 kHz
Low-speed on-chip oscillator
clock frequency accuracy
−15 +15 %
Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and
bits 0 to 2 of HOCODIV register.
2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution
time.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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2.2.3 PLL oscillator characteristics
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Oscillators Parameters Conditions MIN. TYP. MAX. Unit
PLL input frequency Note fPLLIN High-speed system clock 6.00 16.00 MHz
PLL output frequency Note fPLL 48.00 MHz
Lock up time From PLL output enable to stabilization of the
output frequency
40.00 μ s
Interval time From PLL stop to PLL re-operation setteing
Wait time
4.00 μ s
Setting wait time From after PLL input clock stabilization and PLL
setting is fixed to start setting
Wait time required
1.00 μ s
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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2.3 DC Characteristics
2.3.1 Pin characteristics
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output current,
highNote 1
IOH1 Per pin for P00, P01, P14 to P17,
P30, P31, P40, P41, P50, P51, P70 to
P75, P120, P130, P140
2.4 V ≤ VDD ≤ 5.5 V −10.0
Note 2
mA
Total of P00, P01, P40, P41, P120,
P130, P140
(When duty ≤ 70% Note 3)
4.0 V ≤ VDD ≤ 5.5 V −55.0 mA
2.7 V ≤ VDD < 4.0 V −10.0 mA
2.4 V ≤ VDD < 2.7 V −5.0 mA
Total of P14 to P17, P30, P31,
P50, P51, P70 to P75
(When duty ≤ 70% Note 3)
4.0 V ≤ VDD ≤ 5.5 V −80.0 mA
2.7 V ≤ VDD < 4.0 V −19.0 mA
2.4 V ≤ VDD < 2.7 V −10.0 mA
Total of all pins
(When duty ≤ 70%Note 3)
2.4 V ≤ VDD ≤ 5.5 V −135.0 mA
IOH2 Per pin for P20 to P27 2.4 V ≤ VDD ≤ 5.5 V −0.1Not
e 2
mA
Total of all pins
(When duty ≤ 70%Note 3)
2.4 V ≤ VDD ≤ 5.5 V −1.5 mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD
pin to an output pin.
2. However, do not exceed the total current value.
3. Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated
with the following expression (when changing the duty ratio to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOH = −10.0 mA
Total output current of pins = (−10.0 × 0.7)/(80 × 0.01) ≅ −8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Caution P00, P01, P30, and P74 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output current,
lowNote 1
IOL1 Per pin for P00, P01, P14 to P17,
P30, P31, P40, P41, P50, P51,
P70 to P75, P120, P130, P140
2.4V ≤ VDD ≤ 5.5 V 20.0 Note
2
mA
Per pin for P60 to P63 2.4V ≤ VDD ≤ 5.5 V 20.0 Note
2
mA
Total of P00, P01, P40, P41, P120,
P130, P140
(When duty ≤ 70% Note 3)
4.0 V ≤ VDD ≤ 5.5 V 70.0 mA
2.7 V ≤ VDD < 4.0 V 15.0 mA
2.4 V ≤ VDD < 2.7 V 9.0 mA
Total of P14 to P17, P30, P31, P50,
P51, P60 to P63, P70 to P75
(When duty ≤ 70% Note 3)
4.0 V ≤ VDD ≤ 5.5 V 80.0 mA
2.7 V ≤ VDD < 4.0 V 35.0 mA
2.4 V ≤ VDD < 2.7 V 20.0 mA
Total of all pins
(When duty ≤ 70% Note 3)
2.4V ≤ VDD ≤ 5.5 V 150.0 mA
IOL2 Per pin for P20 to P27 2.4V ≤ VDD ≤ 5.5 V 0.4 Note 2 mA
Total of all pins
(When duty ≤ 70%Note 3)
2.4V ≤ VDD ≤ 5.5 V 5.0 mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from an output
pin to the VSS pin.
2. However, do not exceed the total current value.
3. Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated
with the following expression (when changing the duty ratio to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) ≅ 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 24 of 134
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(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Input voltage,
high
VIH1 P00, P01, P14 to P17,
P30, P31, P40, P41, P50, P51, P70
to P75, P120, P140
Normal input buffer
0.8VDD VDD V
VIH2 P00, P01, P30, P50
TTL input buffer
4.0 V
≤
V
DD
≤
5.5 V
2.2 VDD V
TTL input buffer
3.3 V
≤
V
DD
<
4.0 V
2.0 VDD V
TTL input buffer
2.4 V
≤
V
DD
<
3.3 V
1.5 VDD V
VIH3 P20 to P27 0.7VDD VDD V
VIH4 P60 to P63 0.7VDD 6.0 V
VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD VDD V
Input voltage,
low
VIL1 P00, P01, P14 to P17, P30, P31,
P40, P41, P50, P51, P70 to P75,
P120, P140
Normal input buffer
0 0.2VDD V
VIL2 P00, P01, P30, P50
TTL input buffer
4.0 V
≤
V
DD
≤
5.5 V
0 0.8 V
TTL input buffer
3.3 V
≤
V
DD
<
4.0 V
0 0.5 V
TTL input buffer
2.4 V
≤
V
DD
<
3.3 V
0 0.32 V
VIL3 P20 to P27 0 0.3VDD V
VIL4 P60 to P63 0 0.3VDD V
VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2VDD V
Caution The maximum value of VIH of pins P00, P01, P30, and P74 is VDD, even in the N-ch open-drain
mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 25 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output voltage,
high
VOH1 P00, P01, P14 to P17, P30, P31,
P40, P41, P50, P51, P70 to P75,
P120, P130, P140
4.0 V
≤
V
DD
≤
5.5 V,
I
OH1
=
−
10.0 mA
VDD −
1.5
V
4.0 V
≤
V
DD
≤
5.5 V,
I
OH1
=
−
3.0 mA
VDD −
0.7
V
2.7 V
≤
V
DD
≤
5.5 V,
I
OH1
=
−
2.0 mA
VDD −
0.6
V
2.4 V
≤
V
DD
≤
5.5 V,
I
OH1
=
−
1.5 mA
VDD −
0.5
V
VOH2 P20 to P27 2.4 V ≤ VDD ≤ 5.5 V,
IOH2 = −100
μ
A
VDD −
0.5
V
Output voltage,
low
VOL1 P00, P01, P14 to P17, P30, P31,
P40, P41, P50, P51, P70 to P75,
P120, P130, P140
4.0 V
≤
V
DD
≤
5.5 V,
I
OL1
= 20.0 mA
1.3 V
4.0 V
≤
V
DD
≤
5.5 V,
I
OL1
= 8.5 mA
0.7 V
2.7 V
≤
V
DD
≤
5.5 V,
I
OL1
= 3.0 mA
0.6 V
2.7 V
≤
V
DD
≤
5.5 V,
I
OL1
= 1.5 mA
0.4 V
2.4 V
≤
V
DD
≤
5.5 V,
I
OL1
= 0.6 mA
0.4 V
VOL2 P20 to P27 2.4 V ≤ VDD ≤ 5.5 V,
IOL2 = 400
μ
A
0.4 V
VOL3 P60 to P63
4.0 V
≤
V
DD
≤
5.5 V,
I
OL1
= 20.0 mA
2.0 V
4.0 V
≤
V
DD
≤
5.5 V,
I
OL1
= 5.0 mA
0.4 V
2.7 V
≤
V
DD
≤
5.5 V,
I
OL1
= 3.0 mA
0.4 V
2.4 V
≤
V
DD
≤
5.5 V,
I
OL1
= 2.0 mA
0.4 V
Caution P00, P01, P30, and P74 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 26 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Input leakage
current, high
ILIH1 P00, P01, P14 to P17,
P20 to P27, P30, P31,
P40, P41, P50, P51, P60 to
P63, P70 to P75, P120,
P137, P140, RESET
VI = VDD 1
μ
A
ILIH2 P121 to P124
(X1, X2, XT1, XT2, EXCLK,
EXCLKS)
VI = VDD
In input port
or external
clock input
1
μ
A
In resonator
connection
10
μ
A
Input leakage
current, low
ILIL1 P00, P01, P14 to P17,
P20 to P27, P30, P31, P40,
P41, P50, P51, P60 to P63,
P70 to P75, P120, P137, P140,
RESET
VI = VSS −1
μ
A
ILIL2 P121 to P124
(X1, X2, XT1, XT2, EXCLK,
EXCLKS)
VI = VSS
In input port
or external
clock input
−1
μ
A
In resonator
connection
−10
μ
A
On-chip pll-up
resistance
RU P00, P01, P14 to P17,
P30, P31, P40, P41,
P50, P51, P70 to P75, P120,
P140
VI = VSS,
In input port
10 20 100 kΩ
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 27 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
2.3.2 Supply current characteristics
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply
current
Note 1
IDD1 Operating
mode
HS
(High-speed
main) mode
Note 6
fHOCO = 48 MHz
fIH = 24 MHz Note 3
Basic
operation
VDD = 5.0 V 1.7 mA
VDD = 3.0 V 1.7 mA
Normal
operation
VDD = 5.0 V
3.7 5.5 mA
VDD = 3.0 V 3.7 5.5 mA
f
HOCO
= 24 MHz
Note 5
fIH = 12 MHz Note 3
Normal
operation
VDD = 5.0 V
2.3 3.2 mA
VDD = 3.0 V 2.3 3.2 mA
f
HOCO
= 12 MHz
Note 5
fIH = 6 MHz Note 3
Normal
operation
VDD = 5.0 V
1.6 2.0 mA
VDD = 3.0 V 1.6 2.0 mA
fHOCO = 6 MHz Note
5
fIH = 3 MHz Note 3
Normal
operation
VDD = 5.0 V
1.2 1.5 mA
VDD = 3.0 V 1.2 1.5 mA
HS
(High-speed
main) mode
Note 6
f
MX
= 20 MHz
Note 2
,
VDD = 5.0 V
Normal
operation
Square wave input
3.0 4.6 mA
Resonator connection
3.2 4.8 mA
f
MX
= 20 MHz
Note 2
,
VDD = 3.0 V
Normal
operation
Square wave input
3.0 4.6 mA
Resonator connection
3.2 4.8 mA
f
MX
= 10 MHz
Note 2
,
VDD = 5.0 V
Normal
operation
Square wave input
1.9 2.7 mA
Resonator connection
1.9 2.7 mA
f
MX
= 10 MHz
Note 2
,
VDD = 3.0 V
Normal
operation
Square wave input
1.9 2.7 mA
Resonator connection
1.9 2.7 mA
HS
(High-speed
main) mode
(PLL
operation)
Note 6
fPLL = 48 MHz,
fCLK = 24 MHz Note 2
Normal
operation
VDD = 5.0 V
4.0 5.9 mA
VDD = 3.0 V 4.0 5.9 mA
fPLL = 48 MHz,
fCLK = 12 MHz Note 2
Normal
operation
VDD = 5.0 V
2.6 3.6 mA
VDD = 3.0 V 2.6 3.6 mA
fPLL = 48 MHz,
fCLK = 6 MHz Note 2
Normal
operation
VDD = 5.0 V
1.9 2.4 mA
VDD = 3.0 V 1.9 2.4 mA
Subsystem
clock
operation
fSUB = 32.768 kHz
Note 4
TA = −40°C
Normal
operation
Resonator connection
4.1 4.9
μ
A
Square wave input
4.2 5.0
μ
A
fSUB = 32.768 kHz
Note 4
TA = +25°C
Normal
operation
Square wave input
4.1 4.9
μ
A
Resonator connection
4.2 5.0
μ
A
fSUB = 32.768 kHz
Note 4
TA = +50°C
Normal
operation
Square wave input
4.2 5.5
μ
A
Resonator connection
4.3 5.6
μ
A
fSUB = 32.768 kHz
Note 4
TA = +70°C
Normal
operation
Square wave input
4.2 6.3
μ
A
Resonator connection
4.3 6.4
μ
A
fSUB = 32.768 kHz
Note 4
TA = +85°C
Normal
operation
Square wave input
4.8 7.7
μ
A
Resonator connection
4.9 7.8
μ
A
(Notes and Remarks are listed on the next page.)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 28 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD, or VSS. The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip
pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1
(Ultra-low power consumption oscillation). However, not including the current flowing into the RTC,
12-bit interval timer, and watchdog timer.
5. When Operating frequency setting of option byte = 48 MHz. When fHOCO is divided by HOCODIV. When
RDIV[1:0] = 00 (divided by 2: default).
6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
Remarks 1. fHOCO: High-speed on-chip oscillator clock frequency (Max. 48 MHz)
2. fIH: Main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock
by 2, 4, or 8 (Max. 24 MHz)
3. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
4. f
PLL: PLL oscillation frequency
5. f
SUB: Subsystem clock frequency (XT1 clock oscillation frequency)
6. fCLK: CPU/peripheral hardware clock frequency
7. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 29 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply
current
Note 1
IDD2
Note 2
HALT
mode
HS
(High-speed
main) mode
Note 9
fHOCO = 48 MHz
fIH = 24 MHz Note 4
VDD = 5.0 V
0.67 1.25 mA
VDD = 3.0 V 0.67 1.25 mA
fHOCO = 24 MHz Note 7
fIH = 12 MHz Note 4
VDD = 5.0 V
0.50 0.86 mA
VDD = 3.0 V 0.50 0.86 mA
fHOCO = 12 MHz Note 7
fIH = 6 MHz Note 4
VDD = 5.0 V
0.41 0.67 mA
VDD = 3.0 V 0.41 0.67 mA
fHOCO = 6 MHz Note 7
fIH = 3 MHz Note 4
VDD = 5.0 V 0.37 0.58 mA
VDD = 3.0 V 0.37 0.58 mA
HS
(High-speed
main) mode
Note 9
fMX = 20 MHz Note 3,
VDD = 5.0 V
Square wave input
0.28 1.00 mA
Resonator connection
0.45 1.17 mA
fMX = 20 MHz Note 3,
VDD = 3.0 V
Square wave input
0.28 1.00 mA
Resonator connection
0.45 1.17 mA
fMX = 10 MHz Note 3,
VDD = 5.0 V
Square wave input
0.19 0.60 mA
Resonator connection
0.26 0.67 mA
fMX = 10 MHz Note 3,
VDD = 3.0 V
Square wave input
0.19 0.60 mA
Resonator connection
0.26 0.67 mA
HS
(High-speed
main) mode
(PLL
operation)
Note 9
fPLL = 48 MHz,
fCLK = 24 MHz Note 3
VDD = 5.0 V 0.91 1.52 mA
VDD = 3.0 V 0.91 1.52 mA
fPLL = 48 MHz,
fCLK = 12 MHz Note 3
VDD = 5.0 V 0.85 1.28 mA
VDD = 3.0 V 0.85 1.28 mA
fPLL = 48 MHz,
fCLK = 6 MHz Note 3
VDD = 5.0 V 0.82 1.15 mA
VDD = 3.0 V 0.82 1.15 mA
Subsystem
clock
operation
fSUB = 32.768 kHzNote 5
TA = −40°C
Square wave input 0.25 0.57 μA
Resonator
connection
0.44 0.76
μ
A
fSUB = 32.768 kHzNote 5
TA = +25°C
Square wave input 0.30 0.57
μ
A
Resonator
connection
0.49 0.76 μA
fSUB = 32.768 kHzNote 5
TA = +50°C
Square wave input 0.33 1.17
μ
A
Resonator
connection
0.63 1.36
μ
A
fSUB = 32.768 kHzNote 5
TA = +70°C
Square wave input 0.46 1.97 μA
Resonator
connection
0.76 2.16 μA
fSUB = 32.768 kHzNote 5
TA = +85°C
Square wave input 0.97 3.37
μ
A
Resonator
connection
1.16 3.56
μ
A
IDD3Note 6 STOP
mode Note 8
TA = −40°C 0.18 0.50 μA
TA = +25°C 0.23 0.50
μ
A
TA = +50°C 0.26 1.10 μA
TA = +70°C 0.29 1.90
μ
A
TA = +85°C 0.90 3.30
μ
A
(Notes and Remarks are listed on the next page.)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 30 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, LVD circuit, USB 2.0 host/function
module, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and
setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included.
However, not including the current flowing into the 12-bit interval timer and watchdog timer.
6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
7. When Operating frequency setting of option byte = 48 MHz. When fHOCO is divided by HOCODIV. When
RDIV[1:0] = 00 (divided by 2: default).
8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT
mode.
9. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
Remarks 1. f
HOCO: High-speed on-chip oscillator clock frequency (Max. 48 MHz)
2. fIH: Main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock
by 2, 4, or 8 (Max. 24 MHz)
3. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
4. f
PLL: PLL oscillation frequency
5. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
6. f
CLK: CPU/peripheral hardware clock frequency
7. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 31 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low-speed on-chip
oscillator operating
current
IFILNote 1 0.20
μ
A
RTC operating current IRTC
Notes 1, 2, 3
0.02
μ
A
12-bit interval timer
operating current
IIT Notes 1, 2, 4 0.02
μ
A
Watchdog timer
operating current
IWDT
Notes 1, 2, 5
fIL = 15 kHz 0.22
μ
A
A/D converter
operating current
IADC Notes 1,
6
When conversion
at maximum speed
Normal mode, AVREFP = VDD = 5.0 V 1.3 1.7 mA
Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.7 mA
A/D converter reference
voltage current
IADREF Note
1
75.0
μ
A
Temperature sensor
operating current
ITMPS Note 1 75.0
μ
A
LVD operating current ILVD Notes 1,
7
0.08
μ
A
Self-programming
operating current
IFSP Notes 1,
9
2.00 12.20 mA
BGO operating current IBGO Notes 1,
8
2.00 12.20 mA
SNOOZE operating
current
ISNOZ Note 1 ADC operation The mode is performed Note 10 0.50 1.06 mA
The A/D conversion operations are performed,
Low voltage mode, AVREFP = VDD = 3.0 V
1.20 1.62 mA
CSI operation 0.70 0.84 mA
(Notes and Remarks are listed on the next page.)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 32 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
USB operating current IUSBH
Note 11
During USB communication operation under the following settings
and conditions (VDD = 5.0 V, TA = +25°C):
• The internal power supply for the USB is used.
• X1 oscillation frequency (fX) = 12 MHz, PLL oscillation frequency
(fPLL) = 48 MHz
• The host controller (via two ports) is set to operate in full-speed
mode with four pipes (end points) used simultaneously.
(PIPE4: Bulk OUT transfer (64 bytes), PIPE5: Bulk IN transfer (64
bytes), PIPE6: Interrupt OUT transfer, PIPE7: Interrupt IN transfer).
• The USB ports (two ports) are individually connected to a
peripheral function via a 0.5 m USB cable.
9.0 mA
IUSBF
Note 11
During USB communication operation under the following settings
and conditions (VDD = 5.0 V, TA = +25°C):
• The internal power supply for the USB is used.
• X1 oscillation frequency (fX) = 12 MHz, PLL oscillation frequency
(fPLL) = 48 MHz
• The function controller is set to operate in full-speed mode with
four pipes (end points) used simultaneously.
(PIPE4: Bulk OUT transfer (64 bytes), PIPE5: Bulk IN transfer (64
bytes), PIPE6: Interrupt OUT transfer, PIPE7: Interrupt IN transfer).
• The USB port (one port) is connected to the host device via a
0.5 m USB cable.
2.5 mA
ISUSP
Note 12
During suspended state under the following settings and conditions
(VDD = 5.0 V, TA = +25°C):
• The function controller is set to full-speed mode (the UDP0 pin is
pulled up).
• The internal power supply for the USB is used.
• The system is set to STOP mode (When the high-speed on-chip
oscillator, high-speed system clock, and subsystem clock are
stopped. When the watchdog timer is stopped.).
• The USB port (one port) is connected to the host device via a
0.5 m USB cable.
240
μ
A
(Notes and Remarks are listed on the next page.)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 33 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Notes 1. Current flowing to VDD.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed
on-chip ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of
the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT
mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock
operation includes the operational current of the real-time clock.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the
values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT
mode. When the low-speed on-chip oscillator is selected, IFIL should be added.
5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip
oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT
when the watchdog timer is in operation.
6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum
of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
7. Current flowing only to the LVD circuit. The current value of the RL78/G1C is the sum of IDD1, IDD2 or
IDD3 and ILVI when the LVD circuit operates in the Operating, HALT or STOP mode.
8. Current flowing only during data flash rewrite.
9. Current flowing only during self programming.
10. For shift time to the SNOOZE mode.
11. Current consumed only by the USB module and the internal power supply for the USB.
12. Includes the current supplied from the pull-up resistor of the UDP0 pin to the pull-down resistor of the
host device, in addition to the current consumed by this MCU during the suspended state.
Remarks 1. f
IL: Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. f
CLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25°C
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 34 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
2.4 AC Characteristics
2.4.1 Basic operation
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Instruction cycle (minimum
instruction execution time)
TCY Main
system
clock (fMAIN)
operation
HS
(High-speed
main) mode
2.7 V
≤
V
DD
≤
5.5 V
0.04167 1
μ
s
2.4 V
≤
V
DD
<
2.7 V
0.0625 1
μ
s
Subsystem clock (fSUB)
operation
2.4 V
≤
V
DD
≤
5.5 V
28.5 30.5 31.3
μ
s
In the self
programmin
g mode
HS
(High-speed
main) mode
2.7 V
≤
V
DD
≤
5.5 V
0.04167 1
μ
s
2.4 V
≤
V
DD
<
2.7 V
0.0625 1
μ
s
External system clock frequency fEX 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz
2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz
fEXS 32 35 kHz
External system clock input
high-level width, low-level width
tEXH, tEXL 2.7 V ≤ VDD ≤ 5.5 V 24 ns
2.4 V ≤ VDD < 2.7 V 30 ns
tEXHS, tEXLS 13.7
μ
s
TI00 to TI03 input high-level
width, low-level width
tTIH,
tTIL
1/fMCK+10 ns
TO00 to TO03 output frequency fTO High-speed main
mode
4.0 V ≤ VDD ≤ 5.5 V 12 MHz
2.7 V ≤ VDD < 4.0 V 8 MHz
2.4 V ≤ VDD < 2.7 V 4 MHz
PCLBUZ0, PCLBUZ1 output
frequency
fPCL High-speed main
mode
4.0 V ≤ VDD ≤ 5.5 V 16 MHz
2.7 V ≤ VDD < 4.0 V 8 MHz
2.4 V ≤ VDD < 2.7 V 4 MHz
Interrupt input high-level width,
low-level width
tINTH,
tINTL
INTP0 to INTP6,
INTP8, INTP9
2.4 V ≤ VDD ≤ 5.5 V 1
μ
s
Key interrupt input low-level width tKR KR0 to KR5 2.4 V ≤ VDD ≤ 5.5 V 250 ns
RESET low-level width tRSL 10
μ
s
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n =
0 to 3))
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Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
1.0
0.1
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
2.7
0.01
2.4
0.04167
0.0625
0.05
Cycle time TCY [μs]
Supply voltage VDD [V]
When the high-speed on-chip oscillator
clock is selected
During self programming
When high-speed system clock is selected
AC Timing Test Points
V
IH
/V
OH
V
IL
/V
OL
Test points
V
IH
/V
OH
V
IL
/V
OL
External System Clock Timing
EXCLK/EXCLKS
1/f
EX
/
1/f
EXS
t
EXL
/
t
EXLS
t
EXH
/
t
EXHS
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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TI/TO Timing
TI00 to TI03
t
TIL
t
TIH
TO00 to TO03
1/f
TO
Interrupt Request Input Timing
INTP0 to INTP6, INTP8, INTP9
t
INTL
t
INTH
Key Interrupt Input Timing
KR0 to KR5
t
KR
RESET Input Timing
RESET
t
RSL
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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2.5 Peripheral Functions Characteristics
2.5.1 Serial array unit
(1) During communication at same potential (UART mode) (dedicated baud rate generator output)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate fMCK/6 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note
4.0 Mbps
Note The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
User's device
TxDq
RxDq
Rx
Tx
RL78 microcontroller
UART mode bit width (during communication at same potential) (reference)
Baud rate error tolerance
High-/Low-bit width
1/Transfer rate
TxDq
RxDq
Remarks 1. q: UART number (q = 0), g: PIM and POM number (g = 5)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCKp cycle time tKCY1 tKCY1 ≥ 2/fCLK 2.7 V ≤ VDD ≤ 5.5 V 83.3 ns
SCKp high-/low-level width tKH1,
tKL1
4.0 V ≤ VDD ≤ 5.5 V tKCY1/2 − 7 ns
2.7 V ≤ VDD ≤ 5.5 V tKCY1/2 − 10 ns
SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V 23 ns
2.7 V ≤ VDD ≤ 5.5 V 33 ns
SIp hold time (from SCKp↑) Note 2 tKSI1 2.7 V ≤ VDD ≤ 5.5 V 10 ns
Delay time from SCKp↓ to
SOp output Note 3
tKSO1 C = 20 pFNote 3 10 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. This specification is valid only when CSI00’s peripheral I/O redirect function is not used.
2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM numbers (g = 3, 5)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM numbers (g = 0, 3, 5, 7)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 2.7 V ≤ VDD ≤ 5.5 V 167 ns
2.4 V ≤ VDD ≤ 5.5 V 250 ns
SCKp high-/low-level width tKH1,
tKL1
4.0 V ≤ VDD ≤ 5.5 V tKCY1/2 − 12 ns
2.7 V ≤ VDD ≤ 5.5 V tKCY1/2 − 18 ns
2.4 V ≤ VDD ≤ 5.5 V tKCY1/2 − 38 ns
SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V 44 ns
2.7 V ≤ VDD ≤ 5.5 V 44 ns
2.4 V ≤ VDD ≤ 5.5 V 75 ns
SIp hold time (from SCKp↑) Note 2 tKSI1 19 ns
Delay time from SCKp↓ to
SOp output Note 3
tKSO1 C = 30 pFNote 4 25 ns
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCKp cycle time Note 5 tKCY2 4.0 V ≤ VDD ≤ 5.5 V 20 MHz < fMCK 8/fMCK ns
fMCK ≤ 20 MHz 6/fMCK ns
2.7 V ≤ VDD ≤ 5.5 V 16 MHz < fMCK 8/fMCK ns
fMCK ≤ 16 MHz 6/fMCK ns
2.4 V ≤ VDD ≤ 5.5 V 6/fMCK
and 500
ns
SCKp high-/low-level width tKH2,
tKL2
4.0 V ≤ VDD ≤ 5.5 V tKCY2/2 − 7 ns
2.7 V ≤ VDD ≤ 5.5 V tKCY2/2 − 8 ns
2.4 V ≤ VDD ≤ 5.5 V tKCY2/2 −
18
ns
SIp setup time
(to SCKp↑) Note 1
tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK+20 ns
2.4 V ≤ VDD ≤ 5.5 V 1/fMCK+30 ns
SIp hold time
(from SCKp↑) Note 2
tKSI2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK+31 ns
2.4 V ≤ VDD ≤ 5.5 V 1/fMCK+31 ns
Delay time from SCKp↓ to
SOp output Note 3
tKSO2 C = 30 pF Note 4 2.7 V ≤ VDD ≤ 5.5 V 2/fMCK+44 ns
2.4 V ≤ VDD ≤ 5.5 V 2/fMCK+75 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the
SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0),
n: Channel number (n = 0, 1), g: PIM number (g = 0, 3, 5, 7)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
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CSI mode connection diagram (during communication at same potential)
User's device
SCKp
SOp
SCK
SI
SIp SO
RL78 microcontroller
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
SIp Input data
Output data
SOp
t
KCY1, 2
t
KL1, 2
t
KH1, 2
t
SIK1, 2
t
KSI1, 2
t
KSO1, 2
SCKp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
SIp Input data
Output data
SOp
t
KCY1, 2
t
KH1, 2
t
KL1, 2
t
SIK1, 2
t
KSI1, 2
t
KSO1, 2
SCKp
Remarks 1. p: CSI number (p = 00, 01)
2. m: Unit number, n: Channel number (mn = 00, 01)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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(5) During communication at same potential (simplified I2C mode)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. MAX. Unit
SCLr clock frequency fSCL 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
1000 Note 1 kHz
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
400 Note 1 kHz
2.4 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
300 Note 1 kHz
Hold time when SCLr = “L” tLOW 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
475 ns
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1150 ns
2.4 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1550 ns
Hold time when SCLr = “H” tHIGH 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
475 ns
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1150 ns
2.4 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1550 ns
Data setup time (reception) tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 85
Note 2
ns
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1/fMCK + 145
Note 2
ns
2.4 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1/fMCK + 230
Note 2
ns
Data hold time (transmission) tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
0 305 ns
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
0 355 ns
2.4 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
0 405 ns
Notes 1. The value must also be equal to or less than fMCK/4.
2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr
pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and
port output mode register h (POMh).
(Caution and Remarks are listed on the next page.)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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Simplified I2C mode mode connection diagram (during communication at same potential)
User's device
SDAr
SCLr
SDA
SCL
V
DD
R
b
RL78 microcontroller
Simplified I2C mode serial transfer timing (during communication at same potential)
SDAr
tLOW tHIGH
tHD:DAT
SCLr
tSU:DAT
1/fSCL
Remarks 1. Rb[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance
2. r: IIC number (r = 00, 01), g: PIM number (g = 5), h: POM number (h = 3, 5)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number
(m = 0), n: Channel number (n = 0, 1), mn = 00, 01)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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(6) Communication at different potential (2.5 V, 3 V) (UART mode) (1/2)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate reception 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
f
MCK/6Note 1 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 2
4.0 Mbps
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
f
MCK/6Note 1 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 2
4.0 Mbps
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
f
MCK/6Note 1 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 2
4.0 Mbps
Notes 1. Use it with VDD≥Vb.
2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. V
b[V]: Communication line voltage
2. q: UART number (q = 0), g: PIM and POM number (g = 5)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00)
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(6) Communication at different potential (2.5 V, 3 V) (UART mode) (2/2)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate
transmission
4.0 V ≤ VDD ≤ 5.5 V, Note 1 bps
2.7 V ≤ Vb ≤ 4.0 V Theoretical value of the
maximum transfer rate
C
b
= 50 pF, R
b
= 1.4 k
Ω
, V
b
= 2.7 V
2.8
Note 2 Mbps
2.7 V ≤ VDD < 4.0 V Note 3 bps
2.3 V ≤ Vb ≤ 2.7 V Theoretical value of the
maximum transfer rate
C
b
= 50 pF, R
b
= 2.7 k
Ω
, V
b
= 2.3 V
1.2
Note 4 Mbps
2.4 V ≤ VDD < 3.3 V
Notes
5, 6
bps
1.6 V ≤ Vb ≤ 2.0 V Theoretical value of the
maximum transfer rate
C
b
= 50 pF, R
b
= 5.5 k
Ω
, V
b
= 1.6 V
0.43
Note 7
Mbps
Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
Maximum transfer rate = 1 [bps]
{−Cb × Rb × ln (1 − 2.2
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln (1 −
2.2
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
Maximum transfer rate = 1 [bps]
{−Cb × Rb × ln (1 − 2.0
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln
(1 − 2.0
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
5. Use it with VDD ≥ Vb.
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Notes 6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.4 V ≤ VDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
Maximum transfer rate = 1 [bps]
{−Cb × Rb × ln (1 − 1.5
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 1.5
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
7. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
UART mode connection diagram (during communication at different potential)
User's device
TxDq
RxDq
Rx
Tx
V
b
R
b
RL78 microcontroller
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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UART mode bit width (during communication at different potential) (reference)
TxDq
RxDq
Baud rate error tolerance
Baud rate error tolerance
Low-bit width
High-/Low-bit width
High-bit width
1/Transfer rate
1/Transfer rate
Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load
capacitance, Vb[V]: Communication line voltage
2. q: UART number (q = 0), g: PIM and POM number (g = 5)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
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(7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCKp cycle time tKCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
200 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
300 ns
SCKp high-level width tKH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
tKCY1/2 − 50 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
tKCY1/2 −
120
ns
SCKp low-level width tKL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
tKCY1/2 − 7 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
tKCY1/2 − 10 ns
SIp setup time
(to SCKp↑) Note 1
tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
58 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
121 ns
SIp hold time
(from SCKp↑) Note 1
tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
10 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
10 ns
Delay time from SCKp↓ to
SOp output Note 1
tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
60 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
130 ns
SIp setup time
(to SCKp↓) Note 2
tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
23 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
33 ns
SIp hold time
(from SCKp↓) Note 2
tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
10 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
10 ns
Delay time from SCKp↑ to
SOp output Note 2
tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
10 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
10 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
(Caution and Remark are listed on the next page.)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 49 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM number (g = 3, 5)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00)
4. This value is valid only when CSI00’s peripheral I/O redirect function is not used.
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(1/2)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
300 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
500 ns
2.4 V ≤ VDD < 3.3 V,
2.4 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
1150 ns
SCKp high-level width tKH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
tKCY1/2 − 75 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 −
170
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 −
458
ns
SCKp low-level width tKL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
tKCY1/2 − 12 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 − 18 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 − 50 ns
Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance)
mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port
output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input
buffer selected.
2. Use it with VDD ≥ Vb.
(Remarks are listed two pages after the next page.)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 50 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(2/2)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SIp setup time
(to SCKp↑) Note 1
tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
81 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
177 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
479 ns
SIp hold time
(from SCKp↑) Note 1
tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
19 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
19 ns
Delay time from SCKp↓ to
SOp output Note 1
tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
100 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
195 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
483 ns
SIp setup time
(to SCKp↓) Note 2
tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
44 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
44 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
110 ns
SIp hold time
(from SCKp↓) Note 2
tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
19 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
19 ns
Delay time from SCKp↑ to
SOp output Note 2
tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
25 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
25 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
25 ns
(Notes, Cautions and Remarks are listed on the next page.)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 51 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3 Use it with VDD ≥ Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode
for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
V
b
R
b
User's device
<Master>
SCKp
SOp
SCK
SI
SIp SO
V
b
R
b
RL78 microcontroller
Remarks 1. R
b[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g =
0, 3, 5, 7)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
4. CSI01 cannot communicate at different potential. Use other CSI for communication at different
potential.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 52 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
SIp Input data
Output dataSOp
t
KCY1
t
KL1
t
KH1
t
SIK1
t
KSI1
t
KSO1
SCKp
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
SIp Input data
Output data
SOp
t
KCY1
t
KL1
t
KH1
t
SIK1
t
KSI1
t
KSO1
SCKp
Remarks 1. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g
= 0, 3, 5, 7)
2. CSI01 cannot communicate at different potential. Use other CSI for communication at different
potential.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 53 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCKp cycle time Note 1 tKCY2
4.0 V
≤
V
DD
≤
5.5 V,
2.7 V
≤
V
b
≤
4.0 V
20 MHz < fMCK ≤ 24 MHz 12/fMCK ns
8 MHz < fMCK ≤ 20 MHz 10/fMCK ns
4 MHz < fMCK ≤ 8 MHz 8/fMCK ns
fMCK ≤ 4 MHz 6/fMCK ns
2.7 V
≤
V
DD
< 4.0 V,
2.3 V
≤
V
b
≤
2.7 V
20 MHz < fMCK ≤ 24 MHz 16/fMCK ns
16 MHz < fMCK ≤ 20 MHz 14/fMCK ns
8 MHz < fMCK ≤ 16 MHz 12/fMCK ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK ns
fMCK ≤ 4 MHz
6/fMCK ns
2.4 V
≤
V
DD
< 3.3 V,
1.6 V
≤
V
b
≤
2.0 V
Note
2
20 MHz < fMCK ≤ 24 MHz 36/fMCK ns
16 MHz < fMCK ≤ 20 MHz 32/fMCK ns
8 MHz < fMCK ≤ 16 MHz 26/fMCK ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK ns
fMCK ≤ 4 MHz
10/fMCK ns
SCKp high-/low-level
width
tKH2,
tKL2
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
t
KCY2/2 −
12
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
t
KCY2/2 −
18
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2
t
KCY2/2 −
50
ns
SIp setup time
(to SCKp↑) Note 3
tSIK2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK +
20
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK +
20
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 1/fMCK +
30
ns
SIp hold time
(from SCKp↑) Note 4
tKSI2 1/fMCK + 31 ns
Delay time from SCKp↓ to
SOp output Note 5
tKSO2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2/fMCK +
120
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK +
214
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK +
573
ns
Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. Use it with VDD ≥ Vb.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
(Caution and Remarks are listed on the next page.)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 54 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
User's device
<Slave>
SCKp
SOp
SCK
SI
SIp SO
V
b
R
b
RL78 microcontroller
Remarks 1. R
b[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g
= 0, 3, 5, 7)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
4. CSI01 cannot communicate at different potential. Use other CSI for communication at different
potential.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 55 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
SIp Input data
Output data
SOp
tKCY2
tKL2 tKH2
tSIK2 tKSI2
tKSO2
SCKp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
SIp Input data
Output data
SOp
t
KCY2
t
KL2
t
KH2
t
SIK2
t
KSI2
t
KSO2
S
CKp
Remarks 1. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00),
g: PIM and POM number (g = 0, 3, 5, 7)
2. CSI01 cannot communicate at different potential. Use other CSI for communication at different
potential.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 56 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. MAX. Unit
SCLr clock frequency fSCL 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
1000 Note 1 kHz
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1000 Note 1 kHz
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
400 Note 1 kHz
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
400 Note 1 kHz
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
300 Note 1 kHz
Hold time when SCLr = “L” tLOW 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
475 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
475 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
1150 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1150 ns
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
1550 ns
Hold time when SCLr = “H” tHIGH 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
245 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
200 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
675 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
600 ns
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
610 ns
(Notes, Caution and Remarks are listed on the next page.)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 57 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. MAX. Unit
Data setup time (reception) tSU:DAT 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 135
Note 3
ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 135
Note 3
ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
1/fMCK + 190
Note 3
ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1/fMCK + 190
Note 3
ns
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Notes 2,
Cb = 100 pF, Rb = 5.5 kΩ
1/fMCK + 190
Note 3
ns
Data hold time (transmission) tHD:DAT 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
0 305 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
0 305 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
0 355 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
0 355 ns
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
0 405 ns
Notes 1. The value must also be equal to or less than fMCK/4.
2. Use it with VDD ≥ Vb.
3. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin
and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 58 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Simplified I2C mode connection diagram (during communication at different potential)
User's device
SDAr
SCLr
SDA
SCL
V
b
R
b
V
b
R
b
RL78 microcontroller
Simplified I2C mode serial transfer timing (during communication at different potential)
SDAr
tLOW tHIGH
tHD:DAT
SCLr
tSU:DAT
1/fSCL
Remarks 1. R
b[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr)
load capacitance, Vb[V]: Communication line voltage
2. r: IIC number (r = 00), g: PIM, POM number (g = 0, 3, 5, 7)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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2.5.2 Serial interface IICA
(1) I2C standard mode
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
SCLA0 clock frequency fSCL
Standard mode: f
CLK
≥
1
MHz
2.7 V ≤ VDD ≤ 5.5 V 0 100 kHz
2.4 V ≤ VDD ≤ 5.5 V 0 100 kHz
Setup time of restart condition tSU:STA 2.7 V ≤ VDD ≤ 5.5 V 4.7
μ
s
2.4 V ≤ VDD ≤ 5.5 V 4.7
μ
s
Hold timeNote 1 tHD:STA 2.7 V ≤ VDD ≤ 5.5 V 4.0
μ
s
2.4 V ≤ VDD ≤ 5.5 V 4.0
μ
s
Hold time when SCLA0 = “L” tLOW 2.7 V ≤ VDD ≤ 5.5 V 4.7
μ
s
2.4 V ≤ VDD ≤ 5.5 V 4.7
μ
s
Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ VDD ≤ 5.5 V 4.0
μ
s
2.4 V ≤ VDD ≤ 5.5 V 4.0
μ
s
Data setup time (reception) tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V 250
μ
s
2.4 V ≤ VDD ≤ 5.5 V 250
μ
s
Data hold time
(transmission)Note 2
tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V 0 3.45
μ
s
2.4 V ≤ VDD ≤ 5.5 V 0 3.45
μ
s
Setup time of stop condition tSU:STO 2.7 V ≤ VDD ≤ 5.5 V 4.0
μ
s
2.4 V ≤ VDD ≤ 5.5 V 4.0
μ
s
Bus-free time tBUF 2.7 V ≤ VDD ≤ 5.5 V 4.7
μ
s
2.4 V ≤ VDD ≤ 5.5 V 4.7
μ
s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution The values in the above table are applied even when bit 1 (PIOR1) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the
values in the redirect destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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(2) I2C fast mode
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCLA0 clock frequency fSCL Fast mode: fCLK ≥ 3.5
MHz
2.7 V ≤ VDD ≤ 5.5 V 0 400 kHz
2.4 V ≤ VDD ≤ 5.5 V 0 400 kHz
Setup time of restart condition tSU:STA 2.7 V ≤ VDD ≤ 5.5 V 0.6
μ
s
2.4 V ≤ VDD ≤ 5.5 V 0.6
μ
s
Hold timeNote 1 tHD:STA 2.7 V ≤ VDD ≤ 5.5 V 0.6
μ
s
2.4 V ≤ VDD ≤ 5.5 V 0.6
μ
s
Hold time when SCLA0 = “L” tLOW 2.7 V ≤ VDD ≤ 5.5 V 1.3
μ
s
2.4 V ≤ VDD ≤ 5.5 V 1.3
μ
s
Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ VDD ≤ 5.5 V 0.6
μ
s
2.4 V ≤ VDD ≤ 5.5 V 0.6
μ
s
Data setup time (reception) tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V 100 ns
2.4 V ≤ VDD ≤ 5.5 V 100 ns
Data hold time
(transmission)Note 2
tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V 0 0.9
μ
s
2.4 V ≤ VDD ≤ 5.5 V 0 0.9
μ
s
Setup time of stop condition tSU:STO 2.7 V ≤ VDD ≤ 5.5 V 0.6
μ
s
2.4 V ≤ VDD ≤ 5.5 V 0.6
μ
s
Bus-free time tBUF 2.7 V ≤ VDD ≤ 5.5 V 1.3
μ
s
2.4 V ≤ VDD ≤ 5.5 V 1.3
μ
s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution The values in the above table are applied even when bit 1 (PIOR1) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the
values in the redirect destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Fast mode: Cb = 320 pF, Rb = 1.1 kΩ
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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(3) I2C fast mode plus
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCLA0 clock frequency fSCL Fast mode plus:
fCLK ≥ 10 MHz
2.7 V ≤ VDD ≤ 5.5 V 0 1000 kHz
Setup time of restart condition tSU:STA 2.7 V ≤ VDD ≤ 5.5 V 0.26
μ
s
Hold timeNote 1 tHD:STA 2.7 V ≤ VDD ≤ 5.5 V 0.26
μ
s
Hold time when SCLA0 = “L” tLOW 2.7 V ≤ VDD ≤ 5.5 V 0.5
μ
s
Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ VDD ≤ 5.5 V 0.26
μ
s
Data setup time (reception) tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V 50 ns
Data hold time
(transmission)Note 2
tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V 0 0.45
μ
s
Setup time of stop condition tSU:STO 2.7 V ≤ VDD ≤ 5.5 V 0.26
μ
s
Bus-free time tBUF 2.7 V ≤ VDD ≤ 5.5 V 0.5
μ
s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution The values in the above table are applied even when bit 1 (PIOR1) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the
values in the redirect destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ
IICA serial transfer timing
tLOW
tLOW
tHIGH
tHD:STA
Stop
condition Start
condition Restart
condition Stop
condition
tSU:DAT
tSU:STA tSU:STOtHD:STA
tHD:DAT
SCLA0
SDAA0
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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2.5.3 USB
(1) Electrical specifications
(TA = −40 to +85°C, 3.0 V ≤ UVDD ≤ 3.6 V, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
UVDD
UVDD input voltage
characteristic
UVDD VDD = 3.0 to 5.5 V, PXXCON = 1,
VDDUSEB = 0 (UVDD ≤ VDD)
3.0 3.3 3.6 V
UVDD output voltage
characteristic
UVDD VDD = 4.0 to 5.5 V,
PXXCON = VDDUSEB = 1
3.0 3.3 3.6 V
UVBUS UVBUS input voltage
characteristic
UVBUS Function 4.35
(4.02Note)
5.00 5.25 V
Host 4.75 5.00 5.25 V
Note Value of instantaneous voltage
(TA = −40 to +85°C, 3.0 V ≤ UVDD ≤ 3.6 V, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
UDPi/UDMi
pins input
characteristic
(FS/LS
receiver)
Input voltage
VIH 2.0 V
VIL 0.8 V
Difference input
sensitivity
VDI | UDP voltage − UDM voltage | 0.2 V
Difference
common mode
range
VCM 0.8 2.5 V
UDPi/UDMi
pins output
characteristic
(FS driver)
Output voltage VOH IOH = −200
μ
A 2.8 3.6 V
VOL IOL = 2.4 mA 0 0.3 V
Transi-ti
on time
Rising tFR Rising: From 10% to 90 % of
amplitude,
Falling: From 90% to 10 % of
amplitude,
CL = 50 pF
4 20 ns
Falling tFF 4 20 ns
Matching
(TFR/TFF)
VFRFM 90 111.1 %
Crossover voltage VFCRS 1.3 2.0 V
Output
Impedance
ZDRV UVDD voltage = 3.3 V,
Pin voltage = 1.65 V
28 44 Ω
UDPi/UDMi
pins output
characteristic
(LS driver)
Output voltage VOH 2.8 3.6 V
VOL 0 0.3 V
Transi-ti
on time
Rising tLR Rising: From 10% to 90 % of
amplitude,
Falling: From 90% to 10 % of
amplitude,
CL = 200 to 600 pF
When the host controller function is
selected: The UDMi pin (i = 0, 1) is
pulled up via 1.5 kΩ.
When the function controller
function is selected: The UDP0 and
UDM0 pins are individually pulled
down via 15 kΩ
75 300 ns
Falling tLF 75 300 ns
Matching
(TFR/TFF) Note
VLTFM 80 125 %
Crossover voltage
Note
VLCRS 1.3 2.0 V
UDPi/UDMi
pins pull-up,
pull-down
Pull-down resistor RPD 14.25 24.80 kΩ
Pull-up
resistor
(i = 0
only)
Idle RPUI 0.9 1.575 kΩ
Recep-t
ion
RPUA 1.425 3.09 kΩ
UVBUS UVBUS pull-down
resistor
RVBUS UVBUS voltage = 5.5 V 1000 kΩ
UVBUS input
voltage
VIH 3.20 V
VIL 0.8 V
Note Excludes the first signal transition from the idle state.
Remark i = 0, 1
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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Timing of UDPi and UDMi
UDPi
UDMi
90 %
90 %
10 % 10 %
V
CRS
(Crossover voltage)
t
R
t
F
(2) BC standard
(TA = −40 to +85°C, 3.0 V ≤ UVDD ≤ 3.6 V, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
USB
standard
BC1.2
UDPi sink current IDP_SINK 25 175
μ
A
UDMi sink current IDM_SINK 25 175
μ
A
DCD source current IDP_SRC 7 13
μ
A
Dedicated charging
port resistor
RDCP_DAT 0 V < UDP/UDM voltage < 1.0 V 200 Ω
Data detection voltage VDAT_REF 0.25 0.4 V
UDPi source voltage VDP_SRC Output current 250
μ
A 0.5 0.7 V
UDMi source voltage VDM_SRC Output current 250
μ
A 0.5 0.7 V
Remark i = 0, 1
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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R01DS0348EJ0120 Rev.1.20
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(3) BC option standard (Host)
(TA = −40 to +85°C, 4.75 V ≤ UVBUS ≤ 5.25 V, 3.0 V ≤ UVDD ≤ 3.6 V, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
UDPi output
voltage
(UVBUS divider
ratio)
• VDOUEi = 1
VDSELi
[3:0]
(i = 0, 1)
1000 VP20 38 40 42 % UVBUS
1001 VP27 51.6 53.6 55.6 % UVBUS
1010 VP20 38 40 42 % UVBUS
1100 VP33 60 66 72 % UVBUS
UDMi output
voltage
(UVBUS divider
ratio)
• VDOUEi = 1
VDSELi
[3:0]
(i = 0, 1)
1000 VM20 38 40 42 % UVBUS
1001 VM20 38 40 42 % UVBUS
1010 VM27 51.6 53.6 55.6 % UVBUS
1100 VM33 60 66 72 % UVBUS
UDPi
comparing
voltage Note 1
(UVBUS divider
ratio)
• VDOUEi = 1
•
CUSDETEi = 1
VDSELi
[3:0]
(i = 0, 1)
1000 VHDETP_UP0 The rise of pin voltage detection voltage 56.2 % UVBUS
VHDETP_DWN0 The fall of pin voltage detection voltage 29.4 % UVBUS
1001 VHDETP_UP1 The rise of pin voltage detection voltage 60.5 % UVBUS
VHDETP_DWN1 The fall of pin voltage detection voltage 45.0 % UVBUS
1010 VHDETP_UP2 The rise of pin voltage detection voltage 56.2 % UVBUS
VHDETP_DWN2 The fall of pin voltage detection voltage 29.4 % UVBUS
UDMi
comparing
voltage Note 1
(UVBUS divider
ratio)
• VDOUEi = 1
•
CUSDETEi = 1
VDSELi
[3:0]
(i = 0, 1)
1000 VHDETM_UP0 The rise of pin voltage detection voltage 56.2 % UVBUS
VHDETM_DWN0 The fall of pin voltage detection voltage 29.4 % UVBUS
1001 VHDETM_UP1 The rise of pin voltage detection voltage 56.2 % UVBUS
VHDETM_DWN1 The fall of pin voltage detection voltage 29.4 % UVBUS
1010 VHDETM_UP2 The rise of pin voltage detection voltage 60.5 % UVBUS
VHDETM_DWN2 The fall of pin voltage detection voltage 45.0 % UVBUS
UDPi pull-up detection
Note 2
Connect detection with
the full speed function
(pull-up resistor)
1000 RHDET_PULL In full-speed mode, the power supply
voltage range of pull-up resistors
connected to the USB function
module is between 3.0 V and 3.6 V.
1.575 kΩ
1001
1010
UDMi pull-up detection
Note 2
Connect detection with
the low-speed (pull-up
resistor)
1000 RHDET_PULL In low-speed mode, the power supply
voltage range of pull-up resistors
connected to the USB function
module is between 3.0 V and 3.6 V.
1.575 kΩ
1001
1010
UDMi sink current
detection Note 2
Connect detection with
the BC1.2 portable
device (sink resistor)
1000 IHDET_SINK 25
μ
A
1001
1010
Notes 1. If the voltage output from UDPi or UDMi (i = 0, 1) exceeds the range of the MAX and MIN values prescribed
in this specification, DPCUSDETi (bit 8) and DMCUSDETi (bit 9) of the USBBCOPTi register are set to 1.
2. If the pull-up resistance or sink current prescribed in this specification is applied to UDPi or UDMi (i = 0,
1), DPCUSDETi (bit 8) and DMCUSDETi (bit 9) of the USBBCOPTi register are set to 1.
Remark i = 0, 1
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 65 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(4) BC option standard (Function)
(TA = −40 to +85°C, 4.35 V ≤ UVBUS ≤ 5.25 V, 3.0 V ≤ UVDD ≤ 3.6 V, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
UDPi/UDMi
input
reference
voltage
(UVBUS divider
ratio)
• VDOUEi = 0
(i = 0))
VDSELi
[3:0]
(i = 0)
0000 VDDET0 27 32 37 % UVBUS
0001 VDDET1 29 34 39 % UVBUS
0010 VDDET2 32 37 42 % UVBUS
0011 VDDET3 35 40 45 % UVBUS
0100 VDDET4 38 43 48 % UVBUS
0101 VDDET5 41 46 51 % UVBUS
0110 VDDET6 44 49 54 % UVBUS
0111 VDDET7 47 52 57 % UVBUS
1000 VDDET8 51 56 61 % UVBUS
1001 VDDET9 55 60 65 % UVBUS
1010 VDDET10 59 64 69 % UVBUS
1011 VDDET11 63 68 73 % UVBUS
1100 VDDET12 67 72 77 % UVBUS
1101 VDDET13 71 76 81 % UVBUS
1110 VDDET14 75 80 85 % UVBUS
1111 VDDET15 79 84 89 % UVBUS
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 66 of 134
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2.6 Analog Characteristics
2.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Input channel Reference Voltage
Reference voltage (+) =
AVREFP
Reference voltage (−) =
AVREFM
Reference voltage (+) = VDD
Reference voltage (−) = VSS
Reference voltage (+) =
VBGR
Reference voltage (−) =
AVREFM
ANI0 to ANI7 Refer to 2.6.1 (1). Refer to 2.6.1 (3). Refer to 2.6.1 (4).
ANI16, ANI17, ANI19 Refer to 2.6.1 (2).
Internal reference voltage
Temperature sensor output
voltage
Refer to 2.6.1 (1). −
(1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM
= 1), target pin : ANI2 to ANI7, internal reference voltage, and temperature sensor output voltage
(TA = −40 to +85°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−)
= AVREFM = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 10 bit
Overall errorNote 1 AINL
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ VDD ≤ 5.5 V 1.2 ±3.5 LSB
Conversion time tCONV 10-bit resolution
Target pin: ANI2 to
ANI7
3.6 V ≤ VDD ≤ 5.5 V 2.125 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
10-bit resolution
Target pin: Internal
reference voltage,
and temperature
sensor output voltage
(HS (high-speed
main) mode)
3.6 V ≤ VDD ≤ 5.5 V 2.375 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.5625 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ VDD ≤ 5.5 V ±0.25 %FSR
Full-scale errorNotes 1, 2 EFS
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ VDD ≤ 5.5 V ±0.25 %FSR
Integral linearity errorNote 1 ILE
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ VDD ≤ 5.5 V ±2.5 LSB
Differential linearity error Note 1 DLE
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ VDD ≤ 5.5 V ±1.5 LSB
Analog input voltage VAIN ANI2 to ANI7 0 AVREFP V
Internal reference voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main)
mode)
VBGR Note 4 V
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main)
mode)
VTMPS25 Note 4 V
(Notes are listed on the next page.)
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
Page 67 of 134
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Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
4. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) =
AVREFM/ANI1 (ADREFM = 1), target pin : ANI16, ANI17, ANI19
(TA = −40 to +85°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage
(−) = AVREFM = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 10 bit
Overall errorNote 1 AINL
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ VDD ≤ 5.5 V 1.2 ±5.0 LSB
Conversion time tCONV 10-bit resolution
Target ANI pin :
ANI16, ANI17, ANI19
3.6 V ≤ VDD ≤ 5.5 V 2.125 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ VDD ≤ 5.5 V ±0.35 %FSR
Full-scale errorNotes 1, 2 EFS
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ VDD ≤ 5.5 V ±0.35 %FSR
Integral linearity errorNote 1 ILE
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ VDD ≤ 5.5 V ±3.5 LSB
Differential linearity error Note 1 DLE
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ VDD ≤ 5.5 V ±2.00 LSB
Analog input voltage VAIN ANI16, ANI17, ANI19 0 AVREFP
and VDD
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.
RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C)
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(3) Reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), Reference voltage (−) = VSS (ADREFM = 0),
target ANI pin : ANI0 to ANI7, ANI16, ANI17, ANI19, internal reference voltage, and temperature sensor
output voltage
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 10 bit
Overall errorNotes 1, 2 AINL 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 1.2 ±7.0 LSB
Conversion time tCONV 10-bit resolution
Target ANI pin :
ANI0 to ANI7, ANI16,
ANI17, ANI19
3.6 V ≤ VDD ≤ 5.5 V 2.125 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
10-bit resolution
Target ANI pin : Internal
reference voltage, and
temperature sensor
output voltage (HS
(high-speed main) mode)
3.6 V ≤ VDD ≤ 5.5 V 2.375 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.5625 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS
10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR
Full-scale errorNotes 1, 2 EFS
10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR
Integral linearity errorNote 1 ILE 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±4.0 LSB
Differential linearity error Note 1 DLE 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB
Analog input voltage VAIN ANI0 to ANI7, ANI16, ANI17, ANI19 0 VDD V
Internal reference voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main)
mode)
VBGR Note 3 V
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main)
mode)
VTMPS25 Note 3 V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
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(4) When Reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), Reference
voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0 to ANI7, ANI16, ANI17, ANI19
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (−) =
AVREFM Note 4 = 0 V, HS (high-speed main) mode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 Bit
Conversion time tCONV 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR
Integral linearity errorNote 1 ILE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB
Differential linearity error Note 1 DLE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±1.0 LSB
Analog input voltage VAIN 0 VBGR Note 3 V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
4. When reference voltage (−) = VSS, the MAX. values are as follows.
Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (−) = AVREFM.
Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (−) = AVREFM.
Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (−) = AVREFM.
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2.6.2 Temperature sensor/internal reference voltage characteristics
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C 1.05 V
Internal reference voltage VBGR Setting ADS register = 81H 1.38 1.45 1.5 V
Temperature coefficient FVTMPS Temperature sensor that depends on the
temperature
−3.6 mV/°C
Operation stabilization wait time tAMP 5
μ
s
2.6.3 POR circuit characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOR Power supply rise time 1.47 1.51 1.55 V
VPDR Power supply fall time 1.46 1.50 1.54 V
Minimum pulse widthNote TPW 300
μ
s
Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time
required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is
entered or the main system clock (fMAIN) is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the
clock operation status control register (CSC).
T
PW
V
POR
V
PDR
or 0.7 V
Supply voltage (V
DD
)
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2.6.4 LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection
voltage
Supply voltage level VLVD0 Power supply rise time 3.98 4.06 4.14 V
Power supply fall time 3.90 3.98 4.06 V
VLVD1 Power supply rise time 3.68 3.75 3.82 V
Power supply fall time 3.60 3.67 3.74 V
VLVD2 Power supply rise time 3.07 3.13 3.19 V
Power supply fall time 3.00 3.06 3.12 V
VLVD3 Power supply rise time 2.96 3.02 3.08 V
Power supply fall time 2.90 2.96 3.02 V
VLVD4 Power supply rise time 2.86 2.92 2.97 V
Power supply fall time 2.80 2.86 2.91 V
VLVD5 Power supply rise time 2.76 2.81 2.87 V
Power supply fall time 2.70 2.75 2.81 V
VLVD6 Power supply rise time 2.66 2.71 2.76 V
Power supply fall time 2.60 2.65 2.70 V
VLVD7 Power supply rise time 2.56 2.61 2.66 V
Power supply fall time 2.50 2.55 2.60 V
VLVD8 Power supply rise time 2.45 2.50 2.55 V
Power supply fall time 2.40 2.45 2.50 V
Minimum pulse width tLW 300
μ
s
Detection delay time tLD 300
μ
s
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LVD Detection Voltage of Interrupt & Reset Mode
(TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Interrupt and reset
mode
VLVDC0 VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 V
VLVDC1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.56 2.61 2.66 V
Falling interrupt voltage 2.50 2.55 2.60 V
VLVDC2 LVIS1, LVIS0 = 0, 1
Rising release reset voltage 2.66 2.71 2.76 V
Falling interrupt voltage 2.60 2.65 2.70 V
VLVDC3 LVIS1, LVIS0 = 0, 0
Rising release reset voltage 3.68 3.75 3.82 V
Falling interrupt voltage 3.60 3.67 3.74 V
VLVDD0 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 V
VLVDD1 LVIS1, LVIS0 = 1, 0
Rising release reset voltage 2.86 2.92 2.97 V
Falling interrupt voltage 2.80 2.86 2.91 V
VLVDD2 LVIS1, LVIS0 = 0, 1
Rising release reset voltage 2.96 3.02 3.08 V
Falling interrupt voltage 2.90 2.96 3.02 V
VLVDD3 LVIS1, LVIS0 = 0, 0
Rising release reset voltage 3.98 4.06 4.14 V
Falling interrupt voltage 3.90 3.98 4.06 V
2.6.5 Power supply voltage rising slope characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Power supply voltage rising slope SVDD 54 V/ms
Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD
reaches the operating voltage range shown in 30.4 AC Characteristics.
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2.7 RAM Data Retention Characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 1.46Note 5.5 V
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a
POR reset is effected, but data is not retained when a POR reset is effected.
V
DD
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
RAM data retention
V
DDDR
Operation mod
e
2.8 Flash Memory Programming Characteristics
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
CPU/peripheral hardware clock
frequency
fCLK 2.4 V ≤ VDD ≤ 5.5 V 1 24 MHz
Number of code flash rewrites Cerwr Retaining years: 20 years
TA = +85°C
1,000 Times
Number of data flash rewrites
Notes 1, 2, 3
Retaining years: 1 year
TA = +25°C
1,000,000
Retaining years: 5 years
TA = +85°C
100,000
Retaining years: 20 years
TA = +85°C
10,000
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after
the rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library.
3. These specifications show the characteristics of the flash memory and the results obtained from
Renesas Electronics reliability testing.
2.9 Dedicated Flash Memory Programmer Communication (UART)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate During serial programming 115,200 1,000,000 bps
<R>
<R>
<R>
<R>
<R>
<R>
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2.10 Timing Specs for Switching Flash Memory Programming Modes
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
How long from when an external
reset ends until the initial
communication settings are
specified
tSUINIT POR and LVD reset must end before the
external reset ends.
100 ms
How long from when the TOOL0
pin is placed at the low level until
an external reset ends
tSU POR and LVD reset must end before the
external reset ends.
10
μ
s
How long the TOOL0 pin must be
kept at the low level after an
external reset ends
(excluding the processing time of
the firmware to control the flash
memory)
tHD POR and LVD reset must end before the
external reset ends.
1 ms
RESET
TOOL0
<1> <2> <3>
t
SUINIT
723 μs + t
HD
processing
time
t
SU
<4>
00H reception
(TOOLRxD, TOOLTxD mode)
<1> The low level is input to the TOOL0 pin.
<2> The external reset ends (POR and LVD reset must end before the external reset
ends.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete
the baud rate setting.
Remark t
SUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within
100 ms from when the resets end.
tSU: How long from when the TOOL0 pin is placed at the low level until an external reset ends
tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end
(excluding the processing time of the firmware to control the flash memory)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
This chapter describes the electrical specifications for the products "G: Industrial applications (TA = -40 to
+105°C)".
The target products G: Industrial applications ; TA = -40 to +105°C
R5F10JBCGNA, R5F10JBCGFP, R5F10JGCGNA, R5F10JGCGFB,
R5F10KBCGNA, R5F10KBCGFP, R5F10KGCGNA, R5F10KGCGFB
Cautions 1. The RL78 microcontrollers has an on-chip debug function, which is provided for
development and evaluation. Do not use the on-chip debug function in products
designated for mass production, because the guaranteed number of rewritable times of the
flash memory may be exceeded when this function is used, and product reliability therefore
cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the
on-chip debug function is used.
2. The pins mounted depend on the product.
3. Please contact Renesas Electronics sales office for derating of operation under TA = +85°C
to +105°C. Derating is the systematic reduction of load for the sake of improved reliability.
There are following differences between the products "G: Industrial applications (TA = -40 to +105°C)" and the
products “A: Consumer applications”.
Parameter Application
A: Consumer applications G: Industrial applications
Operating ambient temperature TA = -40 to +85°C TA = -40 to +105°C
High-speed on-chip oscillator clock
accuracy
2.4 V ≤ VDD ≤ 5.5 V
±1.0%@ TA = -20 to +85°C
±1.5%@ TA = -40 to -20°C
2.4 V ≤ VDD ≤ 5.5 V
±2.0%@ TA = +85 to +105°C
±1.0%@ TA = -20 to +85°C
±1.5%@ TA = -40 to -20°C
Serial array unit UART
CSI: fCLK/2 (supporting 16 Mbps), fCLK/4
Simplified I2C communication
UART
CSI: fCLK/4
Simplified I2C communication
IICA Normal mode
Fast mode
Fast mode plus
Normal mode
Fast mode
Remark The electrical characteristics of the products G: Industrial applications (TA = -40 to +105°C) are different
from those of the products “A: Consumer applications”. For details, refer to 3.1 to 3.10.
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3.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C) (1/2)
Parameter Symbols Conditions Ratings Unit
Supply voltage VDD −0.5 to +6.5 V
REGC pin input voltage VIREGC REGC −0.3 to +2.8
and −0.3 to VDD +0.3Note 1
V
UVDD pin input voltage VIUVDD UVDD −0.3 to VDD +0.3 V
Input voltage VI1 P00, P01, P14 to P17, P20 to P27, P30, P31, P40,
P41, P50, P51, P70 to P75, P120 to P124, P137,
P140, EXCLK, EXCLKS, RESET
−0.3 to VDD +0.3Note 2 V
VI2 P60 to P63 (N-ch open-drain) −0.3 to +6.5 V
VI3 UDP0, UDM0, UDP1, UDM1 −0.3 to +6.5 V
VI4 UVBUS −0.3 to +6.5 V
Output voltage VO1 P00, P01, P14 to P17, P20 to P27, P30, P31, P40,
P41, P50, P51, P60 to P63, P70 to P75, P120,
P130, P140
−0.3 to VDD +0.3 Note 2 V
VO2 UDP0, UDM0, UDP1, UDM1 −0.3 to +6.5 V
Analog input voltage VAI1 ANI16, ANI17, ANI19 −0.3 to VDD +0.3
and −0.3 to AVREF (+) +0.3
Notes 2, 3
V
VAI2 ANI0 to ANI7 −0.3 to VDD +0.3
and −0.3 to AVREF (+) +0.3
Notes 2, 3
V
Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F). This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2. Must be 6.5 V or lower.
3. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
2. AVREF (+) : The + side reference voltage of the A/D converter. This can be selected from AVREFP, the
internal reference voltage (1.45 V), and VDD.
3. V
SS : Reference voltage
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Absolute Maximum Ratings (TA = 25°C) (2/2)
Parameter Symbols Conditions Ratings Unit
Output current, high IOH1 Per pin P00, P01, P14 to P17, P30, P31,
P40, P41, P50, P51, P70 to P75,
P120, P130, P140
−40 mA
Total of all pins
−170 mA
P00, P01, P40, P41, P120,
P130, P140
−70 mA
P14 to P17, P30, P31,
P50, P51, P70 to P75
−100 mA
IOH2 Per pin P20 to P27 −0.5 mA
Total of all pins −2 mA
Output current, low IOL1 Per pin P00, P01, P14 to P17, P30, P31,
P40, P41, P50, P51, P60 to P63,
P70 to P75, P120, P130, P140
40 mA
Total of all pins
170 mA
P00, P01, P40, P41, P120,
P130, P140
70 mA
P14 to P17, P30, P31,
P50, P51, P60 to P63, P70 to P75
100 mA
IOL2 Per pin P20 to P27 1 mA
Total of all pins 5 mA
Operating ambient
temperature
TA In normal operation mode −40 to +105 °C
In flash memory programming mode
Storage temperature Tstg −65 to +150 °C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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3.2 Oscillator Characteristics
3.2.1 X1, XT1 oscillator characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Resonator Conditions MIN. TYP. MAX. Unit
X1 clock oscillation
frequency (fX)Note
Ceramic resonator/
crystal resonator
2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz
2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz
XT1 clock oscillation
frequency (fXT)Note
Crystal resonator 32 32.768 35 kHz
Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution
time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the
oscillator characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check
the X1 clock oscillation stabilization time using the oscillation stabilization time counter status
register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register
and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the
oscillation stabilization time with the resonator to be used.
3.2.2 On-chip oscillator characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Oscillators Parameters Conditions MIN. TYP. MAX. Unit
High-speed on-chip oscillator
clock frequency Notes 1, 2
fHOCO 1 48 MHz
High-speed on-chip oscillator
clock frequency accuracy
−20 to +85 °C −1.0 +1.0 %
−40 to −20 °C −1.5 +1.5 %
+85 to +105 °C −2.0 +2.0 %
Low-speed on-chip oscillator
clock frequency
fIL 15 kHz
Low-speed on-chip oscillator
clock frequency accuracy
−15 +15 %
Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and
bits 0 to 2 of HOCODIV register.
2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution
time.
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3.2.3 PLL oscillator characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Oscillators Parameters Conditions MIN. TYP. MAX. Unit
PLL input frequency Note fPLLIN High-speed system clock 6.00 16.00 MHz
PLL output frequency Note fPLL 48.00 MHz
Lock up time From PLL output enable to stabilization of the
output frequency
40.00
μ
s
Interval time From PLL stop to PLL re-operation setteing
Wait time
4.00
μ
s
Setting wait time From after PLL input clock stabilization and PLL
setting is fixed to start setting
Wait time required
1.00
μ
s
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
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3.3 DC Characteristics
3.3.1 Pin characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output current,
highNote 1
IOH1 Per pin for P00, P01, P14 to P17,
P30, P31, P40, P41, P50, P51, P70 to
P75, P120, P130, P140
2.4 V ≤ VDD ≤ 5.5 V −3.0 Note
2
mA
Total of P00, P01, P40, P41, P120,
P130, P140
(When duty ≤ 70% Note 3)
4.0 V ≤ VDD ≤ 5.5 V −30.0 mA
2.7 V ≤ VDD < 4.0 V −10.0 mA
2.4 V ≤ VDD < 2.7 V −5.0 mA
Total of P14 to P17, P30, P31,
P50, P51, P70 to P75
(When duty ≤ 70% Note 3)
4.0 V ≤ VDD ≤ 5.5 V −30.0 mA
2.7 V ≤ VDD < 4.0 V −19.0 mA
2.4 V ≤ VDD < 2.7 V −10.0 mA
Total of all pins
(When duty ≤ 70%Note 3)
2.4 V ≤ VDD ≤ 5.5 V -60.0 mA
IOH2 Per pin for P20 to P27 2.4 V ≤ VDD ≤ 5.5 V −0.1Note
2
mA
Total of all pins
(When duty ≤ 70%Note 3)
2.4 V ≤ VDD ≤ 5.5 V −1.5 mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD
pin to an output pin.
2. However, do not exceed the total current value.
3. Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated
with the following expression (when changing the duty ratio to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOH = −10.0 mA
Total output current of pins = (−10.0 × 0.7)/(80 × 0.01) ≅ −8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Caution P00, P01, P30, and P74 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output current,
lowNote 1
IOL1 Per pin for P00, P01, P14 to P17,
P30, P31, P40, P41, P50, P51,
P70 to P75, P120, P130, P140
2.4V ≤ VDD ≤ 5.5 V 8.5 Note 2 mA
Per pin for P60 to P63 2.4V ≤ VDD ≤ 5.5 V 15.0 Note 2 mA
Total of P00, P01, P40, P41, P120,
P130, P140
(When duty ≤ 70% Note 3)
4.0 V ≤ VDD ≤ 5.5 V 40.0 mA
2.7 V ≤ VDD < 4.0 V 15.0 mA
2.4 V ≤ VDD < 2.7 V 9.0 mA
Total of P14 to P17, P30, P31, P50,
P51, P60 to P63, P70 to P75
(When duty ≤ 70% Note 3)
4.0 V ≤ VDD ≤ 5.5 V 40.0 mA
2.7 V ≤ VDD < 4.0 V 35.0 mA
2.4 V ≤ VDD < 2.7 V 20.0
mA
Total of all pins
(When duty ≤ 70% Note 3)
2.4V ≤ VDD ≤ 5.5 V 80.0 mA
IOL2 Per pin for P20 to P27 2.4V ≤ VDD ≤ 5.5 V 0.4 Note 2 mA
Total of all pins
(When duty ≤ 70%Note 3)
2.4V ≤ VDD ≤ 5.5 V 5.0 mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from an output
pin to the VSS pin.
2. However, do not exceed the total current value.
3. Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated
with the following expression (when changing the duty ratio to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) ≅ 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Input voltage,
high
VIH1 P00, P01, P14 to P17,
P30, P31, P40, P41, P50, P51, P70
to P75, P120, P140
Normal input buffer
0.8VDD VDD V
VIH2 P00, P01, P30, P50
TTL input buffer
4.0 V
≤
V
DD
≤
5.5 V
2.2 VDD V
TTL input buffer
3.3 V
≤
V
DD
<
4.0 V
2.0 VDD V
TTL input buffer
2.4 V
≤
V
DD
<
3.3 V
1.5 VDD V
VIH3 P20 to P27 0.7VDD VDD V
VIH4 P60 to P63 0.7VDD 6.0 V
VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD VDD V
Input voltage,
low
VIL1 P00, P01, P14 to P17, P30, P31,
P40, P41, P50, P51, P70 to P75,
P120, P140
Normal input buffer
0 0.2VDD V
VIL2 P00, P01, P30, P50
TTL input buffer
4.0 V
≤
V
DD
≤
5.5 V
0 0.8 V
TTL input buffer
3.3 V
≤
V
DD
<
4.0 V
0 0.5 V
TTL input buffer
2.4 V
≤
V
DD
<
3.3 V
0 0.32 V
VIL3 P20 to P27 0 0.3VDD V
VIL4 P60 to P63 0 0.3VDD V
VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2VDD V
Caution The maximum value of VIH of pins P00, P01, P30, and P74 is VDD, even in the N-ch open-drain
mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 84 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output voltage,
high
VOH1 P00, P01, P14 to P17, P30, P31,
P40, P41, P50, P51, P70 to P75,
P120, P130, P140
4.0 V
≤
V
DD
≤
5.5 V,
I
OH1
=
−
3.0 mA
VDD − 0.7 V
2.7 V
≤
V
DD
≤
5.5 V,
I
OH1
=
−
2.0 mA
VDD − 0.6 V
2.4 V
≤
V
DD
≤
5.5 V,
I
OH1
=
−
1.5 mA
VDD − 0.5 V
VOH2 P20 to P27 2.4 V ≤ VDD ≤ 5.5 V,
IOH2 = −100
μ
A
VDD − 0.5 V
Output voltage,
low
VOL1 P00, P01, P14 to P17, P30, P31,
P40, P41, P50, P51, P70 to P75,
P120, P130, P140
4.0 V
≤
V
DD
≤
5.5 V,
I
OL1
= 8.5 mA
0.7 V
2.7 V
≤
V
DD
≤
5.5 V,
I
OL1
= 3.0 mA
0.6 V
2.7 V
≤
V
DD
≤
5.5 V,
I
OL1
= 1.5 mA
0.4 V
2.4 V
≤
V
DD
≤
5.5 V,
I
OL1
= 0.6 mA
0.4 V
VOL2 P20 to P27 2.4 V ≤ VDD ≤ 5.5 V,
IOL2 = 400
μ
A
0.4 V
VOL3 P60 to P63
4.0 V
≤
V
DD
≤
5.5 V,
I
OL1
= 15.0 mA
2.0 V
4.0 V
≤
V
DD
≤
5.5 V,
I
OL1
= 5.0 mA
0.4 V
2.7 V
≤
V
DD
≤
5.5 V,
I
OL1
= 3.0 mA
0.4 V
2.4 V
≤
V
DD
≤
5.5 V,
I
OL1
= 2.0 mA
0.4 V
Caution P00, P01, P30, and P74 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 85 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Input leakage
current, high
ILIH1 P00, P01, P14 to P17,
P20 to P27, P30, P31,
P40, P41, P50, P51, P60 to
P63, P70 to P75, P120,
P137, P140, RESET
VI = VDD 1
μ
A
ILIH2 P121 to P124
(X1, X2, XT1, XT2, EXCLK,
EXCLKS)
VI = VDD
In input port
or external
clock input
1
μ
A
In resonator
connection
10
μ
A
Input leakage
current, low
ILIL1 P00, P01, P14 to P17,
P20 to P27, P30, P31, P40,
P41, P50, P51, P60 to P63,
P70 to P75, P120, P137, P140,
RESET
VI = VSS −1
μ
A
ILIL2 P121 to P124
(X1, X2, XT1, XT2, EXCLK,
EXCLKS)
VI = VSS
In input port
or external
clock input
−1
μ
A
In resonator
connection
−10
μ
A
On-chip pll-up
resistance
RU P00, P01, P14 to P17,
P30, P31, P40, P41,
P50, P51, P70 to P75, P120,
P140
VI = VSS,
In input port
10 20 100 kΩ
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 86 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
3.3.2 Supply current characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply
current
Note 1
IDD1 Operating
mode
HS
(High-speed
main)
modffe Note 6
fHOCO = 48 MHz
fIH = 24 MHz Note 3
Basic
operation
VDD = 5.0 V 1.7 mA
VDD = 3.0 V 1.7 mA
Normal
operation
VDD = 5.0 V
3.7 5.8 mA
VDD = 3.0 V 3.7 5.8 mA
f
HOCO
= 24 MHz
Note 5
fIH = 12 MHz Note 3
Normal
operation
VDD = 5.0 V
2.3 3.4 mA
VDD = 3.0 V 2.3 3.4 mA
f
HOCO
= 12 MHz
Note 5
fIH = 6 MHz Note 3
Normal
operation
VDD = 5.0 V
1.6 2.2 mA
VDD = 3.0 V 1.6 2.2 mA
fHOCO = 6 MHz Note
5
fIH = 3 MHz Note 3
Normal
operation
VDD = 5.0 V
1.2 1.6 mA
VDD = 3.0 V 1.2 1.6 mA
HS
(High-speed
main) mode
Note 6
f
MX
= 20 MHz
Note 2
,
VDD = 5.0 V
Normal
operation
Square wave input
3.0 4.9 mA
Resonator connection
3.2 5.0 mA
f
MX
= 20 MHz
Note 2
,
VDD = 3.0 V
Normal
operation
Square wave input
3.0 4.9 mA
Resonator connection
3.2 5.0 mA
f
MX
= 10 MHz
Note 2
,
VDD = 5.0 V
Normal
operation
Square wave input
1.9 2.9 mA
Resonator connection
1.9 2.9 mA
f
MX
= 10 MHz
Note 2
,
VDD = 3.0 V
Normal
operation
Square wave input
1.9 2.9 mA
Resonator connection
1.9 2.9 mA
HS
(High-speed
main) mode
(PLL
operation)
Note 6
fPLL = 48 MHz,
fCLK = 24 MHz Note 2
Normal
operation
VDD = 5.0 V
4.0 6.3 mA
VDD = 3.0 V 4.0 6.3 mA
fPLL = 48 MHz,
fCLK = 12 MHz Note 2
Normal
operation
VDD = 5.0 V
2.6 3.9 mA
VDD = 3.0 V 2.6 3.9 mA
fPLL = 48 MHz,
fCLK = 6 MHz Note 2
Normal
operation
VDD = 5.0 V
1.9 2.7 mA
VDD = 3.0 V 1.9 2.7 mA
Subsystem
clock
operation
fSUB = 32.768 kHz
Note 4
TA = −40°C
Normal
operation
Resonator connection
4.1 4.9
μ
A
Square wave input
4.2 5.0
μ
A
fSUB = 32.768 kHz
Note 4
TA = +25°C
Normal
operation
Square wave input
4.1 4.9
μ
A
Resonator connection
4.2 5.0
μ
A
fSUB = 32.768 kHz
Note 4
TA = +50°C
Normal
operation
Square wave input
4.2 5.5
μ
A
Resonator connection
4.3 5.6
μ
A
fSUB = 32.768 kHz
Note 4
TA = +70°C
Normal
operation
Square wave input
4.2 6.3
μ
A
Resonator connection
4.3 6.4
μ
A
fSUB = 32.768 kHz
Note 4
TA = +85°C
Normal
operation
Square wave input
4.8 7.7
μ
A
Resonator connection
4.9 7.8
μ
A
fSUB = 32.768 kHz
Note 4
TA = +105°C
Normal
operation
Square wave input
6.9 19.7
μ
A
Resonator connection
7.0 19.8
μ
A
(Notes and Remarks are listed on the next page.)
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 87 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD, or VSS. The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip
pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1
(Ultra-low power consumption oscillation). However, not including the current flowing into the RTC,
12-bit interval timer, and watchdog timer.
5. When Operating frequency setting of option byte = 48 MHz. When fHOCO is divided by HOCODIV.
When RDIV[1:0] = 00 (divided by 2: default).
6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
Remarks 1. fHOCO: High-speed on-chip oscillator clock frequency (Max. 48 MHz)
2. fIH: Main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock
by 2, 4, or 8 (Max. 24 MHz)
3. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
4. f
PLL: PLL oscillation frequency
5. f
SUB: Subsystem clock frequency (XT1 clock oscillation frequency)
6. fCLK: CPU/peripheral hardware clock frequency
7. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C.
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 88 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply
current
Note 1
IDD2
Note 2
HALT
mode
HS
(High-speed
main) mode
Note 9
fHOCO = 48 MHz
fIH = 24 MHz Note 4
VDD = 5.0 V
0.67 2.25 mA
VDD = 3.0 V 0.67 2.25 mA
fHOCO = 24 MHz Note 7
fIH = 12 MHz Note 4
VDD = 5.0 V
0.50 1.55 mA
VDD = 3.0 V 0.50 1.55 mA
fHOCO = 12 MHz Note 7
fIH = 6 MHz Note 4
VDD = 5.0 V
0.41 1.21 mA
VDD = 3.0 V 0.41 1.21 mA
fHOCO = 6 MHz Note 7
fIH = 3 MHz Note 4
VDD = 5.0 V 0.37 1.05 mA
VDD = 3.0 V 0.37 1.05 mA
HS
(High-speed
main) mode
Note 9
fMX = 20 MHz Note 3,
VDD = 5.0 V
Square wave input
0.28 1.90 mA
Resonator connection
0.45 2.00 mA
fMX = 20 MHz Note 3,
VDD = 3.0 V
Square wave input
0.28 1.90 mA
Resonator connection
0.45 2.00 mA
fMX = 10 MHz Note 3,
VDD = 5.0 V
Square wave input
0.19 1.02 mA
Resonator connection
0.26 1.10 mA
fMX = 10 MHz Note 3,
VDD = 3.0 V
Square wave input
0.19 1.02 mA
Resonator connection
0.26 1.10 mA
HS
(High-speed
main) mode
(PLL
operation)
Note 9
fPLL = 48 MHz,
fCLK = 24 MHz Note 3
VDD = 5.0 V 0.91 2.74 mA
VDD = 3.0 V 0.91 2.74 mA
fPLL = 48 MHz,
fCLK = 12 MHz Note 3
VDD = 5.0 V 0.85 2.31 mA
VDD = 3.0 V 0.85 2.31 mA
fPLL = 48 MHz,
fCLK = 6 MHz Note 3
VDD = 5.0 V 0.82 2.07 mA
VDD = 3.0 V 0.82 2.07 mA
Subsystem
clock
operation
fSUB = 32.768 kHzNote 5
TA = −40°C
Square wave input
0.25 0.57 μA
Resonator connection
0.44 0.76
μ
A
fSUB = 32.768 kHzNote 5
TA = +25°C
Square wave input
0.30 0.57
μ
A
Resonator connection
0.49 0.76 μA
fSUB = 32.768 kHzNote 5
TA = +50°C
Square wave input
0.33 1.17
μ
A
Resonator connection
0.63 1.36
μ
A
fSUB = 32.768 kHzNote 5
TA = +70°C
Square wave input
0.46 1.97 μA
Resonator connection
0.76 2.16 μA
fSUB = 32.768 kHzNote 5
TA = +85°C
Square wave input
0.97 3.37
μ
A
Resonator connection
1.16 3.56
μ
A
fSUB = 32.768 kHzNote 5
TA = +105°C
Square wave input
3.01 15.37
μ
A
Resonator connection
3.20 15.56
μ
A
IDD3Note 6 STOP
mode Note 8
TA = −40°C 0.18 0.50 μA
TA = +25°C 0.23 0.50
μ
A
TA = +50°C 0.26 1.10 μA
TA = +70°C 0.29 1.90
μ
A
TA = +85°C 0.90 3.30
μ
A
TA = +105°C 2.94 15.30
μ
A
(Notes and Remarks are listed on the next page.)
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 89 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, LVD circuit, USB2.0 host/function
module, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and
setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included.
However, not including the current flowing into the 12-bit interval timer and watchdog timer.
6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
7. When Operating frequency setting of option byte = 48 MHz. When fHOCO is divided by HOCODIV. When
RDIV[1:0] = 00 (divided by 2: default).
8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT
mode.
9. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
Remarks 1. f
HOCO: High-speed on-chip oscillator clock frequency (Max. 48 MHz)
2. fIH: Main system clock source frequency obtained by dividing the high-speed on-chip oscillator clock
by 2, 4, or 8 (Max. 24 MHz)
3. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
4. f
PLL: PLL oscillation frequency
5. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
6. f
CLK: CPU/peripheral hardware clock frequency
7. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C.
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 90 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low-speed on-chip
oscillator operating
current
IFILNote 1 0.20
μ
A
RTC operating current IRTC
Notes 1, 2, 3
0.02
μ
A
12-bit interval timer
operating current
IIT Notes 1, 2, 4 0.02
μ
A
Watchdog timer
operating current
IWDT
Notes 1, 2, 5
fIL = 15 kHz 0.22
μ
A
A/D converter
operating current
IADC Notes 1,
6
When conversion
at maximum speed
Normal mode, AVREFP = VDD = 5.0 V 1.3 1.8 mA
Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.8 mA
A/D converter reference
voltage current
IADREF Note
1
75.0
μ
A
Temperature sensor
operating current
ITMPS Note 1 75.0
μ
A
LVD operating current ILVD Notes 1,
7
0.08
μ
A
Self-programming
operating current
IFSP Notes 1,
9
2.00 12.30 mA
BGO operating current IBGO Notes 1,
8
2.00 12.30 mA
SNOOZE operating
current
ISNOZ Note 1 ADC operation The mode is performed Note 10 0.80 1.97 mA
The A/D conversion operations are performed,
Low voltage mode, AVREFP = VDD = 3.0 V
1.20 3.00 mA
CSI operation 0.70 1.56 mA
(Notes and Remarks are listed on the next page.)
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 91 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
USB operating current IUSBH
Note 11
During USB communication operation under the following settings
and conditions (VDD = 5.0 V, TA = +25°C):
• The internal power supply for the USB is used.
• X1 oscillation frequency (fX) = 12 MHz, PLL oscillation frequency
(fPLL) = 48 MHz
• The host controller (via two ports) is set to operate in full-speed
mode with four pipes (end points) used simultaneously.
(PIPE4: Bulk OUT transfer (64 bytes), PIPE5: Bulk IN transfer (64
bytes), PIPE6: Interrupt OUT transfer, PIPE7: Interrupt IN transfer).
• The USB ports (two ports) are individually connected to a
peripheral function via a 0.5 m USB cable.
9.0 mA
IUSBF
Note 11
During USB communication operation under the following settings
and conditions (VDD = 5.0 V, TA = +25°C):
• The internal power supply for the USB is used.
• X1 oscillation frequency (fX) = 12 MHz, PLL oscillation frequency
(fPLL) = 48 MHz
• The function controller is set to operate in full-speed mode with
four pipes (end points) used simultaneously.
(PIPE4: Bulk OUT transfer (64 bytes), PIPE5: Bulk IN transfer (64
bytes), PIPE6: Interrupt OUT transfer, PIPE7: Interrupt IN transfer).
• The USB port (one port) is connected to the host device via a
0.5 m USB cable.
2.5 mA
ISUSP
Note 12
During suspended state under the following settings and conditions
(VDD = 5.0 V, TA = +25°C):
• The function controller is set to full-speed mode (the UDP0 pin is
pulled up).
• The internal power supply for the USB is used.
• The system is set to STOP mode (When the high-speed on-chip
oscillator, high-speed system clock, and subsystem clock are
stopped. When the watchdog timer is stopped.).
• The USB port (one port) is connected to the host device via a
0.5 m USB cable.
240
μ
A
(Notes and Remarks are listed on the next page.)
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 92 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Notes 1. Current flowing to VDD.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed
on-chip ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of
the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT
mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock
operation includes the operational current of the real-time clock.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the
values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT
mode. When the low-speed on-chip oscillator is selected, IFIL should be added.
5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip
oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT
when the watchdog timer is in operation.
6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum
of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
7. Current flowing only to the LVD circuit. The current value of the RL78/G1C is the sum of IDD1, IDD2 or
IDD3 and ILVI when the LVD circuit operates in the Operating, HALT or STOP mode.
8. Current flowing only during data flash rewrite.
9. Current flowing only during self programming.
10. For shift time to the SNOOZE mode.
11. Current consumed only by the USB module and the internal power supply for the USB.
12. Includes the current supplied from the pull-up resistor of the UDP0 pin to the pull-down resistor of the
host device, in addition to the current consumed by this MCU during the suspended state.
Remarks 1. f
IL: Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. f
CLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25°C
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 93 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
3.4 AC Characteristics
3.4.1 Basic operation
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Instruction cycle (minimum
instruction execution time)
TCY Main
system
clock (fMAIN)
operation
HS
(High-speed
main) mode
2.7 V
≤
V
DD
≤
5.5 V
0.04167 1
μ
s
2.4 V
≤
V
DD
<
2.7 V
0.0625 1
μ
s
Subsystem clock (fSUB)
operation
2.4 V
≤
V
DD
≤
5.5 V
28.5 30.5 31.3
μ
s
In the self
programmin
g mode
HS
(High-speed
main) mode
2.7 V
≤
V
DD
≤
5.5 V
0.04167 1
μ
s
2.4 V
≤
V
DD
<
2.7 V
0.0625 1
μ
s
External system clock frequency fEX 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz
2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz
fEXS 32 35 kHz
External system clock input
high-level width, low-level width
tEXH, tEXL 2.7 V ≤ VDD ≤ 5.5 V 24 ns
2.4 V ≤ VDD < 2.7 V 30 ns
tEXHS, tEXLS 13.7
μ
s
TI00 to TI03 input high-level
width, low-level width
tTIH,
tTIL
1/fMCK+10 ns
TO00 to TO03 output frequency fTO High-speed main
mode
4.0 V ≤ VDD ≤ 5.5 V 12 MHz
2.7 V ≤ VDD < 4.0 V 8 MHz
2.4 V ≤ VDD < 2.7 V 4 MHz
PCLBUZ0, PCLBUZ1 output
frequency
fPCL High-speed main
mode
4.0 V ≤ VDD ≤ 5.5 V 16 MHz
2.7 V ≤ VDD < 4.0 V 8 MHz
2.4 V ≤ VDD < 2.7 V 4 MHz
Interrupt input high-level width,
low-level width
tINTH,
tINTL
INTP0 to INTP6,
INTP8, INTP9
2.4 V ≤ VDD ≤ 5.5 V 1
μ
s
Key interrupt input low-level width tKR KR0 to KR5 2.4 V ≤ VDD ≤ 5.5 V 250 ns
RESET low-level width tRSL 10
μ
s
Remark f
MCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n =
0 to 3))
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Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
1.0
0.1
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
2.7
0.01
2.4
0.04167
0.0625
0.05
Cycle time TCY [μs]
Supply voltage VDD [V]
When the high-speed on-chip oscillator
clock is selected
During self programming
When high-speed system clock is selected
AC Timing Test Points
V
IH
/V
OH
V
IL
/V
OL
Test points
V
IH
/V
OH
V
IL
/V
OL
External System Clock Timing
EXCLK/EXCLKS
1/f
EX
/
1/f
EXS
t
EXL
/
t
EXLS
t
EXH
/
t
EXHS
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
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TI/TO Timing
TI00 to TI03
t
TIL
t
TIH
TO00 to TO03
1/f
TO
Interrupt Request Input Timing
INTP0 to INTP6, INTP8, INTP9
t
INTL
t
INTH
Key Interrupt Input Timing
KR0 to KR5
t
KR
RESET Input Timing
RESET
t
RSL
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3.5 Peripheral Functions Characteristics
3.5.1 Serial array unit
(1) During communication at same potential (UART mode) (dedicated baud rate generator output)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate fMCK/12 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note
2.0 Mbps
Note The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
User's device
TxDq
RxDq
Rx
Tx
RL78 microcontroller
UART mode bit width (during communication at same potential) (reference)
Baud rate error tolerance
High-/Low-bit width
1/Transfer rate
TxDq
RxDq
Remarks 1. q: UART number (q = 0), g: PIM and POM number (g = 5)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM numbers (g = 0, 3, 5, 7)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 2.7 V ≤ VDD ≤ 5.5 V 250 ns
2.4 V ≤ VDD ≤ 5.5 V 500 ns
SCKp high-/low-level width tKH1,
tKL1
4.0 V ≤ VDD ≤ 5.5 V tKCY1/2 − 24 ns
2.7 V ≤ VDD ≤ 5.5 V tKCY1/2 − 36 ns
2.4 V ≤ VDD ≤ 5.5 V tKCY1/2 − 76 ns
SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V 66 ns
2.7 V ≤ VDD ≤ 5.5 V 66 ns
2.4 V ≤ VDD ≤ 5.5 V 113 ns
SIp hold time (from SCKp↑) Note 2 tKSI1 38 ns
Delay time from SCKp↓ to
SOp output Note 3
tKSO1 C = 30 pFNote 4 50 ns
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
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(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCKp cycle time Note 5 tKCY2 4.0 V ≤ VDD ≤ 5.5 V 20 MHz < fMCK 16/fMCK ns
fMCK ≤ 20 MHz 12/fMCK ns
2.7 V ≤ VDD ≤ 5.5 V 16 MHz < fMCK 16/fMCK ns
fMCK ≤ 16 MHz 12/fMCK ns
2.4 V ≤ VDD ≤ 5.5 V 12/fMCK
and 1000
ns
SCKp high-/low-level width tKH2,
tKL2
4.0 V ≤ EVDD0 ≤ 5.5 V tKCY2/2 −
14
ns
2.7 V ≤ EVDD0 ≤ 5.5 V tKCY2/2 −
16
ns
2.4 V ≤ VDD ≤ 5.5 V tKCY2/2 −
36
ns
SIp setup time
(to SCKp↑) Note 1
tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK+40 ns
2.4 V ≤ VDD ≤ 5.5 V 1/fMCK+60 ns
SIp hold time
(from SCKp↑) Note 2
tKSI2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK+62 ns
2.4 V ≤ VDD ≤ 5.5 V 1/fMCK+62 ns
Delay time from SCKp↓ to
SOp output Note 3
tKSO2 C = 30 pF Note 4 2.7 V ≤ VDD ≤ 5.5 V 2/fMCK+66 ns
2.4 V ≤ VDD ≤ 5.5 V 2/fMCK+113 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the
SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0),
n: Channel number (n = 0, 1), g: PIM number (g = 0, 3, 5, 7)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
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CSI mode connection diagram (during communication at same potential)
User's device
SCKp
SOp
SCK
SI
SIp SO
RL78 microcontroller
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
SIp Input data
Output data
SOp
t
KCY1, 2
t
KL1, 2
t
KH1, 2
t
SIK1, 2
t
KSI1, 2
t
KSO1, 2
SCKp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
SIp Input data
Output data
SOp
t
KCY1, 2
t
KH1, 2
t
KL1, 2
t
SIK1, 2
t
KSI1, 2
t
KSO1, 2
SCKp
Remarks 1. p: CSI number (p = 00, 01)
2. m: Unit number, n: Channel number (mn = 00, 01)
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(4) During communication at same potential (simplified I2C mode)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. MAX. Unit
SCLr clock frequency fSCL 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
400 Note 1 kHz
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
100 Note 1 kHz
Hold time when SCLr = “L” tLOW 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
1200 ns
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
4600 ns
Hold time when SCLr = “H” tHIGH 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
1200 ns
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
4600 ns
Data setup time (reception) tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 220
Note 2
ns
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1/fMCK + 580
Note 2
ns
Data hold time (transmission) tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
0 770 ns
2.4 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
0 1420 ns
Notes 1. The value must also be equal to or less than fMCK/4.
2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr
pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and
port output mode register h (POMh).
(Caution and Remarks are listed on the next page.)
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
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Simplified I2C mode mode connection diagram (during communication at same potential)
User's device
SDAr
SCLr
SDA
SCL
V
DD
R
b
RL78 microcontroller
Simplified I2C mode serial transfer timing (during communication at same potential)
SDAr
tLOW tHIGH
tHD:DAT
SCLr
tSU:DAT
1/fSCL
Remarks 1. Rb[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance
2. r: IIC number (r = 00, 01), g: PIM number (g = 5), h: POM number (h = 3, 5)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number
(m = 0), n: Channel number (n = 0, 1), mn = 00, 01)
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
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R01DS0348EJ0120 Rev.1.20
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(5) Communication at different potential (2.5 V, 3 V) (UART mode) (1/2)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate reception 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
fMCK/12
Note 1
bps
Theoretical value of the
maximum transfer rate
fCLK = 24 MHz,
fMCK = fCLK Note 2
2.0 Mbps
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
fMCK/12
Note 1
bps
Theoretical value of the
maximum transfer rate
fCLK = 24 MHz,
fMCK = fCLK Note 2
2.0 Mbps
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
fMCK/12
Note 1
bps
Theoretical value of the
maximum transfer rate
fCLK = 24 MHz,
fMCK = fCLK Note 2
2.0 Mbps
Notes 1. Use it with VDD≥Vb.
2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected
Remarks 1. V
b[V]: Communication line voltage
2. q: UART number (q = 0), g: PIM and POM number (g = 5)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00)
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R01DS0348EJ0120 Rev.1.20
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(5) Communication at different potential (2.5 V, 3 V) (UART mode) (2/2)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate
transmission
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
Note 1 bps
Theoretical value of the
maximum transfer rate
C
b
= 50 pF, R
b
= 1.4 k
Ω
, V
b
= 2.7 V
2.6
Note 2 Mbps
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
Note 3 bps
Theoretical value of the
maximum transfer rate
C
b
= 50 pF, R
b
= 2.7 k
Ω
, V
b
= 2.3 V
1.2
Note 4 Mbps
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Notes
5, 6
bps
Theoretical value of the
maximum transfer rate
C
b
= 50 pF, R
b
= 5.5 k
Ω
, V
b
= 1.6 V
0.43
Note 7
Mbps
Notes 1. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
Maximum transfer rate = 1 [bps]
{−Cb × Rb × ln (1 − 2.2
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln (1 −
2.2
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
3. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
Maximum transfer rate = 1 [bps]
{−Cb × Rb × ln (1 − 2.0
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln
(1 − 2.0
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
5. Use it with VDD ≥ Vb.
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Notes 6. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.4 V ≤ VDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
Maximum transfer rate = 1 [bps]
{−Cb × Rb × ln (1 − 1.5
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 1.5
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
7. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected
UART mode connection diagram (during communication at different potential)
User's device
TxDq
RxDq
Rx
Tx
V
b
R
b
RL78 microcontroller
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
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UART mode bit width (during communication at different potential) (reference)
TxDq
RxDq
Baud rate error tolerance
Baud rate error tolerance
Low-bit width
High-/Low-bit width
High-bit width
1/Transfer rate
1/Transfer rate
Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load
capacitance, Vb[V]: Communication line voltage
2. q: UART number (q = 0), g: PIM and POM number (g = 5)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
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(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(1/2)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
600 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1000 ns
2.4 V ≤ VDD < 3.3 V,
2.4 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
2300 ns
SCKp high-level width tKH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
tKCY1/2 −
150
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 −
340
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 −
916
ns
SCKp low-level width tKL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
tKCY1/2 − 24 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 − 36 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 −
100
ns
Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance)
mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port
output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input
buffer selected.
2. Use it with VDD ≥ Vb.
(Remarks are listed two pages after the next page.)
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(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(2/2)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SIp setup time
(to SCKp↑) Note 1
tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
162 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
354 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
958 ns
SIp hold time
(from SCKp↑) Note 1
tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
38 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
38 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
38 ns
Delay time from SCKp↓ to
SOp output Note 1
tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
200 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
390 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
966 ns
SIp setup time
(to SCKp↓) Note 2
tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
88 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
88 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
220 ns
SIp hold time
(from SCKp↓) Note 2
tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
38 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
38 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
38 ns
Delay time from SCKp↑ to
SOp output Note 2
tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
50 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
50 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
50 ns
(Notes, Cautions and Remarks are listed on the next page.)
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Page 108 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3 Use it with VDD ≥ Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode
for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
V
b
R
b
User's device
<Master>
SCKp
SOp
SCK
SI
SIp SO
V
b
R
b
RL78 microcontroller
Remarks 1. R
b[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00), m: Unit number , n: Channel number (mn = 00), g: PIM and POM number (g
= 0, 3, 5, 7)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
4. CSI01 cannot communicate at different potential. Use other CSI for communication at different
potential.
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 109 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
SIp Input data
Output dataSOp
t
KCY1
t
KL1
t
KH1
t
SIK1
t
KSI1
t
KSO1
SCKp
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
SIp Input data
Output data
SOp
t
KCY1
t
KL1
t
KH1
t
SIK1
t
KSI1
t
KSO1
SCKp
Remarks 1. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g
= 0, 3, 5, 7)
2. CSI01 cannot communicate at different potential. Use other CSI for communication at different
potential.
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(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCKp cycle time Note 1 tKCY2
4.0 V
≤
V
DD
≤
5.5 V,
2.7 V
≤
V
b
≤
4.0 V
20 MHz < fMCK ≤ 24 MHz 24/fMCK ns
8 MHz < fMCK ≤ 20 MHz 20/fMCK ns
4 MHz < fMCK ≤ 8 MHz 16/fMCK ns
fMCK ≤ 4 MHz 12/fMCK ns
2.7 V
≤
V
DD
< 4.0 V,
2.3 V
≤
V
b
≤
2.7 V
20 MHz < fMCK ≤ 24 MHz 32/fMCK ns
16 MHz < fMCK ≤ 20 MHz 28/fMCK ns
8 MHz < fMCK ≤ 16 MHz 24/fMCK ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK ns
fMCK ≤ 4 MHz
12/fMCK ns
2.4 V
≤
V
DD
< 3.3 V,
1.6 V
≤
V
b
≤
2.0 V
Note
2
20 MHz < fMCK ≤ 24 MHz 72/fMCK ns
16 MHz < fMCK ≤ 20 MHz 64/fMCK ns
8 MHz < fMCK ≤ 16 MHz 52/fMCK ns
4 MHz < fMCK ≤ 8 MHz
32/fMCK ns
fMCK ≤ 4 MHz
20/fMCK ns
SCKp high-/low-level
width
tKH2,
tKL2
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
t
KCY2/2 −
24
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
t
KCY2/2 −
36
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2
t
KCY2/2 −
100
ns
SIp setup time
(to SCKp↑) Note 3
tSIK2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK +
40
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK +
40
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 1/fMCK +
60
ns
SIp hold time
(from SCKp↑) Note 4
tKSI2 1/fMCK + 62 ns
Delay time from SCKp↓ to
SOp output Note 5
tKSO2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2/fMCK +
240
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK +
428
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK +
1146
ns
Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. Use it with VDD ≥ Vb.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
(Caution and Remarks are listed on the next page.)
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
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R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD
tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode
register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
User's device
<Slave>
SCKp
SOp
SCK
SI
SIp SO
V
b
R
b
RL78 microcontroller
Remarks 1. R
b[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00), g: PIM and POM number (g
= 0, 3, 5, 7)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
4. CSI01 cannot communicate at different potential. Use other CSI for communication at different
potential.
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 112 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
SIp Input data
Output data
SOp
tKCY2
tKL2 tKH2
tSIK2 tKSI2
tKSO2
SCKp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
SIp Input data
Output data
SOp
t
KCY2
t
KL2
t
KH2
t
SIK2
t
KSI2
t
KSO2
S
CKp
Remarks 1. p: CSI number (p = 00), m: Unit number, n: Channel number (mn = 00),
g: PIM and POM number (g = 0, 3, 5, 7)
2. CSI01 cannot communicate at different potential. Use other CSI for communication at different
potential.
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 113 of 134
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(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. MAX. Unit
SCLr clock frequency fSCL 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
400 Note 1 kHz
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
400 Note 1 kHz
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
100 Note 1 kHz
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
100 Note 1 kHz
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
100 Note 1 kHz
Hold time when SCLr = “L” tLOW 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
1200 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1200 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
4600 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
4600 ns
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
4650 ns
Hold time when SCLr = “H” tHIGH 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
620 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
500 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2700 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
2400 ns
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
1830 ns
(Notes, Caution and Remarks are listed on the next page.)
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
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R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. MAX. Unit
Data setup time (reception) tSU:DAT 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 340
Note 3
ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK +
340Note 3
ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
1/fMCK + 760
Note 3
ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1/fMCK + 760
Note 3
ns
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Notes 2,
Cb = 100 pF, Rb = 5.5 kΩ
1/fMCK + 570
Note 3
ns
Data hold time (transmission) tHD:DAT 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
0 770 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
0 770 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
0 1420 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
0 1420 ns
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
0 1215 ns
Notes 1. The value must also be equal to or less than fMCK/4.
2. Use it with VDD ≥ Vb.
3. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin
and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 115 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Simplified I2C mode connection diagram (during communication at different potential)
User's device
SDAr
SCLr
SDA
SCL
V
b
R
b
V
b
R
b
RL78 microcontroller
Simplified I2C mode serial transfer timing (during communication at different potential)
SDAr
tLOW tHIGH
tHD:DAT
SCLr
tSU:DAT
1/fSCL
Remarks 1. R
b[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr)
load capacitance, Vb[V]: Communication line voltage
2. r: IIC number (r = 00), g: PIM, POM number (g = 0, 3, 5, 7)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00)
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 116 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
3.5.2 Serial interface IICA
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
Standard
Mode
Fast Mode
MIN. MAX. MIN. MAX.
SCLA0 clock frequency fSCL Fast mode: fCLK ≥ 3.5 MHz − − 0 400 kHz
Standard mode: fCLK ≥ 1 MHz 0 100 − − kHz
Setup time of restart condition tSU:STA 4.7 0.6
μ
s
Hold timeNote 1 tHD:STA 4.0 0.6
μ
s
Hold time when SCLA0 = “L” tLOW 4.7 1.3
μ
s
Hold time when SCLA0 = “H” tHIGH 4.0 0.6
μ
s
Data setup time (reception) tSU:DAT 250 100 ns
Data hold time (transmission)Note 2 tHD:DAT 0 3.45 0 0.9
μ
s
Setup time of stop condition tSU:STO 4.0 0.6
μ
s
Bus-free time tBUF 4.7 1.3
μ
s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution The values in the above table are applied even when bit 1 (PIOR1) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the
values in the redirect destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
Fast mode: Cb = 320 pF, Rb = 1.1 kΩ
IICA serial transfer timing
t
LOW
t
BUF
t
HIGH
t
HD:STA
Stop
condition Start
condition Restart
condition Stop
condition
t
SU:DAT
t
SU:STA
t
SU:STO
t
HD:STA
t
HD:DAT
SCLA0
SDAA0
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 117 of 134
R01DS0348EJ0120 Rev.1.20
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3.5.3 USB
(1) Electrical specifications
(TA = −40 to +105°C, 3.0 V ≤ UVDD ≤ 3.6 V, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
UVDD
UVDD input voltage
characteristic
UVDD VDD = 3.0 to 5.5 V, PXXCON = 1,
VDDUSEB = 0 (UVDD ≤ VDD)
3.0 3.3 3.6 V
UVDD output voltage
characteristic
UVDD VDD = 4.0 to 5.5 V,
PXXCON = VDDUSEB = 1
3.0 3.3 3.6 V
UVBUS UVBUS input voltage
characteristic
UVBUS Function 4.35
(4.02Note)
5.00 5.25 V
Host 4.75 5.00 5.25 V
Note Value of instantaneous voltage
(TA = −40 to +105°C, 3.0 V ≤ UVDD ≤ 3.6 V, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
UDPi/UDMi
pins input
characteristic
(FS/LS
receiver)
Input voltage
VIH 2.0 V
VIL 0.8 V
Difference input
sensitivity
VDI | UDP voltage − UDM voltage | 0.2 V
Difference
common mode
range
VCM 0.8 2.5 V
UDPi/UDMi
pins output
characteristic
(FS driver)
Output voltage VOH IOH = −200
μ
A 2.8 3.6 V
VOL IOL = 2.4 mA 0 0.3 V
Transi-ti
on time
Rising tFR Rising: From 10% to 90 % of
amplitude,
Falling: From 90% to 10 % of
amplitude,
CL = 50 pF
4 20 ns
Falling tFF 4 20 ns
Matching
(TFR/TFF)
VFRFM 90 111.1 %
Crossover voltage VFCRS 1.3 2.0 V
Output
Impedance
ZDRV UVDD voltage = 3.3 V,
Pin voltage = 1.65 V
28 44 Ω
UDPi/UDMi
pins output
characteristic
(LS driver)
Output voltage VOH 2.8 3.6 V
VOL 0 0.3 V
Transi-ti
on time
Rising tLR Rising: From 10% to 90 % of
amplitude,
Falling: From 90% to 10 % of
amplitude,
CL = 200 to 600 pF
When the host controller function is
selected: The UDMi pin (i = 0, 1) is
pulled up via 1.5 kΩ.
When the function controller
function is selected: The UDP0 and
UDM0 pins are individually pulled
down via 15 kΩ
75 300 ns
Falling tLF 75 300 ns
Matching
(TFR/TFF) Note
VLTFM 80 125 %
Crossover voltage
Note
VLCRS 1.3 2.0 V
UDPi/UDMi
pins pull-up,
pull-down
Pull-down resistor RPD 14.25 24.80 kΩ
Pull-up
resistor
(i = 0
only)
Idle RPUI 0.9 1.575 kΩ
Recep-t
ion
RPUA 1.425 3.09 kΩ
UVBUS UVBUS pull-down
resistor
RVBUS UVBUS voltage = 5.5 V 1000 kΩ
UVBUS input
voltage
VIH 3.20 V
VIL 0.8 V
Note Excludes the first signal transition from the idle state.
Remark i = 0, 1
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 118 of 134
R01DS0348EJ0120 Rev.1.20
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Timing of UDPi and UDMi
UDPi
UDMi
90 %
90 %
10 % 10 %
V
CRS
(Crossover voltage)
t
R
t
F
(2) BC standard
(TA = −40 to +105°C, 3.0 V ≤ UVDD ≤ 3.6 V, 3.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
USB
standard
BC1.2
UDPi sink current IDP_SINK 25 175
μ
A
UDMi sink current IDM_SINK 25 175
μ
A
DCD source current IDP_SRC 7 13
μ
A
Dedicated charging
port resistor
RDCP_DAT 0 V < UDP/UDM voltage < 1.0 V 200 Ω
Data detection voltage VDAT_REF 0.25 0.4 V
UDPi source voltage VDP_SRC Output current 250
μ
A 0.5 0.7 V
UDMi source voltage VDM_SRC Output current 250
μ
A 0.5 0.7 V
Remark i = 0, 1
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 119 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(3) BC option standard (Host)
(TA = −40 to +105°C, 4.75 V ≤ UVBUS ≤ 5.25 V, 3.0 V ≤ UVDD ≤ 3.6 V, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
UDPi output
voltage
(UVBUS divider
ratio)
• VDOUEi = 1
VDSELi
[3:0]
(i = 0, 1)
1000 VP20 38 40 42 % UVBUS
1001 VP27 51.6 53.6 55.6 % UVBUS
1010 VP20 38 40 42 % UVBUS
1100 VP33 60 66 72 % UVBUS
UDMi output
voltage
(UVBUS divider
ratio)
• VDOUEi = 1
VDSELi
[3:0]
(i = 0, 1)
1000 VM20 38 40 42 % UVBUS
1001 VM20 38 40 42 % UVBUS
1010 VM27 51.6 53.6 55.6 % UVBUS
1100 VM33 60 66 72 % UVBUS
UDPi
comparing
voltage Note 1
(UVBUS divider
ratio)
• VDOUEi = 1
•
CUSDETEi = 1
VDSELi
[3:0]
(i = 0, 1)
1000 VHDETP_UP0 The rise of pin voltage detection voltage 56.2 % UVBUS
VHDETP_DWN0 The fall of pin voltage detection voltage 29.4 % UVBUS
1001 VHDETP_UP1 The rise of pin voltage detection voltage 60.5 % UVBUS
VHDETP_DWN1 The fall of pin voltage detection voltage 45.0 % UVBUS
1010 VHDETP_UP2 The rise of pin voltage detection voltage 56.2 % UVBUS
VHDETP_DWN2 The fall of pin voltage detection voltage 29.4 % UVBUS
UDMi
comparing
voltage Note 1
(UVBUS divider
ratio)
• VDOUEi = 1
•
CUSDETEi = 1
VDSELi
[3:0]
(i = 0, 1)
1000 VHDETM_UP0 The rise of pin voltage detection voltage 56.2 % UVBUS
VHDETM_DWN0 The fall of pin voltage detection voltage 29.4 % UVBUS
1001 VHDETM_UP1 The rise of pin voltage detection voltage 56.2 % UVBUS
VHDETM_DWN1 The fall of pin voltage detection voltage 29.4 % UVBUS
1010 VHDETM_UP2 The rise of pin voltage detection voltage 60.5 % UVBUS
VHDETM_DWN2 The fall of pin voltage detection voltage 45.0 % UVBUS
UDPi pull-up detection
Note 2
Connect detection with
the full speed function
(pull-up resistor)
1000 RHDET_PULL In full-speed mode, the power supply
voltage range of pull-up resistors
connected to the USB function
module is between 3.0 V and 3.6 V.
1.575 kΩ
1001
1010
UDMi pull-up detection
Note 2
Connect detection with
the low-speed (pull-up
resistor)
1000 RHDET_PULL In low-speed mode, the power supply
voltage range of pull-up resistors
connected to the USB function
module is between 3.0 V and 3.6 V.
1.575 kΩ
1001
1010
UDMi sink current
detection Note 2
Connect detection with
the BC1.2 portable
device (sink resistor)
1000 IHDET_SINK 25
μ
A
1001
1010
Notes 1. If the voltage output from UDPi or UDMi (i = 0, 1) exceeds the range of the MAX and MIN values prescribed
in this specification, DPCUSDETi (bit 8) and DMCUSDETi (bit 9) of the USBBCOPTi register are set to 1.
2. If the pull-up resistance or sink current prescribed in this specification is applied to UDPi or UDMi (i = 0,
1), DPCUSDETi (bit 8) and DMCUSDETi (bit 9) of the USBBCOPTi register are set to 1.
Remark i = 0, 1
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 120 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(4) BC option standard (Function)
(TA = −40 to +105°C, 4.35 V ≤ UVBUS ≤ 5.25 V, 3.0 V ≤ UVDD ≤ 3.6 V, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
UDPi/UDMi
input
reference
voltage
(UVBUS divider
ratio)
• VDOUEi = 0
(i = 0))
VDSELi
[3:0]
(i = 0)
0000 VDDET0 27 32 37 % UVBUS
0001 VDDET1 29 34 39 % UVBUS
0010 VDDET2 32 37 42 % UVBUS
0011 VDDET3 35 40 45 % UVBUS
0100 VDDET4 38 43 48 % UVBUS
0101 VDDET5 41 46 51 % UVBUS
0110 VDDET6 44 49 54 % UVBUS
0111 VDDET7 47 52 57 % UVBUS
1000 VDDET8 51 56 61 % UVBUS
1001 VDDET9 55 60 65 % UVBUS
1010 VDDET10 59 64 69 % UVBUS
1011 VDDET11 63 68 73 % UVBUS
1100 VDDET12 67 72 77 % UVBUS
1101 VDDET13 71 76 81 % UVBUS
1110 VDDET14 75 80 85 % UVBUS
1111 VDDET15 79 84 89 % UVBUS
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 121 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
3.6 Analog Characteristics
3.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Input channel Reference Voltage
Reference voltage (+) =
AVREFP
Reference voltage (−) =
AVREFM
Reference voltage (+) = VDD
Reference voltage (−) = VSS
Reference voltage (+) = VBGR
Reference voltage (−) =
AVREFM
ANI0 to ANI7 Refer to 3.6.1 (1). Refer to 3.6.1 (3). Refer to 3.6.1 (4).
ANI16, ANI17, ANI19 Refer to 3.6.1 (2).
Internal reference voltage
Temperature sensor output
voltage
Refer to 3.6.1 (1). −
(1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM
= 1), target pin : ANI2 to ANI7, internal reference voltage, and temperature sensor output voltage
(TA = −40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage
(−) = AVREFM = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 10 bit
Overall errorNote 1 AINL
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ AVREFP ≤ 5.5 V 1.2 ±3.5 LSB
Conversion time tCONV 10-bit resolution
Target pin: ANI2 to
ANI7
3.6 V ≤ VDD ≤ 5.5 V 2.125 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
10-bit resolution
Target pin: Internal
reference voltage,
and temperature
sensor output voltage
(HS (high-speed
main) mode)
3.6 V ≤ VDD ≤ 5.5 V 2.375 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.5625 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ AVREFP ≤ 5.5 V ±0.25 %FSR
Full-scale errorNotes 1, 2 EFS
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ AVREFP ≤ 5.5 V ±0.25 %FSR
Integral linearity errorNote 1 ILE
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ AVREFP ≤ 5.5 V ±2.5 LSB
Differential linearity error Note 1 DLE
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ AVREFP ≤ 5.5 V ±1.5 LSB
Analog input voltage VAIN ANI2 to ANI7 0 AVREFP V
Internal reference voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main)
mode)
VBGR Note 4 V
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main)
mode)
VTMPS25 Note 4 V
(Notes are listed on the next page.)
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 122 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
4. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 123 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) =
AVREFM/ANI1 (ADREFM = 1), target pin : ANI16, ANI17, ANI19
(TA = −40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference
voltage (−) = AVREFM = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 10 bit
Overall errorNote 1 AINL
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ AVREFP ≤ 5.5 V 1.2 ±5.0 LSB
Conversion time tCONV 10-bit resolution
Target ANI pin :
ANI16, ANI17, ANI19
3.6 V ≤ VDD ≤ 5.5 V 2.125 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR
Full-scale errorNotes 1, 2 EFS
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR
Integral linearity errorNote 1 ILE
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ AVREFP ≤ 5.5 V ±3.5 LSB
Differential linearity error Note 1 DLE
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ AVREFP ≤ 5.5 V ±2.0 LSB
Analog input voltage VAIN ANI16, ANI17, ANI19 0 AVREFP
and VDD
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 124 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(3) Reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), Reference voltage (−) = VSS (ADREFM = 0),
target ANI pin : ANI0 to ANI7, ANI16, ANI17, ANI19, internal reference voltage, and temperature sensor
output voltage
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 10 bit
Overall errorNotes 1, 2 AINL 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 1.2 ±7.0 LSB
Conversion time tCONV 10-bit resolution
Target ANI pin :
ANI0 to ANI7, ANI16,
ANI17, ANI19
3.6 V ≤ VDD ≤ 5.5 V 2.125 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
10-bit resolution
Target ANI pin : Internal
reference voltage, and
temperature sensor
output voltage (HS
(high-speed main) mode)
3.6 V ≤ VDD ≤ 5.5 V 2.375 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.5625 39
μ
s
2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS
10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR
Full-scale errorNotes 1, 2 EFS
10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR
Integral linearity errorNote 1 ILE 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±4.0 LSB
Differential linearity error Note 1 DLE 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB
Analog input voltage VAIN ANI0 to ANI7, ANI16, ANI17, ANI19 0 VDD V
Internal reference voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main)
mode)
VBGR Note 3 V
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main)
mode)
VTMPS25 Note 3 V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 125 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
(4) When Reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), Reference
voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0 to ANI7, ANI16, ANI17, ANI19
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (−) =
AVREFM Note 4 = 0 V, HS (high-speed main) mode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 Bit
Conversion time tCONV 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR
Integral linearity errorNote 1 ILE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB
Differential linearity error Note 1 DLE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±1.0 LSB
Analog input voltage VAIN 0 VBGR Note 3 V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
4. When reference voltage (−) = VSS, the MAX. values are as follows.
Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (−) = AVREFM.
Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (−) = AVREFM.
Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (−) = AVREFM.
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 126 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
3.6.2 Temperature sensor/internal reference voltage characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C 1.05 V
Internal reference voltage VBGR Setting ADS register = 81H 1.38 1.45 1.5 V
Temperature coefficient FVTMPS Temperature sensor that depends on the
temperature
−3.6 mV/°C
Operation stabilization wait time tAMP 5
μ
s
3.6.3 POR circuit characteristics
(TA = −40 to +105°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOR Power supply rise time 1.45 1.51 1.57 V
VPDR Power supply fall time 1.44 1.50 1.56 V
Minimum pulse widthNote TPW 300
μ
s
Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time
required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is
entered or the main system clock (fMAIN) is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the
clock operation status control register (CSC).
T
PW
V
POR
V
PDR
or 0.7 V
Supply voltage (V
DD
)
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 127 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
3.6.4 LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = −40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection
voltage
Supply voltage level VLVD0 Power supply rise time 3.90 4.06 4.22 V
Power supply fall time 3.83 3.98 4.13 V
VLVD1 Power supply rise time 3.60 3.75 3.90 V
Power supply fall time 3.53 3.67 3.81 V
VLVD2 Power supply rise time 3.01 3.13 3.25 V
Power supply fall time 2.94 3.06 3.18 V
VLVD3 Power supply rise time 2.90 3.02 3.14 V
Power supply fall time 2.85 2.96 3.07 V
VLVD4 Power supply rise time 2.81 2.92 3.03 V
Power supply fall time 2.75 2.86 2.97 V
VLVD5 Power supply rise time 2.70 2.81 2.92 V
Power supply fall time 2.64 2.75 2.86 V
VLVD6 Power supply rise time 2.61 2.71 2.81 V
Power supply fall time 2.55 2.65 2.75 V
VLVD7 Power supply rise time 2.51 2.61 2.71 V
Power supply fall time 2.45 2.55 2.65 V
Minimum pulse width tLW 300
μ
s
Detection delay time tLD 300
μ
s
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 128 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
LVD Detection Voltage of Interrupt & Reset Mode
(TA = −40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Interrupt and reset
mode
VLVDD0 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage 2.64 2.75 2.86 V
VLVDD1 LVIS1, LVIS0 = 1, 0
Rising release reset voltage 2.81 2.92 3.03 V
Falling interrupt voltage 2.75 2.86 2.97 V
VLVDD2 LVIS1, LVIS0 = 0, 1
Rising release reset voltage 2.90 3.02 3.14 V
Falling interrupt voltage 2.85 2.96 3.07 V
VLVDD3 LVIS1, LVIS0 = 0, 0
Rising release reset voltage 3.90 4.06 4.22 V
Falling interrupt voltage 3.83 3.98 4.13 V
3.6.5 Power supply voltage rising slope characteristics
(TA = −40 to +105°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Power supply voltage rising slope SVDD 54 V/ms
Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD
reaches the operating voltage range shown in 3.4 AC Characteristics.
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 129 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
3.7 RAM Data Retention Characteristics
(TA = −40 to +105°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 1.44Note 5.5 V
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a
POR reset is effected, but data is not retained when a POR reset is effected.
V
DD
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
RAM data retention
VDDDR
Operation mod
e
3.8 Flash Memory Programming Characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
CPU/peripheral hardware clock
frequency
fCLK 2.4 V ≤ VDD ≤ 5.5 V 1 24 MHz
Number of code flash rewrites Cerwr Retaining years: 20 years
TA = +85°C Note 4
1,000 Times
Number of data flash rewrites
Notes 1, 2, 3
Retaining years: 1 year
TA = +25°C Note 4
1,000,000
Retaining years: 5 years
TA = +85°C Note 4
100,000
Retaining years: 20 years
TA = +85°C Note 4
10,000
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after
the rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library.
3. These specifications show the characteristics of the flash memory and the results obtained from
Renesas Electronics reliability testing.
4. This temperature is the average value at which data are retained.
3.9 Dedicated Flash Memory Programmer Communication (UART)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate During serial programming 115,200 1,000,000 bps
<R>
<R>
<R>
<R>
<R>
<R>
<R>
RL78/G1C 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Page 130 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
3.10 Timing Specs for Switching Flash Memory Programming Modes
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
How long from when an external
reset ends until the initial
communication settings are
specified
tSUINIT POR and LVD reset must end before the
external reset ends.
100 ms
How long from when the TOOL0
pin is placed at the low level until
an external reset ends
tSU POR and LVD reset must end before the
external reset ends.
10
μ
s
How long the TOOL0 pin must be
kept at the low level after an
external reset ends
(excluding the processing time of
the firmware to control the flash
memory)
tHD POR and LVD reset must end before the
external reset ends.
1 ms
RESET
TOOL0
<1> <2> <3>
t
SUINIT
723 μs + t
HD
processing
time
t
SU
<4>
00H reception
(TOOLRxD, TOOLTxD mode)
<1> The low level is input to the TOOL0 pin.
<2> The external reset ends (POR and LVD reset must end before the external reset
ends.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete
the baud rate setting.
Remark t
SUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within
100 ms from when the resets end.
tSU: How long from when the TOOL0 pin is placed at the low level until an external reset ends
tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end
(excluding the processing time of the firmware to control the flash memory)
RL78/G1C 4. PACKAGE DRAWINGS
Page 131 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
4. PACKAGE DRAWINGS
4.1 32-pin Products
R5F10JBCAFP, R5F10KBCAFP
R5F10JBCGFP, R5F10KBCGFP
0.145±0.055
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
7.00±0.10
7.00±0.10
9.00±0.20
9.00±0.20
1.70 MAX.
0.10±0.10
1.40
c
θ
e
x
y
0.80
0.20
0.10
L0.50±0.20
0° to 8°
0.37±0.05
b
NOTE
1.Dimensions “ 1” and “ 2” do not include mold flash.
2.Dimension “ 3” does not include trim offset.
y
e
xb M
θ
L
c
HD
HE
A1
A2
A
D
E
detail of lead end
8
16
1
32 9
17
25
24
2
1
3
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LQFP32-7x7-0.80 PLQP0032GB-A P32GA-80-GBT-1 0.2
RL78/G1C 4. PACKAGE DRAWINGS
Page 132 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
R5F10JBCANA, R5F10KBCANA
R5F10JBCGNA, R5F10KBCGNA
2013 Renesas Electronics Corporation. All rights reserved.
S
y
e
Lp
SxbA B
M
A
D
E
24
16
17
8
9
1
32
A
S
B
A
D
E
25
EXPOSED DIE PAD
P-HWQFN32-5x5-0.50 PWQN0032KB-A P32K8-50-3B4-5 0.06
8
1
9
16
25
32
INDEX AREA
2
2
D
A
Lp
0.20
3.50
0.40
5.00
5.00
3.50
Referance
Symbol Min Nom Max
Dimension in Millimeters
0.30
0.300.50
b0.18
x
A0.80
y0.05
0.00
0.25
e
Z
Z
c
D
E
1
D
E
2
2
2
E
0.50
0.05
0.75
0.75
0.15 0.25
A1C2
5.05
4.95
5.05
4.95
Z
Z
D
E
17
24
JEITA Package code RENESAS code Previous code MASS (TYP.)[g]
DETAIL OF A PART
<R>
RL78/G1C 4. PACKAGE DRAWINGS
Page 133 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
4.2 48-pin Products
R5F10JGCAFB, R5F10KGCAFB
R5F10JGCGFB, R5F10KGCGFB
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LFQFP48-7x7-0.50 PLQP0048KF-A P48GA-50-8EU-1 0.16
S
y
e
Sxb M
θ
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S
0.145 +0.055
−0.045
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
7.00±0.20
7.00±0.20
9.00±0.20
9.00±0.20
1.60 MAX.
0.10±0.05
1.40±0.05
0.25
c
θ
e
x
y
ZD
ZE
0.50
0.08
0.08
0.75
0.75
L
Lp
L1
0.50
0.60±0.15
1.00±0.20
3°+5°
−3°
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
detail of lead end
0.22±0.05
b
12
24
1
48 13
25
37
36
2012 Renesas Electronics Corporation. All rights reserved.
RL78/G1C 4. PACKAGE DRAWINGS
Page 134 of 134
R01DS0348EJ0120 Rev.1.20
Sep 30, 2016
R5F10JGCANA, R5F10KGCANA
R5F10JGCGNA, R5F10KGCGNA
MASS (Typ) [g]
0.13
Unit: mm
Previous CodeRENESAS Code
PWQN0048KB-A 48PJN-A
P48K8-50-5B4-7
JEITA Package Code
P-HWQFN48-7x7-0.50
D
E
A
A1
b
e
Lp
x
y
ZD
ZE
c2
D2
E2
6.95
6.95
0.00
0.18
0.30
0.15
Min Nom
Dimensions in millimeters
Reference
Symbol
Max
7.00
7.00
0.25
0.50
0.40
0.75
0.75
0.20
5.50
5.50
7.05
7.05
0.80
0.30
0.50
0.05
0.05
0.25
S
y
e
Lp
SxbA B
M
A
D
E
36
24
25
12
13
1
48
A
S
B
A
D2
E2
37
DETAIL OF A PART
EXPOSED DIE PAD
12
1
13
24
37
48
INDEX AREA
A1c2
ZD
ZE
25
36
© 2015 Renesas Electronics Corporation. All rights reserved.
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<R>
Revision History RL78/G1A Data Sheet
Rev.
Date
Description
Page Summary
0.01 Sep 20, 2012 - First Edition issued
1.00 Aug 08, 2013 Throughout Deletion of the bar over SCK and SCKxx
Renaming of fEXT to fEXS
Renaming of interval timer (unit) to 12-bit interval timer
Addition of products for G: Industrial applications (TA = -40 to +105 °C )
1 Change of 1.1 Features
2 Change of 1.2 List of Part Numbers
3 Modification of Figure 1-1. Part Number, Memory Size, and Package of RL78/G1C
4, 5 Addition of remark to 1.3 Pin Configuration (Top View)
15, 16 Change of 1.6 Outline of Functions
17 to 76 Addition of a whole chapter
77 to 131 Addition of a whole chapter
132 Addition of products for G: Industrial applications (TA = -40 to +105 °C )
1.10 Nov 15, 2013 77 Caution 3 added.
79 Note for operating ambient temperature in 3.1 Absolute Maximum Ratings deleted.
1.20 Sep 30, 2016 4 to 7 Modification of pin configuration in 1.3.1 32-pin products
8 to 11 Modification of pin configuration in 1.3.2 48-pin products
15 Modification of description of main system clock in 1.6 Outline of Functions
74 Modification of title of 2.7 RAM Data Retention Characteristics and figure
74 Modification of table of 2.8 Flash Memory Programming Characteristics
129 Modification of title of 3.7 RAM Data Retention Characteristics and figure
129 Modification of table of 3.8 Flash Memory Programming Characteristics and addition
of Note 4
132 Change of figure in 4.1 32-pin Products
134 Change of figure in 4.2 48-pin Products
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
All trademarks and registered trademarks are the property of their respective owners.
C - 1
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
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