PRELIMINARY
32K x 16 Static RAM
CY7C1022
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05090 Rev. ** Revised September 18, 2001
022CY7C10
Features
• 5.0V operation (± 10%)
• High speed
—tAA = 12 ns
• Low active po wer
—825 mW (max., 10 ns, “L” version)
• Very Low standby pow er
—500 µW (max., “L” version)
• Automatic power-down when deselected
• Independent Control of Upper and Lower bytes
• Available in 400-mil SOJ
Functional Description
The CY7C1022 is a high-performance CMOS static RAM or-
ganize d as 32,768 word s by 16 bits. Thi s de vi ce has an au to-
matic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking chip enable
(CE) inpu t HIGH and wr ite enable (WE ) input LOW. If byte low
enable (BLE) is LOW, then data from I/O pins (I/O1 through
I/O8), is wr itte n in to th e lo cation specified on th e address pins
(A0 through A14). If by te hi gh enable (BHE) i s LOW, then da ta
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A14).
Reading from the device is accomplished by taking chip en-
able (CE) HIGH and output enab le (OE) LOW while forcing the
write enable (WE) HIGH. If byte low enable (BLE) is LOW , then
data from the memory location specified by the address pins
will appear on I/O1 to I/O8. If byte high enable (BHE) is LOW,
then data from memory will appear on I/O9 to I/O16. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
LOW), the outputs are d isabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
HIGH, and WE LOW).
The CY7C1022 is available in standard 400-mil-wide SOJ
packages.
2CY7C1022
WE
Logic Block Diagram Pin Configurati on
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
SOJ
12
13
41
44
43
42
16
15 29
30
VCC
A10
A9
A8
A7
NC
NC
A14
OE
VSS
A0
I/O16
A13
I/O3
I/O1
I/O2
BHE
NC
A12
A11
1022-2
18
17
20
19
I/O4
27
28
25
26
22
21 23
24 NC
VSS
I/O7
I/O5
I/O6
I/O8
A1
A2
BLE
VCC
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
A3
A4
A5
A6
32K x 16
RAM Array I/O1 – I/O8
ROW DECODER
A6
A5
A4
A3
A0
COLUMN DECODER
A
9
A
10
A
11
A
12
A
13
A
14
SENSE AMPS
DATA IN DRIVERS
OE
A2
A1I/O9 – I/O16
CE
WE
BLE
BHE
A
8
A
7
CE
Selection Guide
7C1022-12 7C1022-15
Maximum Access Time (ns) 12 15
Maximum Operating Current (mA) 170 160
L140 130
Maximum CMOS Standby Current (mA) 3 3
L0.1 0.1
Shaded areas contain advance information.
CY7C1022
PRELIMINARY
Document #: 38-05090 Rev. ** Page 2 of 8
Maximum Ratings
(Above w hi ch the useful life m ay be im pai red. For user guide-
lines, not tes ted .)
Storage Temperature ................................–65×C to +150×C
Ambient Temperature with
Power Applie d............................................–55×C to +125×C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage[1]................................–0.5V to VCC + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Range Ambient
Temperature[2] VCC
Commercial 0°C to +70°C 4.5V–5.5V
Electrical Characteristics Over the Op erat ing Range
Parameter Description Test Conditions
7C1022-12 7C1022-15
UnitMin. Max. Min. Max.
VOH Output HI GH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
VOL Output LO W Volta ge VCC = Min., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 6.0 2.2 6.0 V
VIL Input LOW Voltage[1] –0.5 0.8 –0.5 0.8 V
IIX Input Load Current GND < VI < VCC –1+1 –1+1 µA
IOZ Output Lea kage
Current GND < VI < VCC,
Output Disabled –2+2 –2+2 µA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
170 160 mA
L140 130
ISB1 Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
20 20 mA
L10 10
ISB2 Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3 V,
or VIN < 0.3V, f=0
3 3 mA
L0.1 0.1 mA
Shaded area contains advance information.
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 8pF
COUT Output Capacitance 8pF
AC Test Loads and W aveforms
Notes:
1. VIL (min.) = –2.0V for pulse durat ions of less than 20 ns.
2. TA is the “instant on” case temp erature.
3. Tested initially and after any design or process changes that may affect these parameters.
1022-3
1022-4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
<3ns <3ns
OUTPUT
R 481ΩR 481Ω
R2
255ΩR2
255Ω
167Ω
Equivalent to: THÉVENIN
EQUIVALENT 1.73V
30 pF
CY7C1022
PRELIMINARY
Document #: 38-05090 Rev. ** Page 3 of 8
Switching Characteristics[4] Over the Operating Range
Parameter Description
7C1022-12 7C1022-15
UnitMin. Max. Min. Max.
READ CYCLE
tRC Read Cyc le Time 12 15 ns
tAA Address to Data Valid 12 15 ns
tOHA Data Hold from Address Change 3 3 ns
tACE CE HIGH to Da ta Valid 12 15 ns
tDOE OE LOW to Data Valid 6 7 ns
tLZOE OE LOW to Low Z 0 0 ns
tHZOE OE HIGH to High Z[5, 6] 6 7 ns
tLZCE CE HIGH to Low Z[6] 3 3 ns
tHZCE CE LOW to High Z[5, 6] 6 7 ns
tPU CE HIGH to Power-Up 0 0 ns
tPD CE LOW to Power-Down 12 15 ns
tDBE Byte enable to Data Valid 6 7 ns
tLZBE Byte enable to Low Z 0 0 ns
tHZBE Byte disable to High Z 6 7 ns
WRITE CYCLE[7]
tWC Write Cycle Time 12 15 ns
tSCE CE HIGH to Write End 910 ns
tAW Address Set-Up to Write End 810 ns
tHA Addr ess Hold from Write End 0 0 ns
tSA Address Set-Up to Write Start 0 0 ns
tPWE WE Pulse W idth 810 ns
tSD Data Set-Up to Write End 610 ns
tHD Data Hold from Write End 0 0 ns
tLZWE WE HIGH to Low Z[6] 3 3 ns
tHZWE WE LOW to High Z[5, 6] 6 7 ns
tBW Byte enable to end of write 8 9 ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V , input pulse levels of 0 to 3.0V , and output loading of the specified
IOL/IOH and 30-pF l oad capa citan ce.
5. tHZOE, tHZBE, tHZCE, and tHZWE are speci fied w ith a load ca pacit ance of 5 pF as in part (b ) of AC Test L oads. T ransi tion i s measured ±500 mV from steady-st ate voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less t han tLZWE for any g iven dev ice.
7. The internal write time of the memory is defined by the overlap of CE HIGH, WE LOW and BHE / BLE LOW . CE HIGH, WE and BHE / BLE must be L OW to in itiate
a writ e, and the transition of these signals c an terminate the write. The input data set-u p and hold timing shou ld be referen ced to the leading edge of the s ignal that terminates
the write.
CY7C1022
PRELIMINARY
Document #: 38-05090 Rev. ** Page 4 of 8
Switching Waveforms
Notes:
8. Device is continuously selected. OE, CE, BHE and/or B HE = VIL
9. WE is HIGH for read c ycle.
10. Address valid prior to or coincident with CE tra nsition HIGH.
Read Cycle No.1
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
1022-5
ADDRESS
DATA OUT
[8, 9]
Read Cycle No.2 (OEControlled)
1022-6
50%
50%
DATA VALID
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
HIGH
OE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
tDBE
tLZBE
tHZCE
BHE,BLE
[9, 10]
CURRENT
ICC
ISB
tRC
CE
CY7C1022
PRELIMINARY
Document #: 38-05090 Rev. ** Page 5 of 8
Notes:
11. Data I/O is high impedance if OE or BHE and/or BL E= VIH.
12. If CE goes L OW s imultaneo usly w ith WE going H IGH, t he out put rema ins in a high-i mpedanc e state.
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)
1022-7
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
DATAI/O
ADDRESS
CE
WE
BHE, BLE
[11, 12]
t
Write Cycle No. 2 (BLEorBHE Controlled)
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
DATAI/O
ADDRESS
BHE,BLE
WE
CE
1022-8
CY7C1022
PRELIMINARY
Document #: 38-05090 Rev. ** Page 6 of 8
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled,OE LOW)
1022-10
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
DATA I/O
ADDRESS
CE
WE
BHE,BLE
tSA
tLZWE
tHZWE
Truth Table
CE OE WE BLE BHE I/O1 - I/O8I/O9 - I/O16 Mode Power
L X X X X High Z High Z Power-Down Standby (ISB)
H L H L L Data Out Data Out Read - All bits Active (ICC)
L H Data Out High Z Read - Lower bits only Active (ICC)
H L High Z Data Out Read - Upper bits only Active (ICC)
H X L L L Data In Data In Wr ite - All bits Active (ICC)
L H Data In High Z Write - Lower bits only Active (ICC)
H L High Z Data In Write - Upper bits only Active (ICC)
H H H X X High Z High Z Selected, Outputs Disa ble d Active (ICC)
H X X H H High Z High Z Selected, Outputs Disa ble d Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
12 CY7C1022-12VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1022
PRELIMINARY
Document #: 38-05090 Rev. ** Page 7 of 8
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagram
44-Lead (400-Mil) Molded SOJ V34
CY7C1022
PRELIMINARY
Document #: 38-05090 Rev. ** Page 8 of 8
Document Title: CY7C1022 32k x 16 Static RAM Data Sheet
Document Number: 38-05090
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 110184 09/29/01 SZV Change from Spec number: 38-00636 to 38-05090
