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LP38501-ADJ

LP38503-ADJ

SNVS522I –AUGUST 2007–REVISED AUGUST 2015

LP3850x-ADJ, LP3850xA-ADJ 3-A FlexCap Low Dropout Linear Regulator for

2.7-V to 5.5-V Inputs

1 Features 3 Description

TI's FlexCap low-dropout (LDO) linear regulators

1• Input Voltage: 2.7 V to 5.5 V feature unique compensation that allow use of any

• Adjustable Output Voltage: 0.6 V to 5 V type of output capacitor with no limits on minimum or

• FlexCap: Stable with Ceramic, Tantalum, or maximum equivalent series resistance (ESR). The

Aluminum Capacitors LP38501 and LP38503 series of LDOs operate from

a 2.7-V to 5.5-V input supply. These ultra-low-dropout

• Stable With 10-µF Input and Output Capacitors linear regulators respond very quickly to step

• Low Ground-Pin Current changes in load, making them suitable for low-voltage

• 25-nA Quiescent Current in Shutdown Mode microprocessor applications. Developed on a CMOS

process (utilizing a PMOS pass transistor) the

• Ensured Output Current of 3 A LP38501-ADJ and LP38503-ADJ have low quiescent

• Ensured VADJ Accuracy of ±1.5% at 25°C (A currents that change little with load current.

Grade) • GND Pin Current: Typically 2 mA at 3-A load

• Ensured Accuracy of ±3.5% at 25°C (STD) current.

• Overtemperature and Overcurrent Protection • Disable Mode: Typically 25-nA quiescent current

• ENABLE (EN) Pin (LP38501 only) when the EN pin is pulled low.

• Simplified Compensation: Stable with any type of

• –40°C to +125°C Operating Temperature Range output capacitor, regardless of ESR.

• Precision Output: Agrade versions available with

2 Applications 1.5% VADJ tolerance (25°C) and 3% over line,

• ASIC Power Supplies In: load, and temperature.

– Printers, Graphics Cards, DVD Players Device Information(1)

– Set Top Boxes, Copiers, Routers PART NUMBER PACKAGE BODY SIZE (NOM)

• DSP and FPGA Power Supplies DDPAK/TO-263 (5) 10.16 mm x 8.42 mm

LP38501

• SMPS Regulator LP38503 TO-263 (5) 10.16 mm x 9.85 mm

• Conversion from 3.3-V or 5-V Rail (1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Application Circuits

*Minimum capacitance required (see Application and Implementation).

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LP38501-ADJ

LP38503-ADJ

SNVS522I –AUGUST 2007–REVISED AUGUST 2015

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Table of Contents

7.4 Device Functional Modes........................................ 14

1 Features.................................................................. 18 Application and Implementation ........................ 15

2 Applications ........................................................... 18.1 Application Information............................................ 15

3 Description............................................................. 18.2 Typical Applications ............................................... 15

4 Revision History..................................................... 29 Power Supply Recommendations...................... 18

5 Pin Configurations and Functions....................... 310 Layout................................................................... 19

6 Specifications......................................................... 410.1 Layout Guidelines ................................................. 19

6.1 Absolute Maximum Ratings ...................................... 410.2 Layout Examples................................................... 19

6.2 ESD Ratings.............................................................. 411 Device and Documentation Support................. 20

6.3 Recommended Operating Conditions....................... 411.1 Documentation Support ........................................ 20

6.4 Thermal Information.................................................. 411.2 Community Resources.......................................... 20

6.5 Electrical Characteristics........................................... 511.3 Trademarks........................................................... 20

6.6 Typical Characteristics.............................................. 711.4 Electrostatic Discharge Caution............................ 20

7 Detailed Description.............................................. 911.5 Glossary................................................................ 20

7.1 Overview................................................................... 912 Mechanical, Packaging, and Orderable

7.2 Functional Block Diagrams ....................................... 9Information........................................................... 20

7.3 Feature Description................................................... 9

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (April 2013) to Revision I Page

• Added Device Information and Pin Configuration and Functions sections, ESD Rating and updated Thermal

Information tables, Feature Description,Device Functional Modes,Application and Implementation,Power Supply

Recommendations,Layout,Device and Documentation Support, and Mechanical, Packaging, and Orderable

Information sections; remove lead temp from Abs Max table (in POA); remove obsolete heatsinking content; update

thermal values ........................................................................................................................................................................ 1

• Deleted obsolete heatsinking information for DDPAK/TO-263 package ............................................................................. 18

Changes from Revision G (April 2013) to Revision H Page

• Changed layout of National data sheet to TI format .............................................................................................................. 1

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5 Pin Configurations and Functions

KTT Package (LP38501) KTT Package (LP38503)

5-Pin DDPAK/TO-263 5-Pin DDPAK/TO-263

Top View Top View

NDQ Package (LP38501) NDQ Package (LP38503)

5-Pin TO-263 5-Pin TO-263

Top View Top View

Pin Functions

LP38501 LP38503 LP38501 LP38503 TYPE DESCRIPTION

NAME DDPAK/TO-263 TO-263

ADJ 5 5 5 5 O Sets output voltage.

Enable (LP38501-ADJ only). Pull high to enable the output,

EN 1 — 1 — I low to disable the output. This pin has no internal bias and

must be either tied to the input voltage, or actively driven.

GND 3 3 3 3 G Ground

IN 2 2 2 2 I Input supply pin.

In the LP38503-ADJ, this pin has no internal connections. It

N/C — 1 — 1 — can be left floating or used for trace routing.

OUT 4 4 4 4 O Regulated output voltage pin.

The DAP is used as a thermal connection to remove heat from

the device to the circuit board DAP copper clad area which

DAP √√√√— acts as the heatsink. The DAP is electrically connected to the

backside of the die. The DAP must be connected to ground

potential, but can not be used as the only ground connection.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

IN pin voltage (survival) −0.3 6 V

EN pin voltage (survival) −0.3 6 V

OUT pin voltage (survival) −0.3 6 V

IOUT (survival) Internally limited

Power dissipation(2) Internally limited

Storage temperature, Tstg −65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Operating junction temperature must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD),

maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (RθJA). See Application and

Implementation.

6.2 ESD Ratings VALUE UNIT

VESD Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)

MIN NOM MAX UNIT

Input supply voltage 2.7 5.5 V

Enable input voltage 0 5.5 V

Output current (DC) 0 3 A

VOUT 0.6 5 V

Junction temperature(2) −40 125 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Operating junction temperature must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD),

maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (RθJA). See Application and

Implementation.

6.4 Thermal Information LP38501 and LP38503

THERMAL METRIC(1) KTT(DDPAK/TO-263) NDQ (TO-263) UNIT

5 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance 41.8 33.3 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 45.0 22.1 °C/W

RθJB Junction-to-board thermal resistance 24.8 16.9 °C/W

ψJT Junction-to-top characterization parameter 13.1 5.8 °C/W

ψJB Junction-to-board characterization parameter 23.8 16.8 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 2.4 2.3 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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6.5 Electrical Characteristics

Unless otherwise specified VIN = 3.3 V, IOUT = 10 mA, CIN = 10 μF, COUT = 10 μF, VEN = VIN, VOUT = 1.8 V. Minimum and

maximum limits apply over the junction temperature (TJ) range of –40°C to +125°C and are specified through test, design, or

statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for reference

purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

2.7 V ≤VIN ≤5.5 V

10 mA ≤IOUT ≤3 A 0.584 0.605 0.626

TJ= 25°C

VADJ ADJ pin voltage(1) V

2.7 V ≤VIN ≤5.5 V 0.575 0.635

10 mA ≤IOUT ≤3 A

2.7 V ≤VIN ≤5.5 V

10 mA ≤IOUT ≤3 A 0.596 0.605 0.614

TJ= 25°C

VADJ ADJ pin voltage (A grade)(1) V

2.7 V ≤VIN ≤5.5 V 0.587 0.623

10 mA ≤IOUT ≤3 A

2.7 V ≤VIN ≤5.5 V 50 nA

TJ= 25°C

IADJ ADJ pin bias current 2.7 V ≤VIN ≤5.5 V 750 nA

IOUT = 3 A 420 550 mV

TJ= 25°C

VDO Dropout voltage(2)

IOUT = 3 A 665 mV

2.7 V ≤VIN ≤5.5 V 0.04

ΔVOUT /TJ= 25°C

Output voltage line regulation(1)(3) %/V

ΔVIN 2.7 V ≤VIN ≤5.5 V 0.05

10 mA < IOUT < 3 A 0.12

ΔVOUT / Output voltage load regulation(1) TJ= 25°C %/A

ΔIOUT (4) 10 mA < IOUT < 3 A 0.24

10 mA < IOUT < 3 A 2 4

Ground pin current in normal TJ= 25°C

IGND mA

operation mode 10 mA < IOUT < 1.5 A 5

VEN < VIL(EN), TJ= 25°C 0.025 0.125

IDISABLED Ground pin current µA

VEN < VIL(EN) 15

IOUT(PK)GND Peak output current VOUT ≥VOUT(NOM) – 5% 6 A

VOUT = 0 V 6

ISC Short-circuit current A

VOUT = 0 V, TJ= 25°C 3.5

ENABLE INPUT (LP38501 Only)

VIH(EN) Enable logic high VOUT = ON 1.4 V

VIL(EN) Enable logic low VOUT = OFF 0.65

Time from VEN < VIL(EN) to VOUT = OFF

td(off) Turnoff delay 25 µs

ILOAD = 3 A

Time from VEN > VIH(EN) to VOUT = ON

td(on) Turnon delay 25 µs

ILOAD = 3 A

IIH(EN) Enable pin high current VEN = VIN 35 nA

IIL(EN) Enable pin low current VEN = 0 V 35

(1) The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included

in the adjust voltage tolerance specification.

(2) Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. For

any output voltage less than 2.5 V, the minimum VIN operating voltage is the limiting factor.

(3) Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage.

(4) Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in the load current.

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Electrical Characteristics (continued)

Unless otherwise specified VIN = 3.3 V, IOUT = 10 mA, CIN = 10 μF, COUT = 10 μF, VEN = VIN, VOUT = 1.8 V. Minimum and

maximum limits apply over the junction temperature (TJ) range of –40°C to +125°C and are specified through test, design, or

statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for reference

purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AC PARAMETERS

VIN = 3 V, IOUT = 3 A, ƒ = 120 Hz 58

PSRR Ripple rejection dB

VIN = 3 V, IOUT = 3 A, ƒ = 1 kHz 56

ρn(l/f) Output noise density ƒ = 120 Hz, COUT = 10 µF CER 1 µV/√Hz

BW = 100 Hz – 100 kHz

enOutput noise voltage 100 µV(RMS)

COUT = 10 µF CER

THERMALS

TSD Thermal shutdown TJrising 170 — °C

ΔTSD Thermal shutdown hysteresis TJfalling from TSD 10 — °C

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6.6 Typical Characteristics

Unless otherwise specified: TJ= 25°C, VIN = 2.7 V, VEN = VIN, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA, VOUT = 1.8 V.

Figure 2. Noise Density

Figure 1. Noise Density

Figure 4. IGND(OFF) vs Temperature

Figure 3. IGND vs Load Current

Figure 6. Dropout Voltage vs Load Current

Figure 5. VADJ vs Temperature

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Typical Characteristics (continued)

Unless otherwise specified: TJ= 25°C, VIN = 2.7 V, VEN = VIN, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA, VOUT = 1.8 V.

Figure 8. Turnon Characteristics

Figure 7. VEN vs Temperature

Figure 9. Load Regulation vs Temperature Figure 10. PSRR

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7 Detailed Description

7.1 Overview

The LP38501-ADJ and LP38503-ADJ are FlexCap and low-dropout adjustable regulators, the output voltage can

be set from 0.6 V to 5 V. Standard regulator features, such as overcurrent and overtemperature protections, are

also included.

The LP38501-ADJ and LP38503-ADJ contain several features:

• Stable with any type of output capacitor

• Fast load transient response

• Disable Mode (LP38501-ADJ only)

7.2 Functional Block Diagrams

Figure 11. LP38501-ADJ Block Diagram

Figure 12. LP38503-ADJ Block Diagram

7.3 Feature Description

7.3.1 Stability and Phase Margin

Any regulator which operates using a feedback loop must be compensated in such a way as to ensure adequate

phase margin, which is defined as the difference between the phase shift and –180 degrees at the frequency

where the loop gain crosses unity (0 dB). For most LDO regulators, the ESR of the output capacitor is required to

create a zero to add enough phase lead to ensure stable operation.

Figure 13 shows the gain/phase plot of the LP38501-ADJ and LP38503-ADJ with an output of 1.2 V, a 10-µF

ceramic output capacitor, delivering 2 A of load current. The unity-gain crossover occurs at 300 kHz, and the

phase margin is about 40° (which is very stable).

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PL OUT

F2 R C

u S u u

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Feature Description (continued)

Figure 13. Gain-Bandwidth Plot for 2-A Load

Figure 14 shows the gain and phase with no external load. In this case, the only load is provided by the gain

setting resistors (about 12 kΩtotal in this test). It is immediately obvious that the unity-gain frequency is

significantly lower (dropping to about 500 Hz), at which point the phase margin is 125°.

Figure 14. Gain-Bandwidth Plot for No Load

The reduction in unity-gain bandwidth as load current is reduced is normal for any LDO regulator using a P-FET

or PNP pass transistor, because they have a pole in the loop gain function given by:

(1)

Equation 1 calculates how the pole goes to the highest frequency when RLis minimum value (maximum load

current). In general, LDOs have maximum bandwidth (and lowest phase margin) at full load current. In the case

of the LP38501-ADJ, good phase margin is seen even when using ceramic capacitors with ESR values of only a

few mΩ.

7.3.2 Load Transient Response

Load transient response is defined as the change in regulated output voltage which occurs as a result of a

change in load current. Many applications have loads which vary, and the control loop of the voltage regulator

must adjust the current in the pass FET transistor in response to load current changes. For this reason,

regulators with wider bandwidths often have better transient response.

The LP38501-ADJ employs an internal feed-forward design which makes the load transient response much

faster than would be predicted simply by loop speed; this feedforward means any voltage changes appearing on

the output are coupled through to the high-speed driver used to control the gate of the pass FET along a signal

path using very fast FET devices. Because of this, the pass transistor’s current can change very quickly.

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Feature Description (continued)

Figure 15 shows the output transient response resulting from a change in load current of 0.1 A – 3 A, and then 3

A – 0.1 A with a load current slew rate of 500 mA/µs. As shown in Figure 15, the resulting change in output

voltage is only about 40 mV (peak), which is just slightly over 2% for the 1.8-V output used for this test. This is

excellent performance for such a small output capacitor.

Figure 15. Load Transient Response: 10-µF Ceramic, 0.5-A/µs Di/Dt

When the load current changes much more quickly, the output voltage will show more change because the loop

and internal feedforward circuitry are not able to react as fast as the load changes. In such cases, it is the output

capacitor which must supply load current during the transition until the loop responds and changes the pass

transistor’s drive to deliver the new value of load current. As an example, the slew rate of the load current will be

increased to 75 A/μs and the same test will be performed. In Figure 16, it can be seen that the peak excursion of

the output voltage during the transient has now increased to about 200 mV, which is just slightly over 11% for the

1.8-V output.

Figure 16. Load Transient Response: 10-μF Ceramic, 75 A/μs di/dt

A better understanding of the load transient can be obtained when the load’s rising edge is expanded in time

scale (Figure 16).

Figure 17. Rising Edge, 10-µF Ceramic, 75 A/µs di/dt

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Feature Description (continued)

Figure 16 shows that the output voltage starts “correcting” back upwards after less than a microsecond, and has

fully reversed direction after about 1.2 µs. This very rapid reaction is a result of the maximum loop bandwidth (full

load is being delivered) and the feedforward effect kicking on the drive to the FET before feedback gets fully

around the loop.

In cases where extremely fast load changes occur, and output voltage regulation better than 10% is required, the

output capacitance must be increased. When selecting capacitors, it must be understood that the better

performing ones usually cost the most. For fast changing loads, the internal parasitics of ESR (equivalent series

resistance) and ESL (equivalent series inductance) degrade the capacitor’s ability to source current quickly to the

load. The best capacitor types for transient performance are (in order):

1. Multilayer Ceramic: with the lowest values of ESR and ESL, they can have ESR values in the range of a few

milli Ohms. Disadvantage: capacitance values above about 22 µF significantly increase in cost.

2. Low-ESR Aluminum Electrolytics: these are aluminum types (like OSCON) with a special electrolyte which

provides extremely low ESR values, and are the closest to ceramic performance while still providing large

amounts of capacitance. These are cheaper (by capacitance) than ceramic.

3. Solid tantalum: can provide several hundred µF of capacitance, transient performance is slightly worse than

OSCON type capacitors, cheaper than ceramic in large values.

4. General purpose aluminum electrolytics: cheap and provide a lot of capacitance, but give the worst

performance.

As a first example, larger values of ceramic capacitance show how much reduction can be obtained from the

200-mV output change (Figure 16) which was seen with only a 10-µF ceramic output capacitor. In Figure 18, the

10-µF output capacitor is increased to 22 µF. The 200-mV transient is reduced to about 160 mV, which is from

about 11% of VOUT down to about 9%.

Figure 18. 22-µF Ceramic Output Capacitor

In Figure 19, the output capacitance is increased to 47 µF ceramic. It can be seen that the output transient is

further reduced down to about 120 mV, which is still about 6.6% of the output voltage. This shows that a 5X

increase in ceramic capacitance from the original 10 µF only reduced the peak voltage transient amplitude by

about 40%.

Figure 19. 47-µF Ceramic Output Capacitor

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Feature Description (continued)

In general, managing load transients is done by paralleling ceramic capacitance with a larger bulk capacitance.

In this way, the ceramic can source current during the rapidly changing edge and the bulk capacitor can support

the load current after the first initial spike in current.

In the next test, the same 10-µF ceramic capacitor is paralleled with a general-purpose (less expensive)

aluminum electrolytic whose capacitance is 220 µF. As shown in Figure 20, there is a small improvement over

the 200 mV peak seen with the 10-µF ceramic capacitor alone. By adding the 220 µF aluminum capacitor, the

peak is reduced to about 160 mV (the same peak value as seen with a 22-µF ceramic capacitor alone).

Figure 20. 10-µF Ceramic Paralleled by 220-µF Generic Aluminum Electrolytic

A solid Tantalum works better, so the aluminum electrolytic is replaced by a 220-µF Tantalum (Figure 21). The

peak amplitude of the output transient is now reduced to about 130 mV, just slightly less efficient than the value

of the 47-µF ceramic capacitor alone.

Figure 21. 10-µF Ceramic Paralleled by 220-µF Tantalum

The OSCON (ultra low ESR) aluminum electrolytic is the best of the electrolytics. Figure 22 shows the output

voltage transient is reduced down to about 90 mV (about 5% of VOUT) when a 220-µF OSCON is added to the 10

µF ceramic. This indicates that some kind of ultra-low ESR aluminum electrolytic used in parallel with some

ceramic capacitance is probably the best approach for extremely fast transients, but each application must be

dialed in for it’s specific load requirements.

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Feature Description (continued)

Figure 22. 10-µF Ceramic Paralleled by 220-µF OSCON

7.3.3 Dropout Voltage

The dropout voltage of a regulator is defined as the input-to-output differential required by the regulator to keep

the output voltage within 2% of the nominal value. For CMOS LDOs, the dropout voltage is the product of the

load current and the RDS(on) of the internal MOSFET pass element.

Because the output voltage is beginning to “drop out” of regulation when it drops by 2%, electrical performance

of the device is reduced compared to the values listed in Electrical Characteristics for some parameters (line and

load regulation and PSRR would be affected).

7.3.4 Reverse Current Path

The internal MOSFET pass element in the LP38501-ADJ and LP38503-ADJ has an inherent parasitic diode.

During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse

biased. However, if the output is pulled above the input in an application, then current flows from the output to

the input as the parasitic diode gets forward biased. The output can be pulled above the input as long as the

current in the parasitic diode is limited to 200-mA continuous and 1-A peak. The regulator output pin must not be

taken below ground potential. If the LP38501-ADJ and LP38503-ADJ is used in a dual-supply system where the

regulator load is returned to a negative supply, the output must be diode-clamped to ground.

7.3.5 Short-Circuit Protection

The LP38501-ADJ and LP38503-ADJ contain internal current limiting which reduces output current to a safe

value if the output is overloaded or shorted. Depending upon the value of VIN, thermal limiting may also become

active as the average power dissipated causes the die temperature to increase to the limit value (about 170°C).

The hysteresis of the thermal shutdown circuitry can result in a “cyclic” behavior on the output as the die

temperature heats and cools.

7.4 Device Functional Modes

7.4.1 Enable Operation (LP38501-ADJ Only)

The ENABLE pin (EN) must be actively terminated by either a 10-kΩpullup resistor to VIN, or a driver which

actively pulls high and low (such as a CMOS rail to rail comparator). If active drive is used, the pullup resistor is

not required. This pin must be tied to VIN if not used (it must not be left floating).

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP38501-ADJ and LP38503-ADJ devices can provide 3-A output current with 2.7-V to 5.5-V input voltage.

These ultra-low-dropout linear regulators respond very quickly to step changes in load, making them suitable for

low-voltage microprocessor applications. Input and output capacitors of at least 10 µF are required.

8.2 Typical Applications

*Minimum capacitance required (see Detailed Design Procedure).

Figure 23. Typical Circuit (LP38501)

*Minimum capacitance required (see Detailed Design Procedure).

Figure 24. Typical Circuit (LP38503)

8.2.1 Design Requirements

For LP3850x-ADJ typical applications, use the parameters listed in Table 1 as the input parameters.

Table 1. Design Parameters

DESIGN PARAMETERS VALUE

Input voltage 2.7 V to 5.5 V

Output voltage 0.6 V to 5 V (adjustable)

Output current 3 A (maximum)

Input capacitor 10 µF (minimum)

Output capacitor 10 µF (minimum)

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8.2.2 Detailed Design Procedure

8.2.2.1 External Capacitors

The LP38501-ADJ and LP38503-ADJ require that at least 10-µF (±20%) capacitors be used at the input and

output pins located within one cm of the device. Larger capacitors may be used without limit on size for both CIN

and COUT. Capacitor tolerances such as temperature variation and voltage loading effects must be considered

when selecting capacitors to ensure that they provide the minimum required amount of capacitance under all

operating conditions for the application.

In general, ceramic capacitors are best for noise bypassing and transient response because of their ultra low

ESR. It must be noted that if ceramics are used, only the types with X5R or X7R dielectric ratings must be used

(never Z5U or Y5F). Capacitors which have the Z5U or Y5F characteristics have a drop in capacitance of as

much as 50% if their temperature increases from 25°C to 85°C. In addition, the capacitance drops significantly

with applied voltage: a typical Z5U or Y5F capacitor can lose as much as 60% of its rated capacitance if only half

of the rated voltage is applied to it. For these reasons, only X5R and X7R ceramics must be used.

8.2.2.2 Input Capacitor

All linear regulators can be affected by the source impedance of the voltage which is connected to the input. If

the source impedance is too high, the reactive component of the source may affect the control loop’s phase

margin. To ensure proper loop operation, the ESR of the capacitor used for CIN must not exceed 0.5 Ω. Any

good quality ceramic capacitor meets this requirement, as well as many good quality tantalums. Aluminum

electrolytic capacitors may also work, but can possibly have an ESR which increases significantly at cold

temperatures. If the ESR of the input capacitor may exceed 0.5 Ω, it is recommended that a 2.2-µF ceramic

capacitor be used in parallel, as this assures stable loop operation.

8.2.2.3 Output Capacitor

Any type of capacitor may be used for COUT, with no limitations on minimum or maximum ESR, as long as the

minimum amount of capacitance is present. The amount of capacitance can be increased without limit.

Increasing the size of COUT typically gives improved load transient response.

8.2.2.4 Setting The Output Voltage

The output voltage of the LP38501-ADJ and LP38503-ADJ can be set to any value between 0.6 V and 5 V using

two external resistors shown as R1 and R2 in Figure 25.

Figure 25. Setting Output Voltage

The value of R2 must always be less than or equal to 10 kΩfor good loop compensation. R1 can be selected for

a given VOUT using the following formula:

VOUT = VADJ (1 + R1/R2) + IADJ (R1)

where

• VADJ is the adjust pin voltage

• IADJ is the bias current flowing into the adjust pin (2)

Product Folder Links: LP38501-ADJ LP38503-ADJ

LP38501-ADJ

LP38503-ADJ

www.ti.com

SNVS522I –AUGUST 2007–REVISED AUGUST 2015

8.2.2.5 RFI/EMI Susceptibility

Radio frequency interference (RFI) and electro-magnetic interference (EMI) can degrade any integrated circuit's

performance because of the small dimensions of the geometries inside the device. In applications where circuit

sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must

be taken to ensure that this does not affect the device regulator.

If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes

from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the

device to reduce the amount of EMI conducted into the device.

If the LP38501-ADJ or LP38503-ADJ output is connected to a load which switches at high speed (such as a

clock), the high-frequency current pulses required by the load must be supplied by the capacitors on the device

output. Because the bandwidth of the regulator loop is less than 300 kHz, the control circuitry cannot respond to

load changes above that frequency. This means the effective output impedance of the device at frequencies

above 300 kHz is determined only by the output capacitor(s). Ceramic capacitors provide the best performance

in this type of application.

In applications where the load is switching at high speed, the output of the device may need RF isolation from

the load. In such cases, it is recommended that some inductance be placed between the output capacitor and

the load, and good RF bypass capacitors be placed directly across the load. PCB layout is also critical in high

noise environments, because RFI/EMI is easily radiated directly into PC traces. Noisy circuitry must be isolated

from clean circuits where possible, and grounded through a separate path. At MHz frequencies, ground planes

begin to look inductive and RFI/EMI can cause ground bounce across the ground plane. In multi-layer PC Board

applications, care must be taken in layout so that noisy power and ground planes do not radiate directly into

adjacent layers which carry analog power and ground.

8.2.2.6 Output Noise

Noise is specified in two ways:

• Spot noise or output noise density is the RMS sum of all noise sources, measured at the regulator output, at

a specific frequency (measured with a 1-Hz bandwidth). This type of noise is usually plotted on a curve as a

function of frequency.

• Total output noise or broadband noise is the RMS sum of spot noise over a specified bandwidth, usually

several decades of frequencies.

Spot noise is measured in units µV/√Hz or nV/√Hz and total output noise is measured in µV(RMS). The primary

source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a low-

frequency component and a high frequency component, which depend strongly on the silicon area and quiescent

current.

Noise can generally be reduced in two ways: by increasing the transistor area or increasing the reference

current. However, enlarging the transistors increases die size, and increasing the reference current means higher

total supply current (GND pin current).

8.2.2.7 Power Dissipation/Heatsinking

The maximum power dissipation (PD(MAX)) of the LP38501-ADJ and LP38503-ADJ is limited by the maximum

junction temperature of 125°C, along with the maximum ambient temperature (TA(MAX)) of the application, and the

thermal resistance (RθJA) of the package. Under all possible conditions, the junction temperature (TJ) must be

within the range specified in the Recommended Operating Conditions. The total power dissipation of the device

is given by:

PD= ((VIN −VOUT) × IOUT) + (VIN × IGND)

where

• IGND is the operating ground current of the device (specified under Electrical Characteristics). (3)

The maximum allowable junction temperature rise (ΔTJ) depends on the maximum expected ambient

temperature (TA(MAX)) of the application, and the maximum allowable junction temperature (TJ(MAX)):

ΔTJ= TJ(MAX)−TA(MAX) (4)

The maximum allowable value for junction-to-ambient thermal resistance, RθJA, can be calculated using the

formula:

RθJA =ΔTJ/ PD(MAX) (5)

Product Folder Links: LP38501-ADJ LP38503-ADJ

LP38501-ADJ

LP38503-ADJ

SNVS522I –AUGUST 2007–REVISED AUGUST 2015

www.ti.com

The LP38501-ADJ and LP38503-ADJ are available in the DDPAK/TO-263 and TO-263 packages. The thermal

resistance depends on the amount of copper area allocated to heat transfer.

8.2.3 Application Curves

Figure 27. Turnon Time

Figure 26. Turnon Time

Figure 28. Load Transient Response: 10-μF Ceramic, 75 A/μs di/dt

9 Power Supply Recommendations

The LP38501-ADJ and LP38503-ADJ devices are designed to operate from an input voltage supply range

between 2.7 V and 5.5 V. The input voltage range provides adequate headroom in order for the device to have a

regulated output. This input supply must be well regulated. An input capacitor of at least 10 μF is required.

Product Folder Links: LP38501-ADJ LP38503-ADJ

Ground

IN OUT

N/C

Input

Capacitor Output

Capacitor

ADJ

Ground

IN OUT

Input

Capacitor Output

Capacitor

Pull-up

Resistor

ADJ

LP38501-ADJ

LP38503-ADJ

www.ti.com

SNVS522I –AUGUST 2007–REVISED AUGUST 2015

10 Layout

10.1 Layout Guidelines

Good layout practices minimize voltage error and prevent instability which can result from ground loops. The

input and output capacitors must be directly connected to the device pins with short traces that have no other

current flowing in them (Kelvin connect).

The best way to do this is to place the capacitors very near the device and make connections directly to the

device pins via short traces on the top layer of the PCB. The regulator ground pin must be connected through

vias to the internal or backside ground plane so that the regulator has a single point ground.

The external resistors which set the output voltage must also be located very near the device with all connections

directly tied via short traces to the pins of the device (Kelvin connect). Do not connect the resistive divider to the

load point or DC error could be induced.

10.2 Layout Examples

Figure 29. LP38501-ADJ TO-263 Layout

Figure 30. LP38503-ADJ TO-263 Layout

Product Folder Links: LP38501-ADJ LP38503-ADJ

LP38501-ADJ

LP38503-ADJ

SNVS522I –AUGUST 2007–REVISED AUGUST 2015

www.ti.com

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Links

Table 2 lists quick access links. Categories include technical documents, support and community resources,

tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &

PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY

LP38501-ADJ Click here Click here Click here Click here Click here

LP38503-ADJ Click here Click here Click here Click here Click here

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LP38501-ADJ LP38503-ADJ

PACKAGE OPTION ADDENDUM

www.ti.com 21-Jul-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP38501ATJ-ADJ/NOPB ACTIVE TO-263 NDQ 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LP38501A

TJ-ADJ

LP38501TJ-ADJ/NOPB ACTIVE TO-263 NDQ 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM LP38501

TJ-ADJ

LP38501TS-ADJ/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38501

TS-ADJ

LP38501TSX-ADJ/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38501

TS-ADJ

LP38503ATJ-ADJ/NOPB ACTIVE TO-263 NDQ 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LP38503A

TJ-ADJ

LP38503TJ-ADJ/NOPB ACTIVE TO-263 NDQ 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LP38503

TJ-ADJ

LP38503TS-ADJ/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38503

TS-ADJ

LP38503TSX-ADJ/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38503

TS-ADJ

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

PACKAGE OPTION ADDENDUM

www.ti.com 21-Jul-2015

Addendum-Page 2

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP38501ATJ-ADJ/NOPB TO-263 NDQ 5 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

LP38501TJ-ADJ/NOPB TO-263 NDQ 5 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

LP38501TSX-ADJ/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP38503ATJ-ADJ/NOPB TO-263 NDQ 5 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

LP38503TJ-ADJ/NOPB TO-263 NDQ 5 1000 330.0 24.4 10.6 15.4 2.45 12.0 24.0 Q2

LP38503TSX-ADJ/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 21-Jul-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP38501ATJ-ADJ/NOPB TO-263 NDQ 5 1000 367.0 367.0 35.0

LP38501TJ-ADJ/NOPB TO-263 NDQ 5 1000 367.0 367.0 35.0

LP38501TSX-ADJ/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP38503ATJ-ADJ/NOPB TO-263 NDQ 5 1000 367.0 367.0 35.0

LP38503TJ-ADJ/NOPB TO-263 NDQ 5 1000 367.0 367.0 35.0

LP38503TSX-ADJ/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 21-Jul-2015

Pack Materials-Page 2

MECHANICAL DATA

NDQ0005A

www.ti.com

TJ5A (Rev F)

MECHANICAL DATA

KTT0005B

www.ti.com

BOTTOM SIDE OF PACKAGE

TS5B (Rev D)

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