_______________General Description
The MX7837/MX7847 are dual, 12-bit, multiplying, volt-
age-output digital-to-analog converters (DACs). Each
DAC has an output amplifier and a feedback resistor.
The output amplifier is capable of developing ±10V
across a 2kΩload. The amplifier feedback resistor is
internally connected to VOUT on the MX7847. No exter-
nal trims are required to achieve full 12-bit performance
over the entire operating temperature range.
The MX7847 has a 12-bit parallel data input, whereas
the MX7837 operates with a double-buffered 8-bit-bus
interface that loads data in two write operations. All
logic signals are level triggered and are TTL and CMOS
compatible. Fast timing specifications make these
DACs compatible with most microprocessors.
________________________Applications
Small Component-Count Analog Systems
Digital Offset/Gain Adjustments
Industrial Process Control
Function Generators
Automatic Test Equipment
Automatic Calibration
Machine and Motion Control Systems
Waveform Reconstruction
Synchro Applications
____________________________Features
♦Two 12-Bit Multiplying DACs with Buffered
Voltage Output
♦Specified with ±12V or ±15V Supplies
♦No External Adjustments Required
♦Fast Timing Specifications
♦24-Pin DIP and SO Packages
♦12-Bit Parallel Interface (MX7847)
8-Bit + 4-Bit Interface (MX7837)
______________Ordering Information
Ordering Information continued on last page.
* Contact factory for availability and processing to MIL-STD-883.
MX7837/MX7847
Complete, Dual, 12-Bit
Multiplying DACs
________________________________________________________________
Maxim Integrated Products
1
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12 13
DB0/DB8
DB1/DB9
DB2/DB10
DB3/DB11
DB4
DB5
DB6
DB7
A0
A1
LDAC
WR
RFBB
DGND
VREFB
VOUTB
AGNDB
VSS
VDD
AGNDA
VOUTA
VREFA
RFBA
CS
DIP/SO
TOP VIEW
MX7837
14
MX7847 on last page.
_________________Pin Configurations
48
12
DAC LATCH A
MSB
INPUT
LATCH
LSB
INPUT
LATCH
DAC A
48
12
DAC LATCH B
MSB
INPUT
LATCH
LSB
INPUT
LATCH
DAC B
CONTROL
LOGIC
LDAC
CS
WR
A0
A1
DB7
DB0
VREFB
VREFA
RFBA
VOUTA
AGNDA
RFBB
VOUTB
AGNDB
DGND VSS
VDD
MX7837
MX7847 on last page.
_________Typical Operating Circuits
Call toll free 1-800-998-8800 for free samples or literature.
19-0158; Rev 0; 7/93
PART TEMP. RANGE PIN-PACKAGE
MX7837JN 0°C to +70°C 24 Narrow Plastic DIP
MX7837KN 0°C to +70°C 24 Narrow Plastic DIP
MX7837JR 0°C to +70°C 24 Wide SO
MX7837KR 0°C to +70°C 24 Wide SO
MX7837C/D 0°C to +70°C Dice*
ERROR
(LSB)
±1
±1/2
±1
±1/2
±1
MX7837/MX7847
Complete, Dual, 12-Bit
Multiplying DACs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
VDD to DGND, AGNDA, AGNDB............................-0.3V to +17V
VSS to DGND, AGNDA, AGNDB (Note 1) ..............+0.3V to -17V
VREFA, VREFB to AGNDA, AGNDB .. (VSS - 0.3V) to (VDD + 0.3V)
AGNDA, AGNDB to DGND.........................-0.3V to (VDD + 0.3V)
VOUTA, VOUTB to AGNDA, AGNDB .....(VSS - 0.3V) to (VDD + 0.3V)
RFBA, RFBB to AGNDA, AGNDB .......(VSS - 0.3V) to (VDD + 0.3V)
Digital Inputs to DGND...............................-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
Narrow Plastic DIP (derate 13.33mW/°C above +70°C)....1067mW
SO (derate 11.76mW/°C above +70°C).........................941mW
Narrow CERDIP (derate 12.50mW/°C above +70°C) ..1000mW
Operating Temperature Ranges:
MX78_7J_/K_ ........................................................0°C to +70°C
MX78_7A_/B_ .................................................. -40°C to +85°C
MX78_7SQ/TQ ............................................... -55°C to +125°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
ELECTRICAL CHARACTERISTICS
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA = VREFB = +10V, RL= 2kΩ, CL= 100pF,
VOUT connected to RFB (MX7837), TA= TMIN to TMAX, unless otherwise noted.) (Note 2)
Note 1: If VSS is open-circuited with VDD and either AGND applied, the VSS pin will float positive exceeding the
Absolute Maximum Ratings
.
If this possibility exists, a Schottky diode connected between VSS and GND ensures the maximum ratings will be observed.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PARAMETER SYMBOL MIN TYP MAX UNITS
±4
±2
Differential Nonlinearity DNL ±1 LSB
Relative Accuracy INL ±1/2 LSB
±3
Zero-Code Offset Error
±5
mV
±5
±2
Resolution N 12 Bits
±1
Loaded with all 0s,
tempco =
±5µV/°C typ
CONDITIONS
MX78_7J/A
TA= +25°C
Guaranteed monotonic
MX78_7K/B/T
MX78_7K/B
MX78_7S/T
MX78_7J/A/S
MX78_7K/B/T
MX78_7J/A/S
TA= +25°C
MX78_7J/A/S ±7
Gain Error Loaded with all 1s,
tempco = ±2ppm
of FSR/°C typ TA= T MIN to TMAX MX78_7K/B/T ±4
LSB
VREF Input Resistance 81013kΩ
V
REFA, VREFB Resistance
Matching ±0.5 ±3 %
Input High Voltage 2.4 V
Input Low Voltage 0.8
Input Current Digital inputs at 0V and VDD ±1 µA
Input Capacitance (Note 4) 8 pF
DC Output Impedance 0.2 Ω
Short-Circuit Current VOUT connected to AGND 15 mA
VINH
TA= T MIN to TMAX
VINL
STATIC PERFORMANCE (Note 3)
REFERENCE INPUTS
DIGITAL INPUTS
ANALOG OUTPUTS
MX7837/MX7847
Complete, Dual, 12-Bit
Multiplying DACs
_______________________________________________________________________________________ 3
PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS
±0.01
±0.01
±0.01
Power-Supply Rejection
±0.01
% per %
Voltage-Output Settling
Time tSSettling time to within ±1/2LSB of final DAC value;
DAC latch alternately loaded will all 0s and all 1s 4 µs
Slew Rate 7 V/µs
Digital-to Analog Glitch
Impulse QDAC latch alternately loaded with 01…11 and
10…00 60 nV-s
Channel-to-Channel Isolation
(VREFA to VOUTB,
VREFB to VOUTA)VREF = 20p-p, 10kHz sine wave, Alternate DAC
Latch Loaded with all 0s -95 dB
Multiplying Feedthrough
Error -90 dB
Unity-Gain Small-Signal
Bandwidth
THD
1 MHz
Full-Power Bandwidth 125 kHz
Total Harmonic Distortion VREF = 6VRMS, 1kHz, DAC latch loaded with all 1s -88 dB
Digital Crosstalk Code transition from all 0s to all 1s; see
Typical
Operating Characteristics
graphs 10 nV-s
Output Noise Voltage at
+25°C (0.1Hz to 10Hz) Amplifier noise and Johnson noise of RFB 2 µVRMS
VDD Range VDD 11.4 16.5 V
Positive Supply Current IDD 510mAOutput unloaded
Negative Supply Current ISS 46mAOutput unloaded
VSS Range VSS -11.4 -16.5 V
VREF = 20Vp-p Sine wave, DAC latch loaded with
all 1s
VREF = 100mVp-p sine wave, DAC latch loaded
with all 1s
VREF_ = 20Vp-p, 10kHz sine wave, latches loaded
with all 0s
VSS = -12V ±5%, VREF = 8.9V
VDD = 12V ±5%, VREF = -8.9V
VSS = -15V ±5%, VREF = 10V
VDD = 15V ±5%, VREF = -10V∆Gain/∆VDD
∆Gain/∆VSS
∆Gain/∆VSS
∆Gain/∆VDD
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA = VREFB = +10V, RL= 2kΩ, CL= 100pF,
VOUT connected to RFB (MX7837), TA= TMIN to TMAX, unless otherwise noted.) (Note 1)
Note 2: The analog outputs can swing to within 2.5V of the supply rails. Hence, for good linearity towards full-scale, |V
REFA| and |VREFB| must
be at least 2.5V lower than VDD and |VSS|. Tests done with supply voltages below ±12.5V are done with VREFA = VREFB = ±8.9V.
Note 3: Static performance tested at V DD = +15V, V SS = -15V. Performance over supplies guaranteed by PSRR test.
Note 4: Guaranteed by design.
POWER REQUIREMENTS
AC CHARACTERISTICS
MX7837/MX7847
Complete, Dual, 12-Bit
Multiplying DACs
4 _______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(TA= +25°C, VDD = 15V, VSS = -15V, RL= 2kΩ, CL= 100pF, unless otherwise noted)
25
010 1k 10k
OUTPUT VOLTAGE SWING
vs. RESISTIVE LOAD
10
20
LOAD RESISTANCE (Ω)
VOUT (Vp-p)
100
15
5
VREF = 20Vp-p at 1kHz
010 100k
NOISE SPECTRAL DENSITY
100
300
FREQUENCY (Hz)
NOISE SPECTRAL DENSITY (nV/ Hz)
200
100 1k 10k
VREF = 0V
DAC CODE = 11...111
GAIN = -1
5
-25 100 10k 10M
SMALL-SIGNAL FREQUENCY RESPONSE
FREQUENCY (Hz)
GAIN (dB)
-5
0
-10
-15
-20
1k 100k 1M
VREF = 100mVp-p
DAC CODE = 11...111
GAIN = -1
-35
-85 1k 100k
MULTIPLYING FEEDTHROUGH ERROR
-75
FREQUENCY (Hz)
ATTENUATION (dB)
-65
-50
-45
-40
-55
-60
-70
-80
10k 1M
VREFA = 20Vp-p
VREFB = AGNDB
DAC CODE = 00...00
-94
-106 100 1k 10k
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (BANDWIDTH = 80kHz)
-102
FREQUENCY (Hz)
THD (dB)
-100
-98
-96
-104
VREF = 6VRMS
DAC CODE = 111...111
-60
-100 100 10k 100k
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (BANDWIDTH > 500kHz)
-75
-65
FREQUENCY (Hz)
THD (dB)
1k
-70
-90
-80
-85
-95
VREF = 6VRMS
DAC CODE = 111...111
PARAMETER MX78_7J/K/A/B
MIN MAX
SYMBOL MX78_7S/T
MIN MAX UNITS
Address to WR SetupTime t6MX7837 only 15 15 ns
Address to WR Hold Time t7MX7837 only 15 15 ns
LDAC Pulse Width t8MX7837 only 80 80 ns
CONDITIONS
CS to WR Hold Time 0
0
CS to WR Setup Time t10 ns
t20 ns
WR Pulse Width t380 80 ns
Data to WR Setup Time t480 80 ns
Data to WR Hold Time t510 10 ns
TIMING CHARACTERISTICS
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, TA= TMIN to TMAX, unless otherwise noted.) (Note 5)
Note 5: All input signals are specified with tR= tF≤5ns. Logic swing is 0V to 5V.
MX7837/MX7847
Complete, Dual, 12-Bit
Multiplying DACs
_______________________________________________________________________________________ 5
A
AGNDA
A = VOUTA, 50mV/div
TIMEBASE = 2µs/div
VREFA = ±100mV SQUARE WAVE
SMALL-SIGNAL PULSE RESPONSE
A
AGNDA
A = VOUTA, 5V/div
TIMEBASE = 2µs/div
VREFA = ±10V SQUARE WAVE
LARGE-SIGNAL PULSE RESPONSE
______________________________________________________________Pin Description
PIN
MX7837 MX7847 NAME FUNCTION
1 – CS Chip Select – active-low logic input
– 1 CSA Chip-Select Input for DAC A – active-low logic input
2 RFBA Amplifier Feedback Resistor for DAC A
– 2 CSB Chip-Select Input for DAC B – active-low logic input
3 3 VREFA Reference Input Voltage for DAC A
4 4 VOUTA Analog Output Voltage from DAC A
5 5 AGNDA Analog Ground for DAC A
6 6 VDD Positive Power Supply
–
7 7 VSS Negative Power Supply
8 8 AGNDB Analog Ground for DAC B
9 9 VOUTB Analog Output Voltage from DAC B
10 10 VREFB Reference Input Voltage for DAC B
11 11 DGND Digital Ground
12 – RFBB Amplifier Feedback Resistor for DAC B
– 12 DB11 Data Bit 11 (MSB)
13 13 WR Write Input – active-low logic input (MX7837); positive-edge-triggered input used with
CSA and CSB (MX7847)
14 – LDAC Asynchronous Load – DAC input, active-low
– 14-24 DB10-DB0 Data Bit 10 to Data Bit 0 (LSB)
15 – A1 Address Input – most significant address input for input latches
16 – A0 Address Input – least significant address input for input latches
17-20 – DB7-DB4 Data Bit 7 to Data Bit 4
21-24 – DB3/DB11-
DB0/DB8 Data Bit 3 to Data Bit 0 (LSB), or Data Bit 11 (MSB) to Data Bit 8
____________________________Typical Operating Characteristics (continued)
(TA= +25°C, VDD = 15V, VSS = -15V, RL= 2kΩ, CL = 100pF, unless otherwise noted.)
MX7837/MX7847
_______________Detailed Description
D/A Section
Figure 1 shows a simplified circuit diagram for one of
the DACs and the output amplifier. Using a segmented
scheme, the two MSBs of the 12-bit data word are
decoded to drive the three switches (A to C). The
remaining 10 bits drive the switches (S0 to S9) in a
standard R-2R ladder.
Each switch (A to C) directs 1/4 of the total reference
current, and the remaining current passes through the
R-2R section.
The output amplifier and feedback resistor convert cur-
rent to voltage as follows: VOUT_ = (-D)(VREF_), where D
is the fractional representation of the digital word. (D
can be set from 0 to 4095/4096.)
The output amplifier is capable of developing ±10V
across a 2kΩload. It is internally compensated and
settles to 0.01% FSR (1/2LSB) in less than 4µs. VOUT
on the MX7837 is not internally connected to RFB.
Interface Logic Information
(MX7847)
Figure 2 shows the MX7847 input control logic. The
device contains two independent DACs, each with its
own CS input and a common WR input. CSA and WR
control data loading to the DAC A latch, and CSB and
WR control data loading to the DAC B latch. The latch-
es are edge triggered so that input data is latched to
the respective latch on WR's rising edge. The same
data will be latched to both DACs if CSA and CSB are
low and WR is taken high. Table 1 shows the device
control-logic truth table, and Figure 3 shows the write-
cycle timing diagram.
Table 1. MX7847 Truth Table
X = Don't Care = Rising Edge Triggered
Interface Logic Information
(MX7837)
The MX7837 input loading structure is configured for
interfacing with 8-bit-wide data-bus microprocessors.
Each DAC has two 12-bit latches: an input latch, and a
DAC latch. Each input latch is subdivided into a least-
significant 8-bit latch and a most-significant 4-bit latch.
The data held in the DAC latches determines the out-
puts. Figure 4 shows the MX7837 input control logic,
and Figure 5 shows the write-cycle timing diagram.
Complete, Dual, 12-Bit
Multiplying DACs
6 _______________________________________________________________________________________
2R 2R 2R2R 2R 2R 2R
CBA S9S8 S0
V
REF RR R
R/2
VOUT
AGND
SHOWN FOR ALL 1s ON DAC
DAC A LATCH
DAC B LATCH
CSA
WR
CSB
Figure 1. D/A Simplified Circuit Diagram
t3
t1t2
t5t4
VALID DATA
WR
CSA, CSB
DATA
Figure 2. MX7847 Input Control Logic Figure 3. MX7847 Write-Cycle Timing Diagram
CSA CSB WR
Function
X X 1 No Data Transfer
1 1 X No Data Transfer
0 1 Data Latched to DAC A
1 0 Data Latched to DAC B
0 0 Data Latched to Both DACs
1 0 Data Latched to DAC A
1 0 Data Latched to DAC B
0 Data Latched to Both DACs
CS, WR, A0, and A1 control data loading to the input
latches. The eight data inputs accept right-justified
data, which can be loaded to the input latches in any
sequence. If LDAC is held high, loading data to the
input latches will not change the analog output. A0
and A1 determine which input latch will receive the
data when CS and WR are low. Table 2 shows the
control logic truth table.
Table 2. MX7837 Truth Table
X = Don't Care
The LDAC input controls 12-bit data transfer from the
input latches to the DAC latches. When LDAC is taken
low, both DAC latches (thus, both analog outputs) are
updated simultaneously. When LDAC is low, the DAC
latches are transparent; DAC data is latched on the ris-
ing edge of LDAC. The LDAC input is asynchronous
and independent of WR. This is useful in many appli-
cations, especially in updating multiple MX7837s simul-
taneously. However, be careful when exercising LDAC
during a write cycle; if an LDAC operation overlaps a
CS and WR operation, invalid data may be latched to
the output. To avoid this, LDAC must remain low after
CS or WR have returned high for a period equal to or
greater than t8, the minimum LDAC pulse width.
Unipolar Binary Operation
Figure 6 shows DAC A (MX7837/MX7847) connected
for unipolar binary operation. Similar connections
apply for DAC B. When VIN is an AC signal, the circuit
performs 2-quadrant multiplication. Table 3 shows the
code table for this circuit. On the MX7847, the RFB
feedback resistor is internally connected to VOUT.
Table 3. Unipolar Code Table
DAC A
MS
INPUT
LATCH
DAC A LATCH
DAC A
LS
INPUT
LATCH DAC B
MS
INPUT
LATCH DAC B
LS
INPUT
LATCH
A1
A0
WR
CS
LDAC DAC B LATCH
12 12
4
8
4
8
8
DB7 DB0
Figure 4. MX7837 Input Control Logic
DAC Latch Contents
MSB LSB
−×
V
IN
4095
4096
MX7837/MX7847
Complete, Dual, 12-Bit
Multiplying DACs
_______________________________________________________________________________________ 7
CS WR LDAC
Function
1 X 1 No Data Transfer
X 1 1 No Data Transfer
0 0 1 DAC A LS Input Latch Transparent
0 0 1 DAC A MS Input Latch Transparent
0 0 1 DAC B LS Input Latch Transparent
0 0 1 DAC B MS Input Latch Transparent
1 1 0 Updated Simultaneously from
the Respective Input Latches
A0
X
X
0
1
0
1
X
A1
X
X
0
0
1
1
X
ADDRESS VALID
VALID DATA
t6t7
t1t2
t5
t3
t4
A0/A1
CS
WR
DATA
LDAC
t8
Figure 5. MX7837 Write-Cycle Timing Diagram
Note : 1LSB V
4096
IN
=
Analog Output, VOUT
1111 1111 1111
1000 0000 0000 −×
=−V 1
2
V
IN IN
2048
4096
0000 0000 0001 −×
V
IN 1
4096
0000 0000 0000 0V
MX7837/MX7847
Bipolar Operation (4-Quadrant
Multiplication)
Figure 7 shows the MX7837/MX7847 connected for
binary operation. The offset-binary coding is shown in
Table 4. When VIN is an AC signal, the circuit performs
4-quadrant multiplication. R1, R2, and R3 resistors
should be 0.01% ratio matched to maintain gain-error
specifications. On the MX7847, the RFB feedback
resistor is internally connected to VOUT.
Table 4. Bipolar Code Table
__________Applications Information
Ground Management
The use of an uninterrupted ground plane is strongly
recommended. AC or transient voltages between ana-
log and digital grounds (between AGNDA/AGNDB and
DGND) can inject noise into the analog circuitry.
Connect the MX7837/MX7847 AGNDs and DGND
directly to the ground plane or to a star ground to
ensure that they are at the same potential. In complex
systems with separate analog and digital ground
planes, connect two diodes (1N914 or equivalent) in
inverse parallel between the AGND and DGND pins.
Power-Supply Decoupling
To minimize noise, decouple the VDD and VSS lines to
DGND using a 10µF capacitor in parallel with a 0.1µF
ceramic capacitor. Minimize capacitor lead lengths for
best noise rejection.
Operation with Reduced
Power-Supply Voltages
The MX7837/MX7847 are specified for operation with
VDD/VSS = ±11.4V to ±16.5V. However, the output
amplifier requires 2.5V of headroom, so the reference
input should not come within 2.5V of VDD/VSS in order to
maintain accuracy at full scale.
Complete, Dual, 12-Bit
Multiplying DACs
8 _______________________________________________________________________________________
DAC A
AGNDA VSS
DGND
RFBA*
VOUTA*VOUT
VIN
VDD
VREFA
VDD
MX7837
MX7847
* INTERNALLY CONNECTED ON MX7847
VSS
VSS
DAC A
AGNDA VSS
DGND
RFBA*
VOUTA
VIN
VDD
VREFA
MX7837
MX7847
VOUT
R1
20k
R2
20k
R3
10k
MAX427
VDD
VSS
* INTERNALLY CONNECTED
ON MX7847
DAC Latch Contents
MSB LSB Analog Output, VOUT
1111 1111 1111 +×
V
2047
2048
IN
1000 0000 0001 +×
V 1
2048
IN
0111 1111 1111 −×
V 1
2048
IN
0000 0000 0000 −×
=−V
2048
2048 V
IN IN
1000 0000 0000 0V
Note : 1LSB V
2048
IN
=
Figure 6. Unipolar Binary Operation Figure 7. Bipolar Offset Binary Operation
MX7837/MX7847
Complete, Dual, 12-Bit
Multiplying DACs
_______________________________________________________________________________________ 9
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12 13
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
WR
DB11
DGND
VREFB
VOUTB
AGNDB
VSS
VDD
AGNDA
VOUTA
VREFA
CSB
CSA
DIP/SO
TOP VIEW
MX7847
14
DAC LATCH A
DAC A
DAC LATCH B
DAC B
CONTROL
LOGIC
CSB
CSA
WR
DB11
DB0
VREFB
VREFA VOUTA
AGNDA
VOUTB
AGNDB
DGND VSS
VDD
MX7847
PART TEMP. RANGE PIN-PACKAGE
MX7837AN -40°C to +85°C 24 Narrow Plastic DIP
MX7837BN -40°C to +85°C 24 Narrow Plastic DIP
MX7837AR -40°C to +85°C 24 Wide SO
MX7837BR -40°C to +85°C 24 Wide SO
MX7837AQ -40°C to +85°C 24 Narrow CERDIP
ERROR
(LSB)
±1
±1/2
±1
±1/2
±1
MX7847BR -40°C to +85°C 24 Wide SO ±1/2
MX7847AQ -40°C to +85°C 24 Narrow CERDIP ±1
MX7847BQ -40°C to +85°C 24 Narrow CERDIP ±1/2
MX7847SQ - 5 5 °C to +125°C 24 Narrow CERDIP ±1
MX7847TQ -5 5°C t o +125°C 24 Narrow CERDIP ±1/2
MX7837BQ -40°C to +85°C 24 Narrow CERDIP ±1/2
MX7837SQ -55°C to +125°C 24 Narrow CERDIP ±1
MX7837TQ -55°C to +125°C 24 Narrow CERDIP ±1/2
MX7847KN 0°C to +70°C 24 Narrow Plastic DIP ±1/2
MX7847JR 0°C to +70°C 24 Wide SO ±1
MX7847KR 0°C to +70°C 24 Wide SO ±1/2
MX7847JN 0°C to +70°C 24 Narrow Plastic DIP ±1
MX7847C/D 0°C to +70°C Dice* ±1
MX7847AN -40°C to +85°C 24 Narrow Plastic DIP ±1
MX7847BN -40°C to +85°C 24 Narrow Plastic DIP ±1/2
MX7847AR -40°C to +85°C 24 Wide SO ±1
______Pin Configurations
(continued)
Typical Operating Cir cuits
(continued)
____Ordering Information
(continued)
MX7837/MX7847
Complete, Dual, 12-Bit
Multiplying DACs
10 ______________________________________________________________________________________
DB3/
DB11
A1
A0
VOUTA
AGNDA
AGNDB
VOUTB
VREFA RFBA
VDD
DB2/DB10
DGND LDAC
RFBB VREFB WR
0.250"
(6.35mm)
0.140"
(3.56mm)
VSS
VSS
DB7
DB6
DB5
DB4
DB1/DB9DB0/DB8CS
TRANSISTOR COUNT: 1240;
SUBSTRATE CONNECTED TO VDD.
MX7837
DB3
DB9
DB8
VOUTA
AGNDA
AGNDB
VOUTB
VREFA CSB
VDD
DB2
DGND DB10
WR
0.250"
(6.35mm)
0.140"
(3.56mm)
VSS
VSS
DB7
DB6
DB5
DB4
DB1DB0CSA
TRANSISTOR COUNT: 1240;
SUBSTRATE CONNECTED TO VDD.
MX7847
DB11VREFB
__________________________________________________________Chip Topographies
MX7837/MX7847
Complete, Dual, 12-Bit
Multiplying DACs
______________________________________________________________________________________ 11
C
AA2
E1
D
E
eA
eB
A3
B1
B
DIM
A
A1
A2
A3
B
B1
C
D
D1
E
E1
e
eA
eB
L
α
MIN
–
0.015
0.125
0.055
0.016
0.050
0.008
1.235
0.050
0.300
0.240
–
0.115
0˚
MAX
0.200
–
0.150
0.080
0.022
0.065
0.012
1.265
0.080
0.325
0.280
0.400
0.150
15˚
MIN
–
0.38
3.18
1.40
0.41
1.27
0.20
31.37
1.27
7.62
6.10
–
2.92
0˚
MAX
5.08
–
3.81
2.03
0.56
1.65
0.30
32.13
2.03
8.26
7.11
10.16
3.81
15˚
INCHES MILLIMETERS
2.54 BSC
7.62 BSC
0.100 BSC
0.300 BSC
A1
L
D1
e
21-337A
24-PIN PLASTIC
DUAL-IN-LINE
(NARROW)
PACKAGE
α
L
DIM
A
A1
B
C
D
E
e
H
h
L
α
MIN
0.093
0.004
0.014
0.009
0.598
0.291
0.394
0.010
0.016
0˚
MAX
0.104
0.012
0.019
0.013
0.614
0.299
0.419
0.030
0.050
8˚
MIN
2.35
0.10
0.35
0.23
15.20
7.40
10.00
0.25
0.40
0˚
MAX
2.65
0.30
0.49
0.32
15.60
7.60
10.65
0.75
1.27
8˚
INCHES MILLIMETERS
α
24-PIN PLASTIC
SMALL-OUTLINE
PACKAGE
HE
D
e
A
A1 C
h x 45˚
0.127mm
0.004in.
B
1.27 BSC0.050 BSC
21-338A
________________________________________________________Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1993 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MX7837/MX7847
Complete, Dual, 12-Bit
Multiplying DACs
C
AE
D
E1
B1
B
DIM
A
B
B1
C
D
E
E1
e
L
L1
Q
S
S1
α
MIN
–
0.014
0.038
0.008
–
0.220
0.290
0.125
0.150
0.015
–
0.005
0˚
MAX
0.200
0.023
0.065
0.015
1.280
0.310
0.320
0.200
–
0.060
0.098
–
15˚
MIN
–
0.36
0.97
0.20
–
5.59
7.37
3.18
3.81
0.38
–
0.13
0˚
MAX
5.08
0.58
1.65
0.38
32.51
7.87
8.13
5.08
–
1.52
2.49
–
15˚
INCHES MILLIMETERS
2.54 BSC0.100 BSC
Q
L
S1
e
21-340B
24-PIN CERAMIC
DUAL-IN-LINE
(NARROW)
PACKAGE
α
S
L1
___________________________________________Package Information (continued)
