3URGXFW 6HOHFWRU *XLGH
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Not e: Plea se contac t a Cyp ress R eprese nt ativ e for pro duct av ai lab ili ty.
Static RAMs
Organization/Density Overview
*NoBL™ (N o Bus Latency™) Synchronous Architectur e
** MoB L™ (More Ba ttery Lif e™ ) Asynch ronou s SRAM s
Density X1 X4 X8 X9 X16 X18 X32 X36
4 Kb 7C148
7C149
7C150
16 Kb 7C167A 7C168A 7C128A
6116
64 Kb to 72 Kb 7C187 7C164
7C166 7C185
6264 7C182
256 K b to
288 Kb 7C197 7C194
7C195 7C199
7C1399/V
62256/V
62256V25
62256V18
7C188
512 Kb 7C1020
7C1020V
1 Mb 7C1007 7C106A/
7C1006 7C109/V33
7C1009/V33
7C1019/V33
62128
62128V/V25/V18
7C1021
7C1021V33
62126V
62127V
7C1031
7C1032
2 Mb 62138V** 7C1011
62136V**
62137V**
7C1324 7C1329
7C1333*
7C1334*
4 Mb 7C1049
7C1049V33
62148
62148V**
7C1041
7C1041V33
62146V**
62147V**
7C1325
7C1352*
7C1353*
7C1338
7C1339 7C1350*
7C1351*
8 Mb 7C1362
7C1363
7C1356*
7C1357*
7C1364
7C1365 7C1354*
7C1355*
7C1360
7C1361
Fast Asynchronous SRAMs
Density Organization VCC Part # PKG Temp Speed Attributes
16 Kb 2K x 8 5V CY6116A D,L M35
CY7C128A P, S, V, D, L C,M 15
4K x 4 5V CY7C168A P, V,D C,M 15 Pow er Down
16K x 1 5V CY7C167A P, V C15
64 Kb 8K x 9 5V CY7C182 P, V C25
8K x 8 5V CY7C185 P, V, S C,I 15 300-mil DIP
CY7C185A D M 20 300-mil DIP
CY7C186A D M 20 600-mil DIP
16K x 4 5V CY7C164 P, V C15 2 CE / no OE
CY7C166 P, V C15 2 CE / 1 OE
64K x 1 5V CY7C187 P, V C15
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MAIN INDEX
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Not e: Plea se contac t a Cyp ress R eprese nt ativ e for pro duct av ai lab ili ty.
256 Kb 32K x 9 5V CY7C188 V C 15
32K x 8 5V CY7C198 D,L,Z C,M 20 600-mil DIP
CY7C199 P, V, Z ,D,L C,I,M 10 300-mil DIP
3.3V CY7C1399 V,Z C,I 12
64K x 4 5V CY7C192 V C 12 Separa te I/O
CY7C194 P, V C12 1 CE
CY7C195 P, V C12 1 CE / 1 OE
256K x 1 5V CY7C197 P, V C12
512 Kb 32K x 16 5V CY7C1020 V,Z C10
CY7C1020L V,Z C10 Low P ower
CY7C1022 V,Z C12 CE High
3.3V CY7C1020V33 V,Z C,I 10
CY7C1020V33L V,Z C,I 10 Low P ower
1 Mb 64K x 16 5V CY7C1021 V,Z C,I 12
3.3V CY7C1021V33 V,Z,BA C,I 10
CY7C1021V33L V,Z,BA C,I 10 Low Power
128K x 8 5V CY7C109 V,Z C,I 12 400-mil SOJ
CY7C1009 VC,I 12 300-mil SOJ
CY7C1019 V C 12 Center-Power/Ground,
400-mil SOJ
3.3V CY7C109V33 V C 15 400-mil SOJ
CY7C1009V33 V C 12 300-mil SOJ
CY7C1019V33 V C 12 Center-Power/Ground,
400-mil SOJ
CY7C1018V33 V C 12 Center-Power/Ground,
300-mil SOJ
256K x 4 5V CY7C106 V C 12 400-mil SOJ
CY7C1006 V C 12 300-mil SOJ
1M x 1 5V CY7C107 V C 12 400-mil SOJ
CY7C1007 V C 12 300-mil SOJ
2Mb 128K x 16 5V CY7C1011 Z C 15
4 Mb 256K x 16 5V CY7C1041 V,Z C15
CY7C1041L V C 17 Low Power
3.3V CY7C1041V33 V,Z C15
512K x 8 5V CY7C1049 VC,I,M 15
CY7C1049L VC,I 17 Low Power
5962-95600 FJ M20
3.3V CY7C1049V33 VC,I 15
CY7C1049V33L V C 15 Low Power
Fast Asynchronous SRAMs (continued)
Density Organization VCC Part # PKG Temp Speed Attributes
MAIN INDEX
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Note:
1. Check a v ailability with PME.
Standard Pi pelined/Flow-Through Synch ronous SRAMs
Density Org. Architecture Speed (MHz) Supply
Voltage I/O Vol tag e Part N u mb er Pins
Packages Burst Sequence
1 Mb 64Kx18 Flow-Through 8-12 ns 5.0 3.3/5.0 CY7C1031 52 PQFP,
PLCC Interleaved Burst
64Kx18 Flow-Through 8-12 ns 5.0 3.3/5.0 CY7C1032 52 PQFP,
PLCC Line ar Burst
2 Mb 64Kx32 Pipelined 100, 133 3.3 2.5/3.3 CY7C1329 100 TQFP Linear/Interleaved
128Kx18 Flow-Through 100, 117 3.3 2.5/3.3 CY7C1324 100 TQFP Linear/Interleaved
4 Mb 256Kx18 Pipelined 100, 133 3.3 2.5/3.3 CY7C1327 100 TQFP /
119 BGA Linear/Interleaved
128Kx32 Pipelined 100, 133 3.3 2.5/3.3 CY7C1339 100 TQFP /
119 BGA Linear/Interleaved
128Kx36 Pipelined 100, 133 3.3 2.5/3.3 CY7C1347 100 TQFP /
119 BGA Linear/Interleaved
256Kx18 Flow-Through 100, 117 3.3 2.5/3.3 CY7C1325 100 TQFP /
119 BGA Linear/Interleaved
128Kx32 Flow-Through 100, 117 3.3 2.5/3.3 CY7C1338 100 TQFP /
119 BGA Linear/Interleaved
128Kx36 Flow-Through 100, 117 3.3 2.5/3.3 CY7C1345 100 TQFP /
119 BGA Linear/Interleaved
8 Mb 256Kx36 Pipelined 100, 133, 166,
200[1] 2.5 2.5 CY7C1360V25 10 0 TQFP /
119 BGA Linear/Interleaved
Pipelined 100, 13 3, 166,
200[1] 3.3 2.5/3.3 CY7C1360 100 TQFP /
119 BGA Linear/Interleaved
Flow-Through 83, 100, 117[1] 2.5 2.5 CY7C1361V25 100 TQFP /
119 BGA Linear/Interleaved
Flow-Through 83, 100, 117[1] 3.3 2.5/3.3 CY7C1361 100 TQFP /
119 BGA Linear/Interleaved
512Kx18 Pipelined 100, 133, 166,
200[1] 2.5 2.5 CY7C1362V25 10 0 TQFP /
119 BGA Linear/Interleaved
Pipelined 100, 13 3, 166,
200[1] 3.3 2.5/3.3 CY7C1362 100 TQFP /
119 BGA Linear/Interleaved
Flow-Through 83, 100, 117[1] 2.5 2.5 CY7C1363V25 100 TQFP /
119 BGA Linear/Interleaved
Flow-Through 83, 100, 117[1] 3.3 2.5/3.3 CY7C1363 100 TQFP /
119 BGA Linear/Interleaved
256Kx32 Pipelined 100, 133, 166,
200[1] 2.5 2.5 CY7C1364V25 10 0 TQFP /
119 BGA Linear/Interleaved
Pipelined 100, 13 3, 166,
200[1] 3.3 2.5/3.3 CY7C1364 100 TQFP /
119 BGA Linear/Interleaved
Flow-Through 83, 100, 117[1] 2.5 2.5 CY7C1365V25 100 TQFP /
119 BGA Linear/Interleaved
Flow-Through 83, 100, 117[1] 3.3 2.5/3.3 CY7C1365 100 TQFP /
119 BGA Linear/Interleaved
NoBL™ (No Bus Latency™) Sync hr onous SRAMs
Density Org. Architecture Speed (MHz) Supply
Voltage I/O Voltag e Part Number Pin s Packag e s
2 Mb 64Kx32 Pipelined 50, 80, 100 3.3 3.3 CY7C1334 100 TQFP
Flow-Through 50, 66 3.3 3.3 CY7C1333 100 TQFP
4 Mb 128Kx36 Pipelined 80, 100, 133 3.3 3.3 CY7C1350 100 TQFP / 119 BGA
Flow-Through 40, 50, 66 3.3 3.3 CY7C1351 100 TQFP / 119 BGA
256Kx18 Pipelined 80, 100, 133 3.3 3.3 CY7C1352 100 TQFP / 119 BGA
Flow-Through 40, 50, 66 3.3 3.3 CY7C1353 100 TQFP / 119 BGA
8 Mb 256Kx36 Pipelined 100, 133, 166, 200[1] 2.5 2.5 CY7C1354V25 100 TQFP / 119 BGA
Flow-Through 83, 100, 117[1] 2.5 2.5 CY7C1355V25 100 TQFP / 119 BGA
512Kx18 Pipelined 100, 133, 166, 200[1] 2.5 2.5 CY7C1356V25 100 TQFP / 119 BGA
Flow-Through 83, 100, 117[1] 2.5 2.5 CY7C1357V25 100 TQFP / 119 BGA
MAIN INDEX
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* Byte Enable Power Down
* Byte Enable Power Down
** 1.8V MoBL2 Intro Q3 ’00
Standard Micro Power SRAMs
Density Org. Supply
Voltage Part # Speed Temp. Package
64 Kb 8K x 8 5V CY6264 70 C28p-SOIC
256 Kb 32K x 8 5V CY62256 70 C, I 28p-SOIC, 28p-RTSOP, 28p-TSOP, 28p-PDIP
2.7–3.6V CY62256V 70 C, I 28p-SOIC, 28p-RTSOP, 28p-TSOP
2.3–2.7V CY62256V25 100 C28p- SOIC, 28p-RTSOP, 28p-TSOP
1.6–2.0V CY62256V18 200 C28p- SOIC, 28p-RTSOP, 28p-TSOP
1 Mb 64K x 16 2.7–3.6V CY62126V 70 C, I 44p-TSOP2, 48b-fBGA
CY62127V* 70 C, I 44p-TSOP2, 48b- fBGA
128K x 8 5V CY62128 70 C, I 32p-SOIC, 32p-TSOP, 32p-STSOP
2.7–3.6V CY62128V 70 C, I 32p-SOIC, 32p-TSOP, 32p-STSOP, 32p-RTSOP
2.3–2.7V CY62128V25 100 C, I 32p-SOIC, 32p-TSOP, 32p-STSOP, 32p-RTSOP
1.6–2.0V CY62128V18 200 C,I 32p-S OIC, 32p-TSOP, 32p-STSOP, 32p- RTSOP
4 Mb 512K x 8 5V CY62148 70 C32p-SOIC, 32p-TSOP2
MoBL™ SRAMs
Density Org . Supply
Voltage Part # Speed Temp. Packages
2 Mb 128K x 16 3V CY62136V 70 ns I48b-fB GA, 44p-TSOP2
1.8V** CY62136V18 70 ns I48b-fBGA
3V CY62137V* 70 ns I48b-fBGA, 44p-TSOP2
1.8V** CY62137V18* 70 ns I48b-fBGA
256K x 8 3V CY62138V 70 ns I36b-fBGA
4 Mb 256K x 16 3V CY62146V 70 ns I48b-fBGA, 44p-TSO P2
1.8V** CY62146V18 70 ns I48b-fBGA
3V CY62147V* 70 ns I48b-fBGA, 44p-TSOP2
1.8V** CY62147V18* 70 ns I48b-fBGA
512K x 8 3V CY62148V 70 ns C, I 36b-fBGA, 32p -TSOP 2, 32p-SOI C
MAIN INDEX
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SRAM Modules
Secondar y Cache Subs ystem s
Size Organization Pins Part Number Speed (MHz) ICC/ISB/ICCDR
(mA @ ns) Packages
512K P54C Cache (Intel Neptune) 160 CYM74SP55 fmax=60, 66 MHz 1500 PM
512K P54C Cache (Intel T riton) 160 CYM74S431 50, 60, 66 MHz 1200 PM
256K P54C Cache (Intel T riton II) 160 CYM74P430B 50, 60, 66 MHz 750 PM
512K P54C Cache (Intel T riton II) 160 CYM74P431B 50, 60, 66 MHz 1400 PM
256K P54C Cache (Intel T riton II ETag) 160 CYM74P434B 50, 60, 66 MHz 900 PM
512K P54C Cache (Intel T riton II ETag) 160 CYM74P435B 50, 60, 66 MHz 1550 PM
256K P54C Cache (Intel T riton II) 160 CYM74P436 50, 60, 66 MHz TBD PM
256K P54C Cache (Intel T riton II ETag) 160 CYM74P438 50, 60, 66 MHz TBD PM
512K P54C Cache (OPTi Viper) 160 CYM74S551 50, 60, 66 MHz 1500 PM
• PC Cache
• x32-Bit Standard SRAM
• x8-, x16-, and x24-B it Standard SRAM
MAIN INDEX
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SRAM Modules (cont inued)
x8-, x16-, and x24-Bit SRAM Modules
x32-Bit Standard SRAM Module Family
DRAM Controller Modules
Size Organization Pins Part Number Speed (ns) ICC/ISB/ICCDR
(mA @ ns) Packages
2M 256K x 8—JEDEC Sep I/O 60 CYM1441 tAA =20, 25, 35, 45 960 @ 25 PZ
4M 512K x 8—JEDEC 32 CYM1464 tAA = 20, 22, 25, 30, 35, 45, 55, 350 @ 20 PD
4M 512K x 8—JEDEC 32 CYM1465 tAA = 70, 85,100,120, 150 110 @ 70 PD
16M 2M x 8 36 CYM1481 tAA = 85, 100, 120 110 @ 85 PS
Size Organization Pins Part Number Speed (ns) ICC/ISB/ICCDR
(mA @ ns) Packages
512K 16K x 32 64 CYM1821 tAA = 20, 25, 35, 45 720 @ 20 PM, PZ
2M 64K x 32 64 CYM1831 tAA = 15, 20, 25, 35, 45 720 @ 25 PM, PN, PZ
2M 64Kx32 64 CYM1831V33 tAA = 20, 25, 35 380@20 PZ
4M 128K x 32 64 CYM1836 tAA = 20, 25, 35, 45
tAA = 15 480 @ 20
760 @ 15 PM, PZ
4M 128Kx32 64 CYM1836V33 tAA = 15, 20, 25, 30, 35 520@15
480@20+ PM, PZ
4M 128K x 32 66 CYM1838 tAA = 25, 30, 35 720 @ 25+ HG
8M 256K x 32 64 CYM1841A tAA = 25, 35, 45, 55
tAA = 20
tAA = 12, 15
960 @ 25
1120 @ 20
1600 @ 12
PM, PN, PR,
PT , PY
8M 256Kx32 64 CYM1841V33 tAA = 20, 25, 35 270@35
300@25
340@20
PZ
8M 256K x 32 (72-pin Superset) 72 CYM1841A tAA=12, 15, 20, 25, 35, 45 960 @ 25
1120 @ 20
1600 @ 15
PM,P5, P6,
P7, P8
16M 512K x 32 (72-pin Superset) 72 CYM1846 tAA= 15, 20, 25, 30, 35 800 @ 20 PM, PZ
16M 512K x 32 (72-pin Superset) 72 CYM1846V33 tAA= 20, 25, 30 360 @ 20 PM, P8, PZ
32M 1M x 32 (72-pin Superset) 72 CYM1851 tAA = 15, 20, 25, 30, 35 1200 @ 20 PM, PN, PZ
32M 1M x 32 (72-pin Superset) 72 CYM1851V33 tAA = 15, 20, 25, 35 1100@20
1250 @ 15 P6, P8, PM,
PN, PZ
64M 2Mx32 72 CYM1861 tAA = 35 2582@35 PM
64M 2Mx32 72 CYM1861V33 tAA = 25, 35 2400@25 PM
Organization Bus Width Part Number Speed (MHz) Package
DRAM Accelerator 32-Bit CYM7232 25/33/40 PGC
DRAM Accelerator 64-Bit CYM7264 25/33/40 PGC
MAIN INDEX
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Dual-Port RAMs
•True Dual-Ported memory cells which allow simul-
taneous reads of the same memory location
•High-speed access: 12 ns
•Fast operati ng sp eed: 100 MHz
•Low power
•Auto matic power-down
•TQF P/PQF P/P LCC packaging available
•Various arbitration schemes avai lable (Busy,
Interrupt, Semaphore)
7C132/142
7C136/146
7C133/143
7C139
7C135/8
7C1342
7C145 7C016
7C0067C144
7C0241 7C0251
7C024 7C025
2Kx8
4Kx9 8Kx9
8Kx84Kx8
4Kx16 8Kx162Kx16
8Kx184Kx18
16Kx8
16Kx9
x8/9
x16/18
1K 2K 4K 8K 16K
W ORD DENSITY
Dual-Port RAM Pr oduct P ortfolio
7C130/140
7C131/141
1Kx8
7C017A
7C007A
7C037
7C027
32Kx9
32Kx8
32Kx16
32Kx18
32K
7C018
7C008
7C038
7C028
64Kx9
64Kx8
64Kx16
64Kx18
64K
7C019
7C009
128Kx9
128Kx8
128K
7C036A
7C026A
16Kx8
16Kx9
5V Async
7C139AV
7C138AV
7C145AV 7C016AV
7C006AV7C144AV
7C0241AV 7C0251AV
7C024AV 7C025AV
4Kx9 8Kx9
8Kx84Kx8
4Kx16 8Kx16
8Kx184Kx18
16Kx8
16Kx9
x8/9
x16/18
4K 8K 16K
W ORD DENSITY
7C017AV
7C007AV
7C037V
7C027V
32Kx9
32Kx8
32Kx16
32Kx18
32K
7C018V
7C008V
7C038V
7C028V
64Kx9
64Kx8
64Kx16
64Kx18
64K
7C019V
7C009V
128Kx9
128Kx8
128K
7C036AV
7C026AV
16Kx8
16Kx9
3.3V Async
x36 7C056V
16Kx36
7C057V
32Kx36
MAIN INDEX
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Mult i-Port RAMs
Org. 5V Part # 3.3V Part #
Speed (ns)
(A vailability Guide: 5 = 5V only; 3 = 3.3V
only; B = 5V and 3.3V) Package ICC
(mA@ns) Features5 6.5 7.5 9 12 15 20 25 30 35 45 55 P J A BA N
QuadPort Synchronous
64K x18 CY7C0430V 3 272 750@133 Four Independent
Ports/Sync Pi pe-
lined/Burst
Counter/Mask
Register/Counter
Readback/BIST/
JTAG IEEE1149
Async
1K x 8 CY7C130 - - - - - - - 5 5 5 5 48 - - - 170@25 Master, Busy, Int
1K x 8 CY7C131 - - - -5-55555-52- 52170@25Master, Busy, Int
7C09159A 7C09169A
7C09349A 7C09359A
8Kx9
8Kx184Kx18
16Kx9
x8/9
x16/18
4K 8K 16K
WORD DENSITY
Du al -Port R AM Prod uc t Po rtfol i o (continued)
7C09179A
7C09079A
7C09379
7C09279
32Kx9
32Kx8
32Kx16
32Kx18
32K
7C09189
7C09089
7C09389
7C09289
64Kx9
64Kx8
64Kx16
64Kx18
64K
7C09199
7C09099
128Kx9
128Kx8
128K
7C09369A
7C09269A
16Kx8
16Kx9
5V Sy nc
7C09159AV 7C09169AV
7C09349AV 7C09359AV
8Kx9
8Kx184Kx18
16Kx9
x8/9
x16/18
4K 8K 16K
WORD DENSITY
7C09179V
7C09079V
7C09379V
7C09279V
32Kx9
32Kx8
32Kx16
32Kx18
32K
7C09189V
7C09089V
7C09389V
7C09289V
64Kx9
64Kx8
64Kx16
64Kx18
64K
7C09199V
7C09099V
128Kx9
128Kx8
128K
7C09369V
7C09269V
16Kx8
16Kx9
3. 3V S y nc
7C09569V
16Kx36
7C09579V
32Kx36
x36
MAIN INDEX
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1K x 8 CY7C140 - - - - - - - 5 5 - 5 48 - - - 170@25 Slave, Busy, Int
1K x 8 CY7C141 - - - -5-55555-52- 52170@25Slave, Busy, Int
2K x 8 CY7C132 - - - - - - - 5 5 5 5 48 - - - 170@25 Master, Busy, Int
2K x 8 CY7C136 - - - -5-55555-52- 52170@25Master, Busy, Int
2K x 8 CY7C142 - - - - - - - 5 5 - 5 48 - - - 170@25 Slave, Busy, Int
2K x 8 CY7C146 - - - -5-55555-52- 52170@25Slave, Busy, Int
4K x 8 CY7C135 - - - - 5 5 5 - 5 - 5 - 52 - - 220@20 No Arbitration
4K x 8 CY7C1342 - - - - 5 5 5 - 5 - - 52 - - 220@20 Sem
4K x 8 CY7C138 CY7C138AV - - - B - B - 5 - 5 - 68 - - 220@15 Sem, Busy, Int,
Master/Slave Pin
4K x 9 CY7C139 CY7C139AV - - - B - B - 5 - 5 - 68 - - 220@15 Sem, Busy, Int,
Master/Slave Pin
8K x 8 CY7C144 CY7C144AV - - - B - B - 5 - 5 - 68 64 - 220@15 Sem, Busy, Int,
Master/Slave Pin
8K x 9 CY7C145 CY7C145AV - - - B - B - 5 - 5 - 68 80 - 220@15 Sem, Busy, Int,
Master/Slave Pin
16K x 8 CY7C006 CY7C006AV - - - B - B - 5 - 5 - 68 64 - 170@15 Sem, Busy, Int,
Master/Slave Pin
16K x 9 CY7C016 CY7C016AV - - - B - B - 5 - 5 - 68 80 - 170@15 Sem, Busy, Int,
Master/Slave Pin
32K x 8 CY7C007A CY7C007AV - - 5 B 5 3 - - - - - - 100 - 195@12 Sem, Busy, Int,
Master/Slave Pin
32K x 9 CY7C017A CY7C017AV - - 5 B 5 3 - - - - - - 100 - 195@12 Sem, Busy, Int,
Master/Slave Pin
64K x 8 CY7C008 CY7C008V - - 5 B 5 3 - - - - - - 100 - 195@12 Sem, Busy, Int,
Master/Slave Pin
64K x 9 CY7C018 CY7C018V - - 5 B 5 3 - - - - - - 100 - 195@12 Sem, Busy, Int,
Master/Slave Pin
128K x 8 CY7C009 CY7C009V - - 5 B 5 3 - - - - - - 100 - 195@12 Sem, Busy, Int,
Master/Slave Pin
128K x 9 CY7C019 CY7C019V - - 5 B 5 3 - - - - - - 100 - 195@12 Sem, Busy, Int,
Master/Slave Pin
2K x 16 CY7C133 - - - - - 5 5 - 5 - 5 - 68 - - 170@25 Master, Busy, Int
2K x 16 CY7C143 - - - - - 5 5 - 5 - 5 - 68 - - 170@25 Slave, Busy, Int
4K x 16 CY7C024 CY7C024AV - - - 5 - B - 5 - 5 - 84 100 - 190@15 Sem, Busy, Int,
Master/Slave Pin
4K x 18 CY7C0241 CY7C0241AV - - - 5 - B - 5 - 5 - 100 - 190@15 Sem, Busy, Int,
Master/Slave Pin
8K x 16 CY7C025 CY7C025AV - - - 5 - B - 5 - 5 - 84 100 - 190@15 Sem, Busy, Int,
Master/Slave Pin
8K x 18 CY7C0251 CY7C0251AV - - - 5 - B - 5 - 5 - 100 - 190@15 Sem, Busy, Int,
Master/Slave Pin
16K x 16 CY7C026A CY7C026AV - - 5 5 B 3 - - - - - - 100 - 195@12 Sem, Busy, Int,
Master/Slave Pin
16K x 18 CY7C036A CY7C036AV - - 5 5 B 3 - - - - - - 100 - 195@12 Sem, Busy, Int,
Master/Slave Pin
32K x 16 CY7C027 CY7C027V - - 5 B B 3 - - - - - - 100 - 195@12 Sem, Busy, Int,
Master/Slave Pin
Mult i-Port RAMs (continued)
Org. 5V Part # 3.3V Part #
Speed (ns)
(A vailability Guide: 5 = 5V only; 3 = 3.3V
only; B = 5V and 3.3V) Package ICC
(mA@ns) Features5 6.5 7.5 9 12 15 20 25 30 35 45 55 P J A BA N
MAIN INDEX
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32K x 18 CY7C037 CY7C037V - - 5 B B 3 - - - - - - 100 - 195@12 Sem, Busy, Int,
Master/Slave Pin
64K x 16 CY7C028 CY7C028V - - 5 B B 3 - - - - - - 100 - 195@12 Sem, Busy, Int,
Master/Slave Pin
64K x 18 CY7C038 CY7C038V - - 5 B B 3 - - - - - - 100 - 195@12 Sem, Busy, Int,
Master/Slave Pin
16K x 36 CY7C056V 3 3 3 144 144 300@12 Bus Matching/Byte
Select
32K x 36 CY7C057V 3 3 3 144 144 300@12 Bus Matching/Byte
Select
Synchr onous Dual Ports
8K x 9 CY7C09159A CY7C09159AV 5 B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
16K x 9 CY7C09169A CY7C09169AV 5 B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
32K x 8 CY7C09079A CY7C09079V 5 B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
32K x 9 CY7C09179A CY7C09179V 5 B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
64K x 8 CY7C09089 CY7C09089V B B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
64K x 9 CY7C09189 CY7C09189V B B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
128K x 8 CY7C09099 CY7C09099V B B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
128K x 9 CY7C09199 CY7C09199V B B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
4K x 18 CY7C09349A CY7C09349AV 5 B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
8K x 18 CY7C09359A CY7C09359AV 5 B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
16K x 16 CY7C09269A CY7C09269V B B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
16K x 18 CY7C09369A CY7C09369V B B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
32K x 16 CY7C09279 CY7C09279V B B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
32K x 18 CY7C09379 CY7C09379V B B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
64K x 16 CY7C09289 CY7C09289V B B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
64K x 18 CY7C09389 CY7C09389V B B B B - - - - - - - - - 100 - 250@8 Pipelined/Flow-
thru Pin
16K x 36 CY7C09569V 3 3 3 144 144 300@5 Bus Matching/Byte
Select
32K x 36 CY7C09579V 3 3 3 144 144 300@5 Bus Matching/Byte
Select
Mult i-Port RAMs (continued)
Org. 5V Part # 3.3V Part #
Speed (ns)
(A vailability Guide: 5 = 5V only; 3 = 3.3V
only; B = 5V and 3.3V) Package ICC
(mA@ns) Features5 6.5 7.5 9 12 15 20 25 30 35 45 55 P J A BA N
MAIN INDEX
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FIFOs
X80 Sync hronous:
•30+Gb/s bandwi dth/200- MHz opera tion
•2.5V available
•Up to 5-Megabit d ensi ty (64K x80)
•Bus Matchin g both ports to x80/40/ 20/10
•288 BG A (19 mm x 19 mm, 1.0-mm pitch)
•Unidi rect i onal
X36 Sync hronous:
•3.3V and 5V avai lable
•Unidi rectional , Bidirecti onal, and Tri Bus
•Up to 1-Megabit d ensi ty (16K x 36 x 2)
•Up to 10 Gb/s bandwidth/133 -MHz operati on
•Bus M atching cap abil ity, retransm it
•128 TQFP / 120 TQFP a v aila b le
Low-Voltage Synchr onous (3.3V):
•3.3V—Low power
•Up to 1-Meg Deep Sync™ density
•100-MHz operation (Deep Sync)
•Progr ammabl e flags
Synchronous (5V):
•Up to 1-Meg Deep Sync density
•100-MHz operat ion
•Low po wer
•Progr ammabl e flags
Asynchronous:
•10-ns access ti m e
•Industry-standar d operati on and pinout
•Densities up to 64Kx9—all d ensities pin compatible
3.3V SYNC
7C4421 7C4201 7C4211 7C4221 7C4231 7C4241
7C4205
64x9 256x9 512x9 1Kx9
256x18
2Kx9 4Kx9
7C4251
8Kx9
7C4261
16Kx9
7C4271
32Kx9
7C4425 7C4215 7C42357C4225
512x1864x18 2Kx181Kx18
7C4245
4Kx18
7C4255
8Kx18
7C4265
16Kx18
FIFO Product Portfolio
256x9x2
7C4801 7C4851
8Kx9x2
7C4841
4Kx9x2
7C4811
512x9x2
7C4821
1Kx9x2
7C4831
2Kx9x2
7C4281/2
64Kx9 128Kx9
32Kx18 64Kx18
5V SYNC
7C4285
7C4275
7C4291/2
7C4421V 7C4201V 7C4211V 7C4221V 7C4231V 7C4241V
7C4205V
64x9 256x9 512x9 1Kx9
256x18
2Kx9 4Kx9
7C4425V 7C4215V 7C4235V7C4225V
512x1864x18 2Kx181Kx18
7C4245V
4Kx18
7C4261V
16Kx9
7C4271V
32Kx9
7C4281/2V
64Kx9 128Kx9
7C4291/2V
7C4251V
8Kx9
7C4255V
8Kx18
7C4265V
16Kx18 32Kx18 64Kx18
7C4285V
7C4275V
7C43622
256x36x2
7C43632 7C43642
512x36x2 1Kx36x2
7C43662
4Kx36x2
3.3V x36 SYNC
7C43682
16Kx36x2
7C43623
256x36
7C43633 7C43643
512x36 1Kx36
7C43663
4Kx36
7C43683
16Kx36
7C43624
256x36x2
7C43634 7C43644
512x36x2 1Kx36x2
7C43664
4Kx36x2
7C43684
16Kx36x2
7C43626
256x36x2
7C43636 7C43646
512x36x2 1Kx36x2
7C43666
4Kx36x2
7C43686
16Kx36x2
7C43642AV
1Kx36x2
7C43662AV
4Kx36x2
7C43682AV
16Kx36x2
7C43643AV
1Kx36
7C43663AV
4Kx36
7C43683AV
16Kx36
7C43644AV
1Kx36x2
7C43664AV
4Kx36x2
7C43684AV
16Kx36x2
7C43646AV
1Kx36x2
7C43666AV
4Kx36x2
7C43686AV
16Kx36x2
5V x36 S YNC
Bidirectional
Unidirectional
Bidirectional w/ BM
Tri Bus
Bidirectional
Unidirectional
Bidirectional w/ BM
Tri Bus
2. 5V x80 SYN C
Unidirectional
7C4804V25
4K x80
7C4806V25
16K x80
7C4808V25
64K x8 0
128K16K
4K 8K
256 512 1K 2K 32K 64K64 W ORD DENSI TY
MAIN INDEX
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FIFOs (continued)
2.5 V X8 0 Sync FIFOs
3.3 V X3 6 Sync FIFOs
5V X36 Sync FIFOs
Organization Pins Part Number Speed (ns) ICC
(mA @ 20 MHz) Packages
64Kx80 Unidirectional 288 CY7C4808V25 200 MHz, 167 MHz 100 BA
16Kx80 Unidirectional 288 CY7C4806V25 200 MHz, 167 MHz 100 BA
4Kx80 Unidirectional 288 CY7C4804V25 200 MHz, 167 MHz 100 BA
Organization Pins Part Number Speed (ns) ICC
(mA @ 20 MHz) Packages
1Kx36x2 Bidirectional 120 CY7C43642AV 7, 10, 15 60 A
1Kx36 Unidirectional w/ Bus Matching 128 CY7C43643AV 7, 10, 15 60 A
1Kx36x2 Bidirectional w/ Bus Matching 128 CY7C43644AV 7, 10, 15 60 A
1Kx36/18x2 T ri Bus 128 CY7C43646AV 7, 10, 15 60 A
4Kx36x2 Bidirectional 120 CY7C43662AV 7, 10, 15 60 A
4Kx36 Unidirectional w/ Bus Matching 128 CY7C43663AV 7, 10, 15 60 A
4Kx36x2 Bidirectional w/ Bus Matching 128 CY7C43664AV 7, 10, 15 60 A
4Kx36/18x2 T ri Bus 128 CY7C43666AV 7, 10, 15 60 A
16Kx36x2 Bidirectional 120 CY7C43682AV 7, 10, 15 60 A
16Kx36 Unidirectional w/ Bus M atching 128 CY7C43683AV 7, 10, 15 60 A
16Kx36x2 Bidirectional w/ Bus Matching 128 CY7C43684AV 7, 10, 15 60 A
16Kx36/18x2 Tri Bus 128 CY7C43686AV 7, 10, 15 60 A
Organization Pins Part Number Speed (ns) ICC
(mA @ 20 MHz) Packages
256x36x2 Bidirectional 120 CY7C43622 7, 10, 15 100 A
256x36 Unidirectional w/ Bus Matching 128 CY7C43623 7, 10, 15 100 A
256x36x2 Bidirectional w/ Bus Matching 128 CY7C43624 7, 10, 15 100 A
256x36/18x2 Tri Bus 128 CY7C43626 7, 10, 15 100 A
512x36x2 Bidirectional 120 CY7C43632 7, 10, 15 100 A
512x36 Unidirectional w/ Bus Matching 128 CY7C43633 7, 10, 15 100 A
512x36x2 Bidirectional w/ Bus Matching 128 CY7C43634 7, 10, 15 100 A
512x36/18x2 Tri Bus 128 CY7C43636 7, 10, 15 100 A
1Kx36x2 Bidirectional 120 CY7C43642 7, 10, 15 100 A
1Kx36 Unidirectional w/ Bus Matching 128 CY7C43643 7, 10, 15 100 A
1Kx36x2 Bidirectional w/ Bus Matching 128 CY7C43644 7, 10, 15 100 A
1Kx36/18x2 T ri Bus 128 CY7C43646 7, 10, 15 100 A
4Kx36x2 Bidirectional 120 CY7C43662 7, 10, 15 100 A
4Kx36 Unidirectional w/ Bus Matching 128 CY7C43663 7, 10, 15 100 A
4Kx36x2 Bidirectional w/ Bus Matching 128 CY7C43664 7, 10, 15 100 A
4Kx36/18x2 T ri Bus 128 CY7C43666 7, 10, 15 100 A
16Kx36x2 Bidirectional 120 CY7C43682 7, 10, 15 100 A
16Kx36 Unidirectional w/ Bus M atching 128 CY7C43683 7, 10, 15 100 A
16Kx36x2 Bidirectional w/ Bus Matching 128 CY7C43684 7, 10, 15 100 A
16Kx36/18x2 Tri Bus 128 CY7C43686 7, 10, 15 100 A
MAIN INDEX
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3.3 V Low -Vol t age S ync hron ous FIFO s
Organization Pins Part Number Speed (ns) ICC
(mA @ 20 MHz) Packages
64 x 9—Low-V oltage Synchronous 32 CY7C4421V 15, 25 20 A, J
256 x 9—Low-V oltage Synchronous 32 CY7C4201V 15, 25 20 A, J
512 x 9—Low-V oltage Synchronous 32 CY7C4211V 15, 25 20 A, J
1K x 9—Low-V oltage Synchronous 32 CY7C4221V 15, 25 20 A, J
2K x 9—Low-V oltage Synchronous 32 CY7C4231V 15, 25 20 A, J
4K x 9—Low-V oltage Synchronous 32 CY7C4241V 15, 25 20 A, J
8K x 9—Low-V oltage Synchronous 32 CY7C4251V 15, 25 20 A, J
16K x 9—Low-V oltage Deep Sync 32 CY7C4261V 10,15, 25 20 J
32K x 9—Low-V oltage Deep Sync 32 CY7C4271V 10,15, 25 20 J
64K x 9—Low-V oltage Deep Sync 32 CY7C4281V 10,15, 25 25 J
64K x 9—Low-V oltage Deep Sync 64 CY7C4282V 10,15, 25 25 AS
128K x 9—Low-V oltage Deep Sync 32 CY7C4291V 10,15, 25 25 J
128K x 9—Low-V oltage Deep Sync 64 CY7C4292V 10,15, 25 25 AS
64 x 18—Low-V oltage Synchronous 64 CY7C4425V 15, 25 30 AS
256 x 18—Low-V oltage Synchronous 64 CY7C4205V 15, 25 30 AS
512 x 18—Low-V oltage Synchronous 64 CY7C4215V 15, 25 30 AS
1K x 18—Low-V oltage Synchronous 64 CY7C4225V 15, 25 30 AS
2K x 18—Low-V oltage Synchronous 64 CY7C4235V 15, 25 30 AS
4K x 18—Low-V oltage Synchronous 64 CY7C4245V 15, 25 30 AS
8K x 18—Low-V oltage Deep Sync 64 CY7C4255V 10,15, 25 30 AS
16K x 18—Low-V oltage Deep Sync 64 CY7C4265V 10,15, 25 30 AS
32K x 18—Low-V oltage Deep Sync 64 CY7C4275V 10,15, 25 30 AS
64K x 18—Low-V oltage Deep Sync 64 CY7C4285V 10,15, 25 30 AS
5V S ync hronous FIFOs
Organization Pins Part Number Speed (ns) ICC
(mA @ 20 MHz) Packages
64 x 9—Synchronous 32 CY7C4421 10, 15, 25 35 A, J
256 x 9—Synchronous 32 CY7C4201 10, 15, 25 35 A, J
512 x 9—Synchronous 32 CY7C4211 10, 15, 25 35 A, J
1K x 9—Synchronous 32 CY7C4221 10, 15, 25 35 A, J
2K x 9—Synchronous 32 CY7C4231 10, 15, 25 35 A, J
4K x 9—Synchronous 32 CY7C4241 10, 15, 25 35 A, J
8K x 9—Synchronous 32 CY7C4251 10, 15, 25 35 A, J
16K x 9—Deep Sync 32 CY7C4261 10, 15, 25 35 A, J
32K x 9—Deep Sync 32 CY7C4271 10, 15, 25 35 A, J
64K x 9—Deep Sync 32 CY7C4281 10, 15, 25 40 J
64K x 9—Deep Sync 64 CY7C4282 10, 15, 25 40 AS
128K x 9—Deep Sync 32 CY7C4291 10, 15, 25 40 J
128K x 9—Deep Sync 64 CY7C4292 10, 15, 25 40 AS
64 x 18—Synchronous 64 CY7C4425 10, 15, 25 45 A, AS
256 x 18—Synchronous 64 CY7C4205 10, 15, 25 45 A, AS
512 x 18—Synchronous 64 CY7C4215 10, 15, 25 45 A, AS
1K x 18—Synchronous 64 CY7C4225 10, 15, 25 45 A, AS
2K x 18—Synchronous 64 CY7C4235 10, 15, 25 45 A, AS
4K x 18—Synchronous 64 CY7C4245 10, 15, 25 45 A, AS
8K x 18—Deep Sync 64 CY7C4255 10, 15, 25 45 A, AS
16K x 18—Deep Sync 64 CY7C4265 10, 15, 25 45 A, AS
32K x 18—Deep Sync 64 CY7C4275 10, 15, 25 50 AS
64K x 18—Deep Sync 64 CY7C4285 10, 15, 25 50 AS
256 x 9—Double Sync 64 CY7C4801 10, 15, 25 60 A
MAIN INDEX
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As ync hronous FIFOs
512 x 9—Double Sync 64 CY7C4811 10, 15, 25 60 A
1K x 9 —Double Sync 64 CY7C4821 10, 15, 25 60 A
2K x 9 —Double Sync 64 CY7C4831 10, 15, 25 60 A
4K x 9— Double Sync 64 CY7C4841 10, 15, 25 60 A
8K x 9—Double Sync 64 CY7C4851 10, 15, 25 60 A
Organization Pins Part Number Speed (ns) ICC
(mA @ 20 MHz) Packages
64 x 8—w/OE and Almost Flags 28S CY7C408A 15, 25, 35 MHz 115 P, V
64 x 9—w/Almost Flags 28S CY7C409A 35 MHz 115 P, V
256 x 9—w/Half Full Flag 28S, 32 CY7C419 10, 15, 20, 25, 40 35 A, L, J, P, V
512 x 9—w/Half Full Flag 28 CY7C420 25, 40, 65 35 P
512 x 9—w/Half Full Flag 28S, 32 CY7C421 10, 15, 20,25, 30, 40, 65 35 A, L, J, P, V
1K x 9—w/ Half Full Flag 28S, 32 CY7C425 10, 15, 20,25, 30, 40, 65 35 A, J, L, P, V
2K x 9—w/ Half Full Flag 28S, 32 CY7C429 10, 15, 20,25, 30, 40, 65 35 A, J, L, P, V
4K x 9—w/Half Full Flag 28S, 32 CY7C433 10, 15, 20, 25, 30, 40, 65 35 A, J, L, P, V
8Kx9—w/ Half Full Flag 28, 32 CY7C460A 10, 15, 25 60 P, P T, J
16Kx9—w/ Half Full Flag 28, 32 CY7C462A 10, 15, 25 60 P, P T, J
32Kx9—w/ Half Full Flag 28, 32 CY7C464A 10, 15, 25 60 P, P T, J, L
64Kx9—w/ Half Full Flag 28, 32 CY7C466A 10, 15, 25 60 P, P T, J, L
5V S ync hronous FIFOs (continued)
Organization Pins Part Number Speed (ns) ICC
(mA @ 20 MHz) Packages
MAIN INDEX
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Communications Products
* Interface: C-Coax; T-twisted pair; F-fiber, P-POF
CY7B923/933: HOTLink™
•Transm itter/receive r chipset
•150–400 Mb/s oper ation
•Fibre Channel/ESCON® compliant
•On-chip 8B/10B enc oding/decoding
•Built-In S elf-Test (BIST)
•Ev aluation boards availab le (CY9266)
•User’s G u ide available
CY7C924DX: HOTLink Transceiver
•Integr ated Tx, Rx, and FI FO
•50–200 Mb/s oper ation
•Fibre Channel/ESCON compliant
•On-chip 8B/10B enc oding/decoding
•Built-In S elf-Test (BIST)
CY7C9689: TAXI Compliant HOT L ink
•Integr ated Tx, Rx, and FI FO
•50–200 Mb/s oper ation
•TAXIchip™ and FDDI Com pliant
•On chip 4B/5B and 5B/6 B encoding/ dec oding
•Built-In S elf-Test (BIST)
CY7C954: Utopia C ompliant HOT Lin k
•Integr ated Tx, Rx, and FI FO
•50–200 Mb/s oper ation
•Fibre Channel/ESCON compliant
•On-chip 8B/10B enc oding/decoding
•Utopia Level 1 and 2 co mpliant
•Built-In S elf-Test (BIST)
CY7C9235/9335: SMPTE Encoder/De coder
•F or High-end Vi deo appl ications
•Compliant to both SMPTE-259M and DVB-ASI
standards
•Wor ks with SMPTE HOTLink Receiver/
Transmitter (CY7B9234/9334)
•Evaluation boards available (CY9267)
CY7B951: SONET/SDH Transceiver
•Performs Clock & Data Recovery of SONET/SDH
frames - single PMD
•OC-1 (51.8 MHz) & OC-3 (155. 5 MHz)
•Meets LAN Bellcore specifications
•Loop-back testing
•Connect s to SONET processors, ATM framers,
Mux/De - Mux, & ASICs
CY7C955: SONET/SDH PHY Transceiver
•F ramer + PMD in one chip = integrated solution
•Pin compat ible to PMC Sierra 5346 (S/UNI-Lite)
•SON ET/SDH and ATM compatible
•OC-1 (51.8 MHz) & OC-3 (155. 5 MHz)
•Available in Industr ial Temperature
CY7B8392: L ow-power Coax Transc eiver
fo r 10 Mbps Ethernet application s
•Pin compat ible to i ndustry standard 8392
•10BASE5 and 10BASE2 applications
•Auto Attachment Unit Interface (AUI)
•Hybr id collision detection
Description Pins Part Number Speed (MHz) ICC (mA) Packages
HOTLink™ Transmitter 28 CY7B923 150-400 65 J, L, S
HOTLink Receiver 28 CY7B933 150-400 120 J, L, S
HOTLink Evaluation Card N/A CY9266 150-400 —N/A C, F, T, P*
HOTLink Transceiver 100 CY7C924 50-200 250 A
T AXI Compatible HOTLink T ransceiver 100 CY7C9689 50-200 250 A
Utopia Compliant HOTLink Transceiver 100 CY7C954 50-200 250 A
SMPTE Encoder 44 CY7C9235 270, 400 250 J
SMPTE Decoder 100 CY7C9335 270, 400 300 A
SMPTE HOTLink Transmitter 28 CY7B9234 270, 400 65 J
SMPTE HOTLink Receiver 28 CY7B9334 270, 400 120 J
SMPTE Evaluation Card N/A CY9267 160-400 —N/A F
SONET/SDH PMD T ransceiver 24 CY7B951 51 & 155 50 S
BellCore SONET/SDH WAN PMD T ransceiver 24 CY7B952 51 & 155 50 S
SONET/SDH LAN PHY Transceiver 128 CY7C955 51 & 155 TBD N
3.3V QUAD SONET/SDH T ransceiver 100 CY7B9514V 51 & 155 400, 5 stby A
10BASE 2/5 Ethernet Coax T ransceiver 16, 28 CY7B8392 10 25 J, P
MAIN INDEX
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Communications Products (continued)
CY7B952: Bellcore WAN SONET /SDH Transceiver
•Performs Cloc k & Data Recov e ry of SONET
frames - si ngle PMD
•OC-1 (51.8 MHz) & OC-3 (155.5 MHz) clock &
data recov ery
•Meets all WAN Bellcore specifications
•Loop-back testing
•Connects to SONET processors, ATM framers ,
Mux /De-Mux , & A SICs
CY7B9514V: 3.3V Quad SONET/SDH Transceiv er
•Performs Clock & Data Recovery for four SONET/
SDH frames - Quad PMD
•OC-1 (51.8 MHz) & OC-3 (155. 5 MHz)
•3.3V
•Meets LAN Bellcore specifications
•Supp ort Loop-back testing
•Connect s to SONET processors, ATM framers,
Mux/De - Mux, & ASICs
VMEbus Interface Products
Cypress offers a broad range of VME interface products ranging from low-cost slave I/O controllers to high-end 32/64-bit master
controllers. All product s are listed in detail in the VME Interface Handbook.
VIC068A and VAC068A
•32-bit VME bus operation
•Complete VME bus interf ace controller/arbiter
•Complete mast er/slav e capability
•Commercial / Industrial / Military
VIC64
•64-bit MBLT operation
•Software and pin compatib le to VIC068A
•Complete mast er/slav e capability
•Commercial / Industrial / Military
CY7C964
•Companion to VIC64, VIC068A, CY7C960 and
CY7C961
•100-pin TQ FP
•Co mme rcial / Military
Serial Bit Stream
155-400 Mbits/Sec
Media:
Fiber
Coax
Twisted-pair
CY7B923
HOTLink
Transmitter
Parallel Data
15.5- 40 M b y t es /S e c
CY7B933
HOTLink
Receiver
Point-to-Point HOTLink
Parallel
Data
SONET/ SDH Tr ansceiver s
PMD Sublayer TC Sublayer
Sonet Frame with
clock & serial data
.............................
PLL Sonet Frame
Serial data
.................
Sonet Frame clock
Serial
to
Parallel
/
Parallel
to
Serial
SONET
Frame
Proc
Sonet Frame
Parallel data
ATM
cells
ATM
cells
PHY Layer 1..... 955
Description Pins Part Number Transfer Rate
(MB/s) ICC (mA) Packages
VME Interface Controller 144/160 VIC068A 40 150 A, B, G, N, U
VME Address Controller 144/160 VAC068A —150 B, G, N, U
64-Bit VIC 144/160 VIC64 80 150 A, B, G, N, U
Bus Interface Logic Circuit 64/68 CY7C964 —120 A,G, N, U
MAIN INDEX
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19
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Complex PLDs (CPLDs)
Delta39K™ CPLDs
•CPLDs at FPGA Densities
•Mor e RA M than any other pro grammab le logic device •Integ rated FIFO cont rol and Dual-port arbitration logic
•Advance d PL L, I/O, an d pa ck a gin g tec h no logy
Delta39K
Ultra37000™ CPLDs
•In-System Reprogram m able™ (ISR™) CPL Ds of-
fering high density and high performance
•From 32 to 512 macrocells
•Tru e 3.3V and 5V versions
•Simple t iming model f or easy des ign and syst em s imu lation
•Suppor ts f ixed pi n assignments
•Full JTAG (IEEE 1149.1) compatibility
•PCI compli ant
Ultra37000
Progr ammable Logic Devices (PLDs)
Cypress’s Programmable Logic offer ing ranges from the
industry-standard Sim ple Programmable Logic Devices
(SPLDs), to high-density Complex Programmable Logic
De vices (CPLDs). The entire f amily is supported by the
Cypress Warp™ developm ent tools for comple te dev ice
independence during the design cycle.
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Device T ypical Gates Macrocells RAM Bits tPD (ns) fMAX (MHz) I/O Pins Packages
39K15 8K-24K 256 40K 6.5 250 126 PQFP, BGA, FBGA
39K30 15K-47K 512 80K 6.5 250 168 PQFP, BGA, FBGA
39K50 22K-71K 768 120K 7.0 222 210 PQFP, BGA, FBGA
39K100 45K-140K 1536 240K 7.5 200 294 PQFP, BGA, FBGA
39K165 74K-238K 2560 400K 8.0 181 378 PQFP, BGA, FBGA
39K200 92K-289K 3200 500K 8.0 181 420 PQFP, BGA, FBGA
39K250 110K-337K 3840 600K 8.5 167 462 PQFP, BGA, FBGA
39K350 154K-473K 5376 840K 9.0 154 546 PQFP, BGA, FBGA
Description Packages Part
Number fMAX
(MHz) tpd
(ns) ts
(ns) tco
(ns)
Typical
ICC
(mA)
5V CPLDs
32-Macrocell ISR CPLD 44P LCC, 44TQFP CY37032 222 5 3 4 15
64-Macrocell ISR CPLD 44P LCC, 44TQFP, 84P LCC, 100TQFP CY37064 200 6 4 4 30
128-Macrocell ISR CPLD 84PLCC, 100TQFP, 160TQFP CY37128 167 6.5 4 4 30
192-Macrocell ISR CPLD 160TQFP CY37192 154 7.5 54.5 90
256-Macrocell ISR CPLD 160TQFP, 208PQFP, 256 BGA CY37256 154 7.5 54.5 120
384-Macrocell ISR CPLD 208PQFP, 256BGA CY37384 125 10 5.5 6.5 180
512-Macrocell ISR CPLD 208PQFP, 256BGA , 352BGA CY37512 125 10 5.5 6.5 240
3.3V CPLDs
32-Macrocell ISR CPLD 3.3V 44PLC C, 44TQF P CY37032V 222 5 3 4 15
64-Macrocell ISR CPLD 3.3V 44PLC C , 44TQF P, 48 FBG A, 84PL CC, 10 0T QF P CY37064V 200 6 4 4 30
128-Macrocell ISR CPLD 3.3V 84PLCC, 100TQFP, 100FBG A, 160TQFP CY37128V 167 6.5 4 4 30
192-Macrocell ISR CPLD 3.3V 160TQFP CY37192V 154 7.5 54.5 90
256-Macrocell ISR CPLD 3.3V 160TQFP, 208PQFP, 256BGA , 256FBGA CY37256V 154 7.5 54.5 120
384-Macrocell ISR CPLD 3.3V 208PQ FP, 256BGA CY37384V 125 10 5.5 6.5 180
512-Macrocell ISR CPLD 3.3V 208PQ FP, 256BGA, 352BGA, 400FBGA CY37512V 125 10 5.5 6.5 240
MAIN INDEX
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Ult ra3 7000 Ar c h itect ur e
LOGIC
BLOCK
G
LOGIC
BLOCK
H
LOGIC
BLOCK
I
LOGIC
BLOCK
J
LOGIC
BLOCK
L
LOGIC
BLOCK
P
LOGIC
BLOCK
M
LOGIC
BLOCK
N
LOGIC
BLOCK
O
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
LOGIC
BLOCK
E
LOGIC
BLOCK
K
LOGIC
BLOCK
F
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
PIM
Input Clock/
Input
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O0−I/O11
I/O12−I/O23
I/O24−I/O35
I/O36−I/O47
I/O48−I/O59
I/O60−I/O71
I/O72−I/O83
I/O84−I/O95
I/O180−I/O191
I/O168−I/O179
I/O156−I/O167
I/O144−I/O155
I/O132−I/O143
I/O120−I/O131
I/O108−I/O119
I/O96−I/O107
4
4
4
96
96
TDI
TCLK
TMS TDO
JTAG Tap
Controller
1
37256-1
FLASH370i™ CPLDs
•In-System-Reprogr ammable (ISR).
•State-of-the-art Flash technology for electri-
cal erasability.
•Unique single-product-ter m sharing and
steering.
•Architecture provides complet e desi gn flex -
ibility for user-assigned pinouts. Even when
you make changes to your logic, y ou will be
able to maintain the same pin configur ation.
•Significant capacity advantages over all oth-
er CPLD architectures.
•Simple t i ming model for easy desi gn and
syste m si mulation .
•Ev ery thing you liked about the 22V10 now
available in high-performance, high-density
logic.
•ISR versi ons are upward compatible from
earlier devices using existing software tools.
FLASH370i Family Architecture
PIM
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
2
4
4
Input
Macrocells
Inpu ts Cl oc k Input s
Logic
Block
Logic
Block
Logic
Block
Logic
Block
Logic
Block
Logic
Block
Logic
Block
Logic
Block
MAIN INDEX
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21
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FLASH370i
MAX340
•Second-sourc ed fam ily of CPLDs.
•High-v olume 0.8µ UV-erasable CMO S
process.
•CY7C340B devices are 0.65µ shrinks of the
or iginal versions offering even faster speed
options.
MAX340
Industry-Standard PLDs
•CMOS Flash and UV erasable technology ex-
pertise
•Compl ete line of SPLDs – GAL® architec-
tures: 16V8, 20V8 , and 22V10
•Packaging options include PDIP, PL CC, a nd
LCC packages
PLDs
* Not recommended f or ne w designs .
Organization Packages Part
Number Speed (ns) ICC/ISB
(mA)
32-Macrocell ISR Flash CPLD 44P LCC, 44TQ FP CY7C371i fMAX/tPD/tS/tCO=143 MHz/ 8.5 ns/5 ns/6 ns 75
32-M acr oc ell I SR Flas h C PL D Lo w Po w er 4 4P LCC, 44TQ FP CY7C371iL fMAX/tPD/tS/tCO=83 MHz/12 ns/8 ns/8 ns 45
64-Macrocell ISR Flash CPLD 44PLCC, 84PLCC,
100TQFP CY7C372i / 3i fMAX/tPD/tS/tCO=125 MHz/10 ns/5.5 ns/6.5ns 75
64-M acr oc ell I SR Flas h C PL D Lo w Po w er 44P LCC, 84PLCC,
100TQFP CY7C372iL /
3iL fMAX/tPD/tS/tCO=83 MHz/2 0 n s/8 ns/8 ns 45
128-Macrocell ISR Flash CPLD 84PLCC, 10 0T Q FP,
160TQFP CY7C374i / 5i fMAX/tPD/tS/tCO = 125 MHz/10 ns/5.5 n s/ 6.5 ns 125
128-Macrocell ISR Flash CPLD Low
Power 8 4PLCC, 10 0T Q FP,
160TQFP CY7C374iL /
5iL fMAX/tPD/tS/tCO = 83 MHz/15 ns/8 ns/8 ns 75
Organization Pins Part Number Speed (ns) ICC/ISB
(mA) Packages
32 Macrocell CPLD 28S CY7C344 tPD/S/CO = 15/ 10/ 10 , 10/6/ 5 200/150 H, J, P,W
64 Macrocell CPLD 44 CY7C343 tPD/S/CO = 20/12/ 12 , 12/8/ 6 135/125 H, J, R
128 Macrocell C PLD 68 CY7C342B tPD/S/CO = 25/15/ 14, 12/ 8/ 6 250/225 H, J, R
128 Macrocell C PLD 84, 100 CY7C346 tPD/S/CO = 25/15/ 14 , 15/ 10/7 250/225 H, J, N, R
192 Macrocell C PLD 84 CY7C341 tPD/S/CO = 25/ 15/ 14 , 15/10/ 7 380/360 H, J , R
Part Number tPD (ns) f (MHz) ICC (mA ) Pins Packages
PALCE16V8 7.5 100 115 20 J, P
PALCE16V8 10/15/25 69/45/37 90 20 D, J, L, P
PALCE16V8L 15/25 45/33 55 20 J, L, P, Q
PLDC20G10* 25 33 55 24/28 J, P, W
PLDC20G10B* 15/20 45/42 70 24/28 D, P, W
PLDC20RA10 15/20/25 45/33/25 75 24/28 D, J, P, W
PALCE20V8 7.5/10 83/58 115 24/28 J, L, P
PALCE20V8 15/25 45/37 90 24/28 D, J, L, P
PALCE20V8L 15/25 45/37 55 24/28 D, J, L, P
PALC22V10* 20/25 42/33 90 24/28 D, J , P, Q, W
PALC22V10L* 25 33 55 24/28 J, P, W
PALC22V10B* 15/20 50/31 90/100 24/28 D, J, L, P, W
PALC22V10D* 7.5 100 130 24/28 J, P
PALC22V10D* 10/15/25 77/55/33 90 24/28 D, J, L, P
PALCE22V10 5/7.5 143/100 130 24/28 J, P
PALCE22V10 10/15/25 77/55/33 90 24/28 D, J, L, P
CY7C331* 20/25 27/24 130 28 J, P
CY7C335 15/20/25 50/45/35 140 28 J, P, W
MAIN INDEX
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Design and Programming Too ls
The capabilities of our Warp™ and programming tools great-
ly sim plify your design effort and let you reach the o ptimal
solution to your design problem in the shortest possible time.
•Warp software supports the entire Programmable Logic
product offering
•Open language support - IEEE-STD-1076/ 1164 VHDL
(Very-high-speed integrated-circui t Hardware
Description Language) and IEEE-STD-1364 Verilog for
programmab le logic desi gn
•Accepts designs as VHDL/Verilog te xt, schemat ic c ap-
ture, graphical Finite State Machine editor or in any com-
bination of these entry m odes
•Cypress deve lo ps its own synthesis technology so opt i -
mum results are guarant eed every time
•Shortens the design process t hrough its extraordinary
capabilities
- VHDL source code verificat i on
- Easy debugging
- Graphical w aveform s imulation and editing
- Graphi cal tim ing simulation and analys is
•Multiple design tool options
- Warp2®, low- cost tool , VHDL or Verilog design
entry, graphical Finite State Machine editor , and a
powerful t i ming sim ul ator.
- Warp3®, adds schemat ic entry, VHDL and Verilog
design entry, VHDL deb ugger and sourc e l evel
simulation.
•Bolt-in Kits seamlessly interface Warp with major third-
party softw are products . Warp2 als o bol ts into many
other third-party softw are products such as Synopsys
and Ex emplar .
• FLASH370i ISR kit is a low-cost kit f or prog ramming of
FLASH370i I SR devices .
•Ultra37000 ISR kit is a low-cost kit f or programming of
Ultra37000 5-volt and 3.3-v ol t dev ic es, complet e wi th
a prototype board containing a CY37256 160-pin de-
vice f o r eas y design t esting.
•The Warp2ISR™ kit combi nes Warp2 with an
Ultra37000 ISR kit f or a complete low-cost ISR design
and programming solution.
•All VHDL software development kits include the pop-
ular textbook “V HDL for Programmable Logic” by
K evin Skahill, an engineer at Cypress.
Design and Pr ogramming Tools
Complete ISR CPLD Solutions
Description Type Part Number
Warp2 for PC and Workstation Complete VHDL/Verilog Design Environment CY3120R52 VHDL PC
CY3120JR52 VHDL PC (Japanese)
CY3125R52 VHDL Workstation
CY3110R52 Verilog PC
CY3110JR52 V erilog PC (Japanese)
CY3115R52 Verilog Workstation
Warp3 for PC VHDL and V erilog Design T ool with Schematics and
VHDL Source Level Simulation CY3130R512
Cypress Synopsys Bolt-in Kit Bolt-In Design Kit for Synopsys Design Compiler CY3146
FLASH370i IS R Kit ISR Programming Kit for FLASH370i on PC CY3600i
Ultr a370 00 I SR Kit ISR Programming Kit for Ultra37000 on PC CY3700i
Warp2IS R for PC VHDL/Verilog Design T ool with ISR Programmer CY3620R52 VHDL
CY3620JR52 VHDL (Japanese)
CY3610R52 Verilog
CY3610JR52 V erilog (Japanese)
MAIN INDEX
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Non-Volatile Memories
•World’s f a stest PROMs
•4K to 256k density
•Industry-standard pinouts
•Lo w-power CMOS technology
•PDIP, PLCC, TSOP, CDIP, LCC packages
•Registered and x16 v ersions
•Direct replacement f or Bipolar PR OMs
CMOS PROMs
CMOS Registered PR OMs
Density Organization Pins
Count Package Part Number Access Time
tAA (ns) Feature
8K 1K x 8 24/28 J,P,D CY7C281A 25/30/45 300-mil D IP
16K 2K x 8 24/28 P, J ,S , W, D, Q , L CY7C291A/AL 20/25/35/50 300 -mi l DIP
16K 2K x 8 24 P, W CY7C292A/AL 20/25/35/50 600 -mi l DIP
16K 2K x 8 24/28 P, W, J CY7C293A/AL 20/25/35/50 P o wer-Down,300-mi l DIP
64K 8K x 8 24/28 P, J, W, D, L , Q CY7C261 20/25/35/45/55 P owe r-Down , 30 0-mil DIP
64K 8K x 8 24/28 J,P,W,D,L,Q CY7C263 20/25/35/45/55 300 -mi l DIP
64K 8K x 8 24 P, W CY7C264 20/25/35/45/55 600 -mil D IP
64K 8K x 8 28/32 P, J, W CY7C266 20/25/35/45 Power-Down
128K 16K x 8 28/32 P, W CY7C251 45/55/65 P owe r-Down, 300-mil DIP
256K 32K x 8 28/32 D,W,Q,L CY7C271 35/45/55 Po wer-Down, Military only
256K 32K x 8 28/32 PC,WC,JC CY7C271A 25/35/45/55 Powe r-Down, Com’l only
256K 16K x 16 44 JC CY7C276 25/30/35 16 Bi t W or d Wide
Density Organization Pins
Count Package Part Number Set-Up
tSA (ns) Clock-to-Out
tCO (ns)
4K 512 x 8 24/28 J,P,D,L CY7C225A 18/25/30/35/40 12/12/15/20/25
8K 1K x 8 24/28 J,P,D,L CY7C235A 18/25/30/40 12/12/15/20
16K 2K x 8 24/28 P,J , W, S ,D, Q , L CY7C245A/AL 15/25/35/45 10/12/12/15/25
64K 8K x 8 28 J,P,W,Q CY7C265 15/25/40/50 12/15/20/25
64K 8K x 8 28 J,P,W,Q CY7C269 15/25/40/50 12/15/20/25
256K 32K x 8 28/32 J,P,W CY7C277 30/40/50 15/20/25
45
55
4K 8K 64K
25
15
7C235A
7C281A
DENSITY
SPEED ns
7C225A
7C245A
7C291A
7C292A
7C293A
16K 128K
7C261
7C263
7C264
7C266
7C265
7C269
7C251
PROMS
35
65
256K
7C271
7C271A
7C274
7C277
7C276
Registered
MAIN INDEX
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24
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Timing Technology Products
Today’s hi gh-per f ormance dig ital de si gns often re quire mul tipl e timi ng s ignal s in order to control all the funct ions on the board. In the
past, this requir ed the desi gne r to use mu lti ple metal -can osc ill ators whi ch inc reased th e siz e and cos t of th e design. Cypress so lves
this problem by providing single-chip solutions that can synthesize multiple frequencies. The C ypress product line contains over 50
Frequency Timing Generator opti ons and consist s of f ive main fami li es of devi ces:
1. Motherboar d FTGs
2. EPROM Programma ble FTGs
3. Spread Spect rum FTGs
4. Zero Dela y Bu ff ers
5. Programmable Sk ew Buff ers (RoboCl ock®)
1. Mother board FTGs
Cypress offers an extensive family of motherboard frequency
ti ming gene rators f or PC designs . T he Cy pre ss offe ring i ncludes
products with 1–3 integrated PLLs and up t o 32 output signal s
to suppo rt sys tem, bus and peri pheral freque nci es on the moth-
erboard. Desktop and mobile applications are supported, as well
as various processor/chipset platforms. The Cypress mother-
board FTGs are designed for high accura cy, low EM I, and max-
imum output flexibility. Ther e are th ree main fami lies
CY227x: 66.6-MHz syste m b us designs
CY228x: 100-MHz system bus designs
CY221x: 133-MHz system bus designs
IO APIC Outp ut s
(16.67 or 33.3 MHz)
Motherboard Frequency Timing Generators
PCI Outputs
(33.3 MHz)
CPU Outputs
(66.6 or 1 00 M H z)
SDRAM Outputs
(2 DIMM s upport)
A GP O utputs
(66 MHz)
REF (14. 318 MHz)
14.318 MHz
USB
(48 MHz)
CY2287-1
I2C
CY227x Family: PC Motherboard Designs with 66.6-MHz System Bus
Part
Number Processor/
Platform Chipset CK
Designator #CPU
2.5/3.3V #PCI
3.3V #Ref
3.3V #SDRAM
3.3V #USB
3.3V #I/O
3.3V #APIC
2.5V Other Package
CY2273A-1
CY2273A-2
CY2273A-3
W48S87-04
P5, PII,
6x 86, K6/
Desktop
Intel 430TX,
440LX,
A LI IV/IV+
-- 4
4
4
4
7
5
7
7
1
1
1
1
12 (3 DIMM)
12 (3 DIMM)
12 (3 DIMM)
12 (3 DIMM)
1
1
1
1
--
--
--
1
--
--
1
1
--
2 AGP
--
--
48 SSOP
48 SSOP
48 SSOP
48 SSOP
CY2275A-12 P5, P6, PII/
Desktop I nte l 440LX CK3D 4 7 1 12 (3 D IMM) -- -- 2-- 48 SSOP
CY2276A-12
CY2276A-21
CY2276A-31
P5, PII, K6/
Desktop,
Server
I nte l 44 0L X CK4D 5
4
5
7
7
7
1
1
2
16 (4 DIMM)
16 (4 DIMM)
13 (3 DIMM)
--
1
2
--
1
--
3
2
2
--
--
--
56 SSOP
56 SSOP
56 SSOP
CY2277A-1
CY2277A-12
CY2277A-2
CY2277A-3
W48S87-72
P5, PII,
6x 86, K6/
Desktop,
Mobile
Intel 430TX CKDM66
CKDM66-M 4
4
4
4
4
7
7
7
7
7
2
2
2
2
2
8 (2 DIMM/4 SO-DIMM)
8 (2 DIMM/4 SO-DIMM)
8 (2 DIMM/4 SO-DIMM)
8 (2 DIMM/4 SO-DIMM)
8 (2 DIMM/4 SO-DIMM)
2 (USB or I/O)
2 (USB or I/O)
2 (USB or I/O)
2 (USB or I/O)
2 (USB or I/O)
1
1
1
1
1
--
--
--
--
--
48 SSOP
48 SSOP
48 SSOP
48 SSOP
48 SSOP
CY2278A-1L
CY2278A-2L
CY2278A-3L
CY2278A-4L
P5, PII/
Mobile Intel 430TX -- 7
7
7
7
10
10
10
10
2
2
2
2
--
--
--
--
2
2
2
2
1
1
1
1
--
--
--
--
8 MHz
8 MHz
8 MHz
8 MHz
48 TSSOP
48 TSSOP
48 TSSOP
48 TSSOP
CY2030 Peripheral Timing Si gnal
Generator CKIO --
-- --
-- 3
3--
-- 2
21
1--
-- 2 Audio
2 Audio 20 SSOP
20 SSOP
MAIN INDEX
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3URGXFW 6HOHFWRU *XLGH
25
Not e: Plea se contac t a Cyp ress R eprese nt ativ e for pro duct av ai lab ili ty.
CY228x Family: PC Motherboard Designs with 100-MHz System Bus
CY23xxANZ Family: 3.3V, 100-MHz SDRAM Buffer Devices (CY228x Companion Chips)
Part
Number Processor/
Platform Chipset CK
Designator #CPU
2.5V #PCI
3.3V #Ref
3.3V #SDRAM
3.3V #USB
3.3V #APIC
2.5V Other Package
CY2280-1
CY2280-11S
CY2280-21S
CY2280-31S
W48C101-01
W48S101-04
W130
W48S111-14
W164
W196
W144
W149
W150
PII/Desktop/
Server/
Workstation
Intel 440BX CK100 4
4
4
4
4
4
4
2
2
2
2
2
3
8
8
8
8
8
8
8
7
7
7
6
6
7
3
3
3
3
3
3
3
1
1
1
2
2
2
--
--
--
--
--
--
--
--
--
--
13
13
17
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
2
Spread
Spectrum
except
CY2280-1
48 SSOP
48 SSOP
48 SSOP
48 SSOP
48 SSOP
48 SSOP
48 SSOP
28 SOIC
28 SOIC
48 SSOP
48 SSOP
48 SSOP
56 SSOP
W214
W199
W211B
W216
PII/Desktop Intel 440BX/
VIA Pro-133/
VIA ProMedia
2
2
2
3
7
6
6
7
1
2
2
2
--
13
13
17
2
2
2
2
1
1
1
2
28 SOIC
48 SSOP
48 SSOP
56 SSOP
W48C111-16
W48C111-17 PII/Mobile Intel 440BX CK100-M 2
26
61
1--
-- 1
1--
-- 28 SOIC
28 SOIC
W127
W156
W156C
PII, 6x86, K6/
Desktop ALI V, VIA MVP3
VIA MVP4 -- 4
4
4
6
6
6
1
2
2
12 (3 DIMM)
13 (3 DIMM)
13 (3 DIMM)
2
2
2
--
--
--
2 AGP
(95 MHz f or K6 -3)
( 97 MHz for
K6-2+)
48 SSOP
48 SSOP
48 SSOP
CY2285-1
CY2285-2
CY2285-3
W137
W237
PII/Mobile Intel 440BX, 440MX CK100-SM
--
CK100-SM
Single chip
2
2
2
2
2
6
7
6
6
7
2
2
1
2
3
--
--
--
--
8
1
1
1
1
--
--
--
--
--
1 USB/IO,
Spread
Spectrum
28 SSOP
28 SSOP
28 SSOP
28 SSOP
48 SSOP
CY2287-1
W147G
W195B
Celeron/
Desktop
(Basic PC)
Intel Whitney CK-WH 3
3
2
8
8
8
1
1
1
9
9
9
2
2
3
2
2
1
2 AGP,
Spread
Spectrum
56 SSOP
56 SSOP
48 SSOP
Part
Number Description CK
Designator # SDRAM clock s
3.3V Other Package
CY2310ANZ-1
W40S11-02 2 DIMM or 4 SO-DIMM Buff er CKBF-M 10 I2C28 SSOP
W40S11-23 3 DIMM Buffer CKBF / -M 13 I2C28 SOIC
W40S11-03 3 DIMM Buffer CKBF / -M 14 I2C28 SOIC
CY2318ANZ-11
W40S01-04 4 DIMM Buffer CKBF 18 I2C48 SSOP
MAIN INDEX
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CY221x Family: PC Motherboard Designs with 133-MHz System Bus
Part
Number Processor/
Platform Chipset CK
Designator #CPU
2.5/3.3V #PCI
3.3V #Ref
3.3V #USB
3.3V #AGP
3.3V #APIC
2.5V Other Comments Package
CY2210-3
W133
CY2210-2
W158
Katmai/Desktop
Xeon/Server
Camino
Carmel
CK133
CK133-W
4
4
4
4
8
8
8
8
2
2
2
2
1
1
1
1
4
4
4
4
3
3
3
3
2 CP U/2
2 CP U/2
2 CP U/2
2 CP U/2 150 ps jitter
150 ps jitter
56 SSOP
56 SSOP
56 SSOP
56 SSOP
W134M
W134S Katmai/Desktop,
Mobile Camino DRCG+
DRCG III --
-- --
-- --
-- --
-- --
-- --
-- Differential
Outputs Direct Ra mbus
Memory Clock 24 SSOP
24 SSOP
CY2215-1
W161 Katmai/Desktop Camino CK133 3
310
10 2
21
13
31
11 CP U/2 48-pin CY2210 48 SSOP
48 SSOP
W167B Katmai/Desktop Camino CK133 310 1 2 3 3 1 CPU/2
I2C48-pin CY2210
w/ over-clocking 48 SSOP
W159 Xeon/Server Carmel CK133-WS 7 2 2 1 4 7 2 CPU/2 Support up to 6
CPU 56 SSOP
W208D
W209C Celeron/Desktop Whitney/
810E CK-810E 3
28
81
12
32
22
19 SDRAM
outputs W208B-Intel Spec
W209C-w/ over-
clocking
56 SSOP
48 SSOP
W218
W219B Celeron/Desktop Solano/
815
2-DIMM
CK-Solano
2-DIMM 3
27
81
12
33
32
19 SDRAM
outputs W218-Intel Spec.
W219-w/ over -
clocking
56 SSOP
48 SSOP
W228B
W229B Celeron/Desktop Solano/
815
3-DIMM
CK-Solano
3-DIMM 2
22
81
12
33
31
113 SDRAM
outputs W228-Intel Spec.
W229-w/ over -
clocking
56 SSOP
56 SSOP
W207B Celeron/Desktop SiS630/
540 -- 3 7 2 2 -- -- 14 SDRAM 4 8 SSOP
CY22K7-1
W210 AMD K7/
Desktop AMD 750
VIA KX133 -- 3
38
62
21
22
-- --
-- 1 USB/IO
13 SDRAM AMD K7
chipsets 48 SSOP
48 SSOP
W212 Katmai/Desktop ALI 1641 -- 2 6 2 1 2 1 13 SDRAM
outputs 48 SSOP
MAIN INDEX
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2. General Purpose EPROM Programmable FTGs
Cypress offers a selection of factory EPROM programmable
(OTP) Frequency Timing Generators for general pur pose appli-
cations such as modems, datacom, networking products, CD-
ROMs, DVD, hard disk drives, and more. Cypress EPROM-
programmable timing products are “customized” for each appli-
cati on and the output fr equencies are progr ammed at the f actory
using EPROM technology. Cypres s is t he only manufact urer of f er-
ing EPROM-programmability, allowing sample delivery of custom
frequency products within days rather than the weeks or months
requi red b y older t echnologies . The Cypress product mix includes
both si ngle and three PLL des ign s with one to ei ght outpu ts an d
signal frequencies up to 130 MHz. The number of unique fre-
quencies possible depends on the number of PLLs in the FTG.
The following table summar izes our offering:
General Purpose EPR OM Pr ogrammab le FTGs
Each user defi ned/
select able
(76.9 kHz- 100 MHz)
Reference In
(User defined)
CPU Output (user defined)
REF
CY2292
S2-S0
(select inputs)
Part
Number #
PLLs #
Outputs Des c ription of
Outputs In put frequency
Range Output frequency
Range VDD Package Temp
CY2907 1 2 Interdependent 2 MHz–32 MHz 2 MHz–13 0 MHz (5V)
2 MH z–90 MHz (3.3V) 5V/3.3V 14 SOIC or
8 SOIC Commercial
CY2907F8 1 2 Interdependent 2 MHz–32 MHz 2 MH z–13 0 MH z (5 V)
2 MH z–90 MHz (3.3V) 5V/3.3V 8 SOIC Field
Programmable
CY2907F14 1 2 Interdependent 2 MHz–32 MHz 2 MHz–13 0 MH z (5 V)
2 MH z–90 MHz (3.3V) 5V/3.3V 14 SOIC Field
Programmable
CY2071A 1 3 Interdependent 10–25 MHz (Cr ystal)
1–32 MHz (TTL/Osc) 500 kHz–130 MHz (5 V)
500 kHz–100 MHz (3 .3 V ) 5V/3.3V 8 SOIC Commercial
CY2071AF 1 3 Interdependent 10–25 MHz (Crystal)
1–32 MHz (TTL/Osc 500 kHz –130 MHz (5 V)
500 kHz–100 MHz (3 .3 V ) 5V/3.3V 8 SOIC Field
Programmable
CY2081 3 3 Independent 10–25 MHz (Crystal)
1–30 MHz (TTL/Osc) 500 kHz–100 MHz (5 V)
500 kHz–80 MHz (3.3V) 5V/3.3V 8 SOIC Commercial
CY2291 3 8 1 Ref, 32 kHz, 1 CPU,
5 Int erdepende n t 10–25 MHz (Cr ystal)
1–30 MHz (TTL/Osc) 76.9 kHz–100 MH z (5V )
76.9 kHz–80 MHz (3.3V) 5V/3.3V 20 SOIC Commercial
CY2292 3 6 1 R ef, 1 CPU,
4 Int erdepende n t 10–25 MHz (Cr ystal)
1–30 MHz (TTL/Osc) 76.9 kHz–100 MH z (5V )
76.9 kHz–80 MHz (3.3V) 5V/3.3V 16 SOIC Commercial
CY2291I 3 8 1 Ref , 32 kHz, 1 CPU,
5 Int erdepende n t 10–25 MHz (Cr ystal)
1–30 MHz (TTL/Osc) 76.9 kHz–80 MHz (5V)
76.9 kHz–66.6 MHz (3.3V) 5V/3.3V 20 SOIC Industrial
CY2292I 3 6 1 Ref, 1 CPU,
4 Int erdepende n t 10–25 MHz (Cr ystal)
1–30 MHz (TTL/Osc) 76.9 kHz–80 MHz (5V)
76.9 kHz–66.6 MHz (3.3V) 5V/3.3V 16 SOIC Industrial
CY2291F 3 8 1 Ref , 32 kHz, 1 CPU,
5 Int erdepende n t 10–25 MHz (Cr ystal)
1–30 MHz (TTL/Osc) 76.9 kHz–80 MHz (5V)
76.9 kHz–66.6 MHz (3.3V) 5V/3.3V 20 SOIC Commercial
Fi el d Pr og .
CY2292F 3 6 1 Ref, 1 CPU,
4 Int erdepende n t 10–25 MHz (Cr ystal)
1–30 MHz (TTL/Osc) 76.9 kHz–80 MHz (5V)
76.9 kHz–66.6 MHz (3.3V) 5V/3.3V 16 SOIC Commercial
Fi el d Pr og .
Application-Specific FTGs
Application Part Number Description
Communications CY25100 155.52-MHz ATM FTG
Multimedia CY2 419x Set Top Box FTG
CY2439x Set Top Box FTG
Video/LCD FTG TBD TBD
MAIN INDEX
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3. Spread Spectrum FTGs (PREMIS™)
Cypress offers a selection of Spre ad Spectrum Frequency Tim-
ing Generators for general-purpose applications such as print -
ers , fa x, LCD displ ays, set- top box es, games, copiers , and more.
Cypress W18x products are standard devices that, in concept,
inject the Spread Spectr um feature onto a clocking signal. The
resulting time-variable frequency output is nominally equal in
frequency to the reference signal. Additional devices available
provide some frequency multiplication capability in addition to
providing the benefits of Spr ead Spectrum Timing.
Cypress Spread Spectrum Timing solutions provide the maxi-
mum EMI reduction on the market; two trademark terms
(PREMIS™ and Spread Aware™) are further evidence of our
leadership in this m arket.
PREMIS pr o duc ts
Extra outputs avail-
able on W184/5
Reference In
(8-75 MHz)
Spread Output
W18x
(select inputs)
Pa rt N u mb er Input Freq ue ncy Output
Frequency Modulation
width Spread Disable # of outputs
spread/nonspread Vdd Package
W180-01 8–28 MH z Input x1 –1.25/–3.75% No 1/0 3.3/5.0 8 SO IC
W180-02 8–15 MH z Input x1 –1.25/–3.75% Ye s 1/0 3.3/5.0 8 S O IC
W180-03 15–28 MHz Input x1 –1.25/–3.75% Ye s 1/0 3.3/5.0 8 S O IC
W181-01 28–75 MHz Input x1 –1.25/–3.75% No 1/0 3.3/5.0 8 SOIC
W181-02 28–48 MHz Input x1 –1.25/–3.75% Ye s 1/0 3.3/5.0 8 S O IC
W181-03 46–75 MHz Input x1 –1.25/–3.75% Ye s 1/0 3.3/5.0 8 S O IC
W182 8–28 MH z Input x1 –1.25/–3.75% Yes 1/1 (REF) 3.3/5.0 14 SOIC
W183 28–75 MHz Input x1 –1.25/–3.75% Yes 1/1 (REF) 3.3/5.0 14 SOIC
W184 8–28 MH z Input x1 –1.25/–3.75% Yes 6/1 (REF) 3.3/5.0 24 SSOP
W185 28–75 MHz Input x1 –1.25/–3.75% Yes 6/1 (REF) 3.3/5.0 24 SSOP
W42C31-03 10–33 MHz Input x1 ±1.0/±1.875/
–2.0% Ye s 1/0 5.0 8 SOIC
W42C31-04 20–30 MHz Input x2.3 ±0.625/
±1.875% Ye s 1/0 5.0 8 SOIC
W42C31-06 14–20 MHz Input x3 ±0.75/±1.25% Yes 1/0 5.0 8 SOIC
W42C31-09 30–50 MHz Input x1 ±0.625/±1.25/
±2.5/–3.75% Yes 1/0 3.3/5.0 8 SOIC
W155 14.31818 MHz Selectable –1.25/–3.75% Ye s 1/1 ( US B) 3.3/5.0 16 SOIC
W166 50–65 MHz Input x1 ±0.625/±1.25/
±2.5/–3.75% Yes 1/0 3.3/5.0 8 SOIC
W42C32-05M 11–26 MHz Selectable ±1.5/±2.5% Ye s 1/1 (REF) 3.3 16 SOIC
MAIN INDEX
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4. Buffers: Zero Delay and St andard
Cypress Zero Delay Buffers accept a 5V or 3.3V timing signal
input and provide multiple 3.3V outputs with low skew and zero
delay between input and outputs. These FTGs are ideal for ap-
plications such as PCI buffering and SDRAM buffering, as well
as high-end datacom and network clocking (Gigabit Ethernet,
ATM, etc.). The standard family consists of four base devices:
W194-70, CY2305, CY2308, and CY2309, which provide 2, 5,
8, and 9 outputs and s upport u p to 130-M Hz fr equenc ies . Wit hin
each CY base device there are several options or “dash-num-
bers” provid ing a total of nine se parate de vices. Output s are split
into two banks (Bank A and B) with i ndividual power-down op-
tions. A feedback loop (external or internal) provides the addi-
tional option of frequency multiplication or division of the input
signal on each bank.
A new and import ant consideration for zero delay buffe rs arises
from the introduction and growing pervasiveness of an EMC
techn ique call ed Spread Spect rum Timi ng. In desi gns where th e
main timing signal is coming from off the board, it will is vital to
design the board so that it is Spread Aware. If the board is not
desi gned to be Sprea d A w are, then it will be f ou nd that it wi ll not
wor k properly with companion products that use Spread Spec-
trum Timing for EMI reduction. Systems which generate the main
system signal t hemselves are al so well served by using Spread
A ware Zero Dela y Buff ers. B y doing so, they leave open the op-
tion of m oving to Spread Spectrum timing to help solve EMI is-
sues at so me poi nt i n the fu ture p erhaps wit hout r ela yi ng out the
board. System s that are a lready usi ng Spre ad Spe ctrum Timi ng
will fi nd Spre ad Awa re Zero Dela y B uff er s not o nly al low t hem t o
maintain synchronization, but they also spread the peak EMI
reduction benefit of the main signal to the entire system.
Zer o Delay Buff ers
BANK A Outputs
Fout = 1 x Input
REFIN
Feedback
CY2308-2 BANK B Outputs
Fout = 1/2 x Inpu t
FBK
Part # # of
Outputs Feedback
Type Supply Voltage Package Multiplication
Ability Output
En a ble Spread Aware
W132-09B 10 ext. 3.3V 24 TSSOP No Yes (2) Yes
W132-10B 11 ext. 3.3V 24 TSSOP No Yes (1) Yes
CY 2308-1, 1H 8 ex t . 3.3V 16 SOIC No Yes (2) No
W152-1, 11 8 ext. 3.3V 16 SOIC No Yes (2) Yes
CY 2308-2, 2H 8 ex t. 3.3V 16 SOIC /2, x1, 2 Yes (2) No
W152-2, 12 8 ext. 3.3V 16 SOIC /2, x1, 2 Yes (2) Yes
CY2308-3 8 ext. 3 .3V 16 SOIC x1, 2, 4 Yes (2) No
W152-3 8 ext. 3 .3V 16 SOIC x1, 2, 4 Ye s (2) Yes
CY2308-4 8 ext. 3.3V 16 SOIC x2 Yes (2) No
W152-4 8 ext. 3.3V 16 SOIC x2 Yes (2) Yes
CY2309, -1H 9 int. 3.3V 16 SOIC No No No
W162-09, -19 9 int. 3.3V 16 SOIC No No Yes
CY2305, -1H 5 int. 3.3V 8 SOIC No Yes (2) No
W163-05, -15 5 int. 3.3V 8 SOIC No Yes (2) Yes
W170-01 2 ext. 3.3 or 5.5V 8 SOIC /2, x1, 2, 4, 8, 16 No Yes
W194-70 2 ext. 3.3 or 5.5V 8 SOIC /2, x1, 2, 4, 8, 16 No No
Part # # of
Ou tputs Supply Voltage Package Output
Enable I2C Con t rol
W40S01-04
CY2318ANZ 18 3.3V 48 SSOP Yes Yes
W40S11-02
CY2310ANZ 10 3.3V 28 SSOP Yes Yes
W40S11-03
CY2314ANZ 14 3.3V 28 SOIC No Yes
W40S11-23
CY2313ANZ 13 3.3V 28 SOIC No Yes
W191 6 3. 3V 16 SSOP No Yes
CY2309NZ 9 3.3V 16 SOIC No No
MAIN INDEX
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5. Programmable Skew/Zero Delay Ro boClock® Family
Cypress Programmable Skew Clock Buffers offer user-select-
able skew control over clock functions. These multiple-output
cloc k driv ers provi de the sy stem integr ator with func tions neces-
sary to optimize the timing of high-performance computer and
network systems. The RoboC lock® family offers:
RoboClock I
5 & 3.3 Volts
8 outputs
3.75–110 MHz
All output pair skew <100 ps typi cal
Zero input to output delay
50% dut y cycle
Low operati ng current
Selectable skew up to 18 ns
Inverter and non-inverted outputs
Operation at 1/2 and 1/ 4 the i nput frequency
Operations at 2x and 4x the input frequen cy
RoboClock II
Dual-Di fferential (or single-ended) inputs
Hot Insertion Capable
3.3 Volts
18 Outputs
12–185 MHz
Zero input to output delay
50% duty cycle
Low operating cur rent
Selectable skew up to 10 ns
Inverter and non-inverted outpu ts
Operation at 1/1–6, 1/8, 1/10, and 1/12 the input frequen cy
Operations at 1–6x, 8x, 10x, and 12x the input frequency
RoboClock Family
CLKIN
Feedback
RoboClock
FBK
RoboClo c k II Fa mil y
CLKIN1
Feedback
RoboClock II
FBK
CLKIN2
MAIN INDEX
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RoboClock Family
Device V#
Outputs Output
Operation Multiplication Division Programmable
Skew Package Tpd
(ps) Tskew
(ps)
CY7B991V-2JC
(TTL) 3.3 83.75–80 MHz 1x, 2x, 4x /2, /4 YES 32 PLCC 250 750
CY7B991V-5JC
(TTL) 3.3 83.75–80 MHz 1x, 2x, 4x /2, /4 YES 32 PLCC 500 750
CY7B991V-5JI
(TTL) 3.3 83.75–80 MHz 1x, 2x, 4x /2, /4 YES 32 PLCC 500 750
CY7B991V-7JC
(TTL) 3.3 83.75–80 MHz 1x, 2x, 4x /2, /4 YES 32 PLCC 700 750
CY7B991-2JC
(TTL) 5 8 3.75–80 M H z 1x, 2x, 4x /2, /4 YES 32 PLCC 250 750
CY7B991-5JC
(TTL) 5 8 3.75–80 M H z 1x, 2x, 4x /2, /4 YES 32 PLCC 500 750
CY7B991-5JI
(TTL) 5 8 3.75–80 M H z 1x, 2x, 4x /2, /4 YES 32 PLCC 500 750
CY7B991-7JC
(TTL) 5 8 3.75–80 M H z 1x, 2x, 4x /2, /4 YES 32 PLCC 700 750
CY7B992-2JC
(CMOS) 5 8 3.75–80 MHz 1x, 2x, 4x /2, /4 YES 32 PLCC 250 750
CY7B992-5JC
(CMOS) 5 8 3.75–80 MHz 1x, 2x, 4x /2, /4 YES 32 PLCC 500 750
CY7B992-5JI
(CMOS) 5 8 3.75–80 MHz 1x, 2x, 4x /2, /4 YES 32 PLCC 500 750
CY7B992-7JC
(CMOS) 5 8 3.75–80 MHz 1x, 2x, 4x /2, /4 YES 32 PLCC 700 750
CY7B9911-5JC
(TTL) 5 8 3.75–100 M H z 1x, 2x, 4x /2, /4 YES 32 PLCC 500 750
CY7B9911-7JC
(TTL) 5 8 3.75–100 M H z 1x, 2x, 4x /2, /4 YES 32 PLCC 700 750
CY7B9910/20-2SC
(TTL/CMOS) 5 8 3.75–80 M H z N/A N/A NO 24 SOIC 250 750
CY7B9910/20-5SC
(TTL/CMOS) 5 8 3.75–80 M H z N/A N/A NO 24 SOIC 500 750
CY7B9910/20-7SC
(TTL/CMOS) 5 8 3.75–80 M H z N/A N/A NO 24 SOIC 700 750
CY7B9911V-5JC
(LVTTL/TTL) 3.3 83.75–110 MHz 1x, 2x, 4x /2, /4 YES 32 PLCC 500 750
CY7B9911V-7JC
(LVTTL/TTL) 3.3 83.75–110 MHz 1x, 2x, 4x /2, /4 YES 32 PLCC 700 750
CY7B993V-5AC
(LVTTL/TTL) 3.3 18 12–100 MHz 1–6x,8x,10x,12x /1–6,/8,/10,/12 YES 100 TQFP 500 625
CY7B993V-5AI
(LVTTL/TTL) 3.3 612–100 MHz 1–6x,8x,10x,12x /1–6,/8,/10,/12 YES 100 TQFP 500 625
CY7B993V-7AC
(LVTTL/TTL) 3.3 18 12–100 MHz 1–6x,8x,10x,12x /1–6,/8,/10,/12 YES 100 TQFP 700 625
CY7B994V-5AC
(LVTTL/TTL) 3.3 18 24–185 MHz 1–6x,8x,10x,12x /1–6,/8,/10,/12 YES 100 TQFP 500 625
CY7B994V-5AI
(LVTTL/TTL) 3.3 624–185 MHz 1–6x,8x,10x,12x /1–6,/8,/10,/12 YES 100 TQFP 500 625
CY7B994V-7AC
(LVTTL/TTL) 3.3 18 24–185 MHz 1–6x,8x,10x,12x /1–6,/8,/10,/12 YES 100 TQFP 700 625
MAIN INDEX
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Wireless RF Products
Dual-PLL Frequency Synthesi zers
* 2nd s o ur c e to Nation al ’s PLLatinum Series Dual-P LL LMX233Xs .
Single-PLL Frequency Synthesizers
* 2nd s o ur c e to Nation al ’s PLLatinum Series Single-PLL LMX232Xs.
P art Number Cr o ss Ref.* PLL1 Frequency
(GHz) Prescaler
Divide Ratio PLL2 Frequency
(GHz) Prescaler
Divide Ratio ICP
(mA) ICC
(mA) VCC
(V) Package Sample
Avail.
CYW2336ZI
WB1356X LMX2336 2.0 GHz 64/65
128/129 1.1 GHz 64/65
128/129 1/3.8 8 2.7
5.5 TSSOP 20 Now
CYW2330ZI
WB1330X LMX2330 2.5 GHz 32/33
64/65 600 MHz 8/9
16/17 1/3.8 8 2.7
5.5 TSSOP 20 Now
CYW3335ZI
WB1315X Sol e Sou r c e 2.5 GHz 32 /33
64/65 2.5 GHz 32/33
64/65 1/3.8 10 2.7
5.5 TSSOP 20 Now
CYW2331ZI
WB1331X LMX 2331 2.0 GHz 64/ 65
128/129 600 MHz 8/9
16/17 1/3.8 6 2.7
5.5 TSSOP 20 Q1’00
CYW2332ZI
WB1332X LMX 2332 1.2 GHz 64/ 65
128/129 600 MHz 8/9
16/17 1/3.8 5 2.7
5.5 TSSOP 20 Q1’00
P art Number Cross Ref.* PLL1 Frequency
(GHz) Prescaler Di vide
Ratio ICP
(mA) ICC
(mA) VCC
(V) Package Sample
Avail.
CYW2315ZI
WB1215X LMX2315 1.2 GHz 64/ 65
128/129 332.7
5.5 TSSOP 20 Now
CYW2320ZI
WB1220X LMX2320 2.0 GHz 64/ 65
128/129 352.7
5.5 TSSOP 20 Now
CYW2325ZI
WB1225X LMX2325 2.5 GHz 32/ 33
64/65 372.7
5.5 TSSOP 20 Now
MAIN INDEX
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USB Microcontroller Family
Cypres s of f ers the i ndustry's br oades t line of USB microco ntr olle rs, as well as a ful l set of de v e lopment t ools , supporting cos t-dr i ven
applications such as keyboards and mice, as well as high-perf ormance applications like printers, scanners, xDSL modems, and digital
cam eras . Cypre ss ha s a wide r ange of solut ions for Lo w-Speed USB App licat ions ( up to 1. 5 Mbits /s si gnali ng rat e), Ful l-Spe ed USB
Appli cati ons (up 12 Mbi ts/s ), and USB Hub App licat ions . Two unique m icroco ntrol ler archi tect ures ha v e be en de v el oped by Cypr ess
that will give peri pheral developers the freedom and fl exibility to choose the solution that best fits their needs.
Take our highly flexible family of custom 8- bit RISC microcontrollers (M8 Series) t hat have been optimized from the ground up fo r
USB appli ca tions. Human Interf ace De vice (HID) appli cat ion s such as mice, ke yboar ds, and jo ysti cks can ta ke adv antage of thi s c ost-
effective, EPROM based product fa mily. But because they ar e fully programmable, the M8 Series is also suited for special purpose
control and other low data rate appli cations .
Cypress's EZ-U SB family of full-speed USB microcontr ollers feature an enhanced 8051 core running at 24 MHz, and a RAM-based
architecture, enab ling the download of firmware from the host PC. The EZ-USB family supports high-bandwidth application s by
providing the maximum nu mb er of endpoints allowed by t he USB specificati on, as well as an efficient mechanism to move data on
or off chip. For da ta intensive applicati ons like modems, scanners, printers , and cameras, the EZ-USB f am il y is th e premier solution.
Cypress also off ers a full line of USB hub solutions. Based on the highly optimized M8 architecture, Cypress's USB hub family includes
4-port and 7-port standalone hub solut ions, as well as integr ated 4-port hub solutions, al lowing designers to implement a full-speed
USB peripher al and 4-port hub usi ng a single chip.
All Cypress USB family members are supported by one of our comprehensive Development Kits. These kits are the fast track to
developing firmware and dri ver software for USB peripherals. Examples com plete with source code are i ncluded to provide the
designer with fast time to mark et.
Cypress M8 Series USB Micro controllers
•Industry’s smallest 8-bi t RISC microcont roll er cor e
•Integrated 128/256 bytes SRAM
•Inte grat ed 2/4/6/8 Kb ytes EPR OM
•Optimi z ed USB ins truction set (34 in structions)
•10–40 Gener a l Purpose I/Os
•USB 1.1 Compliant
EZ-USB Series USB Microcontrollers
•High-Performance I/O port
•RAM Archite cture - 4/8 Kbyte s
•Enhanced 8051 Core
•Pin and Software Compatible Family
• I2C Cont roller
•USB 1.1 Compliant
Low-Speed US B Mic roco ntroll ers
Full-Speed USB Microco ntr o llers
Part Number Core Endpoints RAM (Bytes) EPROM (KB) #I/Os Package
CY7C63000A M8 2128 2 12 20-pin PDIP/SOIC
CY7C63001A M8 2128 4 12 20-pin PDIP/SOIC
CY7C63100A M8 2128 2 16 24-pin SOIC
CY7C63101A M8 2128 4 16 24-pin QSOP/SOIC
CY7C63411 M8 3256 432 40-pin PDIP, 48-pin SSOP
CY7C63412 M8 3256 632 40-pin PDIP, 48-pin SSOP
CY7C63413 M8 3256 832 40-pin PDIP, 48-pin SSOP
CY7C63511 M8 3256 440 48-pin SSOP
CY7C63512 M8 3256 640 48-pin SSOP
CY7C63513 M8 3256 840 48-pin SSOP
CY7C63612 M8 3256 616 28-pin SOIC
CY7C63613 M8 3256 816 28-pin SOIC
Part Number Core RAM Size EPROM Size Isochronous
Support Package
AN2121SC Enhanced 8051 4 Kbyte N/A Yes 44-pin PQFP
AN2125SC Enhanced 8051 4 Kbyte N/A Yes 44-pin PQFP
AN2126SC Enhanced 8051 4 Kbyte N/A No 44-pin PQFP
AN2131SC Enhanced 8051 8 Kbyte N/A Yes 44 pin PQFP
AN2135SC Enhanced 8051 8 Kbyte N/A Yes 44 pin PQFP
AN2136SC Enhanced 8051 8 Kbyte N/A No 44-pin PQFP
AN2131QC Enhanced 8051 8 Kbyte N/A Yes 80-pin PQFP
CY7C64013 M8 256 bytes 8 Kbytes No 28-pin PDIP/SOIC
CY7C64113 M8 256 bytes 8 Kbytes No 48-pin SSOP
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USB Hub and Integrated Hub Solu tions
USB Developmen t Tools
USB Progr a mming Tools
Part Number Core EPROM Size # Hub Ports Full-Speed Peripheral Package
CY7C65013 M8 8 Kbytes 7No 48-pin SSOP
CY7C65113 M8 8 Kbytes 4No 28-pin SOIC
CY7C66013 M8 8 Kbytes 4Yes 48-pin PDIP/SSOP
CY7C66113 M8 8 Kbytes 4Yes 56-pin SSOP
Part Number Description CY Parts Supported
CY3650 Low-Speed, Low I/O Emulator Board (1.5 Mbps) CY7C630xxA, CY7C631xxA
CY3651 Low-Speed, High and Low I/O Emulator Board (1.5 Mbps) CY7C634xx, CY7C635xx, CY7C636xx
CY3652C Full-Speed Emulator Board CY7C640/1xx, CY7C65xxx, CY7C66xxx
CY3660R100-CC C-Compiler (Windows Version) Cypress M8 Series (CY7C6xxxx)
CY3661R100-CC C-Compiler (DOS V ersion) Cypress M8 Series (CY7C6xxxx)
AN2131-DK001 EZ-USB Development EZ-USB Series (AN21xx)
Device Part Number Package Needed For Programming
Hi-Lo Programmer[2] Adapter Matrix Card
CY7C63000A-PC PDIP CY3649-xxxV Not Needed Not Needed
CY7C63000A-SC SOIC CY3649-xxxV See Note 3 Not Needed
CY7C63001A-PC PDIP CY3649-xxxV Not Needed Not Needed
CY7C63001A-SC SOIC CY3649-xxxV See Note 3 Not Needed
CY7C63100A-SC SOIC CY3649-xxxV See Note 3 Not Needed
CY7C63101A-SC SOIC CY3649-xxxV See Note 3 Not Needed
CY7C63101A-QC QSOP CY3649-xxxV See Note 4 Not Needed
CY7C63411-PC PDIP CY3649-xxxV CY3083-DP48 CY3083-01
CY7C63411-PVC SSOP CY3649-xxxV CY3083-SS56 CY3083-01
CY7C63412-PC PDIP CY3649-xxxV CY3083-DP48 CY3083-01
CY7C63412-PVC SSOP CY3649-xxxV CY3083-SS56 CY3083-01
CY7C63413-PC PDIP CY3649-xxxV CY3083-DP48 CY3083-01
CY7C63413-PVC SSOP CY3649-xxxV CY3083-SS56 CY3083-01
CY7C63511-PVC SSOP CY3649-xxxV CY3083-SS56 CY3083-01
CY7C63512-PVC SSOP CY3649-xxxV CY3083-SS56 CY3083-01
CY7C63513-PVC SSOP CY3649-xxxV CY3083-SS56 CY3083-01
CY7C63612-SC SOIC CY3649-xxxV CY3083-SC28 CY3083-06
CY7C63613-SC SOIC CY3649-xxxV CY3083-SC28 CY3083-06
CY7C64013-PC PDIP CY3649-xxxV CY3083-DP48 CY3083-02
CY7C64013-SC SOIC CY3649-xxxV CY3083-SC28 CY3083-02
CY7C64113-PVC SSOP CY3649-xxxV CY3083-SS56 CY3083-03
CY7C65013-PVC SSOP CY3649-xxxV CY3083-SS56 CY3083-03
CY7C65113-SC SOIC CY3649-xxxV CY3083-SC28 CY3083-04
CY7C66013-PC PDIP CY3649-xxxV CY3083-DP48 CY3083-04
CY7C66013-PVC SSOP CY3649-xxxV CY3083-SS56 CY3083-04
CY7C66113-PVC SSOP CY3649-xxxV CY3083-SS56 CY3083-05
Notes:
2. The Hi-Lo programmer can be ordered for 110V support (CY3649-110V) or 220V support (CY3649-220V).
3. An SOIC-to- DIP flow -thr ough adapter (p/n AS -28-2 8-03S-6-GANG) is a vailable from Emulat ion Technologies (www.emulation.com ).
You can contact Emulation Technologies by calling 1-800-ADAPTER.
4. A QSOP-to-DIP flow-through adapter (p/n 130-5304-06) is available from Emulation Technologies (www.emulation.com). You can
contact Emulation Technologies by calling 1-800-ADAPTER.
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Notes:
Military temperature range (–55°C to +125°C) product processed to MIL-STD-883 Revision C is also available for most products. Speed and power
selections may vary from those above. Contact your local sales office for more information.
Commercial grade product is available in plastic, CerDIP, or LCC. Military grade product is available in CerDIP, LCC, or PGA.
Power supplies for most product lines are VCC = 5V ± 1 0% .
22S, 24S, 28S stands for 300 mil. 22-pin, 24-pin, 28-pin, respectively. 28.4 stands for 28-pin 400 mil, 24.4 stands for 24-pin 400 mil.
PLCC, SOJ, and SOIC packages are available on some products.
F, K, and T packages are special order only.
Please contact a Cypress representative for product availability.
Package Code:
A = Thin Quad Flat Pack (TQFP)
AS=Small Thin Quad Plastic Flatpack (STQFP)
B=Plastic Pin Gri d Array
BA=Fine Pitch Ball Grid Array
D=CerDIP
E=Tape Automate d Bond (TAB)
F=Flatpack
FJ=Ceramic SOJ
G=Pin Grid Array (PGA)
H=Windowed Hermetic LCC
J=PLCC
K=Cerpack
L=Leadless Chip Carrier (LCC)
N=Plastic Quad Flatpack
P=Plastic
Q=Windowed LCC
Q=QSOP
R=Windowed PGA
S=SOIC
T= Wi ndowed C er pack
U=Ceramic Quad Flatpack
V=SOJ
W =Wi nd owe d C erd ip
X=DICE
Y=Ceramic LCC
Z=Thin Shrunk Outline Package (TSOP)
ZA=Small Thin S hrunk Outline Pack age (STSOP)
ZR=Reverse TSOP
HD=Hermetic DIP (Module)
HG= Ceramic PGA (Modul e)
PA=TSSOP
PD=Plastic DIP (Module)
PM=Plastic SIMM
PN=Plastic Angled SIMM
PS=Plas tic SIP
PV=SSOP
PZ=Plastic ZIP
SO=SOIC
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