VOUT
SSRESRT
COMP
FB
RAMP
PGND
CSG
CS
LO
SW
HO
HB
VCCVIN
AGND
UVLO
VCCDIS
DEMB
CM
VIN
VOUT
SW
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LM25117/Q1 Wide Input Range Synchronous Buck Controller With Analog Current
Monitor
1 Features 3 Description
The LM25117 is a synchronous buck controller
1 LM25117-Q1 is Qualified for Automotive intended for step-down regulator applications from a
Applications high voltage or widely varying input supply. The
AEC-Q100 Qualified With the Following Results: control method is based upon current mode control
Device Temperature Grade 1: -40°C to 125°C utilizing an emulated current ramp. Current mode
control provides inherent line feed-forward, cycle-by-
Ambient Operating Temperature Range cycle current limiting and ease of loop compensation.
Emulated Peak Current Mode Control The use of an emulated control ramp reduces noise
Wide Operating Range from 4.5 V to 42 V sensitivity of the pulse-width modulation circuit,
Robust 3.3 A Peak Gate Drives allowing reliable control of very small duty cycles
necessary in high input voltage applications.
Adaptive Dead-time Output Driver Control
Free-run or Synchronizable Clock up to 750 kHz The operating frequency is programmable from 50
kHz to 750 kHz. The LM25117 drives external high-
Optional Diode Emulation Mode side and low-side NMOS power switches with
Programmable Output from 0.8 V adaptive dead-time control. A user-selectable diode
Precision 1.5% Voltage Reference emulation mode enables discontinuous mode
operation for improved efficiency at light load
Analog Current Monitor conditions. A high voltage bias regulator that allows
Programmable Current Limit external bias supply further improves efficiency. The
Hiccup Mode Over Current Protection LM25117’s unique analog telemetry feature provides
average output current information. Additional
Programmable Soft-start and Tracking features include thermal shutdown, frequency
Programmable Line Undervoltage Lockout synchronization, hiccup mode current limit and
Programmable Switch-over to External Bias adjustable line undervoltage lockout.
Supply
Thermal Shutdown Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications LM25117 HTSSOP (20) PWP 6.50 mm x 4.40 mm
LM25117-Q1 WQFN (24) RTW 4.00 mm x 4.00 mm
Automotive Infotainment
Industrial DC-DC Motor Drivers (1) For all available packages, see the orderable addendum at
the end of the datasheet.
Automotive USB Power
Telecom Server
Typical Application
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
7.3 Feature Description................................................. 13
1 Features.................................................................. 17.4 Device Functional Modes........................................ 21
2 Applications ........................................................... 18 Application and Implementation ........................ 22
3 Description............................................................. 18.1 Application Information............................................ 22
4 Revision History..................................................... 28.2 Typical Applications ............................................... 22
5 Pin Configuration and Functions......................... 38.3 Detailed Design Procedure..................................... 22
6 Specifications......................................................... 58.4 Application Curves.................................................. 32
6.1 Absolute Maximum Ratings ...................................... 59 Power Supply Recommendations...................... 35
6.2 ESD Ratings (LM25117)........................................... 510 Layout................................................................... 35
6.3 ESD Ratings (LM25117-Q1)..................................... 510.1 Layout Guideline................................................... 35
6.4 Recommended Operating Conditions....................... 611 Device and Documentation Support................. 36
6.5 Thermal Information.................................................. 611.1 Community Resources.......................................... 36
6.6 Electrical Characteristics........................................... 711.2 Related Links ........................................................ 36
6.7 Switching Characteristics.......................................... 811.3 Trademarks........................................................... 36
6.8 Typical Characteristics.............................................. 911.4 Electrostatic Discharge Caution............................ 36
7 Detailed Description............................................ 11 11.5 Glossary................................................................ 36
7.1 Overview................................................................. 11 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram....................................... 12 Information........................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2013) to Revision F Page
Added Device Information and Pin Configuration and Functions sections, ESD Rating table, Feature Description,
Device Functional Modes,Application and Implementation,Power Supply Recommendations,Layout,Device and
Documentation Support , and Mechanical, Packaging, and Orderable Information sections................................................ 1
Changed µH to µF................................................................................................................................................................ 29
Changes from Revision D (March 2013) to Revision E Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 34
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PGND
UVLO
AGND
DEMB
RES
SS
RT
FB
COMP
CM
1
6
2
3
4
5
8 9
20
14
15
19
18
17
16
13
1211
VIN
LO
HB
HO
SW
VCC
CSG
CS
RAMP
21222324
VCCDIS
7 10
NC
NC
NC
NC
EP
UVLO
AGND
DEMB
RES
SS
RT
FB
COMP
CM
VIN
PGND
LO
HB
HO
SW
VCC
CSG
CS
RAMP
1
6
2
3
4
5
8
9
20
14
15
19
18
17
16
13
12
11
EP
VCCDIS
10
7
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5 Pin Configuration and Functions
PWP Package
20-Pin HTSSOP
Top View
RTW Package
24-Pin WQFN
Top View
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Pin Functions
PIN TYPE(1) DESCRIPTION
HTSSO WQFN NAME
P NO. NO.
1 24 UVLO I Undervoltage lockout programming pin. If the UVLO pin voltage is below 0.4V, the regulator is
in the shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4V
and less than 1.25V, the regulator is in standby mode with the VCC regulator operational, the
SS pin grounded, and no switching at the HO and LO outputs. If the UVLO pin voltage is above
1.25 V, the SS pin is allowed to ramp and pulse width modulated gate drive signals are
delivered to the HO and LO pins. A 20μA current source is enabled when UVLO exceeds 1.25V
and flows through the external UVLO resistors to provide hysteresis.
2 1 DEMB I Optional logic input that enables diode emulation when in the low state. In diode emulation
mode, the low-side NMOS is latched off for the remainder of the PWM cycle after detecting
reverse current flow (current flow from output to ground through the low-side NMOS). When
DEMB is high, diode emulation is disabled allowing current to flow in either direction through the
low-side NMOS. A 50kpull-down resistor internal to the LM25117 holds DEMB pin low and
enables diode emulation if the pin is left floating.
3 2 RES O The restart timer pin that configures the hiccup mode current limiting. A capacitor on the RES
pin determines the time the controller remains off before automatically restarting. The hiccup
mode commences when the controller experiences 256 consecutive PWM cycles of cycle-by-
cycle current limiting. After this occurs, an 10μA current source charges the RES pin capacitor
to the 1.25V threshold and restarts LM25117.
4 3 SS I An external capacitor and an internal 10μA current source set the ramp rate of the error
amplifier reference during soft-start. The SS pin is held low when VCC< 4V, UVLO < 1.25V or
during thermal shutdown.
5 4 RT I The internal oscillator is programmed with a single resistor between RT and the AGND. The
recommended maximum oscillator frequency is 750kHz. The internal oscillator can be
synchronized to an external clock by coupling a positive pulse into the RT pin through a small
coupling capacitor.
6 5 AGND G Analog ground. Return for the internal 0.8V voltage reference and analog circuits.
7 7 VCCDIS I Optional input that disables the internal VCC regulator. If VCCDIS>1.25V, the internal VCC
regulator is disabled. VCCDIS has an internal 500kpull-down resistor to enable the VCC
regulator when the pin is left floating. The internal 500kpull-down resistor can be overridden
by pulling VCCDIS above 1.25V with a resistor divider connected to an external bias supply.
8 8 FB I Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this
pin sets the output voltage level. The regulation threshold at the FB pin is 0.8V.
9 9 COMP O Output of the internal error amplifier. The loop compensation network should be connected
between this pin and the FB pin.
10 10 CM O Current monitor output. Average of the sensed inductor current is provided. Monitor directly
between CM and AGND. CM should be left floating when the pin is not used.
11 11 RAMP I PWM ramp signal. An external resistor and capacitor connected between the SW pin, the
RAMP pin and the AGND pin sets the PWM ramp slope. Proper selection of component values
produces a RAMP signal that emulates the AC component of the inductor with a slope
proportional to input supply voltage.
12 12 CS I Current sense amplifier input. Connect to the high-side of the current sense resistor.
13 13 CSG I Kelvin ground connection to the current sense resistor. Connect directly to the low-side of the
current sense resistor.
14 14 PGND G Power ground return pin for low-side NMOS gate driver. Connect directly to the low-side of the
current sense resistor.
15 15 LO O Low-side NMOS gate drive output. Connect to the gate of the low-side synchronous NMOS
transistor through a short, low inductance path.
16 16 VCC P/O/I Bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to
controller as possible.
17 18 SW I/O Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal of
the high-side NMOS transistor and the drain terminal of the low-side NMOS through a short,
low inductance path.
18 19 HO O High-side NMOS gate drive output. Connect to the gate of the high-side NMOS transistor
through a short, low inductance path.
19 20 HB P High-side driver supply for the bootstrap gate drive. Connect to the cathode of the external
bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to
charge the high-side NMOS gate and should be placed as close to controller as possible.
(1) I = Input, O = Output, G = Ground, P = Power
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Pin Functions (continued)
PIN TYPE(1) DESCRIPTION
HTSSO WQFN NAME
P NO. NO.
20 22 VIN P/I Supply voltage input source for the VCC regulator.
EP EP EP - Exposed pad of the package. Electrically isolated. Should be soldered to the ground plane to
reduce thermal resistance.
6 NC - No electrical contact.
17 NC - No electrical contact.
21 NC - No electrical contact.
23 NC - No electrical contact.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN to AGND -0.3 45 V
SW to AGND -3.0 45 V
HB to SW -0.3 15 V
VCC to AGND(2) -0.3 15 V
HO to SW -0.3 HB+0.3 V
LO to AGND -0.3 VCC+0.3 V
FB, DEMB, RES, VCCDIS, UVLO to AGND -0.3 15 V
CM, COMP to AGND(3) -0.3 7 V
SS, RAMP, RT to AGND -0.3 7 V
CS, CSG, PGND, to AGND -0.3 0.3 V
Storage temperature, Tstg -55 150 °C
Junction Temperature -40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See Application and Implementation when input supply voltage is less than the VCC voltage.
(3) These pins are output pins. As such they are not specified to have an external voltage applied.
6.2 ESD Ratings (LM25117) VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V ±750 V
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings (LM25117-Q1) VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1) ±2000 V
V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 ±750 V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN(2) 4.5 42 V
VCC 4.5 14 V
HB to SW 4.5 14 V
Junction -40 125 °C
Temperature
(1) Recommended Operating Conditions are conditions under which operation of the device is intended to be functional, but does not
ensure specific performance limits. For specifications and test conditions see .Electrical Characteristics
(2) Minimum VIN operating voltage is defined with VCC supplied by the internal HV startup regulator and no external load on VCC. When
VCC is supplied by an external source, minimum VIN operating voltage is 4.5 V.
6.5 Thermal Information LM25117, LM25117-Q1
THERMAL METRIC(1) PWP (HTSSOP) RTW (WQFN) UNIT
20 PINS 24 PINS
RθJA Junction-to-ambient thermal resistance 40 40 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 4 6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.6 Electrical Characteristics
Typical limits are for TJ= 25°C only; typical values represent the most likely parametric norm at TJ= 25°C, and are provided
for reference purposes only. Minimum and maximum limits apply over the junction temperature range of –40°C to +125°C.
Unless otherwise specified, the following conditions apply: VVIN = 24 V, VVCCDIS = 0 V, RT= 25 k, no load on LO & HO.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN SUPPLY
IBIAS VIN Operating Current (1) VSS = 0V 4.8 6.2 mA
VSS = 0V, VVCCDIS = 2V 0.4 0.55 mA
ISHUTDOWN VIN Shutdown Current VSS = 0V, VUVLO = 0V 16 40 µA
VCC Regulator
VCC(REG) VCC Regulation No Load 6.85 7.6 8.2 V
VCC Dropout (VIN to VCC) VVIN = 4.5V, No external load 0.05 0.14 V
VVIN = 5.0V, ICC = 20mA 0.4 0.5 V
VCC Sourcing Current Limit VVCC = 0V 30 42 mA
IVCC VCC Operating Current (1) VSS = 0V, VVCCDIS = 2V 4.0 5.0 mA
VSS = 0V, VVCCDIS = 2V, VVCC = 14V 5.8 7.3 mA
VCC Under-voltage Threshold VCC Rising 3.75 4.0 4.15 V
VCC Under-voltage Hysteresis 0.2 V
VCC Disable
VCCDIS Threshold VCCDIS Rising 1.22 1.25 1.29 V
VCCDIS Hysteresis 0.06 V
VCCDIS Input Current VVCCDIS = 0V -20 nA
VCCDIS Pull-down Resistance 500 k
UVLO
UVLO Threshold UVLO Rising 1.22 1.25 1.29 V
UVLO Hysteresis Current VUVLO = 1.4V 15 20 25 µA
UVLO Shutdown Threshold UVLO Falling 0.23 0.3 V
UVLO Shutdown Hysteresis 0.1 V
Soft Start
ISS SS Current Source VSS = 0V 7 10 12 µA
SS Pull-down Resistance 13 24
Error Amplifier
VREF FB Reference Voltage Measured at FB, FB = COMP 788 800 812 mV
FB Input Bias Current VFB = 0.8V 1 nA
VOH COMP Output High Voltage ISOURCE = 3mA 2.8 V
VOL COMP Output Low Voltage ISINK = 3mA 0.26 V
AOL DC Gain 80 dB
fBW Unity Gain Bandwidth 3 MHz
PWM Comparator
tHO(OFF) Forced HO Off-time 260 320 440 ns
tON(MIN) Minimum HO On-time VVIN = 42V 100 ns
COMP to PWM comparator offset 1.2 V
Oscillator
fSW1 Frequency 1 RT= 25k180 200 220 kHz
fSW2 Frequency 2 RT= 10k430 480 530 kHz
RT Output Voltage 1.25 V
RT Sync Positive Threshold 2.6 3.2 3.95 V
Sync Pulse Width 100 ns
(1) Operating current does not include the current into the RTresistor.
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Electrical Characteristics (continued)
Typical limits are for TJ= 25°C only; typical values represent the most likely parametric norm at TJ= 25°C, and are provided
for reference purposes only. Minimum and maximum limits apply over the junction temperature range of –40°C to +125°C.
Unless otherwise specified, the following conditions apply: VVIN = 24 V, VVCCDIS = 0 V, RT= 25 k, no load on LO & HO.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Limit
VCS(TH) Cycle-by-cycle Sense Voltage VRAMP = 0, CSG to CS 106 120 135 mV
Threshold
CS Input Bias Current VCS = 0V -100 -66 µA
CSG Input Bias Current VCSG = 0V -100 -66 µA
Current Sense Amplifier Gain 10 V/V
Hiccup Mode Fault Timer 256 Cycles
RES
IRES RES Current Source 10 µA
VRES RES Threshold RES Rising 1.22 1.25 1.285 V
Diode Emulation
VIL DEMB Input Low Threshold 2.0 1.65 V
VIH DEMB Input High Threshold 2.95 2.5 V
SW Zero Cross Threshold -5 mV
DEMB Input Pull-down Resistance 50 k
Current Monitor
Current Monitor Amplifier Gain CS to CM 17.5 20.5 23.5 V/V
Current Monitor Amplifier Gain Drift over Temperature -2 0 +2 %
Zero Input Offset 25 120 mV
HO Gate Driver
VOHH HO High-state Voltage Drop IHO = –100mA, VOHH = VHB - VHO 0.17 0.3 V
VOLH HO Low-state Voltage Drop IHO = 100mA, VOLH = VHO - VSW 0.1 0.2 V
HO Rise Time C-load = 1000pF (2) 6 ns
HO Fall Time C-load = 1000pF (2) 5 ns
IOHH Peak HO Source Current VHO = 0V, SW = 0V, HB = 7.6V 2.2 A
IOLH Peak HO Sink Current VHO = VHB = 7.6V 3.3 A
HB to SW Under-voltage 2.56 2.9 3.32 V
HB DC Bias Current HB - SW = 7.6V 65 100 µA
LO Gate Driver
VOHL LO High-state Voltage Drop ILO = –100mA, VOHL = VCC-VLO 0.17 0.27 V
VOLL LO Low-state Voltage Drop ILO = 100mA, VOLL = VLO 0.1 0.2 V
LO Rise Time C-load = 1000pF (2) 6 ns
LO Fall Time C-load = 1000pF (2) 5 ns
IOHL Peak LO Source Current VLO = 0V 2.5 A
IOLL Peak LO Sink Current VLO = 7.6V 3.3 A
Thermal
TSD Thermal Shutdown Temperature Rising 165 °C
Thermal Shutdown Hysteresis 25 °C
(2) High and low reference are 80% and 20% of the pulse amplitude respectively.
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TDLH LO fall to HO rise delay 72 ns
No load
TDHL HO fall to LO rise delay 71 ns
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6.8 Typical Characteristics
Figure 1. HO Peak Driver Current Vsoutput Voltage Figure 2. LO Peak Driver Current vs Output Voltage
Figure 3. Driver Dead Time vs VVCC Figure 4. Driver Dead Time vs Temperature
Figure 5. Forced Ho Off-Time vs Temperature Figure 6. Switching Frequency vs RT
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Typical Characteristics (continued)
Figure 7. VVCC vs IVCC Figure 8. VVCC vs VVIN
Figure 9. VCS(TH) vs Temperature Figure 10. VREF vs Temperature
Figure 12. Error Amp Gain And Phase vs Frequency
Figure 11. VVCC vs Temperature
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Typical Characteristics (continued)
Figure 13. VCM vs IOUT Figure 14. VCM vs VCSG-CS
7 Detailed Description
7.1 Overview
The LM25117 high voltage switching controller features all of the functions necessary to implement an efficient
high voltage buck regulator that operates over a very wide input voltage range. This easy to use controller
integrates high-side and low-side NMOS drivers. The regulator control method is based upon peak current mode
control utilizing an emulated current ramp. Peak current mode control provides inherent line feed-forward, cycle-
by-cycle current limiting and ease of loop compensation. The use of an emulated control ramp reduces noise
sensitivity of the PWM circuit, allowing reliable processing of the very small duty cycles necessary in high input
voltage applications.
The switching frequency is user programmable up to 750 kHz. The RT pin allows the switching frequency to be
programmed by a single resistor or synchronized to an external clock. Fault protection features include cycle-by-
cycle and hiccup mode current limiting, thermal shutdown and remote shutdown capability by pulling down UVLO
pin. The UVLO input enables the regulator when the input voltage reaches a user selected threshold and
provides a very low quiescent shutdown current when pulled low. A unique analog telemetry feature provides
averaged output current information, allowing various applications that need either a current monitor or current
control. The functional block diagram and typical application circuit of the LM25117 are shown in Functional
Block Diagram
The device is available in HTSSOP-20 and WQFN-24 (4mm×4mm) package featuring an exposed pad to aid in
thermal dissipation.
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RT
RES
AGND
REF
DISABLE
VCC
HO Driver
LO Driver
LEVEL SHIFT/
ADAPTIVE
TIMER
+
-
S
R Q
Q
CLK
+
-
+
-
-+
+
+
-
1.2V
DEMB
SS Current
VIN
VCC
UVLO
VCC OFF
FB
SS HB
HO
SW
LO
CS
PGND
COMP
CSG
CM
VCC Regulator
THERMAL
SHUTDOWN
UVLO
Shutdown
Threshold
STANDBY
STANDBY
VCC OFF
RES RESET
UVLO
Threshold
UVLO Hysteresis
Current
RESTART
TIMER
HICCUP MODE
FAULT TIMER
256 CYCLES
RES
Current
UVLO
VCC
STANDBY
DE_ENABLE
+
-
STANDBY
RES RESET
HICCUP
10uVCS(TH)
PWM
Comparator
C/L
Comparator
50 k:
+
-
+
-
DE_ENABLE
2.0/2.5V
OSCILLATOR/
SYNC DETECTOR
CLK
A=2
40 k:
CONDITIONER
Current Sense
Amplifier
RAMP
HO_ENABLE
+
-
+
-
ZCD
Comparator -5 mV
DIODE
EMULATION
CONTROL
LO_ENABLE
ERR
AMP
VCCDIS
500 k:
VCCDIS
Threshold
VCC OFF
+
-
DE_ENABLE
LM25117
REF
VOUT
VIN
CIN
COUT1
COUT2
LO
QH
QL
RSNB
CSNB
RS
RGH
RGL
DHB
CVCC
CCS
RCS2
RCS1
CHB
RVIN
CVIN
SYNC
CFT
CRAMP
RRAMP
RFB2
RFB1
RCOMP CCOMP
CHF
CSYNC RT
CRES
CSS
RUV2
RUV1
RCM
CCM
STANDBY
STANDBY
VCC OFF
HO_ENABLE
HB
UVLO
Current Monitor
Amplifier
A=10
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7.2 Functional Block Diagram
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VCC
VCCDIS
LM25117
VOUT
VCCDIS resistor divider is required
when external VCC supplying voltage is
smaller than 8.5V
VIN
LM25117
VIN
VCC
External
VCC Supply
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7.3 Feature Description
7.3.1 High Voltage Startup Regulator and VCC Disable
The LM25117 contains an internal high voltage bias regulator that provides the VCC bias supply for the PWM
controller and NMOS gate drivers. The VIN pin can be connected to an input voltage source as high as 42V. The
output of the VCC regulator is set to 7.6V. When the input voltage is below the VCC set-point level, the VCC
output tracks the VIN with a small dropout voltage. The output of the VCC regulator is current limited at 30mA
minimum.
Upon power-up, the regulator sources current into the capacitor connected to the VCC pin. The recommended
capacitance range for the pin VCC is 0.47µF to 10µF. When the VCC pin voltage exceeds the VCC UV threshold
and the UVLO pin is greater than UVLO threshold, the HO and LO drivers are enabled and a soft-start sequence
begins. The HO and LO drivers remain enabled until either the VCC pin voltage falls below VCC UV threshold,
the UVLO pin voltage falls below UVLO threshold, hiccup mode is activated or the die temperature exceeds the
thermal shutdown threshold. Enabling/Disabling the IC by controlling UVLO is recommended in most of cases.
An output voltage derived bias supply can be applied to the VCC pin to reduce the controller power dissipation at
higher input voltage. The VCCDIS input can be used to disable the internal VCC regulator when external biasing
is supplied. The externally supplied bias should be coupled to the VCC pin through a diode, preferably a
Schottky diode. If the VCCDIS pin voltage exceeds the VCCDIS threshold, the internal VCC regulator is disabled.
VCCDIS has a 500kinternal pull-down resistor to ground for normal operation with no external bias.
The VCC regulator series pass transistor includes a diode between VCC (Anode) and VIN (Cathode) that should
not be forward biased in normal operation. If the voltage of the external bias supply is greater than the VIN pin
voltage, an external blocking diode is required from the input power supply to the VIN pin to prevent the external
bias supply from passing current to the input supply through VCC.
Figure 15. VIN Configuration For VVIN<VVCC
For VOUT between 5V and 14.5V, the output can be connected directly to VCC through a diode.
Figure 16. External VCC Supply For 5 V< VOUT<14.5 V
For VOUT < 5V, a bias winding on the output inductor can be added to generate the external VCC supply voltage.
Figure 17. External VCC Supply For VOUT <5 V
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Product Folder Links: LM25117 LM25117-Q1
LM25117
VIN
UVLO
Shutdown
Threshold SHUTDOWN
UVLO
Threshold
UVLO Hysteresis
Current
UVLO
+
-
+
-
CFT
RUV2
RUV1
STANDBY
VCC
LM25117
VOUT
Zener
R1
R1 is required to limit maximum reverse zener current
30 k: minimum resistive loss at VCC
guarantees minimum reverse zener current
30 k:
LM25117
,
LM25117-Q1
SNVS714F APRIL 2011REVISED AUGUST 2015
www.ti.com
Feature Description (continued)
For 14.5 V <VOUT, the external supply voltage can be regulated by using a series Zener diode from the output to
VCC.
Figure 18. External VCC Supply For 14.5 V <VOUT
In high input voltage applications, extra care should be taken to ensure the VIN pin does not exceed the absolute
maximum voltage rating of 45V. During line or load transients, voltage ringing on the VIN that exceeds the
Absolute Maximum Rating can damage the IC. Both careful PC board layout and the use of quality bypass
capacitors located close to the VIN and AGND pin are essential. Adding an R-C filter (RVIN, CVIN) on VIN is
optional and helps to prevent faulty operation caused by poor PC board layout and high frequency switching
noise injection. The recommended capacitance and resistance range are 0.1µF to 10µF and 1to 10.
7.3.2 UVLO
The LM25117 contains a dual level UVLO (under-voltage lockout) circuit. When the UVLO is less than 0.4 V, the
LM25117 is in shutdown mode. The shutdown comparator provides 100mV of hysteresis to avoid chatter during
transitions. When the UVLO pin voltage is greater than 0.4 V but less than 1.25 V, the controller is in standby
mode. In the standby mode, the VCC bias regulator is active but the HO and LO drivers are disabled and the SS
pin is held low. This feature allows the UVLO pin to be used as a remote shutdown function by pulling the UVLO
pin down below 0.4V with an external open collector or open drain device. When the VCC pin exceeds its under-
voltage lockout threshold and the UVLO pin voltage is greater than 1.25V, the HO and LO drivers are enabled
and normal operation begins.
Figure 19. UVLO Configuration
The UVLO pin should not be left floating. An external UVLO set-point voltage divider from the VIN to AGND is
used to set the minimum input operating voltage of the regulator. The divider must be designed such that the
voltage at the UVLO pin is greater than 1.25V and never exceeds 15V when the input voltage is in the desired
operating range. If necessary, the UVLO pin can be clamped with a Zener diode.
UVLO hysteresis is accomplished with an internal 20μA current source that is switched on or off into the
impedance of the UVLO set-point divider. When the UVLO pin voltage exceeds the 1.25 V threshold, the current
source is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25
V threshold, the current source is disabled causing the voltage at the UVLO pin to quickly fall. The use of a CFT
capacitor in parallel with RUV1 helps to minimize switching noise injection into UVLO pin, but it may slow down
the falling speed of the UVLO pin when the 20μA current source is disabled. The recommended range for CFT is
10pF to 220pF.
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5.2 x 109
RT = - 948 [5]
fSW
1.25V x RUV2
RUV1 = VIN(STARTUP) - 1.25V [5]
VHYS
RUV2 = 20 µA[5]
LM25117
,
LM25117-Q1
www.ti.com
SNVS714F APRIL 2011REVISED AUGUST 2015
Feature Description (continued)
The values of RUV1 and RUV2 can be determined from the following equations:
(1)
(2)
Where VHYS is the desired UVLO hysteresis and VIN(STARTUP) is the desired startup voltage of the regulator during
turn-on.
7.3.3 Oscillator And Sync Capability
The LM25117 switching frequency is programmed by a single external resistor connected between the RT pin
and the AGND pin. The resistor should be located very close to the device and connected directly to the RT and
AGND pins. To set a desired switching frequency (fSW), the resistor value can be calculated from the following
equation:
(3)
The RT pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be
synchronized by AC coupling a positive edge into the RT pin. The voltage at the RT pin is nominally 1.25 V and
the voltage at the RT pin must exceed the RT Sync Positive Threshold to trip the internal synchronization pulse
detector. A 5 V amplitude pulse signal coupled through 100pF capacitor is a good starting point. The frequency
of the external synchronization pulse is recommended to be within +/-10% of the frequency programmed by the
RT resistor but will operate to +100/-40% of the programmed frequency. Care should be taken to make sure that
the RT pin voltage does not go below -0.3V at the falling edge of the external pulse. This may limit the duty cycle
of external synchronization pulse.
The RTresistor is always required, whether the oscillator is free running or externally synchronized.
7.3.4 Ramp Generator and Emulated Current Sense
The ramp signal used in the pulse width modulator for traditional current mode control is typically derived directly
from the high-side switch current. This switch current corresponds to the positive slope portion of the inductor
current. Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response
and provides inherent input voltage feed-forward compensation.
The disadvantage of using the high-side switch current signal for PWM control is the large leading edge spike
due to circuit parasitics that must be filtered or blanked. Minimum achievable pulse width is limited by the
filtering, blanking time and propagation delay with a high-side current sensing scheme.
In the applications where the input voltage may be relatively large in comparison to the output voltage, controlling
small pulse widths and duty cycles are necessary for regulation. The LM25117 utilizes a unique ramp generator
which does not actually measure the high-side switch current but rather reconstructs the signal. Representing or
emulating the inductor current provides a ramp signal to the PWM comparator that is free of leading edge spikes
and measurement or filtering delays, while maintaining the advantages of traditional peak current mode control.
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM25117 LM25117-Q1
LO
RRAMP x CRAMP x RS x AS
K =
HO_ENABLE
SW
CS
RAMP
CSG
+
-
+
-
AS=10
RRAMP CRAMP
RSIL
10 xVCS(TH)
Current Limit
Comparator
Current Sense
Amplifier
LM25117
Sample and Hold
DC Level
tON
ILO x RS x 10
Additional Slope
VIN x tON
RRAMP x CRAMP
RAMPPK =
LM25117
,
LM25117-Q1
SNVS714F APRIL 2011REVISED AUGUST 2015
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Feature Description (continued)
The current reconstruction is comprised of two elements: a sample-and-hold DC level and the emulated inductor
current ramp as shown in Figure 20. The sample-and-hold DC level is derived from a measurement of the
recirculating current flowing through the current sense resistor. The voltage across the sense resistor is sampled
and held just prior to the onset of the next conduction interval of the high-side switch. The current sense amplifier
with a gain of 10 and sample-and-hold circuit provide the DC level of the reconstructed current signal as shown
in Figure 21.
Figure 20. Composition of Emulated Current Sense Signal
Figure 21. Ramp Generator and Current Limit Circuit
The positive slope inductor current ramp is emulated by CRAMP connected between RAMP and AGND and RRAMP
connected between SW and RAMP. RRAMP should not be connected to VIN directly because the RAMP pin
absolute maximum voltage rating could be exceeded under high input voltage conditions. CRAMP is discharged by
an internal switch during the off-time and must be fully discharged during the minimum off-time. This limits the
ramp capacitor to be less than 2nF. A good quality, thermally stable ceramic capacitor is recommended for
CRAMP.
The selection of RRAMP and CRAMP can be simplified by adopting a K factor, which is defined as:
(4)
Where ASis the current sense amplifier gain which is normally 10. By choosing 1 as the K factor, the regulator
removes any error after one switching cycle and the design procedure is simplified. See Application Information
for detailed information.
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10 µA
CSS x 0.8V
tSS = [sec]
FP2 = 1
CCOMP x CHF
CCOMP + CHF
2S x RCOMP x¹
·
©
§[Hz]
2Sx RCOMP x CCOMP
1
FZ = [Hz]
FP1 = 0 [Hz]
VOUT
COMP
FB
LM25117
+
-
RFB2
RFB1
RCOMP CCOMP
CHF
REF
Error
Amplifier
Type 2 Compensation
Components
-+
PWM
Comparator
+
-
RAMP Generator
Output
(optional)
LM25117
,
LM25117-Q1
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Feature Description (continued)
7.3.5 Error Amplifier and PWM Comparator
The internal high-gain error amplifier generates an error signal proportional to the difference between the FB pin
voltage and the internal precision 0.8V reference. The output of error amplifier is connected to the COMP pin
allowing the user to provide Type 2 loop compensation components, RCOMP, CCOMP and optional CHF.
Figure 22. Feedback Configuration and PWM Comparator
RCOMP, CCOMP and CHF configure the error amplifier gain and phase characteristics to achieve a stable voltage
loop gain. This network creates a pole at DC (FP1), a mid-band zero (FZ) for phase boost, and a high frequency
pole (FP2). The recommended range of RCOMP is 2kto 40k. See Application Information for detailed
information.
(5)
(6)
(7)
The PWM comparator compares the emulated current sense signal from Ramp Generator to the voltage at the
COMP pin through a 1.2 V internal voltage drop and terminates the present cycle when the emulated current
sense signal is greater than VCOMP - 1.2 V.
7.3.6 Soft-Start
The soft-start feature allows the regulator to gradually reach the steady state operating point, thus reducing
startup stresses and surges. The LM25117 regulates the FB pin to the SS pin voltage or the internal 0.8V
reference, whichever is lower. The internal 10µA soft-start current source gradually increases the voltage on an
external soft-start capacitor connected to the SS pin. This results in a gradual rise of the output voltage. Soft-start
time (tss) can be calculated from the following equation:
(8)
The LM25117 can track the output of a master power supply during soft-start by connecting a voltage divider
from the output of master power supply to the SS pin. At the beginning of the soft-start sequence, VSS should be
allowed to go below 25mV by the internal SS pull-down switch. During soft-start period, when SS pin voltage is
less than 0.8V, the LM25117 forces diode emulation for startup into a pre-biased load. If the tracking feature is
desired, connect the DEMB pin to GND or leave the pin floating.
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Product Folder Links: LM25117 LM25117-Q1
RSLO
VIN(MAX) x tON(MIN)
+
ILIM_PK = VCS(TH) [A]
0
IOUT IPP
fSW
1
T=
¸
¹
·
¨
©
§
VIN
IPP = 1 - VOUT
VOUT x
LO x fSW [A]
2
IPP
IL(MAX)_AVE = IL(MAX)_PK -[A]
VOUT
fSW x AS x RS x RRAMP x CRAMP
+ IPP -
VCS(TH)
RS
IL(MAX)_PK =[A]
LM25117
,
LM25117-Q1
SNVS714F APRIL 2011REVISED AUGUST 2015
www.ti.com
Feature Description (continued)
7.3.7 Cycle-By-Cycle Current Limit
The LM25117 contains a current limit monitoring scheme to protect the regulator from possible over-current
conditions as shown in Figure 21. If the emulated ramp signal exceeds 1.2 V, the present cycle is terminated. For
the case where the switch current overshoots when the inductor is saturated or the output is shorted to ground,
the sample-and-hold circuit detects the excess recirculating current before the high-side NMOS driver is turned
on again. The high-side NMOS driver is disabled and will skip pulses until the current has decayed below the
current limit threshold. This approach prevents current runaway conditions since the inductor current is forced to
decay to a controlled level following any current overshoot. Maximum peak inductor current can be calculated as:
(9)
(10)
Where IPP represents inductor peak to peak ripple current in Figure 23, and is defined as:
(11)
Figure 23. Inductor Current
During an output short condition, the worst case peak inductor current is limited to:
(12)
Where tON(MIN) is the minimum HO on-time.
In most of cases, especially if the output voltage is relatively high, it is recommended that a soft-saturating
inductor such as a powder core device is used. If a sharp-saturating inductor is used, the inductor saturation
level must be above ILIM_PK. The temperatures of the NMOS devices, RSand inductor should be checked under
this output short condition.
7.3.8 Hiccup Mode Current Limiting
To further protect the regulator during prolonged current limit conditions, LM25117 provides a hiccup mode
current limit. An internal hiccup mode fault timer counts the PWM clock cycles during which cycle-by-cycle
current limiting occurs. When the hiccup mode fault timer detects 256 consecutive cycles of current limiting, an
internal restart timer forces the controller to enter a low power dissipation standby mode and starts sourcing
10μA current into the RES pin capacitor CRES. In this standby mode, HO and LO outputs are disabled and the
soft-start capacitor CSS is discharged.
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RES
LM25117
VCC
CRES
RES
LM25117
RES
LM25117
VCC
(a) Hiccup Mode
Current Limit (b) Latch-off Mode
Current Limit (c) Cycle-by-cycle
Current Limit
RES
RESTART
TIMER
HICCUP MODE
FAULT TIMER
256 CYCLES
RES
Current
STANDBY
HICCUP
Current Limit
Comparator
CRES
+
-
LM25117
HO
LO
SS
RES 0V
1.25V RES Threshold
0.8V REF
Current Limit
Detected
Current Limit
persists during 256
consecutive cycles
tSS
tRES
IRES = 10 µA
ISS = 10 µA
10 PA
CRES x 1.25V
tRES = [sec]
LM25117
,
LM25117-Q1
www.ti.com
SNVS714F APRIL 2011REVISED AUGUST 2015
Feature Description (continued)
CRES is connected from RES pin to AGND and determines the time (tRES) in which the LM25117 remains in the
standby before automatically restarting. When the RES pin voltage exceeds the 1.25 V RES threshold, RES
capacitor is discharged and a soft-start sequence begins. tRES can be calculated from the following equation:
(13)
Figure 24. Hiccup Mode Current Limit Timing Diagram
Figure 25. Hiccup Mode Current Limit Circuit
The RES pin can also be configured for latch-off mode current limiting or non-hiccup mode cycle-by-cycle current
limiting. If the RES pin is tied to VCC or a voltage greater than the RES threshold at initial power-on, the restart
timer is disabled and the regulator operates with non-hiccup mode cycle-by-cycle current limit. If the RES pin is
tied to GND, the regulator enters into the standby mode after 256 consecutive cycles of current limiting and then
never restarts until UVLO shutdown is cycled. The restart timer is configured during initial power-on when UVLO
is above the UVLO threshold and VCC is above the VCC UV threshold.
Figure 26. Res Configurations
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( ) [ ]
CM _ AVE PEAK VALLEY S S
V I I R A V= + ´ ´
CM
AM = 2
40 k:
RCM
CCM
Current Monitor
Amplifier
Current Sense
Amplifier Output LM25117
CONDITIONER
LM25117
,
LM25117-Q1
SNVS714F APRIL 2011REVISED AUGUST 2015
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Feature Description (continued)
7.3.9 HO and LO Drivers
The LM25117 contains high current NMOS drivers and an associated high-side level shifter to drive the external
high-side NMOS device. This high-side gate driver works in conjunction with an external diode DHB, and
bootstrap capacitor CHB. A 0.1μF or larger ceramic capacitor, connected with short traces between the HB and
SW pin, is recommended. During the off-time of the high-side NMOS driver, the SW pin voltage is approximately
0V and the CHB is charged from VCC through the DHB. When operating with a high PWM duty cycle, the high-
side NMOS device is forced off each cycle for 320ns to ensure that CHB is recharged.
The LO and HO outputs are controlled with an adaptive dead-time methodology which insures that both outputs
are never enabled at the same time. When the controller commands HO to be enabled, the adaptive dead-time
logic first disables LO and waits for the LO voltage to drop. HO is then enabled after a small delay (LO Fall to HO
Rise Delay). Similarly, the LO turn-on is delayed until the HO voltage has discharged. LO is then enabled after a
small delay (HO Fall to LO Rise Delay). This technique insures adequate dead-time for any size NMOS device,
especially when VCC is supplied by a higher external voltage source. The adaptive dead-time circuitry monitors
the voltages of HO and LO outputs and insures the dead-time between the HO and LO outputs. Adding a gate
resister, RGH or RGL, may decrease the effective dead-time.
Care should be exercised in selecting an output NMOS device with the appropriate threshold voltage, especially
if VCC is supplied by an external bias supply voltage below the VCC regulation level. During startup at low input
voltages, the low-side NMOS device gate plateau voltage should be lower than the VCC under-voltage lockout
threshold. Otherwise, there may be insufficient VCC voltage to completely enhance the NMOS device as the
VCC under-voltage lockout is released during startup. If the high-side NMOS drive voltage is lower than the high-
side NMOS device gate plateau voltage during startup, the regulator may not start or it may hang up momentarily
in a high power dissipation state. This condition can be addressed by selecting an NMOS device with a lower
threshold voltage. This situation can be avoided if the minimum input voltage programmed by the UVLO resistor
is above the VCC regulation level.
7.3.10 Current Monitor
The LM25117 provides average output current information, enabling various applications requiring monitoring or
control of the output current.
Figure 27. Current Monitor
The average of CM output can be calculated by:
(14)
The current monitor output is only valid in continuous conduction operation. The current monitor has a limited
bandwidth of approximately one tenth of fSW. Adding an R-C filter, RCM and CCM, on the output of current monitor
with the cut off frequency below one tenth of fSW is recommended to attenuate sampling noise.
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,
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Feature Description (continued)
7.3.11 Maximum Duty Cycle
When operating with a high PWM duty cycle, the high-side NMOS device is forced off each cycle for 320ns to
ensure that CHB is recharged and to allow time to sample and hold the current in the low-side NMOS FET. This
forced off-time limits the maximum duty cycle of the controller. When designing a regulator with high switching
frequency and high duty cycle requirements, a check should be made of the required maximum duty cycle
against the graph shown in Figure 28. The actual maximum duty cycle varies with the switching frequency as
follows:
Figure 28. Maximum Duty Cycle vs Switching Frequency
7.3.12 Thermal Protection
Internal thermal shutdown circuitry is provided to protect the controller in the event the maximum junction
temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power shutdown
mode, disabling the output drivers and the VCC regulator. This feature is designed to prevent overheating and
destroying the device.
7.4 Device Functional Modes
7.4.1 Diode Emulation
A fully synchronous buck regulator implemented with a freewheeling NMOS rather than a diode has the
capability to sink current from the output in certain conditions such as light load, over-voltage or pre-bias startup.
The LM25117 provides a diode emulation feature that can be enabled to prevent reverse current flow in the low-
side NMOS device. When configured for diode emulation, the low-side NMOS driver is disabled when SW pin
voltage is greater than -5mV during the off-time of the high-side NMOS driver, preventing reverse current flow.
A benefit of the diode emulation is lower power loss at no load or light load conditions. The negative effect of
diode emulation is degraded light load transient response.
The diode emulation feature is configured with the DEMB pin. To enable diode emulation, connect the DEMB pin
to GND or leave the pin floating. If continuous conduction operation is desired, the DEMB pin should be tied to a
voltage greater than 3V and may be connected to VCC. The LM25117 forces the regulator to operate in diode
emulation mode when SS pin voltage is less than the internal 0.8 V reference, allowing for startup into a pre-
biased load with the continuous conduction configuration.
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Product Folder Links: LM25117 LM25117-Q1
RLOAD
RS x AS
Where AM (Modulator DC gain) = ,
ZZ_ESR
1 +
VOUT
VCOMP = AM x
s
1+ s
ZP_LF
©
§¹
·
^
^
LM25117
,
LM25117-Q1
SNVS714F APRIL 2011REVISED AUGUST 2015
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM25117 is a step-down dc-dc controller. The device is typically used to convert a higher dc voltage to a
lower dc voltage. Use the following design procedure to select component values. Alternately, use the
WEBENCH® software to generate a complete design. The WEBENCH software uses an iterative design
procedure and accesses a comprehensive database of components when generating a design.
8.2 Typical Applications
Figure 29. 3.3 V, 9 A Typical Application Schematic
8.3 Detailed Design Procedure
8.3.1 Feedback Compensation
Open loop response of the regulator is defined as the product of modulator transfer function and feedback
transfer function. When plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and
feedback gain.
The modulator transfer function includes a power stage transfer function with an embedded current loop and can
be simplified as one pole and one zero system as shown in the following equations.
(15)
(16)
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K - 0.5
fSW
Zp_HF =
2 x ' x RS x RFB2 x AS x COUT
RCOMP
fCROSS = [Hz]
RFB2 x (CCOMP + CHF)
1
Where AFB (Feedback DC gain) = ,
RCOMP x CCOMP
1
wZ_EA (Low frequency zero) = ,
RCOMP x CHF
1
wP_EA (High frequency pole) =
=s
AFB x
ZP_EA
VOUT
^
VCOMP
^
-ZZ_EA
1 +
s
s x (1+ )
1
RLOAD x COUT
ZP_LF (Load pole) =
ZZ_ESR (ESR zero) = 1
RESR x COUT ,
LM25117
,
LM25117-Q1
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Detailed Design Procedure (continued)
(17)
(18)
If the ESR of COUT (RESR) is very small, the modulator transfer function can be further simplified to a one pole
system and the voltage loop can be closed with only two loop compensation components, RCOMP and CCOMP,
leaving a single pole response at the crossover frequency. A single pole response at the crossover frequency
yields a very stable loop with 90 degrees of phase margin.
The feedback transfer function includes the feedback resistor divider and loop compensation of the error
amplifier. RCOMP, CCOMP and optional CHF configure the error amplifier gain and phase characteristics and create
a pole at origin, a low frequency zero and a high frequency pole. This is shown mathematically in the following
equations.
(19)
(20)
The pole at the origin minimizes output steady state error. The low frequency zero should be placed to cancel the
load pole of the modulator. The high frequency pole can be used to cancel the zero created by the output
capacitor ESR or to decrease noise susceptibility of the error amplifier. By placing the low frequency zero an
order of magnitude less than the crossover frequency, the maximum amount of phase boost can be achieved at
the crossover frequency. The high frequency pole should be placed well beyond the crossover frequency since
the addition of CHF adds a pole in the feedback transfer function.
The crossover frequency (loop bandwidth) is usually selected between one twentieth and one fifth of the fSW. In a
simplified formula, the crossover frequency can be defined as:
(21)
For higher crossover frequency, RCOMP can be increased, while proportionally decreasing CCOMP. Conversely,
decreasing RCOMP while proportionally increasing CCOMP, results in lower bandwidth while keeping the same zero
frequency in the feedback transfer function.
The sampled gain inductor pole is inversely proportional to the K factor, which is defined as:
(22)
The maximum achievable loop bandwidth, in fact, is limited by this sampled gain inductor pole. In traditional
current mode control, the maximum achievable loop bandwidth varies with input voltage. With the LM25117’s
unique slope compensation scheme, the sampled gain inductor pole is independent of changes to the input
voltage. This frees the user from additional concerns in wide varying input range applications and is an
advantage of the LM25117.
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Product Folder Links: LM25117 LM25117-Q1
= 1 - K
1
dl0
dl1
Steady-State
Inductor
Current
dI0
dI1
tON
Inductor Current with
Initial Perturbation
LM25117
,
LM25117-Q1
SNVS714F APRIL 2011REVISED AUGUST 2015
www.ti.com
Detailed Design Procedure (continued)
If the sampled gain inductor pole or the ESR zero is close to the crossover frequency, it is recommended that the
comprehensive formulas in Table 1 be used and the stability should be checked by a network analyzer. The
modulator transfer function can be measured and the feedback transfer function can be configured for the
desired open loop transfer function. If a network analyzer is not available, step load transient tests can be
performed to verify acceptable performance. The step load goal is minimum overshoot/undershoot with a
damped response.
8.3.2 Sub-Harmonic Oscillation
Peak current mode regulators can exhibit unstable behavior when operating above 50% duty cycle. This
behavior is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the
SW pin. Sub-harmonic oscillation can be prevented by adding an additional voltage ramp (slope compensation)
on top of the sensed inductor current shown in Figure 20. By choosing K1, the regulator will not be subject to
sub-harmonic oscillation caused by a varying input voltage.
In time-domain analysis, the steady-state inductor current starts and ends at the same value during one clock
cycle. If the magnitude of the end-of-cycle current error, dI1, caused by an initial perturbation, dI0, is less than the
magnitude of dI0or dI1/dI0> -1, the perturbation naturally disappears after a few cycles. When dI1/dI0< -1, the
initial perturbation does not disappear, resulting in sub-harmonic oscillation in steady-state operation.
Figure 30. Effect of Initial Perturbation when dl1/dl0< -1
dI1/dI0can be calculated by:
(23)
The relationship between dI1/dI0and K factor is illustrated graphically in Figure 31.
Figure 31. dl1/dl0vs K Factor
The minimum value of K is 0.5. When K<0.5, the amplitude of dI1is greater than the amplitude of dI0and any
initial perturbation results in sub-harmonic oscillation. If K=1, any initial perturbation will be removed in one
switching cycle. This is known as one-cycle damping. When -1<dl1/dl0<0, any initial perturbation will be under-
damped. Any perturbation will be over-damped when 0<dl1/dl0<1.
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5.2 x 109
RT = 230 x 103- 948 = 21.7 k:
1
S(K-0.5)
Q =
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,
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Detailed Design Procedure (continued)
In the frequency-domain, Q, the quality factor of the sampling gain term in the modulator transfer function, is
used to predict the tendency for sub-harmonic oscillation, which is defined as:
(24)
The relationship between Q and K factor is illustrated graphically in Figure 32.
Figure 32. Sampling Gain Q vs K Factor
The minimum value of K is 0.5 again. This is the same as time domain analysis result. When K<0.5, the regulator
is unstable. High gain peaking at 0.5 results in sub-harmonic oscillation at FSW/2. When K=1, one-cycle damping
is realized. Q is equal to 0.673 at this point. A higher K factor may introduce additional phase shift by moving the
sampled gain inductor pole closer to the crossover frequency, but will help reduce noise sensitivity in the current
loop. The maximum allowable value of K factor can be calculated by the Maximum Crossover Frequency
equation in Table 1.
8.3.3 Design Requirements
DESIGN PARAMETER EXAMPLE VALUE
Output Voltage VOUT 3.3 V
Full Load Current IOUT 9 A
Minimum Input Voltage VIN(MIN) 6 V
Maximum Input Voltage VIN(MAX) 36 V
Switching Frequency fSW 230 kHz
Diode Emulation Yes
External VCC Supply No
8.3.4 Timing Resistor RT
Generally, higher frequency applications are smaller but have higher losses. Operation at 230 kHz was selected
for this example as a reasonable compromise between small size and high efficiency. The value of RTfor 230
kHz switching frequency can be calculated from Equation 3.
(25)
A standard value of 22.1kwas chosen for RT.
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¸
¹
·
¨
©
§36V
PRS = 1 - x 9A2 x 8 m: = 0.59W
3.3V
¸
¹
·
¨
©
§
VIN(MAX)
PRS = 1 - IOUT2 x RS
VOUT x[W]
9A x 1.5 + 230 kHz x 6.8 µH
3.3 x 1
RS = 0.12V = 7.9 m:
0.95A
2
_
RS = VCS(TH) >:@
IOUT(MAX) + fSW x LO
VOUT x K IPP
2
_
¸
¹
·
¨
©
§36V
IPP(MAX) = x 1 - 3.3V
3.3V
6.8 PH x 230 kHz = 1.9A
¸
¹
·
¨
©
§36V
LO = x 1 - 3.3V
3.3V
9A x 0.2 x 230 kHz = 7.2 PH
( )
OUT OUT
O
PP(MAX) SW IN MAX
V V
L 1 [H]
I f V
æ ö
ç ÷
= ´ -
ç ÷
´è ø
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8.3.5 Output Inductor LO
The maximum inductor ripple current occurs at the maximum input voltage. Typically, 20% to 40% of the full load
current is a good compromise between core loss and copper loss of the inductor. Higher ripple current allows for
a smaller inductor size, but places more of a burden on the output capacitor to smooth the ripple voltage on the
output. For this example, a ripple current of 20% of 9A was chosen. Knowing the switching frequency, maximum
ripple current, maximum input voltage and the nominal output voltage, the inductor value can be calculated as
follows:
(26)
(27)
The closest standard value of 6.8μH was chosen for LO. Using the value of 6.8μH for LO, calculate IPP again. This
step is necessary if the chosen value of LOdiffers significantly from the calculated value.
From Equation 11,
(28)
At the minimum input voltage, this value is 0.95A.
8.3.6 Diode Emulation Function
The DEMB pin is left floating since this example uses diode emulation to reduce the power loss under no load or
light load conditions.
8.3.7 Current Sense Resistor RS
The performance of the converter will vary depending on the K value. For this example, K=1 was chosen to
control sub-harmonic oscillation and achieve one-cycle damping. The maximum output current capability
(IOUT(MAX)) should be 20~50% higher than the required output current, to account for tolerances and ripple
current. For this example, 150% of 9A was chosen. The current sense resistor value can be calculated from
Equation 9 and Equation 10 as follows:
(29)
(30)
A value of 8mwas chosen for RS. A larger value resistor can be placed in parallel with RSto adjust the
maximum output current capability. The sense resistor must be rated to handle the power dissipation at
maximum input voltage when current flows through the low-side NMOS for the majority of the PWM cycle. The
maximum power dissipation of RScan be calculated as:
(31)
(32)
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PDC (Low-Side) = (1 ± D) x (IOUT2 x RDS(ON) x 1.3) [W]
PDC (High-Side) = D x (IOUT2 x RDS(ON) x 1.3) [W]
1.25V x 50 k:
5.7V - 1.25V
RUV1 = = 14.0 k:
1V
20 µA
RUV2 = = 50 k:
6.8 PH
1 x 820 pF x 8 m:x 10
RRAMP = = 104 k:
LO
K x CRAMP x RSx AS
RRAMP = [:@
8 m:6.8 PH
36V x 100 ns
+
ILIM_PK = 0.12V = 15.5A
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The worst case peak inductor current under the output short condition can be calculated from Equation 12 as
follows:
(33)
Where tON(MIN) is normally 100ns.
8.3.8 Current Sense Filter RCS and CCS
The LM25117 itself is not affected by the large leading edge spike because it samples valley current just prior to
the onset of the high-side switch. A current sense filter is used to minimize a noise injection from any external
noise sources. In general, a current sense filter is not necessary. In this example, a current sense filter is not
used
Adding RCS resistor changes the current sense amplifier gain which is defined as AS=10k / (1k+RCS). A small
value of RCS resistor below 100is recommended to minimize the gain change which is caused by the
temperature coefficient difference between internal and external resistors.
8.3.9 Ramp Resistor RRAMP and Ramp Capacitor CRAMP
The positive slope of the inductor current ramp signal is emulated by RRAMP and CRAMP. For this example, the
value of CRAMP was set at the standard capacitor value of 820pF. With the inductor, sense resistor and the K
factor selected, the value of RRAMP can be calculated from Equation 4 as follows:
(34)
(35)
The standard value of 105 kwas selected for RRAMP.
8.3.10 UVLO Divider RUV2, RUV1 and CFT
The desired startup voltage and the hysteresis are set by the voltage divider RUV1 and RUV2. Capacitor CFT
provides filtering for the divider. For this design, the startup voltage was set to 5.7V, 0.3V below VIN(MIN). VHYS
was set to 1V. The value of RUV1, RUV2 can be calculated from Equation 1 and Equation 2 as follows:
(36)
(37)
The standard value of 50kwas selected for RUV2. RUV1 was selected to be 14k. A value of 100pF was chosen
for CFT.
8.3.11 VCC Disable and External VCC Supply
In this example, VCCDIS is left floating to enable the internal VCC regulator.
8.3.12 Power Switches QHand QL
Selection of the power NMOS devices is governed by the same trade-offs as switching frequency. Breaking
down the losses in the high-side and low-side NMOS devices is one way to compare the relative efficiencies of
different devices. Losses in the power NMOS devices can be broken down into conduction loss, gate charging
loss, and switching loss.
Conduction loss PDC is approximately:
(38)
(39)
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CHB Qg
'VHB
t[F]
PSW = 0.5 x VIN x IOUT x (tR + tF) x fSW [W]
PGC = n x VVCC x Qg x fSW [W]
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Where D is the duty cycle and the factor of 1.3 accounts for the increase in the NMOS device on-resistance due
to heating. Alternatively, the factor of 1.3 can be eliminated and the high temperature on-resistance of the NMOS
device can be estimated using the RDS(ON) vs Temperature curves in the MOSFET datasheet.
Gate charging loss (PGC) results from the current driving the gate capacitance of the power NMOS devices and is
approximated as:
(40)
Qg refers to the total gate charge of an individual NMOS device, and ‘n’ is the number of NMOS devices. Gate
charge loss differs from conduction and switching losses in that the actual dissipation occurs in the controller IC.
Switching loss (PSW) occurs during the brief transition period as the high-side NMOS device turns on and off.
During the transition period both current and voltage are present in the channel of the NMOS device. The
switching loss can be approximated as:
(41)
tRand tFare the rise and fall times of the high-side NMOS device. The rise and fall times are usually mentioned
in the MOSFET datasheet or can be empirically observed with an oscilloscope. Switching loss is calculated for
the high-side NMOS device only. Switching loss in the low-side NMOS device is negligible because the body
diode of the low-side NMOS device turns on before and after the low-side NMOS device switches. For this
example, the maximum drain-to-source voltage applied to either NMOS device is 36V. The selected NMOS
devices must be able to withstand 36V plus any ringing from drain to source and must be able to handle at least
the VCC voltage plus any ringing from gate to source.
8.3.13 Snubber Components RSNB and CSNB
A resistor-capacitor snubber network across the low-side NMOS device reduces ringing and spikes at the
switching node. Excessive ringing and spikes can cause erratic operation and can couple noise to the output
voltage. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure
the lead lengths for the snubber connections are very short. Start with a resistor value between 5 and 50.
Increasing the value of the snubber capacitor results in more damping, but higher snubber losses. Select a
minimum value for the snubber capacitor that provides adequate damping of the spikes on the switch waveform
at heavy load. A snubber may not be necessary with an optimized layout.
8.3.14 Bootstrap Capacitor CHB and Bootstrap Diode DHB
The bootstrap capacitor between the HB and SW pin supplies the gate current to charge the high-side NMOS
device gate during each cycle’s turn-on and also supplies recovery charge for the bootstrap diode. These current
peaks can be several amperes. The recommended value of the bootstrap capacitor is at least 0.1μF. CHB should
be a good quality, low ESR, ceramic capacitor located at the pins of the IC to minimize potentially damaging
voltage transients caused by trace inductance. The absolute minimum value for the bootstrap capacitor is
calculated as:
(42)
Where Qg is the high-side NMOS gate charge and ΔVHB is the tolerable voltage droop on CHB, which is typically
less than 5% of VCC or 0.15V conservatively. A value of 0.47μF was selected for this design.
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0.047 µF x 0.8V
tSS = 10 µA= 3.8 ms
'VIN = 4 x 230 kHz x 2.2 PFx 7
9 A = 0.63 V
'VIN = 4 x x CIN
fSW
IOUT [V]
12
¸
¹
·
¨
©
§
8 x 230 kHz x 680 PF
'VOUT = 1.9 x 0.01:2 + =19 mV
12
¸
¹
·
¨
©
§8 x x COUT
fSW
'VOUT = IPP x RESR2 + [V]
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8.3.15 VCC Capacitor CVCC
The primary purpose of the VCC capacitor (CVCC) is to supply the peak transient currents of the LO driver and
bootstrap diode as well as provide stability for the VCC regulator. These peak currents can be several amperes.
The recommended value of CVCC should be no smaller than 0.47μF, and should be a good quality, low ESR,
ceramic capacitor. CVCC should be placed at the pins of the IC to minimize potentially damaging voltage
transients caused by trace inductance. A value of 1μF was selected for this design.
8.3.16 Output Capacitor CO
The output capacitors smooth the output voltage ripple caused by inductor ripple current and provide a source of
charge during transient loading conditions. For this design example, a 680μF electrolytic capacitor with maximum
10mESR was selected as the main output capacitor. The fundamental component of the output ripple voltage
with maximum ESR is approximated as:
(43)
(44)
Additional low ERS / ESL ceramic capacitors can be placed in parallel with the main output capacitor to further
reduce the output voltage ripple and spikes. In this example, two 22μF capacitors were added.
8.3.17 Input Capacitor CIN
The regulator input supply voltage typically has high source impedance at the switching frequency. Good quality
input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current
during the on-time. When the high-side NMOS device turns on, the current into the device steps to the valley of
the inductor current waveform, ramps up to the peak value, and then drops to the zero at turnoff. The input
capacitor should be selected for RMS current rating and minimum ripple voltage. A good approximation for the
required ripple current rating necessary is IRMS > IOUT / 2.
In this example, seven 2.2μF ceramic capacitors were used. With ceramic capacitors, the input ripple voltage will
be triangular. The input ripple voltage can be approximated as:
(45)
(46)
Capacitors connected in parallel should be evaluated for RMS current rating. The current will split between the
input capacitors based on the relative impedance of the capacitors at the switching frequency.
8.3.18 VIN Filter RVIN, CVIN
An R-C filter (RVIN, CVIN) on VIN is optional. The filter helps to prevent faults caused by high frequency switching
noise injection into the VIN pin. 0.47μF ceramic capacitor is used for CVIN in the example.
8.3.19 Soft-Start Capacitor CSS
The capacitor at the SS pin (CSS) determines the soft-start time (tSS), which is the time for the output voltage to
reach the final regulated value. The tSS for a given CSS can be calculated from Equation 8 as follows:
(47)
For this example, a value of 0.047μF was chosen for a soft-start time of 3.8ms.
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CHF 5 m: x 724 µF x 10 nF
27.4 k: x 10 nF - 5 m: x 724 µF
== 134 pF
CHF RESR x COUT x CCOMP
RCOMP x CCOMP - RESR x COUT
=[F]
CCOMP 27.4 k:
=x 724 µF
3.3V
9A = 10 nF
CCOMP RLOAD x COUT
RCOMP
=[F]
RCOMP = 2Sx 8 m: x 10 x 724 µF x 3.24 k: x 23 kHz = 27.1 k:
RCOMP = 2Sx RS x AS x COUT x RFB2 x fCROSS [:@
10
fCROSS = = 23 kHz
fSW
RFB2 - 1
RFB1 VOUT
0.8V
=
0.47 µF x 1.25V
10 µA= 59 ms
tRES =
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8.3.20 Restart Capacitor CRES
The capacitor at the RES pin (CRES) determines tRES, which is the time the LM25117 remains off before a restart
attempt is made in hiccup mode current limiting. tRES for a given CRES can be calculated from Equation 13 as
follows:
(48)
For this example, a value of 0.47μF was chosen for a restart time of 59ms.
8.3.21 Output Voltage Divider RFB2 and RFB1
RFB1 and RFB2 set the output voltage level. The ratio of these resistors is calculated as:
(49)
The ratio between RCOMP and RFB2 determines the mid-band gain, AFB_MID. A larger value for RFB2 may require a
corresponding larger value for RCOMP. RFB2 should be large enough to keep the total divider power dissipation
small. 3.24kwas chosen for RFB2 in this example, which results in a RFB1 value of 1.05kfor 3.3V output.
8.3.22 Loop Compensation Components CCOMP, RCOMP and CHF
RCOMP, CCOMP and CHF configure the error amplifier gain and phase characteristics to produce a stable voltage
loop. For a quick start, follow the 4 steps listed below.
STEP1: Select fCROSS
By selecting one tenth of the switching frequency, fCROSS is calculated as follows:
(50)
STEP2: Determine required RCOMP
Knowing fCROSS, RCOMP is calculated as follows:
(51)
(52)
The standard value of 27.4kwas selected for RCOMP
STEP3: Determine CCOMP to cancel load pole
Knowing RCOMP, CCOMP is calculated as follows:
(53)
(54)
The standard value of 10nF was selected for CCOMP
STEP4: Determine CHF to cancel ESR zero
Knowing RCOMP and CCOMP, CHF is calculated as follows:
(55)
(56)
Half of the maximum ESR is assumed as a typical ESR. The standard value of 150pF was selected for CHF.
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1
ZP_EA = RCOMP x CHF
1
ZP_EA = RCOMP x (CHF // CCOMP
)
ZZ_EA =RCOMP x CCOMP
1
ZZ_EA =RCOMP x CCOMP
1
AFB_MID = RCOMP
RFB2
AFB_MID = RCOMP
RFB2
AFB = 1
RFB2 x (CCOMP + CHF)
AFB = 1
RFB2 x (CCOMP + CHF)
=s
AFB x
ZP_EA
VOUT
^
VCOMP
^
-ZZ_EA
1 +
s
s x (1+ )
=s
AFB x
ZP_EA
VOUT
^
VCOMP
^
-ZZ_EA
1 +
s
s x (1+ )
K = 1
K = LO
RRAMP x CRAMP x RS x AS
2
fSW
Zn = ZSW
2=Sx fSW or fn =
Q = 1
S(K - 0.5)
ZP_HF Q x Zn
=
ZP_HF fSW
K 0.5
= or
ZP_LF = RLOAD x COUT
1
ZP_LF = (RLOAD + RESR1) x (COUT1 + COUT2)LO x (COUT1 + COUT2) x ZP_HF
1 1
+
RESR1
1
ZP_ESR = x (COUT1 // COUT2
)
ZZ_ESR = RESR
1
x COUT
ZZ_ESR = RESR1
1
x COUT1
AM = RLOAD
RS x AS x LO
ZP_HF
x 1
1 +
RLOAD
AM = RLOAD
RS x AS
(1 + )
ZZ_ESR
=s
VOUT
^
VCOMP
^AM x
ZP_LF
1 +
s
=
VOUT
^
VCOMP
^AM x ZZ_ESR
1 +
s
s
(1 + )
ZP_LF x(1 + )
ZP_ESR x(1 + + )
ss
ZP_HF s2
Zn2
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Table 1. LM25117 Frequency Analysis Formulas
SIMPLE FORMULA COMPREHENSIVE FORMULA(1)
Modulator
Transfer
Function
Modulator DC
Gain
ESR Zero
ESR Pole Not considered
Dominant Load
Pole
Sampled Gain Not considered
Inductor Pole
Quality Factor Not considered
Sub-harmonic Not considered
Double Pole
K Factor
Feedback
Transfer
Function
Feedback DC
Gain
Mid-band Gain
Low Frequency
Zero
High Frequency
Pole
(1) Comprehensive Equation includes an inductor pole and a gain peaking at fSW/2, which caused by sampling effect of the current mode
control. Also it assumes that a ceramic capacitor COUT2 (No ESR) is connected in parallel with COUT1. RESR1 represents ESR of COUT1 .
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 31
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fCROSS_MAX = fSW
5
fCROSS_MAX = fSW
4 x Q 1 + 4 x Q2-1
x ( )
ZP_EA = ZZ_ESR
ZZ_EA = ZP_LF
when &
fCROSS < ZP_HF
2 x S x 10
& & fCROSS < ZP_ESR
2 x S x 10
ZP_EA = ZZ_ESR
ZZ_EA = ZP_LF &
when
2 x ' x RS x RFB2 x AS x COUT
RCOMP
fCROSS =
2 x ' x RS x RFB2 x AS x (COUT1 + COUT2)
RCOMP
fCROSS =
ZZ_EA = ZP_LF
when
ZP_EA = ZZ_ESR
ZZ_EA = ZP_LF &
when
T(s) = s
AM x AFB xZZ_ESR
1 +
s
s
(1 + )
ZP_EA x(1 + )
ZP_ESR x(1 + + )
ss
ZP_HF s2
Zn2
T(s) AM x AFB
s
=
T(s) = AM x AFB x ZZ_EA
s
(1 + )
ZP_EA
1 +
s
s x
s
(1 + )
ZP_LF
x
ZZ_ESR
1 +
s
T(s) = AM x AFB x x
ZZ_ESR
1 +
s
s
(1 + )
ZP_LF x(1 + )
ZP_ESR x(1 + + )
ss
ZP_HF s2
Zn2s
(1 + )
ZP_EA
s x
ZZ_EA
1 +
s
LM25117
,
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Table 1. LM25117 Frequency Analysis Formulas (continued)
SIMPLE FORMULA COMPREHENSIVE FORMULA(1)
Open-Loop
Response
Crossover
Frequency
(Open Loop
Bandwidth)
Maximum
Crossover
Frequency The frequency at which 45° phase shift occurs in modulator phase
characteristics.
8.4 Application Curves
Figure 34. Typical Efficiency vs Load Current
Figure 33. Start-Up with Resistive Load
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VOUT
SS
RES
RT
COMP
FB
RAMP
PGND
CSG
CS
LO
SW
HO
HB
VCC
VIN
AGND
UVLO
VCCDIS
DEMB
CM
VIN
VOUT
SW
LM25117
CIN
QH
QL
CHB
DHB
CVCC
Hiccup Mode OVP
Triggered at 13.4V
CC Mode: 2A
100k:
15 k:
80 µF
68 µH
1500 pF
100 k:
22.1 k:0.47 µF
3.24 k:
2.37 k:
0.022 µF
47 m:
Current Control (CC)
3.24 k:
332:
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Application Curves (continued)
8.4.1 Constant Current Regulator
The LM25117 can be configured as a constant current regulator by using the current monitor feature (CM) as the
feedback input. A voltage divider at the VCCDIS pin from VOUT to AGND can be used to protect against output
over-voltage. When the VCCDIS pin voltage is greater than the VCCDIS threshold, the controller disables the
VCC regulator and the VCC pin voltage decays. When the VCC pin voltage is less than the VCC UV threshold,
both HO and LO outputs stop switching. Due to the time delay required for VCC to decay below the VCC UV
threshold, the over-voltage protection operates in hiccup mode. See Figure 35.
Figure 35. Constant Current Regulator with Hiccup Mode Output OVP
8.4.2 Constant Voltage and Constant Current Regulator
The LM25117 also can be configured as a constant voltage and constant current regulator, known as CV+CC
regulator. In this configuration, there is much less variation in the current limiting as compared to peak cycle-by-
cycle current limiting of the inductor current. The LMV431 and the PNP transistor create a voltage-to-current
amplifier in the current loop. This amplifier circuitry does not affect the normal operation when the output current
is less than the current limit set-point. When the output current is greater than the set-point, the PNP transistor
sources a current into CRAMP and increases the positive slope of emulated inductor current ramp until the output
current is less than or equal to the current limit set-point. See Figure 36 and Figure 37.
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VOUT
SS
RES
RT
COMP
FB
RAMP
PGND
CSG
CS
LO
SW
HO
HB
VCC
VIN
AGND
UVLO
VCCDIS
DEMB
CM
VIN
VOUT
SW
LM25117
CIN
QH
QL
Current Control (CC)
CHB
DHB
CVCC
VCC
Voltage Control (CV)
LMV431
CV Mode : 5V
CC Mode: 2A
100 k:
15 k:
80 PF
68 PH
1500 pF
100 k:
22.1 k:0.33 PF x2
3.24 k:
619:
34.8 k:0.1 PF
47 m:
1 nF
100 k:
10 k:100:
PNP
200 k:
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Application Curves (continued)
Figure 36. Constant Voltage Regulator with Accurate Current Limit
Figure 37. Current Limit Comparison
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Controller
VOUTGNDGNDVIN
Inductor
CIN
CIN
COUT
COUT
RSENSE
QH
QL
Place controller as
close to the switches
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9 Power Supply Recommendations
LM25117 is a power management device. The power supply for the device is any DC voltage source within the
specified input range.
10 Layout
10.1 Layout Guideline
Figure 38. Layout Example
10.1.1 PC Board Layout Recommendations
In a buck regulator the primary switching loop consists of the input capacitor, NMOS power switches and current
sense resistor. Minimizing the area of this loop reduces the stray inductance and minimizes noise and possible
erratic operation. High quality input capacitors should be placed as close as possible to the NMOS power
switches, with the VIN side of the capacitor connected directly to the high-side NMOS drain and the ground side
of the capacitor connected as close as possible to the current sense resistor ground connection.
Connect all of the low power ground connections (RUV1, RT, RFB1, CSS, CRES, CCM, CVIN, CRAMP) directly to the
regulator AGND pin. Connect CVCC directly to the regulator PGND pin. Note that CVIN and CVCC must be as
physically close as possible to the IC. AGND and PGND must be directly connected together through a top-side
copper pattern connected to the exposed pad. Ensure no high current flows beneath the underside exposed pad.
The LM25117 has an exposed thermal pad to aid power dissipation. Adding several vias under the exposed pad
helps conduct heat away from the IC. The junction to ambient thermal resistance varies with application. The
most significant variables are the area of copper in the PC board, the number of vias under the exposed pad and
the amount of forced air cooling. The integrity of the solder connection from the IC exposed pad to the PC board
is critical. Excessive voids greatly decrease the thermal dissipation capacity.
The highest power dissipating components are the two power switches. Selecting NMOS switches with exposed
pads aids the power dissipation of these devices.
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
LM25117 Click here Click here Click here Click here Click here
LM25117-Q1 Click here Click here Click here Click here Click here
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: LM25117 LM25117-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM25117PMH/NOPB ACTIVE HTSSOP PWP 20 73 RoHS & Green SN Level-3-260C-168 HR -40 to 125 LM25117
PMH
LM25117PMHE/NOPB ACTIVE HTSSOP PWP 20 250 RoHS & Green SN Level-3-260C-168 HR -40 to 125 LM25117
PMH
LM25117PMHX/NOPB ACTIVE HTSSOP PWP 20 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 LM25117
PMH
LM25117PSQ/NOPB ACTIVE WQFN RTW 24 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L25117P
LM25117PSQE/NOPB ACTIVE WQFN RTW 24 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L25117P
LM25117PSQX/NOPB ACTIVE WQFN RTW 24 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L25117P
LM25117QPMH/NOPB ACTIVE HTSSOP PWP 20 73 RoHS & Green SN Level-3-260C-168 HR -40 to 125 LM25117
QPMH
LM25117QPMHE/NOPB ACTIVE HTSSOP PWP 20 250 RoHS & Green SN Level-3-260C-168 HR -40 to 125 LM25117
QPMH
LM25117QPMHX/NOPB ACTIVE HTSSOP PWP 20 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 LM25117
QPMH
LM25117QPSQ/NOPB ACTIVE WQFN RTW 24 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L25117Q
LM25117QPSQE/NOPB ACTIVE WQFN RTW 24 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L25117Q
LM25117QPSQX/NOPB ACTIVE WQFN RTW 24 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L25117Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM25117, LM25117-Q1 :
Catalog: LM25117
Automotive: LM25117-Q1
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM25117PMHE/NOPB HTSSOP PWP 20 250 178.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
LM25117PMHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
LM25117PSQ/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM25117PSQE/NOPB WQFN RTW 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM25117PSQX/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM25117QPMHE/NOPB HTSSOP PWP 20 250 178.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
LM25117QPMHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
LM25117QPSQ/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM25117QPSQE/NOPB WQFN RTW 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM25117QPSQX/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM25117PMHE/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0
LM25117PMHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 38.0
LM25117PSQ/NOPB WQFN RTW 24 1000 210.0 185.0 35.0
LM25117PSQE/NOPB WQFN RTW 24 250 210.0 185.0 35.0
LM25117PSQX/NOPB WQFN RTW 24 4500 367.0 367.0 35.0
LM25117QPMHE/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0
LM25117QPMHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 38.0
LM25117QPSQ/NOPB WQFN RTW 24 1000 210.0 185.0 35.0
LM25117QPSQE/NOPB WQFN RTW 24 250 210.0 185.0 35.0
LM25117QPSQX/NOPB WQFN RTW 24 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 2
MECHANICAL DATA
PWP0020A
www.ti.com
MXA20A (Rev C)
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