MC10H131 Dual D Type Master-Slave Flip-Flop The MC10H131 is a MECL 10H part which is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in clock speed and propagation delay and no increase in power-supply current. * Propagation Delay, 1.0 ns Typical * Power Dissipation, 235 mW Typical * Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) * Voltage Compensated * MECL 10K-Compatible http://onsemi.com MARKING DIAGRAMS 16 CDIP-16 L SUFFIX CASE 620 MC10H131L AWLYYWW 1 LOGIC DIAGRAM 16 S1 5 D1 7 CE1 6 Q1 2 Q1 3 PDIP-16 P SUFFIX CASE 648 MC10H131P AWLYYWW 1 1 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 R1 4 CC 9 R2 13 CE2 11 D2 10 Q2 14 Q2 15 PLCC-20 FN SUFFIX CASE 775 A WL YY WW S2 12 CLOCKED TRUTH TABLE RS TRUTH TABLE R S L L Qn+1 Qn C D L X L H H H L L L L H H H H H N.D. ORDERING INFORMATION Device C = CE + CC A clock H is a clock transition from a low to a high state. DIP PIN ASSIGNMENT VCC1 1 16 Q1 2 15 VCC2 Q2 Q1 3 14 Q2 R1 4 13 R2 S1 5 12 S2 CE1 6 11 CE2 D1 7 10 D2 VEE 8 9 CC = Assembly Location = Wafer Lot = Year = Work Week Qn+1 Qn H N.D. = Not Defined 10H131 AWLYYWW Package Shipping MC10H131L CDIP-16 25 Units/Rail MC10H131P PDIP-16 25 Units/Rail MC10H131FN PLCC-20 46 Units/Rail Pin assignment is for Dual-in-Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). Semiconductor Components Industries, LLC, 2000 March, 2000 - Rev. 6 1 Publication Order Number: MC10H131/D MC10H131 MAXIMUM RATINGS Symbol Rating Unit VEE VI Power Supply (VCC = 0) Characteristic -8.0 to 0 Vdc Input Voltage (VCC = 0) 0 to VEE Vdc Iout Output Current - Continuous - Surge 50 100 mA TA Tstg Operating Temperature Range 0 to +75 C -55 to +150 -55 to +165 C C Storage Temperature Range - Plastic - Ceramic ELECTRICAL CHARACTERISTICS (VEE = -5.2 V 5%) (See Note 1.) 0 Symbol 75 Min Max Min Max Min Max Unit Power Supply Current - 62 - 56 - 62 mA IinH Input Current High Pins 6, 11 Pin 9 Pins 7, 10 Pins 4, 5, 12, 13 - - - - 530 660 485 790 - - - - 310 390 285 465 - - - - 310 390 285 465 IinL VOH VOL Input Current Low VIH VIL IE Characteristic 25 A 0.5 - 0.5 - 0.3 - A High Output Voltage -1.02 -0.84 -0.98 -0.81 -0.92 -0.735 Vdc Low Output Voltage -1.95 -1.63 -1.95 -1.63 -1.95 -1.60 Vdc High Input Voltage -1.17 -0.84 -1.13 -0.81 -1.07 -0.735 Vdc Low Input Voltage -1.95 -1.48 -1.95 -1.48 -1.95 -1.45 Vdc Propagation Delay Clock, CE Set, Reset 0.8 0.6 1.6 1.6 0.8 0.7 1.7 1.7 0.8 0.7 1.8 1.8 Rise Time 0.6 2.0 0.6 2.0 0.6 2.2 ns Fall Time 0.6 2.0 0.6 2.0 0.6 2.2 ns Set-up Time 0.7 - 0.7 - 0.7 - ns Hold Time 0.8 - 0.8 - 0.8 - ns AC PARAMETERS tpd tr tf tset thold ns ftog Toggle Frequency 250 - 250 - 250 - MHz 1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. APPLICATION INFORMATION In this case, the enable inputs perform the function of controlling the common clock. The output states of the flip-flop change on the positive transition of the clock. A change in the information present at the data (D) input will not affect the output information at any other time due to master slave construction. The MC10H131 is a dual master-slave type D flip-flop. Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock Enable (CE) inputs. Each flip-flop may be clocked separately by holding the common clock in the new low state and using the enable inputs for the clocking function. If the common clock is to be used to clock the flip-flop, the Clock Enable inputs must be in the low state. http://onsemi.com 2 MC10H131 PACKAGE DIMENSIONS PLCC-20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775-02 ISSUE C 0.007 (0.180) M T L-M B Y BRK -N- U N S 0.007 (0.180) M T L-M S S N S D -L- -M- Z W 20 D 1 G1 X V 0.010 (0.250) S T L-M S N S VIEW D-D A 0.007 (0.180) M T L-M S N S R 0.007 (0.180) M T L-M S N S 0.007 (0.180) M T L-M H S N S Z K1 K C E F 0.007 (0.180) M T L-M S 0.004 (0.100) G J -T- VIEW S G1 0.010 (0.250) S T L-M S N S VIEW S SEATING PLANE NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 3 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10 _ 0.310 0.330 0.040 --- MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10 _ 7.88 8.38 1.02 --- N S MC10H131 -A- 16 9 1 8 -B- CDIP-16 L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE T C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. L DIM A B C D E F G H K L M N -T- K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M -A- 9 1 8 B F C L S -T- SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R 16 S INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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