Hybrid Systems Sipex Carperator HS 3120 Double Buffered 12-Bit MDAC FEATURES Monolithic Construction 12 Bit Resolution 0.01% Non-Linearity LP Compatible 4-Quadrant Multiplication Latch-up Protected DESCRIPTION The HS 3120 is a precision monolithic 12-bit multiplying DAC with internal two-stage input storage registers for easy interfacing with microprocessor busses. It is packaged in a 28-pin DIP to give high I/O design flexibility. DOUBLE BUFFERED The input registers are sectioned into 3 segments of 4 bits each, all individually addressable. The DAC-register, following the input registers, is a parallel 12-bit register for holding the DAC data while the input registers are updated, Only the data held in the DAC register determines the analog output value of the converter. MICRO PROCESSOR COMPATIBLE The HS 3120 has been designed for great flexibility in connecting to bus- oriented systems, The 12 data inputs are organized into 3 independent addressable 4-bit input registers such that the HS 3120 can be connected to either a 4, 8 or 16-bit data bus. The control logic of the HS 3120 includes chip enable and latch enable inputs for flexible memory mapping. All FUNCTIONAL DIAGRAM controls are level-triggered to allow static or dynamic operation. VERSATILE OUTPUTS A total of 5 output lines are pro- vided by the HS 3120 to allow unipolar and bipolar output connection with a minimum of external components, The feedback resistor is internal. The resistor ladder network termination is externally available, thus eliminating an external resistor for the 1 LSB offset in bipolar mode. MONOLITHIC CMOS CONSTRUCTION The HS 3120 is a one-chip CMOS circuit with a resistor ladder network de- signed for 0.01% linearity without laser trimming. Small chip size and high manufacturing yields result in greatly reduced cost. (MSB} (LSB) BIT) 2 3 4 5 6 7 8 9 10 11 BITI2 VReF 090 90 00900 e 9 9 6 9| 10 11 12 13 14 5) 16 T7{ 18] 19] 20 4 Xow ry INPUT REGISTER - INPUT REGISTER -- INPUT REGISTER 25 HBEO CONTROL LoGic ITF me 0-24 | = LBE OS LDAC 21 DAC REGISTER > 12 BIT MDAC HS 3120 i 27 Ypo1 ve Vpp2 ~~ GND 8 GND LDTR 143SPECIFICATIONS (Typical @ 25C, nominal power supply, VREF = +10V, unipolar unless otherwise noted). MODEL HS 3120-2 HS 3120-0 TYPE MULTIPLYING, DOUBLE BUFFERED INPUTS * DIGITAL INPUT Resolution 12-Bits * 2- Quad. Unipolar Coding Binary !, Comp. Binary! * 4-Quad. Bipolar Coding Offset Binary * Logic Compatibility CMOS, TTL * Input Current +1 pA (max) * Data Set-up Times 250nS (min) * Strobe Width 250nS (min) * Data Hold Times OnS (min) * REFERENCE INPUT Voltage Range +25V (max) * Input Impedance Bk +50% * ANALOG OUTPUT Scale Factor 125LA/V Ret 250% * Scale Factor Accuracy4 $0.4% * Output Leakage @ 25C <10nA (max) * @ 126C <200nA (max) * Output Capacitance Cour 1, all inputs high 80pF * Cour 1, all inputs low 40pF * CourT 2. ali inputs high 40pF * Cour 2, ali inputs low 80pF * STATIC PERFORMANCE {ntegral Linearity Differential Linearity Monotonicity Monotonicity Temp. Range C-Models B-Mode!s DYNAMIC PERFORMANCE Digital Small Signal Settling Full Scale Transition Settling to 0.01% (strobed) Reference Feedthrough Error (VRe = 20Vpp) @ 1kHz @ 10kHz Delay to output from Bits input from LDAC from CE STABILITY (Over Specified Temp. Range) +0,015% F.S.R, (max) +0.024% F.S.R. (max) Guaranteed to 12 bits 0C to +70C -55C to +126C 1 .Ousec 2.Ousec <1mV 2mv 100ns8 200ns8 120ns6 +0,05 % F.S.R. (max) +0,097% F.S.R. (max) Guaranteed to 10 bits * * Seale Factor4 Integral Linearity Differential Linearity Monotonicity Temp, Range C-Option B-Option POWER SUPPLY (Vpp) 2 ppm F.S.R./C (max) 0.2 ppm F.S.R./C (max) 0.2 ppm F.S.R./C (max) 0C to +70C -55C to +125C Operating Voltage (specifications guaranteed) Maximum Voltage Range Current Rejection Ratio TEMPERATURE RANGE +15V 15% +5V to 16V 2.5mA {max} 0.002%/% (max) xe KX Operating C-Option Operating B-Option 0C to +70C -58C to +125C Storage -65C to +150C * MECHANICAL Case Style 28-pin double DIP * C-Option plastic or ceramic * B-Option ceramic * NOTES: * Same as HS 3120-2 1. The input coding is complementary binary if Io2 is used. 2. Digital input voltage must not exceed supply voltage or go below ~0.5V. "0" <O,BV, 2.4V <1" <Vpop. 3. Alli strobes are level triggered. See TIMING DIAGRAM. 4. Using the internal feedback resistor and an external opamp. 5. The output leakage current will create an offset voltage at the external opamps output. It doubles every 10C temperature increase. 6. Delay times are twice the amount shown at Ta = +1 25C 144PIN ASSIGNMENTS PIN FUNCTION 1 FBqg, Feedback Bipolar Operation 2 LOTR, Ladder Termination 3 FB3, Feedback Bipolar Operation 4 VReF. Reference Voltage Input 5 FBy, Feedback, Unipolar/Bipolar 6 191, Current out into virtual ground 7 192, Current out-complement of I94 8 Vgs, Ground, Analog and DAC Register 9 Bit 1, MSB 10 Bit 2 11 Bit 3 12 Bit 4 13 Bit 5 14 Bit 6 15 Bit 7 16 Bit 8 17 Bit 9 18 Bit 10 19 Bit 11 20 Bit 12 21 LDAC, Transfers data from input to DAC register 22 CE, Chip Enable, active low 23 LBE, Bit 12 to Bit 9 Enable 24 MBE, Bit 8 to Bit 5 Enable 25 HBE, Bit 4 to Bit 1 Enable 26 Vpp2. Supply Analog and DAC Register 27 Vss1, Ground input latches 28 Vpp1, Supply input latches NOTE: Pins 8 and 27 and pins 26 and 28 must be connected externally. MECHANICAL TOP VIEW =-SU,, fo + 254) PIN | lf 0.05. (1,27) ; oj F L 9.17 0.05 0.610 (4.3) (1.27) (15.49) go pt DIMENSIONS } 0,006 inch 0,85 (0.152) immi (2.16) Le ifouy TYP CONNECTIONS Unipolar Operation: Connect Io and FB, as shown in diagram. Tie Iq (Pin 7), FB3 (Pin 3), FBg, (Pin 1) all to Ground (Pin 8} Connect Io1, 192, FB1, FB3, FBq as shown in diagram. Tie LDTR tol 92 Bipolar Operation: Grounding: Connect all GRD to system analog ground and tie this to digital ground. NOTE: All unused input pins must be grounded. APPLICATIONS INFORMATION Connection Diagram, Unipolar Operation 4002 VREF +15V Yop2 |Yop1 l ( 1 DIGITAL INPUTS HS 3120 | | | { o1 cEO Ygs |ss1 HBE | MBE O- = LBE OI = LDAC OJ Connection Diagram, Bipolar Operation 4002 VREF +15V Ypp2 | Yoo1 i t ( DIGITAL INPUTS HS 3120 eo_! Ros2 Vss | Vss1 HBE MBE O LBE O___" Lbac O__ _ 3 1o2 Ky 3K LDTA yn Vout 1 At, A2, LF411ACN Connection Diagram, Bipolar Operation (for applications where bipolar offset temperature drift (~ 10 ppm/C) is not critical} NOTE: To maintain specified linearity, external amplifiers must be zeroed. This is best done with Vp_er set to zero and, Unipolar: load the DAC register with all bits at zero and adjust Rog for Vouy = OV Bipolar: load the DAC register with 10... .0 (MSB =1) and set Rosz for Vout 1 = OV. Then set Rosi for TRANSFER FUNCTION (N=12) BINARY INPUT | UNIPOLAR OUTPUT] BIPOLAR OUTPUT 4...411 ~VRe_er (1-2-N) -Vper (1-2 -(N-1)) 100... 001 Vref (1/2+2-N) | -Vper (2 -(N- 1)) 100... 000 -VREF 0 2 o1i...141 -Vre_r (1/2 - 2-N} Vaer (2-(N- 1) 000... 000 0 VREF 145BIPOLAR OFFSET ADJUST (external) -15V +15V 20k 4M ADJUSTMENT RANGE 0,2% TO Io1 NOTE: External opamps have to be zeroed before the bipolar offset adjust circuit is connected. CONTROL LOGIC CE 9 ape [tf >)} TO INPUT REGISTER BIT 1- BIT 4 MBE O _f }- TO INPUT REGISTER BIT 5 - BIT 8 isco] TO INPUT REGISTER BIT 9. BIT 12 LOAC O_--_-_ _ TO DAC REGISTER NOTE: The transfer from input register to DAC register can be performed without Enabling Chip. STROBE LOGIC Strobe Function 0 data latched (held) 1 data changing (transfer) TIMING DIAGRAM INPUT DATA |e | 7 HBE LDAC | >| ty | Ly OUTPUT by el ty be TIME AXIS NOT TO SCALE. ALL STROBES ARE LEVEL TRIGGERED. ty Data Setup Time. Time data must be stable before strobe (byte enable/LDAC) goes to 0", ty (min) = 250 nsec. tg: Strobe Width. tg (min) = 250 nsec. (CE, LBE, MBE, HBE, LDAC). tz Hold Time. Time data must be stable after strobe goes to 0, tz = O nsec. ta Delay from LDAC to Output. ty = 200 nsec. NOTE: Minimum common active time for CE and any byte enable is 250 nsec. 146 ORDERING INFORMATION MODEL DESCRIPTION HS 3120C-0 Double Buffered 12-Bit MDAC, Commercial HS 3120C-2 Double Buffered 12-Bit MDAC, Commercial HS 3120B-0 Double Buttered 12-Bit MDAC, MIL-STD-883C HS 3120B-2 Doubte Buffered 12-Bit MDAC, MIL-STD-883C CAUTION: ESD (Electro-Static Discharge) sensitive de- vice. Permanent damage may occur when unconnected devices are subjected to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. Protective foam should be discharged to the destin- ation socket before devices are removed. Devices should be handled at static safe workstations only. Unused dig- ital inputs must be grounded or tied to the logic supply voltage. Unless otherwise noted, the supply voltage at any digital input should never exceed the supply voltage by more than 0.5 volts or go below -0.5 volts. If this condition cannot be maintained, limit input current on digital in- puts by using series resistors or contact Hybrid Systems for technical assistance. Specifications subject to change without notice.