Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-08513 Rev. *C Revised June 28, 2017
MB3773
Power Supply Monitor with
Watch-Dog Timer
Description
MB3773 generates the reset signal to protect an arbitrary system when the power-supply voltage momentarily is intercepted or
decreased. It is IC for the power-supply voltage watch and “Power on reset” is generated at the normal return of the power supply.
MB3773 sends the microprocessor the reset signal when decreasing more than the voltage, which the power supply of the system
specified, and the computer data is protected from an accidental deletion.
In addition, the watch-dog timer for the operation diagnosis of the system is built into, and various microprocessor systems can provide
the fail-safe function. If MB3773 does not receive the clock pulse from the processor for a specified period, MB3773 generates the
reset signal.
Features
■Precision voltage detection (VS = 4.2 V ± 2.5%)
■Detection threshold voltage has hysteresis function
■Low voltage output for reset signal (VCC = 0.8 V Typ)
■Precision reference voltage output (VR = 1.245 V ± 1.5%)
■With built-in watch-dog timer of edge trigger input.
■External parts are few.(1 piece in capacity)
■The reset signal outputs the positive and negative both theories reason.
■One type of package (SOP-8pin : 1 type)
Application
■Industrial Equipment
■Arcade Amusement etc.
Document Number: 002-08513 Rev. *C Page 2 of 28
MB3773
Contents
Description ............................................................................. 1
Features .................................................................................. 1
Application ............................................................................. 1
Contents ................................................................................. 2
1. Pin Assignment ................................................................. 3
2. Block Diagram ................................................................... 3
3. Functional Descriptions .................................................... 4
4. Operation Sequence .......................................................... 6
5. Absolute Maximum Ratings ............................................ 7
6. Recommended Operating Conditions ............................. 7
7. Electrical Characteristics .................................................. 8
7.1 DC Characteristics ..................................................... 8
7.2 AC Characteristics ...................................................... 9
8. Typical Characteristic Curves ........................................ 10
9. Application Circuit ........................................................... 13
10. Notes on Use .................................................................. 25
11. Ordering Information ..................................................... 25
12. RoHS Compliance Information of Lead (Pb)
Free version ......................................................................... 25
13. Package Dimension ....................................................... 26
Document History ................................................................ 27
Sales, Solutions, and Legal Information ........................... 28
Document Number: 002-08513 Rev. *C Page 3 of 28
MB3773
1. Pin Assignment
2. Block Diagram
(SOE008)
CT
RESET
CK
GND VCC
VREF
VS
RESET
(TOP VIEW)
1
2
3
4
8
7
6
5
CT
+
_
+
_
82
7
3
1
4
5
GND
RESET
VS
VC
R
S
Q
≈ 1.24 V
≈ 40 kΩ
≈ 1.24 V
≈ 10 μA
≈ 1.2 μA
≈ 100
kΩ
Watch-
Dog
Timer
P.G
+
_
Reference Voltage Generator +
_
Reference AMP
VREF
6
COMP.O
RESET
≈ 10 μA
Inhibit
CK
COMP.S
Document Number: 002-08513 Rev. *C Page 4 of 28
MB3773
3. Functional Descriptions
Comp.S is comparator including hysteresis. it compare the reference voltage and the voltage of Vs, so that when the voltage of Vs
terminal falls below approximately 1.23 V, reset signal outputs.
Instantaneous breaks or drops in the power can be detected as abnormal conditions by the MB3773 within a 2 μs interval.
However because momentary breaks or drops of this duration do not cause problems in actual systems in some cases, a delayed
trigger function can be created by connecting capacitors to the Vs terminal.
Comp.O is comparator for turning on/off the RESET/RESET outputs and, compare the voltage of the CT terminal and the threshold
voltage. Because the RESET/RESET outputs have built-in pull-up circuit, there is no need to connect to external pull-up resistor when
connected to a high impedance load such as CMOS logic IC.
(It corresponds to 500 kΩ at Vcc = 5 V.) when the voltage of the CK terminal changes from the “high” level into the “Low” level, pulse
generator is sent to the watch-dog timer by generating the pulse momentarily at the time of drop from the threshold level.
When power-supply voltages fall more than detecting voltages, the watch-dog timer becomes an interdiction.
The Reference amplifier is an op-amp to output the reference voltage.
If the comparator is put up outside, two or more power-supply voltage monitor and overvoltage monitor can be done.
If it uses a comparator of the open-collector output, and the output of the comparator is connected with the Vs terminal of MB3773
without the pull-up resistor, it is possible to voltage monitor with reset-hold time.
Document Number: 002-08513 Rev. *C Page 5 of 28
MB3773
RESET
V
CC
V
SH
V
SL
0.8 V
CK
C
T
T
CK
T
PR
T
WD
T
WR
T
PR
(1) (2) (3)(4)(5) (5) (6) (7) (8)(9) (10) (11) (12)
MB3773 Basic Operation
VCC
RESET
RESET
CK
Logic Circuit
TPR (ms) ≈1000 · CT (μF)
TWD (ms) ≈100 · CT (μF)
TWR (ms) ≈20 · CT (μF)
Example : CT = 0.1 μF
TRR (ms) ≈ 100 (ms)
TWD (ms) ≈ 10 (ms)
TWR (ms) ≈ 2 (ms)
RESET
RESET
CK
GND
CT
VCC
Document Number: 002-08513 Rev. *C Page 6 of 28
MB3773
4. Operation Sequence
1. When Vcc rises to about 0.8 V, RESET goes “Low” and RESET goes “High”.
The pull-up current of approximately 1 μA (Vcc = 0.8 V) is output from RESET.
2. When Vcc rises to VSH (≈ 4.3V), the charge with CT starts.
At this time, the output is being reset.
3. When CT begins charging, RESET goes “High” and RESET goes “Low”.
After TPR reset of the output is released.
Reset hold time: TPR (ms) ≈ 1000 × CT (μF)
After releasing reset, the discharge of CT starts, and watch-dog timer operation starts.
TPR is not influenced by the CK input.
4. C changes from the discharge into the charge if the clock (Negative edge) is input to the CK terminal while discharging CT.
5. C changes from the charge into the discharge when the voltage of CT reaches a constant
threshold (≈ 1.4 V).
4 and 5 are repeated while a normal clock is input by the logic system.
6. When the clock is cut off, gets, and the voltage of CT falls on threshold (≈ 0.4 V) of reset on, RESET goes “Low” and RESET goes
“High”.
Discharge time of CT until reset is output: TWD is watch-dog timer monitoring time.
TWD (ms) ≈ 100 × CT (μF)
Because the charging time of CT is added at accurate time from stop of the clock and getting to the output of reset of the clock,
TWD becomes maximum TWD + TWR by minimum TWD.
7. Reset time in operating watch-dog timer: TWR is charging time where the voltage of CT goes up to off
threshold (≈ 1.4 V) for reset.
TWR (ms) ≈ 20 × CT (μF)
Reset of the output is released after CT reaches an off threshold for reset, and CT starts the discharge, after that if the clock is
normally input, operation repeats 4 and 5, when the clock is cut off, operationrepeats 6 and 7.
8. When Vcc falls on VSL (≈ 4.2 V), reset is output. CT is rapidly discharged of at the same time.
9. When Vcc goes up to VSH, the charge with CT is started.
When Vcc is momentarily low,
After falling VSL or less Vcc, the time to going up is the standard value of the Vcc input pulse width in VSH or more.
After the charge of CT is discharged, the charge is started if it is TPI or more.
10.Reset of the output is released after TPR, after Vcc becomes VSH or more, and the watch-dog timer starts. After that, when Vcc
becomes VSL or less, 8 to 10 is repeated.
11.While power supply is off, when Vcc becomes VSL or less, reset is output.
12.The reset output is maintained until Vcc becomes 0.8 V when Vcc falls on 0 V.
Document Number: 002-08513 Rev. *C Page 7 of 28
MB3773
5. Absolute Maximum Ratings
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of absolute maximum ratings. Do not exceed these ratings.
6. Recommended Operating Conditions
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device.All of the device’s electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their Cypress representatives
beforehand.
Parameter Symbol
Rating
Unit
Min Max
Supply voltage VCC - 0.3 + 18 V
Input voltage
VS- 0.3 VCC + 0.3 ( ≤ +18) V
VCK - 0.3 + 18 V
RESET, RESET Supply voltage VOH - 0.3 VCC + 0.3 ( ≤ +18) V
Power dissipation (Ta ≤ +85°C) PD— 200 mW
Storage temperature TSTG - 55 + 125 °C
Parameter Symbol
Value
Unit
Min Max
Supply voltage VCC + 3.5 + 16 V
RESET, RESET sink current IOL 020mA
VREF output current IOUT - 200 + 5 μA
Watch clock setting time tWD 0.1 1000 ms
CK Rising/falling time tFC, tRC — 100 μs
Terminal capacitance CT0.001 10 μF
Operating ambient temperature Ta - 40 + 85 °C
Document Number: 002-08513 Rev. *C Page 8 of 28
MB3773
7. Electrical Characteristics
7.1 DC Characteristics
(VCC = 5 V, Ta = + 25°C)
Parameter Symbol Condition
Value
Unit
Min Typ Max
Supply current ICC Watch-dog timer operating — 600 900 μA
Detection voltage
VSL
VCC 4.10 4.20 4.30
V
Ta = - 40°C to + 85°C 4.05 4.20 4.35
VSH
VCC 4.20 4.30 4.40
Ta = - 40°C to + 85°C 4.15 4.30 4.45
Hysteresis width VHYS VCC 50 100 150 mV
Reference voltage VREF
— 1.227 1.245 1.263
V
Ta = - 40°C to + 85°C 1.215 1.245 1.275
Reference voltage change rate ∆VREF1 VCC = 3.5 V to 16 V — 3 10 mV
Reference voltage output
loading change rate ∆VREF2 IOUT = - 200 μA to + 5 μA- 5—+ 5mV
CK threshold voltage VTH Ta = - 40°C to + 85°C 0.8 1.25 2.0 V
CK input current
IIH VCK = 5.0 V — 0 1.0
μA
IIL VCK = 0.0 V - 1.0 - 0.1 —
CT discharge current ICTD
Watch-dog timer operating
VCT = 1.0 V 71014μA
High level output voltage
VOH1 VS open, IRESET = - 5 μA4.54.9—
V
VOH2 VS = 0 V, IRESET = - 5 μA4.54.9—
Output saturation voltage
VOL1 VS = 0 V, IRESET = 3 mA — 0.2 0.4
V
VOL2 VS = 0 V, IRESET = 10 mA — 0.3 0.5
VOL3 VS open, IRESET = 3 mA — 0.2 0.4
VOL4 VS open, IRESET = 10 mA — 0.3 0.5
Output sink current
IOL1 VS = 0 V, VRESET = 1.0 V 20 60 —
mA
IOL2 VS open, VRESET = 1.0 V 20 60 —
CT charge current ICTU
Power on reset operating
VCT = 1.0 V 0.5 1.2 2.5 μA
Min supply voltage for RESET VCCL1
VRESET = 0.4 V,
IRESET = 0.2 mA —0.81.2V
Min supply voltage for RESET VCCL2
VRESET = VCC - 0.1 V,
RL (between pin 2 and GND) = 1 MΩ—0.81.2V
Document Number: 002-08513 Rev. *C Page 9 of 28
MB3773
7.2 AC Characteristics
(VCC = 5 V, Ta = + 25°C)
* : Output rising/falling time are measured at 10 % to 90 % of voltage.
Parameter Symbol Condition Value Unit
Min Typ Max
VCC input pulse width TPI VCC 8.0 — — μs
CK input pulse width TCKW CK 3.0 — — μs
CK input frequency TCK —20——μs
Watch-dog timer watching time TWD CT = 0.1 μF51015ms
Watch-dog timer reset time TWR CT = 0.1 μF123ms
Rising reset hold time TPR CT = 0.1 μF, VCC 50 100 150 ms
Output propagation
delay time from VCC
TPD1
RESET, RL = 2.2 kΩ,
CL = 100 pF —210
μs
TPD2
RESET, RL = 2.2 kΩ,
CL = 100 pF —310
Output rising time* tR
RL = 2.2 kΩ,
CL = 100 pF —1.01.5
μs
Output falling time* tF
RL = 2.2 kΩ,
CL = 100 pF —0.10.5
5 V
4 V
or
Document Number: 002-08513 Rev. *C Page 10 of 28
MB3773
8. Typical Characteristic Curves
(Continued)
6.0
5.0
4.0
3.0
2.0
1.0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
Ta = + 85 °C
Ta = + 25 °C
Ta = − 40 °C
4.50
4.44
4.30
4.20
4.10
4.00
−40 −20 0 +20 +40 +60 +80 +100
VSH
VSL
400
300
200
0 2.0 10.0 12.0 14.0 16.04.0 6.0 8.0 18.0
100
CT = 0.1μF
Ta = + 85 °C
Ta = − 40 °C
Ta = + 25 °C
400
300
200
100
0 2.0 10.0 12.0 14.0 16.04.0 6.0 8.0 18.0
CT = 0.1μF
Ta = −40 °C
Ta = +25 °C
Ta = +85 °C
500
(RESET, RESET terminal)
Supply current vs. Supply voltage
Supply voltage VCC (V) Supply voltage VCC (V)
Output voltage vs. Supply voltage
(RESET terminal)
Supply voltage VCC (V)
Pull up 2.2 kΩ
Output voltage vs. Supply voltage
(RESET terminal)
Detection voltage (VSH, VSL) vs.
Operating ambient temperature
Operating ambient temperature Ta (°C)
Output saturation voltage
vs. Output sink current
(RESET terminal)
Output sink current IOL2 (mA)
Output saturation voltage
vs. Output sink current
(RESET terminal)
Output sink current IOL8 (mA)
Pull up 2.2 kΩ
Supply current ICC (mA)
Output voltage VRESET (V)
Detection voltage VSH, VSL (V)
Output voltage VRESET (V)
Output saturation voltage VOL2 (mV)
Output saturation voltage VOL2 (mV)
0.65
0.75
0.55
0.45
0.35
0.25
0.15
0 4.02.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0
Ta = − 40 °C
Ta = − 40 °C
Ta = + 25 °C
Ta = + 85 °C
CT = 0.1 μF
Ta = + 25 °CTa = + 85 °C
6.0
5.0
4.0
3.0
2.0
1.0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
Ta = − 40 °C, + 25 °C, + 85 °C
Document Number: 002-08513 Rev. *C Page 11 of 28
MB3773
(Continued)
Ta = +25 °C
Ta = +85 °C
Ta = −40 °C
C
T
= 0.1 μF
5.0
4.5
4.0 0−5−10 −15
5.0
4.5
4.0 0−5−10 −15
CT = 0.1 μF
Ta = +25 °C
Ta = +85 °C
Ta = −40 °C
1.246
1.244
1.242
1.240
1.238
1.236
1.234
0 3.0 5.0 7.0 9.0 13.011.0 17.0 19.0 21.015.0
Ta = −40 °C
Ta = +25 °C
Ta = +85 °C
C
T
= 0.1 μF
Ta = +85 °C
1.255
1.250
1.245
1.240
0−40 −80 −120 −160 −200 −240
C
T
= 0.1 μF
Ta = +25 °C
Ta = −40 °C
−20 0 +20−40
1.27
1.25
1.26
1.24
1.23
1.22
1.21
+40 +60 +80 +100
−20 0 +20−40 +40 +60 +80 +100
160
140
120
100
80
60
0
40
CT = 0.1 μF
VCC = 5 V
Reference voltage
vs. Reference current
High level output voltage
vs. High level output current
(RESET terminal)
High level output voltage
vs. High level output current
(RESET terminal)
Reference voltage
vs. Supply voltage
Supply voltage VCC (V) Reference current IREF (μA)
Reference voltage vs.
Operating ambient temperature
Operating ambient temperature Ta (°C)
Rising reset hold time vs.
Operating ambient temperature
Operating ambient temperature Ta (°C)
High level output current IOH2 (μA) High level output current IOH8 (μA)
High level output voltage VOH2 (V)
High level output voltage VOH8 (V)
Reference voltage VREF (V)
Reference voltage VREF (V)
Reference voltage VREF (V)
Rising reset hold time TPR (ms)
Document Number: 002-08513 Rev. *C Page 12 of 28
MB3773
(Continued)
3
2
1
0−40 −20 +200 +40 +60 +80 +100
C
T
= 0.1 μF
V
CC
= 5 V
−40 −20 +200 +40 +60 +80 +100
16
14
12
10
8
6
4
0
CT = 0.1 μF
VCC = 5 V
10
6
10
5
10
4
10
3
10
2
10
1
10
0
10
−1
10
−2
10
−3
10
−3
10
−2
10
−1
10
0
10
1
10
2
Ta = −40 °C
Ta =
+25 °C, +85 °C
10
−
3
10
−
2
10
−
1
10
0
10
1
10
2
10 2
10 1
10 0
10 −1
10 −2
10 −3
Ta = +25 °C,
+85 °C
Ta =
−40 °C
10
6
10
5
10
4
10
3
10
2
10
1
10
0
10
−1
10
−2
10
−3
10
−3
10
−2
10
−1
10
0
10
1
10
2
Ta = −40 °C
Ta = +25 °C, +85 °C
Rising reset hold time vs.
CT terminal capacitance
Watch-dog timer watching time vs.
Operating ambient temperature
Operating ambient temperature Ta (°C)
Reset time vs.
Operating ambient temperature
Operating ambient temperature Ta (°C)
CT terminal capacitance CT (μF)
(At watch-dog timer)
Reset time vs.
CT terminal capacitance
Watch-dog timer watching time
vs.
CT terminal capacitance
CT terminal capacitance CT (μF)
(at watch-dog timer)
CT terminal capacitance CT (μF)
Reset time TWR (ms)
Watch-dog timer
watching time TWD (ms)
Rising reset hold time TPR (ms)
Reset time TWR (ms)
Watch-dog timer
watching time TWD (ms)
10
−
3
10
−
2
10
−
1
10
0
10
1
10
2
10 2
10 1
10 0
10 −1
10 −2
10 −3
Ta = +25 °C,
+85 °C
Ta =
−40 °C
Document Number: 002-08513 Rev. *C Page 13 of 28
MB3773
9. Application Circuit
EXAMPLE 1: Monitoring 5V Supply Voltage and Watch-dog Timer
VCC (5V)
MB3773
RESET
RESET
CK
GND
Logic circuit
Notes :
• Supply voltage is monitored using VS.
• Detection voltage are VSH and VSL.
CT
1
2
3
4
8
7
6
5
EXAMPLE 2: 5V Supply Voltage Monitoring (external fine-tuning type)
VCC (5V)
1
2
3
4
8
7
6
5
MB3773
RESET
RESET
CK
GND
Logic circuit
Notes :
• Vs detection voltage can be adjusted externally.
• Based on selecting R1 and R2 values that are sufficiently lower than the resistance of the IC’s internal voltage
divider, the detection voltage can be set according to the resistance ratio of R1 and R2 (Refer to the table
below.)
R1
R2
CT
R1 (kΩ)R
2 (kΩ) Detection voltage: VSL (V) Detection voltage: VSH (V)
10 3.9 4.4 4.5
9.1 3.9 4.1 4.2
Document Number: 002-08513 Rev. *C Page 14 of 28
MB3773
EXAMPLE 3: With Forced Reset (with reset hold)
VCC
1
2
3
4
8
7
6
5
MB3773
RESET
RESET
CK
GND
Logic circuit
Note : Grounding pin 7 at the time of SW ON sets RESET (pin 8) to Low and RESET (pin 2) to High.
SW
VCC
1
2
3
4
8
7
6
5
MB3773
RESET
RESET
CK
GND
Logic circuit
Note : Feeding the signal to terminal RESIN and turning on Tr sets the RESET terminal to Low and the
RESET terminal to High.
10 kΩ
Tr
RESIN
10 kΩ
Cr
CT
(a)
(b)
Document Number: 002-08513 Rev. *C Page 15 of 28
MB3773
EXAMPLE 4: Monitoring Two Supply Voltages (with hysteresis, reset output and NMI)
VCC1 (5
1
2
3
4
8
7
6
5
MB3773
RESET
RESET
CK
GND
Comp. 2
Example : Comp. 1, Comp. 2
: MB4204, MB47393
NMI or port
R6
+
_
+
_
VCC2(12
180 kΩ
R4
30 kΩ
R3
5.1 kΩ
R2
1.2 kΩ
R1
4.7 kΩ
R5
Comp. 1
Notes :
• The 5 V supply voltage is monitored by the MB3773.
• The 12 V supply voltage is monitored by the external circuit. Its output is connected to the NMI terminal and, when
voltage drops, Comp. 2 interrupts the logic circuit.
•Use V
CC1 ( = 5 V) to power the comparators (Comp. 1 and Comp. 2) in the external circuit shown above.
• The detection voltage of the VCC2 ( = 12 V) supply voltage is approximately 9.2 V/9.4 V and has a hysteresis width
of approximately 0.2 V.
VCC2 detection voltage and hysteresis width can be found using the following formulas:
→ Detection voltage
→ Hysteresis width VHYS = V2H − V2L
R3 + (R4 // R5)
R4 // R5
× VREF
V2L = R3 + R5
R5
× VREF
(Approximately 9.4 V in the above illustration)
(Approximately 9.2 V in the above illustration)
CT
Logic circuit
V2H =
10 kΩ
Document Number: 002-08513 Rev. *C Page 16 of 28
MB3773
EXAMPLE 5: Monitoring Two Supply Voltages (with hysteresis and reset output)
VCC1 (5 V)
1
2
3
4
8
7
6
5
MB3773
RESET
RESET
CK
GND
Comp. 2
Example : Comp. 1, Comp. 2
: MB4204, MB47393
20 kΩ
R6
+
_
+
_
VCC2 (12
180 kΩ
R4
30 kΩ
R3
5.1 kΩ
R2
1.2 kΩ
R1
4.7 kΩ
R5
Comp. 1
Notes :
• When either 5 V or 12 V supply voltage decreases below its detection voltage (VSL), the MB3773 RESET terminal
is set to High and the MB3773 RESET terminal is set to Low.
• Use VCC1 ( = 5 V) to power the comparators (Comp. 1 and Comp. 2) in the external circuit shown above.
• The detection voltage of the VCC2 ( = 12 V) supply voltage is approximately 9.2 V/9.4 V and has a hysteresis width
of approximately 0.2 V. For the formulas for finding hysteresis width and detection voltage, refer to section 4.
Logic circuit
Diode
CT
Document Number: 002-08513 Rev. *C Page 17 of 28
MB3773
EXAMPLE 6: Monitoring Low voltage and Overvoltage Monitoring (with hysteresis)
VCC (5
1
2
3
4
8
7
6
5
MB3773
RESET
RESET
CK
GND
Comp. 2
Example : Comp. 1, Comp. 2
: MB4204, MB47393
20 kΩ
R6
_
+
180 kΩ
R4
30 kΩ
R3
5.6 kΩ
R6
1.2 kΩ
R1
4.7 kΩ
R5
Comp. 1
Notes :
• Comp. 1 and Comp. 2 are used to monitor for overvoltage while the MB3773 is used to monitor for low voltage.
Detection voltages V1L/V1H at the time of low voltage are approximately 4.2 V/4.3 V. Detection voltages V2L/V2H at
the time of overvoltage are approximately 6.0 V/6.1 V.For the formulas for finding hysteresis width and detection
voltage, see EXAMPLE 4.
•Use V
CC ( = 5 V) to power the comparators (Comp. 1 and Comp. 2) in the external circuit shown above.
Logic circuit
Diode
RESET
0V1L V1H V2L V2H
VCC
+
_
CT
Document Number: 002-08513 Rev. *C Page 18 of 28
MB3773
EXAMPLE 7: Monitoring Supply Voltage Using Delayed Trigger
VCC
1
2
3
4
8
7
6
5
MB3773
RESET
RESET
CK
GND
Logic circuit
Note : Adding voltage such as shown in the figure to VCC increases the minimum input pulse
width by 50 μs (C1 = 1000 pF).
C1
VCC
5V
4V
CT
Document Number: 002-08513 Rev. *C Page 19 of 28
MB3773
(Continued)
EXAMPLE 8: Stopping Watch-dog Timer (Monitoring only supply voltage)
(a) Using NPN transistor
These are example application circuits in which the MB3773 monitors supply voltage alone without resetting the micropro-
cessor even if the latter, used in standby mode, stops sending the clock pulse to the MB3773.
• The watch-dog timer is inhibited by clamping the CT terminal voltage to VREF.
The supply voltage is constantly monitored even while the watch-dog timer is inhibited.
For this reason, a reset signal is output at the occurrence of either instantaneous disruption or a sudden drop to low voltage.
Note that in application examples (a) and (b), the hold signal is inactive when the watch-dog timer is inhibited at the time of
resetting.
If the hold signal is active when tie microprocessor is reset, the solution is to add a gate, as in examples (c) and (d).
VCC(5 V)
1
2
3
4
8
7
6
5
MB3773
RESET
RESET
CK
GND
Logic circuit
R2=1 kΩ
HALT
R1=1 MΩ
(b) Using PNP transistor
VCC (5 V)
1
2
3
4
8
7
6
5
MB3773
RESET
RESET
CK
GND
Logic circuit
R2=1 kΩ
HALT
R1=51
CT
CT
Document Number: 002-08513 Rev. *C Page 20 of 28
MB3773
(Continued)
(c) Using NPN transistor
VCC (5 V)
1
2
3
4
8
7
6
5
CT
MB3773
RESET
RESET
CK
GND
Logic circuit
R2=1 kΩ
HALT
R1=1 MΩ
(d) Using PNP transistor
VCC (5 V)
1
2
3
4
8
7
6
5
CT
MB3773
RESET
RESET
CK
GND
Logic circuit
R2=1 kΩ
HALT
R1=51 kΩ
Document Number: 002-08513 Rev. *C Page 21 of 28
MB3773
EXAMPLE 9: Reducing Reset Hold Time
VCC( = 5 V)
1
2
3
4
8
7
6
5
CT
MB3773
RESET
RESET
CK
GND
Logic circuit
(a) TPR reduction method
VCC ( = 5 V)
1
2
3
4
8
7
6
5
CT
MB3773
RESET
RESET
CK
GND
Logic circuit
Notes :
• RESET is the only output that can be used.
• Standard TPR, TWD and TWR value can be found using the following formulas.
Formulas:TPR (ms) ≈ 100 × CT (μF)
TWD (ms) ≈ 100 × CT (μF)
TWR (ms) ≈ 16 × CT (μF)
• The above formulas become standard values in determining TPR, TWD and TWR.
Reset hold time is compared below between the reduction circuit and the standard circuit.
(b) Standard usage
CT = 0.1 μF
TPR reduction circuit Standard circuit
TPR ≈10 ms 100 ms
TWD ≈10 ms 10 ms
TWR ≈1.6 ms 2.0 ms
Document Number: 002-08513 Rev. *C Page 22 of 28
MB3773
EXAMPLE 10: Circuit for Monitoring Multiple Microprocessor
VCC ( = 5
1
2
3
4
8
7
6
5
CT
MB3773
RESET
RESET
CK
GND
Notes :
• connects from FF1 and FF2 outputs Q1 and Q2 to the NOR input.
• Depending on timing, these connections may not be necessary.
•Example : R
1 = R2 = 2.2 kΩ
CT = 0.1 μF
RESET
RESET
CK
GND
RESET
RESET
CK
GND
S
D3
CK
R
Q3
Q3
S
D2
CK2
R
Q2
Q2
S
D1
CK
R
Q1
Q1
FF3FF2FF1
R2
R1
CK1
Q1
CK2
Q2
CK3
Q3
NOR
Output
Figure 1
Figure 2
***
*: Microprocessor
Document Number: 002-08513 Rev. *C Page 23 of 28
MB3773
Description of Application Circuits
Using one MB3773, this application circuit monitors multiple microprocessor in one system. Signals from each microprocessor are
sent to FF1, FF2 and FF3 clock inputs. Figure 2 shows these timings. Each flip-flop operates using signals sent from microprocessor
as its clock pulse. When even one signal stops, the relevant receiving flip-flop stops operating. As a result, cyclical pulses are not
generated at output Q3. Since the clock pulse stops arriving at the CK terminal of the MB3773, the MB3773 generates a reset signal.
Note that output Q3 frequency f will be in the following range, where the clock frequencies of CK1, CK2 and CK3 are f1, f2 and f3
respectively.
where f0 is the lowest frequency among f1, f2 and f3.
1
f0
---- 1
f
---1
f1
---- 1
f2
---- 1
f3
----
++≤≤
Document Number: 002-08513 Rev. *C Page 24 of 28
MB3773
CRT1
0.01 μF10 kΩ30 μs
0.1 μF10 k
Ω300 μs
EXAMPLE 11: Circuit for Limiting Upper Clock Input Frequency
Notes :
• This is an example application to limit upper frequency fH of clock pulses sent from the microprocessor.
If the CK cycle sent from the microprocessor exceeds fH, the circuit generates a reset signal.
(The lower frequency has already been set using CT.)
• When a clock pulse such as shown below is sent to terminal CK, a short T2 prevents C2 voltage from reaching the
CK input threshold level ( := 1.25 V), and will cause a reset signal to be output.
The T1 value can be found using the following formula :
Example : Setting C and R allow the upper T1 value to be set (Refer to the table below).
VCC (5 V)
1
2
3
4
8
7
6
5
CT
RESET
RESET
CK
GND
R2
R1=10 kΩ
C2
Tr1
T1 ≈ 0.3 C2R2
T2
CK waveform
T3
C2 voltage T
where VCC = 5 V, T3 ≥ 3.0 μs, T2 ≥ 20 μs
Document Number: 002-08513 Rev. *C Page 25 of 28
MB3773
10. Notes on Use
■Take account of common impedance when designing the earth line on a printed wiring board.
■Take measures against static electricity.
❐For semiconductors, use antistatic or conductive containers.
❐When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container.
❐The work table, tools and measuring instruments must be grounded.
❐The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series.
■Do not apply a negative voltage
❐Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in
malfunction.
11. Ordering Information
12. RoHS Compliance Information of Lead (Pb) Free version
The LSI products of Cypress with “E1” are compliant with RoHS Directive , and has observed the standard of lead, cadmium, mercury,
Hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE) .
The product that conforms to this standard is added “E1” at the end of the part number.
Part number Package Remarks
MB3773PF-❏❏❏E1 8-pin plastic SOP
(SOE008) –
Document Number: 002-08513 Rev. *C Page 26 of 28
MB3773
13. Package Dimension
$//',0(16,216$5(,10,//,0(7(5
',0(16,21,1*$1'72/(5$1&,1*3(5$60(<0
',0(16,21,1*',1&/8'(02/')/$6+',0(16,21,1*('2(6127,1&/8'(
,17(5/($')/$6+253527586,21,17(5/($')/$6+253527586,216
6+$//127(;&(('PP3(56,'('DQG(',0(16,21$5('(7(50,1('
$7'$780+
7+(3$&.$*(7230$<%(60$//(57+$17+(3$&.$*(%27720
',0(16,21,1*'DQG($5('(7(50,1('$77+(287(50267
(;75(0(62)7+(3/$67,&%2'<(;&/86,9(2)02/')/$6+
7+(%$5%8556*$7(%8556$1',17(5/($')/$6+%87,1&/8',1*
$1<0,60$7&+%(7:((17+(723$1'%277202)7+(3/$67,&%2'<
'$7806$%72%('(7(50,1('$7'$780+
1,67+(0$;,080180%(52)7(50,1$/326,7,216)257+(63(&,),('
3$&.$*(/(1*7+
7+(',0(16,21$33/<727+()/$76(&7,212)7+(/($'%(7:((1PP
72PP)5207+(/($'7,3
',0(16,21E'2(6127,1&/8'(7+('$0%$53527586,21$//2:$%/(
'$0%$53527586,216+$//%(PP727$/,1(;&(662)7+(E',0(16,21
$70$;,0800$7(5,$/&21',7,21
7+('$0%$50$<127%(/2&$7('217+(/2:(55$',862)7+()227
7+,6&+$0)(5)($785(,6237,21$//),7,612735(6(177+(1$3,1
,'(17,),(50867%(/2&$7(':,7+,17+(,1'(;$5($,1',&$7('
$,6'(),1('$67+(9(57,&$/',67$1&()5207+(6($7,1*3/$1(72
7+(/2:(6732,17217+(3$&.$*(%2'<(;&/8',1*7+(/,'$1'25
7+(50$/(1+$1&(0(1721&$9,7<'2:13$&.$*(&21),*85$7,216
127(6
L11.25 REF
L
c
0.45
0.13
0.60 0.75
0.20
NOM.MIN.
7.80 BSC
E
0°
D
A
1A
6.35 BSC
0.05
SYMBOL
MAX.
8°
2.25
0.20
ș
E15.30 BSC
b0.39 0.47 0.55
e1.27 BSC
DIMENSION
L20.25 BSC
11. JEDEC SPECIFICATION NO. REF : N/A
D
4
5
E1 E
0.40 CA-B D
A
A1
10
DETAIL A
e0.10 C
SEATING
PLANE
b0.13 CA-B D8
SIDE VIEW
TOP VIEW
b
SECTION A-A'
c
L1
L
GAUGE
PLANE
DETAIL A
L2
șA
A'
0.25 H D
;
0.25 H D
㻭㻰
㻯
4
5
INDEX AREA
;
㻮
BOTTOM VIEW
Package Code: SOE008
002-15857 Rev. **
Document Number: 002-08513 Rev. *C Page 27 of 28
MB3773
Document History
Spansion Publication Number: DS04-27401-8Ea
Document Title: MB3773 Power Supply Monitor with Watch-Dog Timer
Document Number: 002-08513
Revision ECN Orig. of
Change
Submission
Date Description of Change
** – TAOA 05/11/2006 Migrated to Cypress and assigned document number 002-08513.
No change to document contents or format.
*A 5199075 TAOA 04/04/2016 Updated to Cypress format.
*B 5592858 HIXT 01/23/2017
Updated Pin Assignment: Change the package name from FPT-8P-M01 to SOE008
Updated Ordering Information: Change the package name from FPT-8P-M01 to SOE008
Updated Package Dimension: Updated to Cypress format
Deleted “Marking Format (Lead Free version)”
Deleted “Labeling Sample (Lead free version)”
Deleted “MB3773PF-❏❏❏E1 Recommended Conditions of Moisture Sensitivity Level”
Deleted the part number, “MB3773PF-❏❏❏”, from Ordering Information
Deleted the words in the Remarks, “Lead Free version”, from Ordering Information
*C 5788613 MASG 06/28/2017 Adapted Cypress new logo.
Document Number: 002-08513 Rev. *C Revised June 28, 2017 Page 28 of 28
© Cypress Semiconductor Corporation, 2003-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners..
ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
MB3773
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