dsPIC30F4011/4012
DS70135D-page 224 © 2006 Microchip Technology Inc.
Data EEPROM Memory...................................................... 51
Erasing........................................................................ 52
Erasing, Block .............................................................52
Erasing, Word ............................................................. 52
Protection Against Spurious Write ..............................55
Reading....................................................................... 51
Write Verify ................................................................. 55
Writing......................................................................... 53
Writing, Block ..............................................................54
Writing, Word ..............................................................53
DC Characteristics ............................................................ 171
BOR .......................................................................... 178
I/O Pin Input Specifications....................................... 176
I/O Pin Output Specifications ....................................177
Idle Current (IIDLE) .................................................... 174
Operating Current (IDD)............................................. 173
Power-Down Current (IPD) ........................................ 175
Program and EEPROM............................................. 178
DC Temperature and Voltage Specifications .................... 172
Dead-Time Generators ....................................................... 96
Ranges........................................................................ 97
Development Support ....................................................... 167
Device Configuration
Register Map.............................................................158
Device Configuration Registers......................................... 156
FBORPOR ................................................................ 156
FGS........................................................................... 156
FOSC ........................................................................ 156
FWDT........................................................................ 156
Divide Support..................................................................... 16
DSP Engine......................................................................... 16
Multiplier...................................................................... 18
dsPIC30F4011 Port Register Map ...................................... 59
dsPIC30F4012 Port Register Map ...................................... 60
Dual Output Compare Match Mode ....................................82
Continuous Output Pulse Mode .................................. 82
Single Output Pulse Mode ..........................................82
E
Edge-Aligned PWM............................................................. 95
Electrical Characteristics................................................... 171
Equations
A/D Conversion Clock...............................................136
Baud Rate ................................................................. 119
I2CBRG Value ..........................................................112
PWM Period................................................................94
PWM Period (Center-Aligned Mode) .......................... 94
PWM Resolution ......................................................... 94
Time Quantum for Clock Generation ........................ 129
Errata .................................................................................... 6
External Interrupt Requests ................................................ 43
F
Fast Context Saving............................................................43
Flash Program Memory....................................................... 45
In-Circuit Serial Programming (ICSP) ......................... 45
Run-Time Self-Programming (RTSP) ......................... 45
Table Instruction Operation Summary ........................45
I
I/O Ports
Parallel I/O (PIO)......................................................... 57
I2C Module
10-bit Slave Mode Operation .................................... 109
Reception.......................................................... 110
Transmission..................................................... 110
7-bit Slave Mode Operation ...................................... 109
Reception ......................................................... 109
Transmission .................................................... 109
Addresses................................................................. 109
Automatic Clock Stretch ........................................... 110
During 10-bit Addressing (STREN = 1) ............ 110
During 7-bit Addressing (STREN = 1) .............. 110
Reception ......................................................... 110
Transmission .................................................... 110
General Call Address Support .................................. 111
Interrupts .................................................................. 111
IPMI Support............................................................. 111
Master Operation...................................................... 111
Baud Rate Generator (BRG) ............................ 112
Clock Operation................................................ 112
Multi-Master Communication, Bus
Collision and Arbitration............................ 112
Reception ......................................................... 112
Transmission .................................................... 111
Master Support ......................................................... 111
Operating Function Description ................................ 107
Operation During CPU Sleep and
Idle Modes ........................................................ 112
Pin Configuration ...................................................... 107
Programmer’s Model ................................................ 107
Register Map ............................................................ 113
Registers .................................................................. 107
Slope Control............................................................ 111
Software Controlled Clock Stretching
(STREN = 1)..................................................... 110
Various Modes.......................................................... 107
In-Circuit Serial Programming (ICSP)............................... 145
Independent PWM Output .................................................. 98
Initialization Condition for RCON Register, Case 2 .......... 154
Initialization Condition for RCON Register, Case 1 .......... 154
Input Capture Module ......................................................... 77
In CPU Idle Mode ....................................................... 79
In CPU Sleep Mode.................................................... 78
Interrupts .................................................................... 79
Register Map .............................................................. 80
Simple Capture Event Mode....................................... 78
Input Change Notification Module....................................... 61
Register Map (bits 7-0) ............................................... 61
Input Diagrams
QEA/QEB Input ........................................................ 194
Instruction Addressing Modes ............................................ 33
File Register Instructions ............................................ 33
Fundamental Modes Supported ................................. 33
MAC Instructions ........................................................ 34
MCU Instructions ........................................................ 33
Move and Accumulator Instructions............................ 34
Other Instructions ....................................................... 34
Instruction Set Overview................................................... 162
Instruction Set Summary .................................................. 159
Internal Clock Timing Examples ....................................... 182
Internet Address ............................................................... 228
Interrupt Controller
Register Map .............................................................. 44
Interrupt Priority .................................................................. 40
Interrupt Sequence ............................................................. 43
Interrupt Stack Frame................................................. 43