Virtex-4 FPGA User Guide www.xilinx.com UG070 (v2.6) December 1, 2008
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Revision History
The following table shows the revision history for this document.
R
Date Version Revision
08/02/04 1.0 Initial Xilinx release. Printed Handbook version.
09/10/04 1.1 In Chapter 1, “Clock Resources”:
Removed Table 1-6: "BUFGMUX_VIRTEX4 Attributes". Updated Table 1-1, Table 1-2,
Table 1-5, the new Table 1-6. Revised Figure 1-2, Figure 1-5, Figure 1-6, Figure 1-7,
Figure 1-9, Figure 1-10, Figure 1-13, Figure 1-14, and Figure 1-16. Associated text around
these tables and figures were revised.
In Chapter 2, “Digital Clock Managers (DCMs)”, changes to “FACTORY_JF Attribute” and
in Table 2-6.
In Chapter 9, “System Monitor”:
Changed in Figure 9-4, Figure 9-5, Figure 9-7, Figure 9-8, Figure 9-9, Figure 9-10, Figure 9-21,
Figure 9-25, Figure 9-26, and Figure 9-27. Changes to the equation in the Temperature Sensor
section. The following tables had changes: Table 9-3, Table 9-5, Table 9-6, Table 9-9, Table 9-
11, Table 9-12, Table 9-14, and Table 9-15. Changes to the entire System Monitor Calibration,
System Monitor VHDL and Verilog Design Example sections.
02/01/05 1.2 In Chapter 1, “Clock Resources”, revised “Global Clock Buffers”, “Clock Regions”, and
“Clock Capable I/O” sections.
In Chapter 4, “Block RAM,” revised “Reset,” page 151 description and Table 4-13.
In Chapter 6, “SelectIO Resources,” removed the device configuration section. The Virtex-4
Configuration Guide describes this information in detail. Edited “SSTL (Stub-Series
Terminated Logic),” page 281. Replaced LVDS_25_DCI with LVDCI_25 in “Compatible
example:,” page 302. Added rule “7” to “DCI in Virtex-4 FPGA Hardware,” page 241. Added
“Simultaneous Switching Output Limits,” page 306.
Removed Chapter 9: System Monitor.