Lattice Semi conductor Home Page: http://www.latticesemi.com Applications & Li terature Hotline: 1-800-LATTICE
Copyright 2003 Latt i ce Sem i conduct or Cor porati on. Latt ic e Sem i conduct or, L(styl i zed) Lat ti ce S em ic onductor Corporat i on, Lat ti ce ( design), ISP , I n-Sy stem Program m abl e, E2CMOS , SuperFAST , G AL, i spGAL, i spLEVER and ispVM are
either r egi stered tr adem arks or t radem arks of Lat ti ce S em ic onductor Corporat ion i n t he Uni ted St ates and/or other c ountr ies. O ther product nam es used in thi s publi cat i ons are f or i denti f i cat i on purposes only and m ay be the t radem ark s
of t heir respective companies.
32-Pin QFN
February 2003 #PB1164
Lattice Releases World ’ s Fastest and Smallest PLD
Industry’s First Low-Power, 1.8-Volt ISP™ 22V10
Available in Space-Saving 32-Pin QFN Package
Introduction
Lattice Semiconductor, the pioneer of ISP technology and the leading
supplier of low-density CMOS PLDs, is pleased to announce the imm ediate
availability of its ispGAL®22V10A SuperFAST™, high-performance in-
system programmable E2CMOS SPLD family. The ispGAL22V10A family
of devices delivers SuperFAST performance with 2.3ns pin-to-pin delays
(tPD), 2.0ns clock-to-output delays (tCO), 1.3ns set-up times (tSU) and
455MHz operating frequencies (fMAX). The ispGAL22V10A family is offered
in the space-saving 32-Pin QFN (Quad Flat-pack No-lead) package along
with the 28-Pin PLCC. The 32- Pin QFN is 84% sm aller (5m m x 5m m) , 80% thinner
(0.9mm) and 95% lighter (0.06 grams) and has 50% better electrical packaging parasitics than the 28-Pin PLCC
package, which makes it ideal for high-density PCBs used in small-scale electronic applications such as cellular
phones, pagers and PDAs. This family of devices is off ered in 1.8, 2.5 and 3.3-volt power supply versions, designated
as the ispGAL22V10AC, ispGAL22V10AB, and ispGAL22V10AV devices, respectively. The ispGAL22V10A family
provides enhanced I/O support including LVCMOS 3.3V, 2.5V and 1.8V outputs independent of core supply voltage in
the QFN pack age. The I/Os on the is pG AL22V10A f amily are 5-volt tolerant to fac ilitate connec tion to legac y chips and
interfaces. The ispGAL22V10A is functionally compatible with the ispGAL22LV10, GAL22LV10 and GAL22V10.
ispGAL22V10A Family Members
ispGAL22V10AV ispGAL22V10AB ispGAL22V10AC
tPD (ns) 2.3* 2.3* 2.3*
tSU (ns) 1.3 1.3 1.3
tCO (ns) 2.0 2.0 2.0
fMAX (MHz) 455 455 455
Static Icc (Typ) 7 mA 7 mA 150 µA
Supply Voltage (V) 3.3V 2.5V 1.8V
Packages 32-Pin QFN
28-Pin PLCC 32-Pin QFN
28-Pin PLCC 32-Pin QFN
28-Pin PLCC
*QFN only/2.8ns in PLCC
Product
Bulletin
5 mm
Lattice Semi conductor Home Page: http://www.latticesemi.com Applications & Li terature Hotline: 1-800-LATTICE
Copyright 2003 Latt i ce Sem i conduct or Cor porati on. Latt ic e Sem i conduct or, L(styl i zed) Lat ti ce S em ic onductor Corporat i on, Lat ti ce ( design), ISP , I n-Sy stem Program m abl e, E2CMOS , SuperFAST , G AL, i spGAL, i spLEVER and ispVM are
either r egi stered tr adem arks or t radem arks of Lat ti ce S em ic onductor Corporat ion i n t he Uni ted St ates and/or other c ountr ies. O ther product nam es used in thi s publi cat i ons are f or i denti f i cat i on purposes only and m ay be the t radem ark s
of t heir respective companies.
32-Pin QFN
Actual Size
ispGAL22V10A Family Features
High Performance
• fMAX = 455MHz (QFN)/363MHz (PLCC) maximum
operating frequency
• tPD = 2.3ns (QFN)/2.8ns (PLCC)
• tCO = 2.0ns (QFN)/2.5ns (PLCC) maximum from clock
input to data output
• tSU = 1.3ns (QFN)/2.0ns (PLCC) clock set-up time
Low Power
• 1.8V core E2CMOS technology
• CMOS design techniques provide low static and
dynamic power
• Low (<300µW) standby current (ispGAL22V10AC)
Space Saving QFN Package
• Available in 32-Pin QFN (Quad Flat-pack, No-lead)
In-System Programmable
• IEEE 1149.1 boundary scan testable
• 3.3V.2.5V/1.8V in-system programmable (ISP) using
IEEE 1532 compliant interface
Boundary Scan USERCODE Register
• Supports electronic identification
Easy System Integration
• Operation with 3.3V, 2.5V or 1.8V supplies
• 3.3V, 2.5V or 1.8V LVCMOS inputs and outputs
independent of core supply voltage (QFN package) *
• 5 tolerant I/O for LVCMOS 3.3, LVTTL and PCI
interface
• Hot socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Programmable output slew rate
• 3.3V PCI compatible
E2 Cell Technology
• In-system programmable logic
• 100% tested/100% yields
• High speed electrical erasure (<50ms)
Applications Include
• DMA control
• State machine control
• High speed graphics processing
• Software-driven hardware configuration
*For PLCC package, I/O supply voltage is tied to Vcc.
Product Availability and Pricing
The ispGAL22V10A fa mily of devices is available now in the 28-Pin PLCC pac k age as
well as the space saving 32-Pin QFN package. Pricing, in high volumes, will be less
than $1.00.
Softw are and Programming Support
The ispGAL22V10A family will be supported in our new software platform ispLEVER™ Version 3.0 SP 2003.01.
Programming support will be through Lattice’s ispVM™ version 13.0 software, which is downloadable from
http://www.latticesemi.com/products/devtools/software/index.cfm.
Literature Ite m s
Datasheet, Application/Tec hnical Notes and related literature for the is pGAL22V10A fam ily can be f ound on the Lattice
Semiconductor web site at http://www.latticesemi.com.
Summary
The ispGAL22V10A family of devices combines the industry standard 22V10 architecture with in-system
programmability, industry leading performance, low static power and space-saving packaging to support today’s high
performance systems.