935272008125 - NXP - Pdf.Support

DATA SH EET

Product speciﬁcation

Supersedes data of 2001 Apr 06 2002 May 15

INTEGRATED CIRCUITS

74HC1G126; 74HCT1G126

Bus buffer/line driver; 3-state

2002 May 15 2

Philips Semiconductors Product speciﬁcation

Bus buffer/line driver; 3-state 74HC1G126; 74HCT1G126

FEATURES

•Wide operating voltage from 2.0 to 6.0 V

•Symmetrical output impedance

•High noise immunity

•Low power dissipation

•Balanced propagation delays

•Very small 5 pins package

•Output capability: bus driver.

DESCRIPTION

The 74HC1G/HCT1G126 is a highspeed Si-gate CMOS

device.

The 74HC1G/HCT1G126 provides one non-inverting

buffer/line driver with 3-state output. The 3-state output is

controlled by the output enable input pin (OE). A LOW at

pin OE causes the output as assume a high-impedance

OFF-state.

The bus driver output currents are equal compared to the

74HC/HCT126.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25°C; tr=r

f≤6.0 ns.

Notes

1. CPD is used to determine the dynamic power dissipation (PDin µW).

PD=C

PD ×VCC2×fi+(C

L×V

CC2×fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in Volts.

2. For HC1G the conditions is VI= GND to VCC.

For HCT1G the conditions is VI= GND to VCC −1.5 V.

FUNCTION TABLE

See note 1.

Note

1. H = HIGH voltage level;

L = LOW voltage level;

X = don’t care;

Z = high-impedance OFF-state.

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

HC1G HCT1G

tPHL/tPLH propagation delay A to Y CL= 15 pF; VCC = 5 V 9 10 ns

CIinput capacitance 1.5 1.5 pF

CPD power dissipation capacitance notes 1 and 2 30 27 pF

INPUTS OUTPUT

OE A Y

HLL

HHH

LXZ

2002 May 15 3

Philips Semiconductors Product speciﬁcation

Bus buffer/line driver; 3-state 74HC1G126; 74HCT1G126

ORDERING INFORMATION

PIN DESCRIPTION

TYPE NUMBER PACKAGES

TEMPERATURE

RANGE PINS PACKAGE MATERIAL CODE MARKING

74HC1G126GW −40 to +125 °C 5 SC88A plastic SOT353 HN

74HCT1G126GW −40 to +125 °C 5 SC88A plastic SOT353 TN

74HC1G126GV −40 to +125 °C 5 SC-74A plastic SOT753 H26

74HCT1G126GV −40 to +125 °C 5 SC-74A plastic SOT753 T26

PIN SYMBOL NAME AND FUNCTION

1 OE output enable input

2 A data input A

3 GND ground (0 V)

4 Y data output Y

CC supply voltage

handbook, halfpage

MNA124

126

VCC

GND

Fig.1 Pin configuration.

handbook, halfpage

MNA125

Fig.2 Logic symbol.

handbook, halfpage

MNA126

Fig.3 IEC logic symbol.

handbook, halfpage

MNA127

Fig.4 Logic diagram.

2002 May 15 4

Philips Semiconductors Product speciﬁcation

Bus buffer/line driver; 3-state 74HC1G126; 74HCT1G126

RECOMMENDED OPERATING CONDITIONS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V);

notes 1 and 2.

Notes

1. Stresses beyond those listed may cause permanent damage to the device. These are stress rating only and

functional operation of the device at these or any other conditions beyond those under ‘recommended operating

conditions’ is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device

reliability.

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

3. Above 55 °C the value of PD derates linearly with 2.5 mW/K.

SYMBOL PARAMETER CONDITIONS 74HC1G 74HCT1G UNIT

MIN. TYP. MAX. MIN. TYP. MAX.

VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V

VIinput voltage 0 −VCC 0−VCC V

VOoutput voltage 0 −VCC 0−VCC V

Tamb operating ambient

temperature see DC and AC

characteristicsper

device

−40 +25 +125 −40 +25 +125 °C

tr,t

finput rise and fall times VCC = 2.0 V −−1000 −−−ns

VCC = 4.5 V −−500 −−500 ns

VCC = 6.0 V −−400 −−−ns

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCC supply voltage −0.5 +7.0 V

IIK input diode current VI<−0.5 V or VI>V

CC + 0.5 V −±20 mA

IOK output diode current VO<−0.5 V or VO>V

CC + 0.5 V −±20 mA

IOoutput source or sink current −0.5V<V

O<V

CC + 0.5 V −±35.0 mA

ICC VCC or GND current −±70 mA

Tstg storage temperature −65 +150 °C

PDpower dissipation per package for temperature range from −40 to +125 °C;

note 3 −200 mW

2002 May 15 5

Philips Semiconductors Product speciﬁcation

Bus buffer/line driver; 3-state 74HC1G126; 74HCT1G126

DC CHARACTERISTICS

Family 74HC1G

At recommended operating conditions; voltages are referenced to GND (ground=0V).

Note

1. All typical values are measured at Tamb =25°C.

SYMBOL PARAMETER

TEST CONDITIONS Tamb (°C)

UNIT

OTHER VCC

(V) −40 to +85 −40 to +125

MIN. TYP.(1) MAX. MIN. MAX.

VIH HIGH-level input voltage 2.0 1.5 1.2 −1.5 −V

4.5 3.15 2.4 −3.15 −V

6.0 4.2 3.2 −4.2 −V

VIL LOW-level input voltage 2.0 −0.8 0.5 −0.5 V

4.5 −2.1 1.35 −1.35 V

6.0 −2.8 1.8 −1.8 V

VOH HIGH-level output

voltage VI=V

IH or VIL;

IO=−20 µA2.0 1.9 2.0 −1.9 −V

VI=V

IH or VIL;

IO=−20 µA4.5 4.4 4.5 −4.4 −V

VI=V

IH or VIL;

IO=−20 µA6.0 5.9 6.0 −5.9 −V

VI=V

IH or VIL;

IO=−6.0 mA 4.5 3.84 4.32 −3.7 −V

VI=V

IH or VIL;

IO=−7.8 mA 6.0 5.34 5.81 −5.2 −V

VOL LOW-level output voltage VI=V

IH or VIL;

IO=20µA2.0 −0 0.1 −0.1 V

VI=V

IH or VIL;

IO=20µA4.5 −0 0.1 −0.1 V

VI=V

IH or VIL;

IO=20µA6.0 −0 0.1 −0.1 V

VI=V

IH or VIL;

IO= 6.0 mA 4.5 −0.15 0.33 −0.4 V

VI=V

IH or VIL;

IO= 7.8 mA 6.0 −0.16 0.33 −0.4 V

ILI input leakage current VI=V

CC or GND 6.0 −−1.0 −1.0 µA

IOZ 3-state output current

OFF-state VI=V

IH or VIL;

VO=V

CC or GND 6.0 −−5−10 µA

ICC quiescent supply current VI=V

CC or GND;

IO=0 6.0 −−10 −20 µA

2002 May 15 6

Philips Semiconductors Product speciﬁcation

Bus buffer/line driver; 3-state 74HC1G126; 74HCT1G126

Family 74HCT1G

At recommended operating conditions; voltages are referenced to GND (ground=0V).

Note

1. All typical values are measured at Tamb =25°C.

SYMBOL PARAMETER

TEST CONDITIONS Tamb (°C)

UNIT

OTHER VCC (V) −40 to +85 −40 to +125

MIN. TYP.(1) MAX. MIN. MAX.

VIH HIGH-level input

voltage 4.5 to 5.5 2.0 1.6 −2.0 −V

VIL LOW-level input

voltage 4.5 to 5.5 −1.2 0.8 −0.8 V

VOH HIGH-level output

voltage VI=V

IH or VIL;

IO=−20 µA4.5 4.4 4.5 −4.4 −V

VI=V

IH or VIL;

IO=−6.0 mA 4.5 3.84 4.32 −3.7 −V

VOL LOW-level output

voltage VI=V

IH or VIL;

IO=20µA4.5 −0 0.1 −0.1 V

VI=V

IH or VIL;

IO= 6.0 mA 4.5 −0.16 0.33 −0.4 V

ILI input leakage current VI=V

CC or GND 5.5 −−1.0 −1.0 µA

IOZ 3-state output current

OFF-state VI=V

IH or VIL;

VO=V

CC or GND 5.5 −−5−10 µA

ICC quiescent supply

current VI=V

CC or GND;

IO=0 5.5 −−10 −20 µA

∆ICC additional supply

current per input VI=V

CC −2.1 V;

IO=0 4.5 to 5.5 −−500 −850 µA

2002 May 15 7

Philips Semiconductors Product speciﬁcation

Bus buffer/line driver; 3-state 74HC1G126; 74HCT1G126

AC CHARACTERISTICS

Type 74HC1G

GND = 0 V; tr=t

f≤6.0 ns; CL=50pF.

Note

1. All typical values are measured at Tamb =25°C.

Type 74HCT1G

GND = 0 V; tr=t

f≤6.0 ns; CL=50pF.

Note

1. All typical values are measured at Tamb =25°C.

SYMBOL PARAMETER

TEST CONDITIONS Tamb (°C)

UNIT

WAVEFORMS VCC (V) −40 to +85 −40 to +125

MIN. TYP.(1) MAX. MIN. MAX.

tPHL/tPLH propagation

delay A to Y see Figs 5 and 7 2.0 −24 125 −150 ns

4.5 −10 25 −30 ns

6.0 −921−26 ns

tPZH/tPZL 3-state output

enable time

OE to Y

see Figs 6 and 7 2.0 −24 155 −190 ns

4.5 −10 31 −38 ns

6.0 −826−32 ns

tPHZ/tPLZ 3-state output

disable time

OE to Y

see Figs 6 and 7 2.0 −16 155 −190 ns

4.5 −12 31 −38 ns

6.0 −11 26 −32 ns

SYMBOL PARAMETER

TEST CONDITIONS Tamb (°C)

UNIT

WAVEFORMS VCC (V) −40 to +85 −40 to +125

MIN. TYP.(1) MAX. MIN. MAX.

tPHL/tPLH propagation

delay A to Y see Figs 5 and 7 4.5 −11 30 −36 ns

tPZH/tPZL 3-state output

enable time

OE to Y

see Figs 6 and 7 4.5 −10 35 −42 ns

tPHZ/tPLZ 3-state output

disable time

OE to Y

see Figs 6 and 7 4.5 −12 31 −38 ns

2002 May 15 8

Philips Semiconductors Product speciﬁcation

Bus buffer/line driver; 3-state 74HC1G126; 74HCT1G126

AC WAVEFORMS

handbook, halfpage

MNA121

A input

Y output

tPHL tPLH

GND

Fig.5 The input (A) to output (Y) propagation delays.

For HC1G: VM= 50%; VI= GND to VCC

For HCT1G: VM= 1.3 V; VI= GND to 3.0 V.

handbook, full pagewidth

MNA129

tPLZ

tPHZ

output

disabled output

enabled

VOH −0.3 V

VOL +0.3 V

output

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

OE input

VCC

GND

tPZL

tPZH

Fig.6 The 3-state enable and disable times.

For HC1G: VM= 50%; VI= GND to VCC

For HCT1G: VM= 1.3 V; VI= GND to 3.0 V.

2002 May 15 9

Philips Semiconductors Product speciﬁcation

Bus buffer/line driver; 3-state 74HC1G126; 74HCT1G126

handbook, full pagewidth

open

GND

VCC

VIVO

MNA232

D.U.T.

RL =

1000 Ω

PULSE

GENERATOR

Fig.7 Load circuitry for switching times.

Definitions for test circuit:

CL= Load capacitance including jig and probe capacitance (see “AC characteristics” for values).

RL= Load resistance (see “AC characteristics” for values).

RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.

TEST S1

tPLH/tPHL open

tPLZ/tPZL VCC

tPHZ/tPZH GND

2002 May 15 10

Philips Semiconductors Product speciﬁcation

Bus buffer/line driver; 3-state 74HC1G126; 74HCT1G126

PACKAGE OUTLINES

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

SOT353

wBM

detail X

vMA

0 1 2 mm

scale

132

Plastic surface mounted package; 5 leads SOT353

UNIT A1

max bpcD

E (2) e1HELpQywv

mm 0.1 0.30

0.20 2.2

1.8

0.25

0.10 1.35

1.15 0.65

1.3 2.2

2.0 0.2 0.10.2

DIMENSIONS (mm are the original dimensions)

0.45

0.15 0.25

0.15

1.1

0.8

97-02-28SC-88A

2002 May 15 11

Philips Semiconductors Product speciﬁcation

Bus buffer/line driver; 3-state 74HC1G126; 74HCT1G126

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT753 SC-74A

wBM

detail X

vMA

0 1 2 mm

scale

132

Plastic surface mounted package; 5 leads SOT753

UNIT A1bpcDEH

Qywv

mm 0.100

0.013 0.40

0.25 3.1

2.7

0.26

0.10 1.7

1.3

0.95 3.0

2.5 0.2 0.10.2

DIMENSIONS (mm are the original dimensions)

0.6

0.2 0.33

0.23

1.1

0.9

02-04-16

2002 May 15 12

Philips Semiconductors Product speciﬁcation

Bus buffer/line driver; 3-state 74HC1G126; 74HCT1G126

SOLDERING

Introduction to soldering surface mount packages

Thistextgivesaverybriefinsightto acomplex technology.

A more in-depth account of soldering ICs can be found in

our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for

certainsurfacemount ICs,but itisnotsuitablefor finepitch

SMDs. In these situations reflow soldering is

recommended.

Reﬂow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

tothe printed-circuit boardbyscreen printing, stencillingor

pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,

convection or convection/infrared heating in a conveyor

type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending

on heating method.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 220 °C for

thick/large packages, and below 235 °C for small/thin

packages.

Wave soldering

Conventional single wave soldering is not recommended

forsurfacemount devices(SMDs) orprinted-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

•Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

The footprint must incorporate solder thieves at the

downstream end.

•Forpackageswith leadson foursides,thefootprintmust

be placed at a 45°angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

2002 May 15 13

Philips Semiconductors Product speciﬁcation

Bus buffer/line driver; 3-state 74HC1G126; 74HCT1G126

Suitability of surface mount IC packages for wave and reﬂow soldering methods

Notes

1. Formore detailed informationon the BGApackages refer tothe

“(LF)BGAApplication Note

”(AN01026); orderacopy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,

the solder might be deposited on the heatsink surface.

4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE(1) SOLDERING METHOD

WAVE REFLOW(2)

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable

HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,

HVSON, SMS not suitable(3) suitable

PLCC(4), SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended(4)(5) suitable

SSOP, TSSOP, VSO not recommended(6) suitable

2002 May 15 14

Philips Semiconductors Product speciﬁcation

Bus buffer/line driver; 3-state 74HC1G126; 74HCT1G126

DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

DATA SHEET STATUS(1) PRODUCT

STATUS(2) DEFINITIONS

Objective data Development This data sheet contains data from the objective specification for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

Preliminary data Qualiﬁcation This data sheet contains data from the preliminary specification.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

Product data Production This data sheet contains data from the product specification. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Changes will be

communicated according to the Customer Product/Process Change

Notiﬁcation (CPCN) procedure SNW-SQ-650A.

DEFINITIONS

Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

atthese orat anyother conditionsabovethose givenin the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Application information  Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

norepresentationorwarrantythatsuchapplicationswillbe

suitable for the specified use without further testing or

modification.

DISCLAIMERS

Life support applications  These products are not

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductorscustomersusingor sellingtheseproducts

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes  Philips Semiconductors

reserves the right to make changes, without notice, in the

products, including circuits, standard cells, and/or

software, described or contained herein in order to

improve design and/or performance. Philips

Semiconductors assumes no responsibility or liability for

theuseof anyof theseproducts,conveysnolicence ortitle

under any patent, copyright, or mask work right to these

products,and makesnorepresentations orwarrantiesthat

these products are free from patent, copyright, or mask

work right infringement, unless otherwise specified.

2002 May 15 15

Philips Semiconductors Product speciﬁcation

Bus buffer/line driver; 3-state 74HC1G126; 74HCT1G126

NOTES

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825

For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Printed in The Netherlands 613508/03/pp16 Date of release: 2002 May 15 Document order number: 9397 750 09719