General Description
The MAX5945 quad network power controller is designed
for use in IEEE 802.3af-compliant power-sourcing equip-
ment (PSE). The device provides power devices (PD) dis-
covery, classification, current-limit, and both DC and AC
load disconnect detections. The MAX5945 can be used
in either endpoint PSE (LAN switches/routers) or midspan
PSE (power injector) applications. The MAX5945 is pin
and function compatible with LTC4259A.
The MAX5945 can operate autonomously or be con-
trolled by software through an I2C-compatible interface.
Separate input and output data lines (SDAIN and
SDAOUT) allow usage with optocouplers. The
MAX5945 is a slave device. Its four address inputs
allow 16 unique MAX5945 addresses. A separate INT
output and four independent shutdown inputs (SHD_)
allow fast response from a fault to port shutdown. A
RESET input allows hardware reset of the device. A
special watchdog feature allows the hardware to grace-
fully take over control if the software crashes. A
cadence timing feature allows the MAX5945 to be used
in midspan systems.
The MAX5945 is fully software configurable and program-
mable. A class-overcurrent detection function enables
system power management to detect if a PD draws more
current than the allowable amount for its class. Other fea-
tures are input under/overvoltage lockout, overtempera-
ture protection, output-voltage slew-rate limit during
startup, power-good, and fault status. The MAX5945’s
programmability includes gate-charging current, current-
limit threshold, startup timeout, overcurrent timeout,
autorestart duty cycle, PD disconnect AC detection
threshold, and PD disconnect detection timeout.
The MAX5945 is available in a 36-pin SSOP package
and is rated for both extended (-40°C to +85°C) and
commercial (0°C to +70°C) temperature ranges.
Applications
Power-Sourcing Equipment (PSE)
Power-Over-LAN/Power-Over-Ethernet
Switches/Routers
Midspan Power Injectors
Features
♦IEEE 802.3af Compliant
♦Pin and Function Compatible with LTC4259A
♦Controls Four Independent, -48V-Powered
Ethernet Ports in Either Endpoint or Midspan PSE
Applications
♦Wide Digital Power Input, VDIG, Common-Mode
Range: VEE to (AGND + 7.7V)
♦PD Violation of Class Current Protection
♦PD Detection and Classification
♦Provides Both DC and AC Load Removal
Detections
♦I2C-Compatible, 3-Wire Serial Interface
♦Fully Programmable and Configurable Operation
Through I2C Interface
♦Current Foldback and Duty-Cycle-
Controlled/Programmable Current Limit
♦Short-Circuit Protection with Fast Gate Pulldown
♦Direct Fast Shutdown Control Capability
♦Programmable Direct Interrupt Output
♦Watchdog Mode Enable Hardware Graceful
Takeover
MAX5945
Quad Network Power Controller
for Power-Over-LAN
________________________________________________________________ Maxim Integrated Products 1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
OSC_IN
AUTO
OUT1
GATE1
SENSE1
OUT2
GATE4
GATE2
SENSE2
VEE
OUT3
GATE3
SENSE3
OUT4
DET4
DET3
DET2
DET1
A0
A1
A2
A3
SDAIN
SDAOUT
SCL
MIDSPAN
SSOP
TOP VIEW
MAX5945
22
21
20
19
15
16
17
18
SENSE4
AGNDVDD
DGND
RESET
INT
SHD1
SHD2 SHD3
SHD4
Pin Configuration
19-3428; Rev 1; 9/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX5945CAX**
0°C to +70°C 36 SSOP
MAX5945EAX -40°C to +85°C 36 SSOP
**Future product—contact factory for availability.
Typical Operating Circuits appear at end of data sheet.
MAX5945
Quad Network Power Controller
for Power-Over-LAN
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(Voltages referenced to VEE, unless otherwise noted.)
AGND, DGND, DET_, VDD, RESET, A3, A2, A1, A0, SHD_,
OSC_IN, SCL, SDAIN, OUT_ and AUTO............-0.3V to +80V
GATE_ (internally clamped, Note 1)....................-0.3V to +11.4V
SENSE_ ..................................................................-0.3V to +24V
VDD, RESET, A3, A2, A1, A0, SHD_, OSC_IN, SCL, SDAIN and
AUTO to DGND ....................................................-0.3V to +7V
INT and SDAOUT to DGND....................................-0.3V to +12V
Maximum Current into INT, SDAOUT, DET_ .......................80mA
Maximum Power Dissipation
36-Pin SSOP (derate 11.4mW/°C above +70°C) .........941mW
Operating Temperature Ranges:
MAX5945EAX ..................................................-40°C to +85°C
MAX5945CAX .....................................................0°C to +70°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(AGND = +32V to +60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
negative otherwise.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
POWER SUPPLIES
VAGND
VAGND - VEE 32 60
VDGND
060
VDD to VDGND, VDGND = VAGND
1.71 5.50
Operating Voltage Range
VDD VDD to VDGND, VDGND = VEE 3.0 5.5
V
IEE
OUT_ = VEE, SENSE_ = VEE, DET_ = AGND,
all logic inputs open, SCL = SDAIN = VDD,
INT and SDAOUT open; measured at AGND
in power mode after GATE_ pullup
4.2 6.8
Supply Currents
IDIG All logic inputs high, measured at VDD 2.7 5.6
mA
GATE DRIVER AND CLAMPING
GATE_ Pullup Current IPU
Power mode, gate drive on, VGATE = VEE (Note 2) -40
-50 -60 µA
Weak GATE_ Pulldown Current
IPDW SHD_ = DGND, VGATE_ = VEE + 5V 30 40 50 µA
Maximum Pulldown Current IPDS VSENSE = 1V, VGATE_ = VEE + 2V
100
mA
External Gate Drive VGS VGATE - VEE , power mode, gate drive on 9 10 11 V
CURRENT LIMIT
Current-Limit Clamp Voltage
VSU_LIM
Maximum VSENSE_ allowed during current limit,
VOUT_ = VEE (Note 3)
202 212 220
mV
Default, class 0,
class 3, class 4
178.5 196
Class 1 49 61
Overcurrent Threshold After
Startup
VFLT_LIM
Overcurrent VSENSE_
threshold allowed for
t ≤ tFAULT after startup;
VOUT_ = VEE Class 2 90
104
mV
Foldback Initial OUT_ Voltage
VFLBK_ST
VOUT_ - VEE, above which the current-limit trip
voltage starts folding back 30 V
Foldback Final OUT_ Voltage
VFLBK_END
VOUT_ - VEE, above which the current-limit trip
voltage reaches VTH_FB 50 V
Note 1: GATE_ is internally clamped to 11.4V above VEE. Driving GATE_ higher than 11.4V above VEE may damage the device.
MAX5945
Quad Network Power Controller
for Power-Over-LAN
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +32V to +60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
negative otherwise.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Minimum Foldback Current-
Limit Threshold
VTH_FB
VOUT_ = VAGND 64 mV
SENSE_ Input Bias Current VSENSE_ = VEE -2 µA
SUPPLY MONITORS
VEE Undervoltage Lockout
VEEUVLO
VAGND - VEE, (VAGND - VEE) increasing 27
28.5
30 V
VEE Undervoltage-Lockout
Hysteresis
VEEUVLOH
3V
VEE Overvoltage
VEE_OV
(VAGND - VEE) > VEE_OV, VAGND increasing 61
62.5
64 V
VEE Overvoltage Hysteresis VOVH 1V
VEE Undervoltage
VEE_UV
(VAGND - VEE) < VEE_UV, VAGND decreasing 39 40 41 V
VDD Overvoltage
VDD_OV
(VDD - VDGND) > VDD_OV, VDD increasing
3.57 3.71 3.90
V
VDD Undervoltage
VDD_UV
(VDD - VDGND) < VDD_UV, VDD decreasing
2.55 2.82 2.97
V
VDD Undervoltage Lockout
VDDUVLO
Device operates when (VDD - VDGND) >
VDDUVLO, VDD increasing 1.7 V
VDD Undervoltage-Lockout
Hysteresis
VDDHYS 120
mV
Thermal-Shutdown Threshold TSHD
Ports shut down and device resets if its junction
temperature exceeds this limit, temperature
increasing
+150
°C
Thermal-Shutdown Hysteresis
TSHDH
20 °C
OUTPUT MONITOR
OUT_ Input Current IBOUT VOUT = VAGND, all modes 2 µA
Idle Pullup Current at OUT_ IDIS
OUT_ discharge current, detection and
classification off, port shutdown,
VOUT_ = VAGND - 2.8V
200 260
µA
PGOOD High Threshold PGTH VOUT_ - VEE, OUT_ decreasing 1.8 2.0 2.2 V
PGOOD Hysteresis
PGHYS 220
mV
PGOOD Low-to-High Glitch
Filter
tPGOOD
Minimum time PGOOD has to be high to set bit in
register 10h 24ms
LOAD DISCONNECT
DC Load Disconnect
Threshold
VDCTH
Minimum VSENSE allowed before disconnect (DC
disconnect active), VOUT_ = VEE 345mV
MAX5945
Quad Network Power Controller
for Power-Over-LAN
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +32V to +60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
negative otherwise.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
AC Load Disconnect
Threshold (Note 4) IACTH Current into DET_, ACD_EN_ bit = high,
OSC_IN = 2.2V
300 325 350
µA
Oscillator Buffer Gain AOSC VDET_ / VOSC_IN, ACD_EN_ bit = high,
CDET = 400nF
2.92 2.98 3.04
V/V
OSC_IN Fail Threshold
(Note 5)
V
OS C _F AI L
Port will not power on if VOSC_IN < VOSC_FAIL and
ACD_EN_ bit = high 1.8 1.9 2.1 V
OSC_IN Input Resistance ZOSC OSC_IN input impedance when all the ACD_EN_
are active
100
kΩ
OSC_IN Input Capacitance
COSC_IN
5pF
Load Disconnect Timer tDISC Time from VSENSE < VDCTH or current into DET_
< IACTH to gate shutdown (Note 6)
300 400
ms
DETECTION
Detection Probe Voltage
(First Phase) VDPH1 VAGND - VDET_ during the first detection phase 3.8 4 4.2 V
Detection Probe Voltage
(Second Phase) VDPH2 VAGND - VDET_ during the second detection
phase 9.0 9.3 9.6 V
Current-Limit Protection IDLIM VDET_ = VAGND, during detection, measure
current through DET_ 1.5
1.75
2.0 mA
Short-Circuit Threshold VDCP If V
A GN D
- V
OU T
< V
D C P
after the fi r st d etecti on
p hase a shor t ci r cui t to AG N D i s d etected
1.62
V
Open-Circuit Threshold
ID_OPEN
First point measurement current threshold for
open condition
12.5
µA
Resistor Detection Window RDOK (Note 7)
18.6 26.5
kΩ
Detection rejects lower values 16
Resistor Rejection Window
RDBAD
Detection rejects higher values 30 kΩ
CLASSIFICATION
Classification Probe Voltage VCL VAGND - VDET_ during classification 16 20 V
Current-Limit Protection IClLIM VDET_ = VAGND, during classification,
measure current through DET_ 50 75 mA
Class 0, class 1 5.5 6.5 7.5
Class 1, class 2
13.5 14.5 15.5
Class 2, class 3
21.5
23
24.5
Class 3, class 4 31 33 35
Classification Current
Thresholds ICL
Classification current
thresholds between
classes
>Class 4 45 48 51
mA
DIGITAL INPUTS/OUTPUTS (REFERRED to DGND)
Digital Input Low VIL 0.9 V
Digital Input High VIH 2.4 V
MAX5945
Quad Network Power Controller
for Power-Over-LAN
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +32V to +60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
negative otherwise.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Internal Input Pullup/Pulldown
Resistor RDIN Pullup (pulldown) resistor to VDD (DGND) to set
default level 25 50 75 kΩ
Open-Drain Output Low
Voltage VOL ISINK = 15mA 0.4 V
Open-Drain Leakage IOL Open-drain high impedance, VO = 3.3V 2 µA
TIMING
Startup Time tSTART
Time during which a current limit set by VSU_LIM
is allowed, starts when the GATE_
is turned on (Note 8)
50 60 70 ms
Fault Time tFAULT Maximum allowed time for an overcurrent
condition set by VFLT_LIM after startup (Note 8) 50 60 70 ms
Port Turn-Off Time tOFF Minimum delay between any port turning off,
does not apply in the case of a reset 0.5
0.75
1.0 ms
Detection Time tDET Maximum time allowed before detection
is completed
320
ms
Midspan Mode Detection
Delay tDMID 2.0 2.4 s
Classification Time
tCLASS
Time allowed for classification 40 ms
VEEUVLO Turn-On Delay tDLY Time VAGND must be above the VEEUVLO
thresholds before the device operates 24ms
RSTR bits = 00 16 x
tFAULT
RSTR bits = 01 32 x
tFAULT
RSTR bits = 10 64 x
tFAULT
Restart Timer
tRESTART
Ti m e a p or t has to w ai t
b efor e tur ni ng on after an
over cur r ent faul t,
RS TR_E N b i t = hi g h
RSTR bits = 11 0
ms
Watchdog Clock Period tWD Rate of decrement of the watchdog timer
164
ms
TIMING CHARACTERISTICS for 2-WIRE FAST MODE (Figures 5 and 6)
Serial Clock Frequency fSCL (Note 9)
400 kHz
Bus Free Time Between a
STOP and a START Condition
tBUF (Note 9) 1.2 µs
Hold Time for Start Condition
tHD
,
STA
(Note 9) 0.6 µs
Low Period of the SCL Clock tLOW (Note 9) 1.2 µs
High Period of the SCL Clock tHIGH (Note 9) 0.6 µs
MAX5945
Quad Network Power Controller
for Power-Over-LAN
6 _______________________________________________________________________________________
Note 2: Default values. The charge/discharge currents are programmable through the serial interface (see the Register Map and
Description section).
Note 3: Default values. The current-limit thresholds are programmed through the I2C-compatible serial interface (see the Register
Map and Description section).
Note 4: This is the default value. Threshold can be programmed through serial interface R23h[2:0].
Note 5: AC disconnect works only if VDD - VDGND ≥3V.
Note 6: tDISC can also be programmed through the serial interface (R29h) (see the Register Map and Description section).
Note 7: RD= (VOUT_2 - VOUT_1) / (IDET_2 - IDET_1). VOUT_1, VOUT_2, IDET_2 and IDET_1 represent the voltage at OUT_ and the current
at DET_ during phase 1 and 2 of the detection.
Note 8: Default values. The startup and fault times can also be programmed through the I2C serial interface (see the Register Map
and Description section).
Note 9: Guaranteed by design. Not subject to production testing.
ANALOG SUPPLY CURRENT
vs. INPUT VOLTAGE
MAX5945 toc01
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
5752474237
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
3.5
32 62
MEASURED AT AGND
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX5945 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
3.2
3.4
3.6
3.8
4.0
4.2
4.4
4.6
4.8
5.0
3.0
-40 85
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
MAX5945 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
-40 85
Typical Operating Characteristics
(VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5Ω, all registers = default setting,
TA= +25°C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +32V to +60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
negative otherwise.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Setup Time for a Repeated
START Condition (Sr)
tSU
,
STA
(Note 9) 0.6 µs
Data Hold Time
tHD
,
DAT
(Note 9) 0
150
ns
Data Setup Time
tSU
,
DAT
(Note 9)
100
ns
Rise Time of Both SDA and
SCL Signals, Receiving tR(Note 9)
20 + 0.1CB300
ns
Fall Time of SDA Transmitting
tF(Note 9)
20 + 0.1CB300
ns
Setup Time for STOP Condition
tSU
,
STO
(Note 9) 0.6 µs
C ap aci ti ve Load for E ach Bus
Li ne CB(Note 9)
400
pF
Pulse Width of Spike
Suppressed tSP (Note 9) 50 ns
MAX5945
Quad Network Power Controller
for Power-Over-LAN
_______________________________________________________________________________________ 7
DIGITAL SUPPLY CURRENT
vs. INPUT VOLTAGE
MAX5945 toc04
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
4.64.23.83.43.02.62.2
1
2
3
4
5
6
0
1.8 5.0
MEASURED AT VDD
VEE UNDERVOLTAGE LOCKOUT
vs. TEMPERATURE
MAX5945 toc05
TEMPERATURE (°C)
UNDERVOLTAGE LOCKOUT (V)
603510-15
27.5
28.0
28.5
29.0
29.5
30.0
27.0
-40 85
GATE OVERDRIVE
vs. INPUT VOLTAGE
MAX5945 toc06
INPUT VOLTAGE (V)
GATE OVERDRIVE (V)
5752474237
9.80
9.82
9.84
9.86
9.88
9.90
9.92
9.94
9.96
9.98
9.78
32 62
GATE OVERDRIVE
vs. TEMPERATURE
MAX5945 toc07
TEMPERATURE (°C)
GATE OVERDRIVE (V)
603510-15
9.6
9.7
9.8
9.9
10.0
10.1
10.2
10.3
10.4
10.5
9.5
-40 85
SENSE TRIP VOLTAGE
vs. TEMPERATURE
MAX5945 toc08
TEMPERATURE (°C)
SENSE TRIP VOLTAGE (mV)
603510-15
175
180
185
190
195
200
170
-40 85
SENSE TRIP VOLTAGE
vs. INPUT VOLTAGE
MAX5945 toc09
INPUT VOLTAGE (V)
SENSE TRIP VOLTAGE (mV)
5752474237
182
184
186
188
190
180
32 62
FOLDBACK CURRENT-LIMIT
THRESHOLD vs. OUTPUT VOLTAGE
MAX5945 toc10
VOUT - VEE (V)
VSENSE - VEE (mV)
40302010
50
100
150
200
250
300
0
050
ZERO-CURRENT DETECTION
THRESHOLD vs. TEMPERATURE
MAX5945 toc11
TEMPERATURE (°C)
DETECTION THRESHOLD (mV)
603510-15
1
2
3
4
5
0
-40 85
Typical Operating Characteristics (continued)
(VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5Ω, all registers = default setting,
TA= +25°C, unless otherwise noted.)
MAX5945
Quad Network Power Controller
for Power-Over-LAN
8 _______________________________________________________________________________________
OVERCURRENT TIMEOUT
(RLOAD = 240Ω TO 57Ω)
MAX5945 toc12
20ms/div
0V
IOUT
200mA/div
VEE
GATE 10V/div
0A
INT
2V/div
(AGND - OUT)
20V/div
0V
OVERCURRENT RESPONSE WAVEFORM
(RLOAD = 240Ω TO 57Ω)
MAX5945 toc13
400µs/div
0V
IOUT
200mA/div
GATE
10V/div
VEE
0A
INT
2V/div
(AGND - OUT)
20V/div
0V
SHORT-CIRCUIT RESPONSE TIME
MAX5945 toc14
20ms/div
0V
IOUT
250mA/div
GATE
10V/div
VEE
0A
(AGND - OUT)
20V/div
SHORT-CIRCUIT RESPONSE TIME
MAX5945 toc15
4µs/div
0V
IOUT
5A/div
GATE
10V/div
VEE
0A
(AGND - OUT)
20V/div
RESET TO OUTPUT TURN-OFF DELAY
MAX5945 toc16
100µs/div
0V
IOUT
200mA/div
GATE
10V/div
VEE
0A
RESET
(AGND - OUT)
20V/div
ZERO-CURRENT DETECTION WAVEFORM
MAX5945 toc17
100ms/div
0V
IOUT
200mA/div
GATE
10V/div
INT
5V/div
(AGND - OUT)
20V/div
Typical Operating Characteristics (continued)
(VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5Ω, all registers = default setting,
TA= +25°C, unless otherwise noted.)
MAX5945
Quad Network Power Controller
for Power-Over-LAN
_______________________________________________________________________________________ 9
OVERCURRENT RESTART DELAY
MAX5945 toc18
400ms/div
0V
0A
IOUT
200mA/div
GATE
10V/div
VEE
(AGND - OUT)
20V/div
STARTUP WITH VALID PD
(25kΩ AND 0.1µF)
MAX5945 toc19
100ms/div
0V
IOUT
100mA/div
GATE_
VEE
(AGND - OUT)
20V/div
DETECTION WITH INVALID PD
(25kΩ AND 10µF)
MAX5945 toc20
40ms/div
0V
IOUT
1mA/div
(AGND - OUT)
2V/div
DETECTION WITH INVALID PD (15kΩ)
MAX5945 toc21
100ms/div
0V
0A
IOUT
1mA/div
(AGND - OUT)
5V/div
DETECTION WITH INVALID PD (33kΩ)
MAX5945 toc22
100ms/div
0V
0A
IOUT
1mA/div
(AGND - OUT)
5V/div
STARTUP IN MIDSPAN MODE
WITH VALID PD (25kΩ AND 0.1µF)
MAX5945 toc23
100ms/div
0V
0A
IOUT
100mA/div
VEE
GATE_
10V/div
(AGND - OUT)
20V/div
Typical Operating Characteristics (continued)
(VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5Ω, all registers = default setting,
TA= +25°C, unless otherwise noted.)
MAX5945
Quad Network Power Controller
for Power-Over-LAN
10 ______________________________________________________________________________________
DETECTION WITH MIDSPAN MODE
WITH INVALID PD (15kΩ)
MAX5945 toc24
400ms/div
0V
0A
IOUT
1mA/div
VEE
GATE_
10V/div
(AGND - OUT)
5V/div
DETECTION WITH MIDSPAN MODE
WITH INVALID PD (33kΩ)
MAX5945 toc25
400ms/div
0V
0A
IOUT
1mA/div
VEE
GATE_
10V/div
(AGND - OUT)
5V/div
DETECTION WITH OUTPUT SHORTED
MAX5945 toc26
40ms/div
0V
0A
IOUT
1mA/div
VEE
GATE_
10V/div
(AGND - OUT)
5V/div
DETECTION WITH INVALID PD (OPEN CIRCUIT,
USING TYPICAL OPERATING CIRCUIT 1)
MAX5945 toc27
100ms/div
0A
0V
IOUT
1mA/div
VEE
GATE_
10V/div
(AGND - OUT)
5V/div
DETECTION WITH INVALID PD (OPEN CIRCUIT,
USING TYPICAL OPERATING CIRCUIT 2)
MAX5945 toc28
100ms/div
IOUT
2mA/div
0V
GATE_
10V/div
(AGND - OUT)
5V/div
STARTUP WITH DIFFERENT PD CLASSES
MAX5945 toc29
40ms/div
IOUT
10mA/div
(AGND - OUT)
5V/div
CLASS0
CLASS1
CLASS2
CLASS3
CLASS4
Typical Operating Characteristics (continued)
(VEE = -48V, VDD = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5Ω, all registers = default setting,
TA= +25°C, unless otherwise noted.)
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 11
PIN NAME FUNCTION
1RESET
Hardware Reset. Pull RESET low for at least 300µs to reset the device. All internal registers reset to
their default value. The address (A0–A3), and AUTO and MIDSPAN input logic levels latch on during
low-to-high transition of RESET. Internally pulled up to VDD with 50kΩ resistor.
2 MIDSPAN
MIDSPAN Mode Input. An internal 50kΩ pulldown resistor to DGND sets the default mode to endpoint
PSE operation (power-over-signal pairs). Pull MIDSPAN TO VDIG to set MIDSPAN operation. The
MIDSPAN value latches after the IC is powered up or reset (see the PD Detection section).
3INT
Open-Drain Interrupt Output. INT goes low whenever a fault condition exists. Reset the fault condition
using software or by pulling RESET low (see the Interrupt section of the Detailed Description for more
information about interrupt management).
4 SCL Serial Interface Clock Line
5 SDAOUT Serial Output Data Line. Connect the data line optocoupler input to SDAOUT (see the Typical
Application Circuit). Connect SDAOUT to SDAIN if using a 2-wire I2C-compatible system.
6 SDAIN Serial Interface Input Data Line. Connect the data line optocoupler output SDAIN (see the Typical
Application Circuit). Connect SDAIN to SDAOUT if using a 2-wire wire I2C-compatible system.
7–10
A3, A2, A1, A0
Address Bits. A3, A2, A1, and A0 form the lower part of the device’s address. Address inputs default
high with an internal 50kΩ pullup resistor to VDD. The address values latch when VDD or VEE ramps
up and exceeds its UVLO threshold or after a reset. The 3 MSB bits of the address are set to 010.
11–14
DET1, DET2,
DET3, DET4
Detection and Classification Voltage Outputs. Use DET1 to set the detection and classification probe
voltages on port 1. Use DET1 for the AC voltage sensing of port 1 when using the AC disconnect
scheme (see the Typical Application Circuit).
15 DGND Connect to Digital Ground
16 VDD Positive Digital Supply. Connect to digital supply (referenced to DGND).
17–20
SHD1, SHD2,
SHD3, SHD4
Port Shutdown Inputs. Pull SHD_ low to turn off the external FET on port_. Internally pulled up to VDD
with a 50kΩ resistor.
21 AGND Analog Ground. Connect to the high-side analog supply.
22, 25,
29, 32
SENSE4, SENSE3,
SENSE2, SENSE1
MOSFET Source Current-Sense Negative Inputs. Connect to the source of the power MOSFET and
connect a current-sense resistor between SENSE_ and VEE (see the Typical Application Circuit).
23, 26,
30, 33
GATE4, GATE3,
GATE2, GATE1
Port_ MOSFET Gate Drivers. Connect GATE_ to the gate of the external FET (see the Typical
Application Circuit).
24, 27,
31, 34
OUT4, OUT3,
OUT2, OUT1
MOSFET Drain-Output Voltage Senses. Connect OUT_ to the power MOSFET drain through a resistor
(100Ω to 100kΩ). The low leakage at OUT_ limits the drop across the resistor to less than 100mV
(see the Typical Application Circuit).
28 VEE Low-Side Analog Supply Input. Connect the low-side analog supply to VEE (-48V). Bypass with a 1µF
capacitor between AGND and VEE.
35 AUTO
AUTO or SHUTDOWN Mode Input. Force high to enter AUTO mode after a reset or power-up. Drive
low to put the MAX5945 into SHUTDOWN mode. In SHUTDOWN mode, software controls the
operational modes of the MAX5945. A 50kΩ internal pulldown resistor defaults AUTO low. AUTO
latches when VDD or VEE ramps up and exceeds its UVLO threshold or when the device resets.
Software commands can take the MAX5945 out of AUTO while AUTO is high.
36 OSC_IN
Oscillator Input. AC-disconnect detection function uses OSC_IN. Connect a 100Hz ±10%, 2VP-P
±5%, +1.2V offset sine wave to OSC_IN. If the oscillator positive peak falls below the OSC_FAIL
threshold of 2V, the ports that have the AC function enabled shut down and are not allowed to power
up. When not using the AC-disconnect detection function, leave OSC_IN unconnected.
Pin Description
MAX5945
Detailed Description
The MAX5945 four-port network power controller con-
trols -32V to -60V negative supply rail systems. Use the
MAX5945, which is compliant with the IEEE 802.3af
standard for PSE in power-over-LAN applications. The
MAX5945 provides PD discovery, classification, current
limit, both DC and AC load disconnect detections, and
other necessary functions for an IEEE 802.3af-compli-
ant PSE. The MAX5945 can be used in either endpoint
PSE (LAN switch/router) or midspan PSE (power injec-
tor) applications.
The MAX5945 is fully software-configurable and pro-
grammable with more than 25 internal registers. The
device features an I2C-compatible, 3-wire serial inter-
face and a class-overcurrent detection. The class-over-
current detection function enables system power man-
Quad Network Power Controller
for Power-Over-LAN
12 ______________________________________________________________________________________
50µA
90µA
100mA
MAX
FAST
DISCHARGE
CONTROL
212mV182mV
13V CLAMP
CURRENT-LIMIT
DETECTOR
4mV
OVERCURRENT
(OVC)
OPEN CIRCUIT
(OC)
CURRENT
LIMIT (ILIM)
PWR_EN
10V
VOLTAGE
SENSING
FOLDBACK
CONTROL
9-BIT ADC
CONVERTER
VOLTAGE PROBING
AND
CURRENT-LIMIT
CONTROL
CURRENT SENSING
SENSE_
GATE_
OUT_
DET_
A = 3
AC
DETECTION
ACD_ENABLE
AC DISCONNECT
SIGNAL
(ACD)
ACD
REFERENCE
CURRENT
DETECTION/
CLASSIFICATION
SM
PORT
STATE
MACHINE
(SM)
REGISTER FILE
SERIAL
PORT
INTERFACE
(SPI)
AUTO
MIDSPAN
A0
A1
A2
A3
ANALOG
BIAS/
SUPPLY
MONITOR
AGND
VEE
+10V ANALOG
+5V DIG
VOLTAGE
REFERENCES
CURRENT
REFERENCES
CENTRAL LOGIC UNIT
(CLU)
DGNDOSC_INSCL SDAIN SDAOUT
VDD
OSCILLATOR
MONITOR
SHD_
RESET
INT
MAX5945
Figure 1. MAX5945 Functional Diagram
agement where it detects a PD that draws more current
than the allowable amount for its class. The MAX5945’s
extensive programmability enhances system flexibility
and allows for uses in other applications.
The MAX5945 has four different operating modes: auto
mode, semi-auto mode, manual mode, and shutdown
mode (see the Operation Modes section). A special
watchdog feature allows the hardware to gracefully
take over control if the software/firmware crashes. A
cadence timing feature allows the MAX5945 to be used
in midspan systems.
The MAX5945 provides input undervoltage lockout,
input undervoltage detection, input overvoltage lockout,
overtemperature protection, output-voltage slew-rate
limit during startup, power-good status, and fault
status. The MAX5945’s programmability includes
gate-charging current, current-limit threshold, startup
timeout, overcurrent timeout, autorestart duty cycle, PD
disconnect AC detection threshold and PD disconnect
detection timeout.
The MAX5945 communicates with the system
microcontroller through an I2C-compatible interface.
The MAX5945 features separate input and output data
lines (SDAIN and SDAOUT) for use with optocoupler
isolation. The MAX5945 is a slave device. Its four
address inputs allow 16 unique MAX5945 addresses. A
separate INT output and four independent shutdown
inputs (SHD_) allow fast interrupt signals between the
MAX5945 and the microcontroller. A RESET input
allows hardware reset of the device.
Reset
Reset is a condition the MAX5945 enters after any of
the following conditions:
• After power-up (VEE and VDD rise above their UVLO
thresholds).
• Hardware reset. The RESET input is driven low and
up high again any time after power-up.
• Software reset. Writing a 1 into R1Ah[4] any time
after power-up.
• Thermal shutdown.
During a reset, the MAX5945 resets its register map to
the reset state as shown in Table 30 and latches in the
state of AUTO (pin 35) and MIDSPAN (pin 2). During
normal operation, changes at the AUTO and MIDSPAN
inputs are ignored. While the condition that caused the
reset persists (i.e., high temperature, RESET input low,
or UVLO conditions) the MAX5945 will not acknowl-
edge any addressing from the serial interface.
Port Reset (R1Ah[3:0])
Set high anytime during normal operation to turn off
power and clear the events and status registers of the
corresponding port. Port reset only resets the events
and status registers.
Operation Modes
The MAX5945 contains four independent but identical
state machines to provide reliable and real-time control
of the four network ports. Each state machine has four
different operating modes: auto, semi-auto, manual,
and shutdown. Auto mode allows the device to operate
automatically without any software supervision. Semi-
auto mode, upon request, continuously detects and
classifies a device connected to a port but does not
power up that port until instructed by software. Manual
mode allows total software control of the device and is
useful in system diagnostic. Shutdown mode terminates
all activities and securely turns off power to the ports.
Switching between AUTO, SEMI, or MANUAL mode
does not take effect until the part finishes its current
task. When the port is set into SHUTDOWN mode, all
the port operations are immediately stopped and the
port remains idle until SHUTDOWN is exited.
Automatic (AUTO) Mode
Enter automatic (AUTO) mode by forcing the
AUTO input high prior to a reset, or by setting
R12h[P_ M1,P_M0] to [1,1] during normal operation
(see Tables 15 and 15a). In AUTO mode, the MAX5945
performs detection, classification, and powers up the
port automatically once a valid PD is detected at the
port. If a valid PD is not detected at the port, the
MAX5945 repeats the detection routine continuously
until a valid PD is detected.
Going into AUTO mode, the DET_EN and CLASS_EN
bits are set to high and stay high unless changed by
software. Using software to set DET_EN and/or
CLASS_EN low causes the MAX5945 to skip detection
and/or classification. As a protection, disabling the
detection routine in AUTO mode will not allow the corre-
sponding port to power up, unless the DET_BYP
(R23H[4]) is set to 1.
The AUTO status is latched into the register only during
a reset. Any changes to the AUTO input after reset is
ignored.
Semi-Automatic (SEMI) Mode
Enter semi-automatic (SEMI) mode by setting
R12h[P_M1,P_M0] to [1,0] during normal operation
(see Tables 15 and 15a). In SEMI mode, the MAX5945,
upon request, performs detection and/or classification
repeatedly but does not power up the port(s), regard-
less of the status of the port connection.
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 13
MAX5945
Setting R19h[PWR_ON_] (Table 21) high immediately
terminates detection/classification routines and turns on
power to the port(s).
R14h[DET_EN_, CLASS_EN_] default to low in SEMI
mode. Use software to set R14h[DET_EN_,
CLASS_EN_] to high to start the detection and/or classi-
fication routines. R14h[DET_EN_, CLASS_EN_] are
reset every time the software commands a power-off of
the port (either through reset or PWR_OFF). In any other
case, the status of the bits is left unchanged (including
when the state machine turns off the power because a
load disconnect or a fault condition is encountered).
MANUAL Mode
Enter MANUAL mode by setting R12h[P_M1,P_M0] to
[0,1] during normal operation (see Tables 15 and 15a).
MANUAL mode allows the software to dictate any
sequence of operation. Write a 1 to both R14h[DET_ EN_]
and R14h[CLASS_EN_] start detection and classifica-
tion operations, respectively, and in that priority order.
After execution, the command is cleared from the regis-
ter(s). PWR_ON_ has highest priority. Setting PWR_ON_
high at any time causes the device to immediately enter
the powered mode. Setting DET_EN and CLASS_EN
high at the same time causes detection to be per-
formed first. Once in the powered state, the device
ignores DET_EN_ or CLASS_EN_ commands.
When switching to MANUAL mode from another mode,
DET_EN_, CLASS_EN_ default to low. These bits
become pushbutton rather than configuration bits (i.e.,
writing ones to these bits while in MANUAL mode com-
mands the device to execute one cycle of detection
and/or classification. The bits are reset back to zeros at
the end of the execution). Putting the MAX5945 into
shutdown mode immediately turns off power and halts
all operations to the corresponding port. The event and
status bits of the affected port(s) are also cleared. In
SHUTDOWN mode, the DET_EN_, CLASS_EN_, and
PWR_ON_ commands are ignored.
In SHUTDOWN mode, the serial interface operates
normally.
Watchdog
R1Dh, R1Eh, and R1Fh registers control watchdog oper-
ation. The watchdog function, when enabled, allows the
MAX5945 to gracefully take over control or securely shut
down the power to the ports in case of software/firmware
crashes. Contact the factory for more details.
PD Detection
When PD detection is activated, the MAX5945 probes
the output for a valid PD. After each detection cycle,
the device sets the DET_END_ bit R04h/05h[3:0] high
and reports the detection results in the status registers
R0Ch[2:0], R0Dh[2:0], R0Eh[2:0], and R0Fh[2:0]. The
DET_END_ bit is reset to low when read through R05h
or after a port reset. Both DET_END_ bit status registers
are cleared after the port powers down.
A valid PD has a 25kΩdiscovery signature characteris-
tic as specified in the IEEE 802.3af standard. Table 1
shows the IEEE 802.3af specification for a PSE detect-
ing a valid PD signature (see the Typical Application
Circuit and Figure 2). The MAX5945 can probe and cat-
egorize different types of devices connected to the port
such as a valid PD, an open circuit, a low resistive load,
a high resistive load, a high capacitive load, a positive
DC supply, or a negative DC supply.
During detection, the MAX5945 turns off the external
MOSFET and forces two probe voltages through the
DET_ input. The current through the DET_ input is mea-
sured as well as the voltage at OUT_. A two-point slope
measurement is used as specified by the IEEE 802.3af
standard to verify the device connected to the port. The
MAX5945 implements appropriate settling times and a
100ms digital integration to reject 50Hz/60Hz power-
line noise coupling.
An external diode, in series with the DET_ input,
restricts PD detection to the 1st quadrant as specified
by the IEEE 802.3af standard. To prevent damage to
non-PD devices and to protect itself from an output
short circuit, the MAX5945 limits the current into DET_
to less than 2mA maximum during PD detection.
In midspan mode, the MAX5945 waits 2.2s before
attempting another detection cycle after every failed
detection. The first detection, however, happens imme-
diately after issuing the detection command.
Power Device Classification
(PD Classification)
During the PD classification mode, the MAX5945 forces
a probe voltage (-18V) at DET_ and measures the cur-
rent into DET_. The measured current determines the
class of the PD.
After each classification cycle, the device sets the
CL_END_ bit (R04h/05h[7:4]) high and reports the clas-
sification results in the status registers R0Ch[6:4],
R0Dh[6:4], R0Eh[6:4], and R0Fh[6:4]. The CL_END_ bit
is reset to low when read through register R05h or after
a port reset. Both CL_END_ bit status registers are
cleared after the port powers down.
Quad Network Power Controller
for Power-Over-LAN
14 ______________________________________________________________________________________
Table 2 shows the IEEE 802.3af requirement for a PSE
classifying a PD at the power interface (PI).
Powered State
When the part enters PWR MODE, the tSTART and tDISC
timers are reset. Before turning on the power, the part
checks if any other port is not turning on and if the
tFAULT timer is zero. Another check is performed if the
ACD_EN bit is set, in this case OSC_FAIL bit must be
low (oscillator is okay) for the port to be powered.
If these conditions are met then the part enters startup
where it turns on power to the port. An internal signal,
POK_, is asserted high when VOUT is within 2V from
VEE. PGOOD_ status bits are set high if POK_ stays
high longer than tPGOOD. PGOOD immediately resets
when POK goes low.
The PWR_CHG bit sets when a port powers up or down.
PWR_EN sets when a port powers up and resets when a
port shuts down. The port shutdown timer lasts 0.5ms
and prevents other ports from turning off during that peri-
od, except in the case of emergency shutdowns (RESET
= L, RESET_IC = H, VEEUVLO, VDDUVLO, and TSHD).
The MAX5945 always checks the status of all ports before
turning off. A priority logic system determines the order to
prevent the simultaneous turn-on or turn-off of the ports.
The port with the lesser ordinal number gets priority over
the others (i.e., port 1 turns on first, port 2 second, port 3
third and port 4 fourth). Setting PWR_OFF_ high turns off
power to the corresponding port.
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 15
PARAMETER
SYMBOL
MIN
MAX
UNITS
ADDITIONAL INFORMATION
Open-Circuit Voltage VOC — 30 V In detection mode only
Short-Circuit Current ISC — 5 mA In detection mode only
Valid Test Voltage
VVALID
2.8 10 V
Voltage Difference Between
Test Points
∆VTEST
1—V
Time Between Any Two Test
Points tBP 2 — ms This timing implies a 500Hz maximum probing frequency
Slew Rate
VSLEW
— 0.1
V/µs
Accept Signature Resistance
RGOOD
19
26.5
kΩ
Reject Signature Resistance
RBAD
< 15 > 33
kΩ
Open-Circuit Resistance
ROPEN 500
—kΩ
Accept Signature
Capacitance
CGOOD
—
150
nF
Reject Signature
Capacitance CBAD 10 — µF
Signature Offset Voltage
Tolerance VOS 0 2.0 V
Signature Offset Current
Tolerance IOS 012µA
Table 1. PSE PI Detection Modes Electrical Requirement
(Table 33-2 of the IEEE 802.3af Standard)
MEASURED ICLASS (mA) CLASSIFICATION
0 to 5 Class 0
> 5 and < 8 May be Class 0 and 1
8 to 13 Class 1
> 13 and < 16 May be Class 0, 1, or 2
16 to 21 Class 2
> 21 and < 25 May be Class 0, 2, or 3
25 to 31 Class 3
> 31 and <35 May be Class 0, 3, or 4
35 to 45 Class 4
> 45 and < 51 May be Class 0 or 4
Table 2. PSE Classification of a PD
(Table 33-4 of the IEEE 802.3af Standard)
MAX5945
Overcurrent Protection
A sense resistor (RS), connected between SENSE_ and
VEE, monitors the load current. Under all circum-
stances, the voltage across RSnever exceeds the
threshold VSU_LIM. If SENSE_ exceeds VSU_LIM, an
internal current-limiting circuit regulates the GATE volt-
age, limiting the current to ILIM = VSU_LIM / RS. During
transient conditions, if the SENSE_ voltage exceeds
VSU_LIM, a fast pulldown circuit activates to quickly
recover from the current overshoot. During startup, if
the current-limit condition persists, when the startup
timer, tSTART, times out, the port shuts off and the
STRT_FLT_ bit is set. In normal powered state, the
MAX5945 checks for overcurrent conditions as deter-
mined by VFLT_LIM = ~88% of VSU_LIM. The tFAULT
counter sets the maximum allowed continuous
overcurrent period. The tFAULT counter increases when
VSENSE exceeds VFLT_LIM and decreases at a slower
pace when VSENSE drops below VFLT_LIM. A slower
decrement for the tFAULT counter allows for detecting
repeated short-duration overcurrents. When the counter
reaches the tFAULT limit, the MAX5945 powers off the
port and asserts the IMAX_FLT_ bit. For a continuous
overstress, a fault latches exactly after a period of
tFAULT. VSU_LIM, is programmable using R27h[4-7].
tFAULT is programmable using R16h[2-3] and R28[4-7].
After power-off due to an overcurrent fault, and if the
RSTR_EN bit is set, the tFAULT timer is not immediately
reset but starts decrementing at the same slower pace.
The MAX5945 allows the port to be powered on only
when the tFAULT counter is at zero. This feature sets an
automatic duty-cycle protection to the external MOSFET
to avoid overheating. The duty cycle is programmable
using R16h[6-7].
The MAX5945 continuously flags when the current
exceeds the maximum current allowed for the class as
indicated in the CLASS status register. When class
overcurrent occurs, the MAX5945 sets the IVC bit in
register R09h.
Foldback Current
During startup and normal operation, an internal circuit
senses the voltage at OUT_ and reduces the current-
limit value when (VOUT_ - VEE) > 30V. The foldback
function helps to reduce the power dissipation on the
FET. The current limit eventually reduces to 1/3 of ILIM
when (VOUT_ - VEE ) > 50V (see Figure 4).
Quad Network Power Controller
for Power-Over-LAN
16 ______________________________________________________________________________________
Figure 2. Detection, Classification, and Power-Up Port
Sequence
OUT_
-4V
-9V
-18V
-48V
t
tDETI tDETII tCLASS
150ms 150ms 21.3ms
0V
0V
80ms
Figure 3. PGOOD Timing
PGOOD
POK tPGOOD
MOSFET Gate Driver
Connect the gate of the external n-channel MOSFET to
GATE_. An internal 50µA current source pulls GATE_ to
(VEE + 10V) to turn on the MOSFET. An internal 40µA
current source pulls down GATE_ to VEE to turn off the
MOSFET.
The pullup and pulldown current controls the maximum
slew rate at the output during turn-on or turn-off. The
pullup current (gate-charging current) is programmable
using R23h[5-7]. Use the following equation to set the
maximum slew rate:
where CGD is the total capacitance between GATE and
DRAIN of the external FET. Current limit and the capac-
itive load at the drain control the slew rate during start-
up. During current-limit regulation, the MAX5945
manipulates the GATE_ voltage to control the voltage at
SENSE_. A fast pulldown activates if SENSE_ over-
shoots the limit threshold. The fast pulldown current
increases with the amount of overshoot. The maximum
fast pulldown current is 100mA.
During turn-off, when the GATE voltage reaches a value
lower than 1.2V, a strong pulldown switch is activated
to keep the FET securely off.
Digital Logic
VDD supplies power for the internal logic circuitry. VDD
ranges from +1.71V to +3.7V and determines the logic
thresholds for the CMOS connections (SDAIN,
SDAOUT, SCL, AUTO, SHD_, A_). This voltage range
enables the MAX5945 to interface with a nonisolated
low-voltage microcontroller. The MAX5945 checks the
digital supply for compatibility with the internal logic.
The MAX5945 also features a VDD undervoltage lockout
(VDDUVLO) of +1.35V. A VDDUVLO condition keeps the
MAX5945 in reset and the ports shut off. Bit 0 in the
supply event register shows the status of VDDUVLO
(Table 11) after VDD has recovered. All logic inputs and
outputs reference to DGND. DGND and AGND are
completely isolated internally to the MAX5945. In a
completely isolated system, the digital signal can be
referenced indifferently to VAGND or VEE or at voltages
even higher than AGND (up to 60V). VDD - VDGND must
be greater than 3.0V when VDGND ≤(VEE + 3.0V)
When using the AC disconnect detection feature,
AGND must be connected directly to DGND and VDD
must be greater than +3V. In this configuration, con-
nect DGND to AGND at a single point in the system as
close to MAX5945 as possible.
Hardware Shutdown
SHD_ shuts down the respective ports without using
the serial interface. Hardware shutdown offers an emer-
gency turn-off feature that allows a fast disconnect of
the power supply from the port. Pull SHD_ low to
remove power.
Interrupt
The MAX5945 contains an open-drain logic output (INT)
that goes low when an interrupt condition exists. R00h
and R01h (Tables 5 and 6) contain the definitions of the
interrupt registers. The mask register R01h determines
events that trigger an interrupt. As a response to an
interrupt, the controller reads the status of the event reg-
ister to determine the cause of the interrupt and takes
subsequent actions. Each interrupt event register also
contains a clear-on-read (CoR) register. Reading
through the CoR register address clears the interrupt.
INT remains low when reading the interrupt through the
read-only addresses. For example, to clear a startup
fault on port 4 read address 09h (see Table 10). Use the
global pushbutton bit on register 1Ah (bit 7, Table 22) to
clear interrupts, or use a software or hardware reset.
Undervoltage and Overvoltage Protection
The MAX5945 contains several undervoltage and over-
voltage protection features. Table 11 in the Register Map
and Description section shows a detailed list of the
undervoltage and overvoltage protection features. An
internal VEE undervoltage lockout (VEEUVLO) circuit
keeps the MOSFET off and the MAX5945 in reset until
VAGND - VEE exceeds 29V for more than 3ms. An internal
VEE overvoltage (VEE_OV) circuit shuts down the ports
when (VAGND - VEE) exceeds 60V. The digital supply also
contains an undervoltage lockout (VDDUVLO).
∆
∆
V
t
I
C
OUT GATE
GD
=
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 17
Figure 4. Foldback Current Characteristics
50V30V
VSU_LIM
VSU_LIM / 3
(VSENSE_ - VEE)
(VOUT_ - VEE)
MAX5945
The MAX5945 also features three other undervoltage
and overvoltage interrupts: VEE undervoltage interrupt
(VEEUV), VDD undervoltage interrupt (VDDUV), and VDD
overvoltage interrupt (VDDOV). A fault latches into the
supply events register (Table 11) but the MAX5945 does
not shut down the ports with a VEEUV, VDDUV, or VDDOV.
DC Disconnect Monitoring
Setting R13h[DCD_EN_] bits high enable DC load mon-
itoring during a normal powered state. If SENSE_ falls
below the DC load disconnect threshold, VDCTH, for
more than tDISC, the device turns off power and asserts
the LD_DISC_ bit of the corresponding port. tDISC is
programmable using R16h[0-1] and R27h[0-3].
AC Disconnect Monitoring
The MAX5945 features AC load disconnect monitoring.
Connect an external sine wave to OSC_IN. The oscilla-
tor requirements are:
• Frequency x VP-P = 200VP-P x Hz ±15%
• Positive peak voltage > +2V
• Frequency > 60Hz
• A 100Hz ±10%, 2VP-P ±5%, with +1.2V offset
(VPEAK = +2.2V, typ) is recommended.
The MAX5945 buffers and amplifies 3x the external
oscillator signal and sends the signal to DET_, where
the sine wave is AC coupled to the output. The
MAX5945 senses the presence of the load by monitor-
ing the amplitude of the AC current returned to DET_
(see the Functional Diagram).
Setting R13h[ACD_EN_] bits high enable AC load dis-
connect monitoring during the normal powered state. If
the AC current peak at the DET_ pin falls below IACTH
for more than tDISC, the device turns off power and
asserts the LD_DISC_ bit of the corresponding port.
IACTH is programmable using R23h[0-3].
An internal comparator checks for a proper amplitude
of the oscillator input. If the positive peak of the input
sinusoid falls below a safety value of 2V, OSC_FAIL
sets and the port shuts down. Power cannot be applied
to the ports when ACD_EN is set high and OSC_FAIL is
set high. Leave OSC_IN unconnected or connect it to
DGND when not using AC disconnect detection.
When using the AC disconnect detection feature, con-
nect AGND directly to DNGD as close as possible to
the IC. The MAX5945 also requires a VDD of greater
than +3V for this function. See the Typical Application
Circuit with AC disconnect for other external compo-
nent requirements.
Thermal Shutdown
If the MAX5945 die temperature reaches +150°C, an
overtemperature fault generates and the MAX5945
shuts down and the MOSFETs turn off. The die temper-
ature of the MAX5945 must cool down below +130°C to
remove the overtemperature fault condition. After a
thermal shutdown, the part is reset.
Address Inputs
A3, A2, A1, and A0 represent the four LSBs of the chip
address, the complete 7-bit chip address (see Table 3).
The four LSBs latch on the low-to-high transition of
RESET or after a power-supply start (either on VDD or
VEE). Address inputs default high through an internal
50kΩpullup resistor to VDD. The MAX5945 also
responds to the call through a global address 60h (see
the Global Addressing and Alert Response Protocol
section).
I2C-Compatible Serial Interface
The MAX5945 operates as a slave that sends and
receives data through an I2C-compatible, 2-wire or 3-
wire interface. The interface uses a serial data input line
(SDAIN), a serial data output line (SDAOUT), and a ser-
ial clock line (SCL) to achieve bidirectional communica-
tion between master(s) and slave(s). A master (typically
a microcontroller) initiates all data transfers to and from
the MAX5945, and generates the SCL clock that syn-
chronizes the data transfer. In most applications, con-
nect the SDAIN and the SDAOUT lines together to form
the serial data line (SDA).
Using the separate input and output data lines allows
optocoupling with the controller bus when an isolated
supply powers the microcontroller.
The MAX5945 SDAIN line operates as an input. The
MAX5945 SDAOUT operates as an open-drain output.
A pullup resistor, typically 4.7kΩ, is required on
SDAOUT. The MAX5945 SCL line operates only as an
input. A pullup resistor, typically 4.7kΩ, is required on
SCL if there are multiple masters, or if the master in a
single-master system has an open-drain SCL output.
Serial Addressing
Each transmission consists of a START condition (Figure
7) sent by a master, followed by the MAX5945 7-bit slave
address plus R/Wbit, a register address byte, one or
more data bytes, and finally a STOP condition.
Quad Network Power Controller
for Power-Over-LAN
18 ______________________________________________________________________________________
010
A3 A2 A1 A0
R/W
Table 3. MAX5945 Address
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master fin-
ishes communicating with the slave, the master issues
a STOP (P) condition by transitioning SDA from low to
high while SCL is high. The stop condition frees the bus
for another transmission.
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 19
Figure 5. 2-Wire Serial Interface Timing Details
SCL
SDAIN
tLOW
tHIGH
tRtF
tBUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITION
START CONDITION
tHD, STA
tSU, DAT
tHD, DAT
tSU, STA tHD, STA
tSU, STO
Figure 6. 3-Wire Serial Interface Timing Details
SCL
SDAIN/SDA
tLOW
tHIGH
tRtF
tBUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITION
START CONDITION
tHD, STA
tSU, DAT
tHD, DAT
tSU, STA tHD, STA
tSU, STO
Figure 8. Bit Transfer
SDA
SCL
DATA LINE STABLE;
DATA VALID
.
CHANGE OF
DATA ALLOWED
Figure 7. Start and Stop Conditions
START STOP
SP
SDA/
SDAIN
SCL
MAX5945
Bit Transfer
Each clock pulse transfers one data bit (Figure 8). The
data on SDA must remain stable while SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 9),
which the recipient uses as a handshake receipt of each
byte of data. Thus each byte effectively transferred
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA (or the SDAOUT
in the 3-wire interface) during the acknowledge clock
pulse, so the SDA line is stable low during the high peri-
od of the clock pulse. When the master transmits to the
MAX5945, the MAX5945 generates the acknowledge bit.
When the MAX5945 transmits to the master, the master
generates the acknowledge bit.
Slave Address
The MAX5945 has a 7-bit long slave address (Figure
10). The bit following the 7-bit slave address (bit eight)
is the R/Wbit, which is low for a write command and
high for a read command.
010 always represent the first three bits (MSBs) of the
MAX5945 slave address. Slave address bits A3, A2,
A1, and A0 represent the states of the MAX5945’s A3,
A2, A1, and A0 inputs, allowing up to sixteen MAX5945
devices to share the bus. The states of the A3, A2, A1,
and A0 latch in upon the reset of the MAX5945 into reg-
ister R11h. The MAX5945 monitors the bus continuous-
ly, waiting for a START condition followed by the
MAX5945’s slave address. When the MAX5945 recog-
nizes its slave address, it acknowledges and is then
ready for continued communication.
Global Addressing and Alert Response Protocol
The global address call is used in writing mode to write
the same register to multiple devices (address 0x60). In
read mode (address 0x61), the global address call is
used as the alert response address. When responding to
a global call, the MAX5945 puts out on the data line its
own address whenever its interrupt is active and so does
every other device connected to the SDAOUT line that
has an active interrupt. After every bit is transmitted, the
MAX5945 checks that the data line effectively corre-
sponds to the data it is delivering. If it is not, it then backs
off and frees the data line. This litigation protocol always
allows the part with the lowest address to complete the
transmission. The microcontroller can then respond to
the interrupt and take proper actions. The MAX5945
does not reset its own interrupt at the end of the alert
response protocol. The microcontroller has to do it by
clearing the event register through their CoR addresses
or activating the CLR_INT pushbutton.
Quad Network Power Controller
for Power-Over-LAN
20 ______________________________________________________________________________________
Figure 9. Acknowledge
SCL
SDA
BY TRANSMITTER
CLOCK PULSE FOR ACKNOWLEDGEMENT
START CONDITION
SDA
BY RECEIVER
12 89
S
Figure 10. Slave Address
SDA
SCL
1
0A3 A2 A1 A00
MSB LSB
ACKR/W
Message Format for Writing the MAX5945
A write to the MAX5945 comprises of the MAX5945’s
slave address transmission with the R/Wbit set to 0, fol-
lowed by at least one byte of information. The first byte
of information is the command byte (Figure 11). The
command byte determines which register of the
MAX5945 is written to by the next byte, if received. If
the MAX5945 detects a STOP condition after receiving
the command byte, then the MAX5945 takes no further
action beyond storing the command byte. Any bytes
received after the command byte are data bytes. The
first data byte goes into the internal register of the
MAX5945 selected by the command byte. If the
MAX5945 transmits multiple data bytes before the
MAX5945 detects a STOP condition, these bytes store
in subsequent MAX5945 internal registers because the
control byte address auto-increments.
Any bytes received after the control byte are data
bytes. The first data byte goes into the internal register
of the MAX5945 selected by the control byte (Figure 8).
If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are stored in subse-
quent MAX5945 internal registers because the control
byte address auto-increments.
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 21
Figure 11. Control Byte Received
SAAP0SLAVE ADDRESS CONTROL BYTE
ACKNOWLEDGE FROM MAX5945
ACKNOWLEDGE FROM MAX5945
D15 D14 D13 D12 D11 D10 D9 D8
CONTROL BYTE IS STORED ON RECEIPT OF STOP CONDITION
R/W
Figure 12. Control and Single Data Byte Received
SAAAP0SLAVE ADDRESS CONTROL BYTE DATA BYTE
ACKNOWLEDGE FROM MAX5945
1 BYTE
AUTO-INCREMENT
MEMORY WORD ADDRESS
D15 D14 D13 D12 D11 D10 D9 D8 D1 D0D3 D2D5 D4D7 D6
HOW CONTROL BYTE AND DATA BYTE MAP
INTO THE REGISTER
ACKNOWLEDGE FROM MAX5945 ACKNOWLEDGE FROM MAX5945
R/W
Figure 13. ‘n’ Data Bytes Received
SAAAP0SLAVE ADDRESS CONTROL BYTE DATA BYTE
ACKNOWLEDGE FROM MAX5945
n BYTES
AUTO-INCREMENT
MEMORY WORD ADDRESS
D15 D14 D13 D12 D11 D10 D9 D8 D1 D0D3 D2D5 D4D7 D6
HOW CONTROL BYTE AND DATA BYTE MAP
INTO THE REGISTER
ACKNOWLEDGE FROM MAX5945 ACKNOWLEDGE FROM MAX5945
R/W
MAX5945
Message Format for Reading
The MAX5945 reads using the MAX5945’s internally
stored command byte as an address pointer, the same
way the stored command byte is used as an address
pointer for a write. The pointer auto-increments after
reading each data byte using the same rules as for a
write. Thus, a read is initiated by first configuring the
MAX5945’s command byte by performing a write
(Figure 12). The master now reads ‘n’ consecutive
bytes from the MAX5945, with the first data byte read
from the register addressed by the initialized command
byte (Figure 13). When performing read-after-write veri-
fication, remember to reset the command byte’s
address because the stored control byte address auto-
increments after the write.
Operation with Multiple Masters
When the MAX5945 operates on a 2-wire interface with
multiple masters, a master reading the MAX5945
should use repeated starts between the write that sets
the MAX5945’s address pointer, and the read(s) that
takes the data from the location(s). It is possible for
master 2 to take over the bus after master 1 has set up
the MAX5945’s address pointer but before master 1
has read the data. If master 2 subsequently resets the
MAX5945’s address pointer then master 1’s read may
be from an unexpected location.
Command Address Auto-Incrementing
Address auto-incrementing allows the MAX5945 to be
configured with fewer transmissions by minimizing the
number of times the command address needs to be
sent. The command address stored in the MAX5945
generally increments after each data byte is written or
read (Table 4). The MAX5945 is designed to prevent
overwrites on unavailable register addresses and unin-
tentional wrap-around of addresses.
Register Map And Description
The interrupt register (Table 5) summarizes the event
register status and is used to send an interrupt signal
(INT goes low) to the controller. Writing a 1 to R1Ah[7]
clears all interrupt and events registers. A reset sets
R00h to 00h.
INT_EN (R17h[7]) is a global interrupt mask (Table 6).
The MASK_ bits activate the corresponding interrupt
bits in register R00h. Writing a 0 to INT_EN (R17h[7])
disables the INT output.
A reset sets R01h to AAA00A00b, where A is the state
of the AUTO input prior to the reset.
The power event register (Table 7) records changes in
the power status of the four ports. Any change in
PGOOD_ (R10h[7:4]) sets PG_CHG_ to 1. Any change
in the PWR_EN_ (R10h[3:0]) sets PWEN_CHG_ to 1.
PG_CHG_ and PWEN_CHG_ trigger on the edges of
PGOOD_ and PWR_EN_ and do not depend on the
actual level of the bits. The power event register has
two addresses. When read through the R02h address,
the content of the register is left unchanged. When read
through the CoR R03h address, the register content will
be cleared. A reset sets R02h/R03h = 00h.
DET_END_/CL_END_ is set high whenever detection/
classification is completed on the corresponding port.
A 1 in any of the CL_END_ bits forces R00h[4] to 1. A 1
in any of the DET_END_ bits forces R00h[3] to 1. As
with any other events register, the detect event register
(Table 8) has two addresses. When read through the
R04h address, the content of the register is left
unchanged. When read through the CoR R05h
address, the register content will be cleared. A reset
sets R04h/R05h = 00h.
LD_DISC_ is set high whenever the corresponding port
shuts down due to detection of load removal.
IMAX_FLT_ is set high when the port shuts down due to
an extended overcurrent event after a successful start-
up. A 1 in any of the LD_DISC_ bits forces R00h[2] to 1.
A 1 in any of the IMAX_FLT_ bits forces R00h[5] to 1.
As with any of the other events register, the fault event
register (Table 9) has two addresses. When read
through the R06h address, the content of the register is
left unchanged. When read through the CoR R07h
address, the register content will be cleared. A reset
sets R06h/R07h = 00h.
Quad Network Power Controller
for Power-Over-LAN
22 ______________________________________________________________________________________
COMMAND BYTE
ADDRESS RANGE
AUTO-INCREMENT BEHAVIOR
0x00 to 0x26 Command address will auto-
increment after byte read or written
0x26 Command address remains at 0x26
after byte written or read
Table 4. Auto-Increment Rules
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 23
ADDRESS = 00h
SYMBOL
BIT R/W
DESCRIPTION
SUP_FLT
7R
Interrupt signal for supply faults. SUP_FLT is the logic OR of all the bits [7:0] in register R0Ah/R0Bh
(Table 8).
TSTR_FLT
6R
Interrupt signal for startup failures. TSRT_FLT is the logic OR of bits [7:0] in register R08h/R09h
(Table 7).
IMAX_FLT
5R
Interrupt signal for current-limit violations. IMAX_FLT is the logic OR of bits [3:0] in register
R06h/R07h (Table 6).
CL_END
4R
Interrupt signal for completion of classification. CL_END is the logic OR of bits [7:4] in register
R04h/R05h (Table 5)
DET_END
3R
Interrupt signal for completion of detection. DET_END is the logic OR of bits [3:0] in register
R04h/R05h (Table 5).
LD_DISC
2R
Interrupt signal for load disconnection. LD_DISC is the logic OR of bits [7:4] in register R06h/R07h
(Table 6).
PG_INT 1 R Interrupt signal for PGOOD status change. PG_INT is the logic OR of bits [7:4] in register R02h/R03h
(Table 4).
PE_INT 0 R Interrupt signal for power-enable status change. PEN_INT is the logic OR of bits [3:0] in register
R02h/R03h (Table 4).
Table 5. Interrupt Register
ADDRESS = 01h
SYMBOL
BIT R/W
DESCRIPTION
MASK7 7
R/W
Interrupt mask bit 7. A logic high enables the SUP_FLT interrupts. A logic low disables the SUP_FLT
interrupts.
MASK6 6
R/W
Interrupt mask bit 6. A logic high enables the TSTR_FLT interrupts. A low disables the TSTR_FLT
interrupts.
MASK5 5
R/W
Interrupt mask bit 5. A logic high enables the IMAX_FLT interrupts. A logic low disables the
IMAX_FLT interrupts.
MASK4 4
R/W
Interrupt mask bit 4. A logic high enables the CL_END interrupts. A logic low disables the CL_END
interrupts.
MASK3 3
R/W
Interrupt mask bit 3. A logic high enables the DET_END interrupts. A logic low disables the
DET_END interrupts.
MASK2 2
R/W
Interrupt mask bit 2. A logic high enables the LD_DISC interrupts. A logic low disables the LD_DISC
interrupts.
MASK1 1
R/W
Interrupt mask bit 1. A logic high enables the PG_INT interrupts. A logic low disables the PG_INT
interrupts.
MASK0 0
R/W
Interrupt mask bit 0. A logic high enables the PEN_INT interrupts. A logic low disables the PEN_INT
interrupts.
Table 6. Interrupt Mask Register
MAX5945
Quad Network Power Controller
for Power-Over-LAN
24 ______________________________________________________________________________________
ADDRESS =
02h 03h
SYMBOL
BIT R/W R/W
DESCRIPTION
PG_CHG4
7 R CoR
PGOOD change event for port 4
PG_CHG3
6 R CoR
PGOOD change event for port 3
PG_CHG2
5 R CoR
PGOOD change event for port 2
PG_CHG1
4 R CoR
PGOOD change event for port 1
PWEN_CHG4
3 R CoR
Power enable change event for port 4
PWEN_CHG3
2 R CoR
Power enable change event for port 3
PWEN_CHG2
1 R CoR
Power enable change event for port 2
PWEN_CHG1
0 R CoR
Power enable change event for port 1
Table 7. Power Event Register
ADDRESS =
06h 07h
SYMBOL
BIT R/W R/W
DESCRIPTION
LD_DISC4
7 R CoR
Disconnect on port 4
LD_DISC3
6 R CoR
Disconnect on port 3
LD_DISC2
5 R CoR
Disconnect on port 2
LD_DISC1
4 R CoR
Disconnect on port 1
IMAX_FLT4
3 R CoR
Overcurrent on port 4
IMAX_FLT3
2 R CoR
Overcurrent on port 3
IMAX_FLT2
1 R CoR
Overcurrent on port 2
IMAX_FLT1
0 R CoR
Overcurrent on port 1
Table 9. Fault Event Register
ADDRESS =
04h 05h
SYMBOL
BIT R/W R/W
DESCRIPTION
CL_END4
7 R CoR
Classification completed on port 4
CL_END3
6 R CoR
Classification completed on port 3
CL_END2
5 R CoR
Classification completed on port 2
CL_END1
4 R CoR
Classification completed on port 1
DET_END4
3 R CoR
Detection completed on port 4
DET_END3
2 R CoR
Detection completed on port 3
DET_END2
1 R CoR
Detection completed on port 2
DET_END1
0 R CoR
Detection completed on port 1
Table 8. Detect Event Register
If the port remains in current limit or the PGOOD condi-
tion is not met at the end of the startup period, the port
shuts down and the corresponding STRT_FLT_ is set to
1. A 1 in any of the STRT_FLT_ bits forces R00h[6] to 1.
IVC_ is set to 1 whenever the port current exceeds the
maximum allowed limit for the class (determined during
the classification process). A 1 in any of IVC_ forces
R00h[6] to 1. When the CL_DISC (R17h[2]) is set to 1,
the port will also limit the load current according to its
class as specified in the Electrical Characteristics
table. As with any other events register, the startup
event register (Table 10) has two addresses. When
read through the R08h address, the content of the reg-
ister is left unchanged. When read through the CoR
R09h address, the register content will be cleared. A
reset sets R08h/R09h = 00h.
The MAX5945 continuously monitors the power supplies
and sets the appropriate bits in the supply event register
(Table 11). VDD_OV / VEE_OV is set to 1 whenever VDD /
VEE exceeds its overvoltage threshold. VDD_UV / VEE_UV
is set to 1 whenever VDD / VEE falls below its undervolt-
age threshold.
OSC_FAIL is set to 1 whenever the amplitude of the
oscillator signal at the OSC_input falls below a level
that might compromise the AC disconnect detection
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 25
ADDRESS =
08h 09h
SYMBOL
BIT R/W R/W
DESCRIPTION
IVC4
7 R CoR
Class overcurrent flag for port 4
IVC3
6 R CoR
Class overcurrent flag for port 3
IVC2
5 R CoR
Class overcurrent flag for port 2
IVC1
4 R CoR
Class overcurrent flag for port 1
STRT_FLT4
3 R CoR
Startup failed on port 4
STRT_FLT3
2 R CoR
Startup failed on port 3
STRT_FLT2
1 R CoR
Startup failed on port 2
STRT_FLT1
0 R CoR
Startup failed on port 1
Table 10. Startup Event Register
ADDRESS =
0Ah 0Bh
SYMBOL
BIT R/W R/W
DESCRIPTION
TSD
7 R CoR
Overtemperature shutdown
VDD_OV
6 R CoR
VDD overvoltage condition
VDD_UV
5 R CoR
VDD undervoltage condition
VEE_UVLO
4 R CoR
VEE undervoltage lockout condition
VEE_OV
3 R CoR
VEE overvoltage condition
VEE_UV
2 R CoR
VEE undervoltage condition
OSC_FAIL
1 R CoR
Oscillator amplitude is below limit
VDD_UVLO
0 R CoR
VDD undervoltage lockout condition
Table 11. Supply Event Register
ADDRESS = 0Ch, 0Dh, 0Eh, 0Fh
SYMBOL BIT
R/W
DESCRIPTION
Reserved 7 R Reserved
6 R CLASS_[2]
5 R CLASS_[1]CLASS_
4 R CLASS_[0]
Reserved 3 R Reserved
2 R DET_[2]
1 R DET_[1]DET_ST_
0 R DET_[0]
Table 12. Port Status Registers
MAX5945
function. OSC_FAIL generates an interrupt only if at
least one of the ACD_EN (R13h[7:4]) bits is set high.
A thermal-shutdown circuit monitors the temperature of
the die and resets the MAX5945 if the temperature
exceeds +150°C. TSD is set to 1 after the MAX5945
returns to normal operation. TSD is also set to 1 after
every UVLO reset.
When VDD and/or |VEE| is below its undervoltage lock-
out (UVLO) threshold, the MAX5945 is in reset mode
and securely holds all ports off. When VDD and |VEE|
rise to above their respective UVLO thresholds, the
device comes out of reset as soon as the last supply
crosses the UVLO threshold. The last supply corre-
sponding UV and UVLO bits in the supply event regis-
ter will be set to 1.
A 1 in any supply event register’s bits forces R00h[7] to
1. As with any other events register, the supply event
register has two addresses. When read through the
R0Ah address, the content of the register is left
unchanged. When read through the CoR R0Bh
address, the register content will be cleared. A reset
sets R0Ah/R0Bh to 00100001 if VDD comes up after
VEE or to 00010100 if VEE comes up after VDD.
The port status register (Table 12) records the results of
the detection and classification at the end of each phase
in three encoding bits each. R0Ch contains detection and
classification status of port 1. R0Dh corresponds to port
2, R0Eh corresponds to port 3 and R0Fh corresponds to
port 4. Tables 12a and 12b show the detection/classifica-
tion result decoding charts, respectively.
As a protection, when POFF_CL (R17h[3], Table 20) is
set to 1, the MAX5945 prohibits turning on power to the
port that returns a status 111 after classification. A reset
sets 0Ch, 0Dh, 0Eh, and 0Fh = 00h.
PGOOD_ is set to 1 (Table 13) at the end of the power-up
startup period if the power-good condition is met (0 <
(VOUT - VEE) < PGTH). The power-good condition must
remain valid for more than tPGOOD to assert PGOOD_.
PGOOD_ is reset to 0 whenever the output falls out of the
power-good condition. A fault condition immediately
forces PGOOD_ low.
PWR_EN_ is set to 1 when the port power is turned on.
PWR_EN_ resets to 0 as soon as the port turns off. Any
transition of PGOOD_ and PWR_EN_ bits set the corre-
sponding bit in the power event registers R02h/R03h
(Table 7). A reset sets R10h = 00h.
A3, A2, A1, A0 (Table 14) represent the four LSBs of the
MAX5945 address (Table 3). During a reset, the device
latches into R11h. These four bits address from the cor-
responding inputs as well as the state of the MIDSPAN
and AUTO inputs. Changes to those inputs during nor-
mal operation are ignored.
The MAX5945 uses two bits for each port to set the mode
of operation (Table 15). Set the modes according to
Table 15a.
A reset sets R12h = AAAAAAAA where A represents
the latched-in state of the AUTO input prior to the reset.
Use software to change the mode of operation.
Quad Network Power Controller
for Power-Over-LAN
26 ______________________________________________________________________________________
DET_ST_[2:0]
DETECTED
DESCRIPTION
000
None
Detection status unknown
001
DCP
Positive DC supply connected at the port (AGND - VOUT_ < 1.65V)
010
HIGH CAP
High capacitance at the port (>5µF)
011
RLOW
Low resistance at the port. RPD < 17kΩ.
100
DET_OK
Detection pass. 17kΩ > RPD > 28kΩ.
101
RHIGH
High resistance at the port. RPD > 28kΩ.
110
OPEN0
Open port (I < 12.5µA)
111
DCN
Negative DC supply connected to the port (VOUT - VEE < 2V)
Table 12a. Detection Result Decoding Chart
CLASS_[2:0] CLASS RESULT
000 Unknown
001 1
010 2
011 3
100 4
101 Undefined (treated as CLASS 0)
110 0
111 Current limit (>ICILIM)
Table 12b. Classification Result
Decoding Chart
Software resets of ports (RESET_P_ bit, Table 22) do
not affect the mode register.
Setting DCD_EN_ to 1 enables the DC load disconnect
detection feature (Table 16). Setting ACD_EN_ to 1
enables the AC load disconnect feature. If enabled, the
load disconnect detection starts during power mode
and after startup when the corresponding PGOOD_ bit
in register R10h (Table 13) goes high. A Reset sets
R13h = 0000AAAA where A represents the latched-in
state of the AUTO input prior to the reset.
Setting DET_EN_/CLASS_EN_ to 1 (Table 17) enables
load detection/classification, respectively. Detection
always has priority over classification. To perform clas-
sification without detection, set the DET_EN_ bit low
and CLASS_EN_ bit high.
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 27
ADDRESS = 10h
SYMBOL
BIT R/W
DESCRIPTION
PGOOD4
7R
Power-good condition on port 4
PGOOD3
6R
Power-good condition on port 3
PGOOD2
5R
Power-good condition on port 2
PGOOD1
4R
Power-good condition on port 1
PWR_EN4
3R
Power is enabled on port 4
PWR_EN3
2R
Power is enabled on port 3
PWR_EN2
1R
Power is enabled on port 2
PWR_EN1
0R
Power is enabled on port 1
Table 13. Power Status Register
ADDRESS = 11h
SYMBOL
BIT R/W
DESCRIPTION
Reserved
7R
Reserved
Reserved
6R
Reserved
A3
5R
Device address, A3 pin latched-in status
A2
4R
Device address, A2 pin latched-in status
A1
3R
Device address, A1 pin latched-in status
A0
2R
Device address, A0 pin latched-in status
MIDSPAN
1R
MIDSPAN input’s latched-in status
AUTO
0R
AUTO input’s latched-in status
Table 14. Address Input Status Register
ADDRESS = 12h
SYMBOL
BIT R/W
DESCRIPTION
P4_M1
7 R/W
M0DE[1] for port 4
P4_M0
6 R/W
M0DE[0] for port 4
P3_M1
5 R/W
M0DE[1] for port 3
P3_M0
4 R/W
M0DE[0] for port 3
P2_M1
3 R/W
M0DE[1] for port 2
P2_M0
2 R/W
M0DE[0] for port 2
P1_M1
1 R/W
M0DE[1] for port 1
P1_M0
0 R/W
M0DE[0] for port 1
Table 15. Mode Register
MAX5945
In MANUAL mode, R14h works like a pushbutton. Set
the bits high to begin the corresponding routine. The bit
clears after the routine finishes.
When entering AUTO mode, R14h defaults to FFh.
When entering MANUAL mode, R14h defaults to 00h.
When entering SEMI mode, R1h is left unchanged but it
is reset every time the software commands power off
the port. A reset or power-up sets R14h = AAAAAAAAb
where A represents the latched-in state of the AUTO
input prior to the reset.
Setting BCKOFF_ to 1 (Table 18) enables Cadence
timing on each port where the port backs off and waits
2.2s after each failed load discovery detection. The IEEE
802.3af standard requires a PSE that delivers power
through the spare pairs (midspan PSE) to have cadence
timing. A reset sets R14h = 0000XXXX where X is the
logic AND of the MIDSPAN and AUTO input state prior to
a reset. BCKOFF_ can be changed by software at any
time while changes to the MIDSPAN and AUTO input
state during normal operation are ignored.
TSTART[1,0] (Table 19) programs the startup timers,
startup time is the time the port is allowed to be in current
limit during startup. TFAULT_[1,0] programs the fault
time. Fault time is the time allowable for the port to be in
current limit during normal operation. RSTR[1,0] pro-
grams the discharge rate of the TFAULT_ counter and
effectively sets the time the port remains off after an over-
current fault. TDISC[1,0] programs the load disconnect
detection time. The device turns off power to the port if it
fails to provide a minimum power maintenance signal for
longer than the load disconnect detection time (TDISC).
Set the bits in R16h to scale the TSTART, TFAULT, and
TDISC to a multiple of their nominal value specified in
the Electrical Characteristics table. R27h and R28h fur-
Quad Network Power Controller
for Power-Over-LAN
28 ______________________________________________________________________________________
MODE DESCRIPTION
00 Shutdown
01 MANUAL
10 Semi AUTO
11 AUTO
Table 15a. Mode Status
ADDRESS = 13h
SYMBOL
BIT R/W
DESCRIPTION
ACD_EN4
7 R/W
Enable AC disconnect detection on port 4
ACD_EN3
6 R/W
Enable AC disconnect detection on port 3
ACD_EN2
5 R/W
Enable AC disconnect detection on port 2
ACD_EN1
4 R/W
Enable AC disconnect detection on port 1
DCD_EN4
3 R/W
Enable DC disconnect detection on port 4
DCD_EN3
2 R/W
Enable DC disconnect detection on port 3
DCD_EN2
1 R/W
Enable DC disconnect detection on port 2
DCD_EN1
0 R/W
Enable DC disconnect detection on port 1
Table 16. Load Disconnect Detection Enable Register
ADDRESS = 14h
SYMBOL
BIT R/W
DESCRIPTION
CLASS_EN4
7 R/W
Enable classification on port 4
CLASS_EN3
6 R/W
Enable classification on port 3
CLASS_EN4
5 R/W
Enable classification on port 2
CLASS_EN3
4 R/W
Enable classification on port 1
DET_EN4
3 R/W
Enable detection on port 4
DET_EN3
2 R/W
Enable detection on port 3
DET_EN2
1 R/W
Enable detection on port 2
DET_EN1
0 R/W
Enable detection on port 1
Table 17. Detection and Classification Enable Register
ther extend the programming range of these timers and
also increase the programming resolution.
When the MAX5945 shuts down a port due to an
extended overcurrent condition (either during startup or
normal operation), if RSRT_EN is set high, then the part
does not allow the port to power back on before the
restart timer (Table 19a) returns to zero. This effectively
sets a minimum duty cycle that protects the external
MOSFET from overheating during prolonged output
overcurrent conditions.
A reset sets R16h = 00h.
Setting CL_DISC to 1 (Table 20) enables port-over-
class current protection, where the MAX5945 scales
down the overcurrent limit (VFLT_LIM) according to the
port classification status. This feature provides protec-
tion to the system against PDs that violate their maxi-
mum class current allowance.
A reset sets R17h = 0xC0.
Power-enable pushbutton (Table 21) for SEMI and
MANUAL modes. Setting PWR_ON_ to 1 turns on
power to the corresponding port. Setting PWR_OFF_ to
1 turns off power to the port. PWR_ON_ is ignored
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 29
ADDRESS = 15h
SYMBOL BIT
R/W
DESCRIPTION
Reserved 7 R Reserved
Reserved 6 R Reserved
Reserved 5 R Reserved
Reserved 4 R Reserved
BCKOFF4 3
R/W
Enable Cadence timing on port 4
BCKOFF3 2
R/W
Enable Cadence timing on port 3
BCKOFF2 1
R/W
Enable Cadence timing on port 2
BCKOFF1 0
R/W
Enable Cadence timing on port 1
Table 18. Backoff Enable Register
ADDRESS = 16h
SYMBOL
BIT R/W
DESCRIPTION
RSTR[1]
7 R/W
Restart timer programming bit 1
RSTR[0]
6 R/W
Restart timer programming bit 0
TSTART[1]
5 R/W
Startup timer programming bit 1
TSTART[0]
4 R/W
Startup timer programming bit 0
TFAULT[1]
3 R/W
Overcurrent timer programming bit 1
TFAULT[0]
2 R/W
Overcurrent timer programming bit 0
TDISC[1]
1 R/W
Load disconnect timer programming bit 1
TDISC[0]
0 R/W
Load disconnect timer programming bit 0
Table 19. Timing Register
BIT [1:0] RSTR tDISC tSTART tFAULT
00 16 x tFAULT tDISC nominal
(350ms, typ)
tSTART nominal
(60ms, typ)
tFAULT nominal
(60ms, typ)
01
32 x tFAULT
1/4 x tDISC nominal 1/2 x tSTART nominal 1/2 x tFAULT nominal
10
64 x tFAULT 1/2 x tDISC nominal 2 x tSTART nominal 2 x tFAULT nominal
11
0 x tFAULT 2 x tDISC nominal 4 x tSTART nominal 4 x tFAULT nominal
Table 19a. Startup, Fault, and Load Disconnect Timers with Default Values in the
Register 27h and 28h
MAX5945
when the port is already powered and during shut-
down. PWR_OFF_ is ignored when the port is already
off and during shutdown. After execution, the bits reset
to 0. During detection or classification, if PWR_ON_
goes high, the MAX5945 gracefully terminates the cur-
rent operation and turn-on power to the port. The
MAX5945 ignores the PWR_ON_ in AUTO mode. A
reset sets R19h = 00h.
Quad Network Power Controller
for Power-Over-LAN
30 ______________________________________________________________________________________
ADDRESS = 17h
SYMBOL
BIT R/W
DESCRIPTION
INT_EN
7 R/W
A logic high enables INT functionality
RSTR_EN
6R
A logic high enables the autorestart protection time off (as set by the RSRT[1:0] bits)
Reserved
5R
Reserved
Reserved
4R
Reserved
POFF_CL
3R
A l og i c hi g h p r events p ow er - up after a cl assi fi cati on fai l ur e ( I > 50m A, val i d onl y i n AU TO m od e)
CL_DISC 2
R/W
A logic high enables reduced current-limit voltage threshold (VFLT_LIM) according to port
classification result
Reserved
1 R/W
Reserved
Reserved
0 R/W
Reserved
Table 20. Miscellaneous Configurations
ADDRESS = 19h
SYMBOL
BIT R/W
DESCRIPTION
PWR_OFF4
7W
A logic high powers off port 4
PWR_OFF3
6W
A logic high powers off port 3
PWR_OFF2
5W
A logic high powers off port 2
PWR_OFF1
4W
A logic high powers off port 1
PWR_ON4
3W
A logic high powers on port 4
PWR_ON3
2W
A logic high powers on port 3
PWR_ON2
1W
A logic high powers on port 2
PWR_ON1
0W
A logic high powers on port 1
Table 21. Power Enable Pushbuttons
ADDRESS = 1Ah
SYMBOL
BIT R/W
DESCRIPTION
CLR_INT
7 W A logic high clears all interrupts
Reserved
6 Reserved
Reserved
5 Reserved
RESET_IC
4 W A logic high resets the MAX5945
RESET_P4
3 W A logic high softly resets port 4
RESET_P3
2 W A logic high softly resets port 3
RESET_P2
1 W A logic high softly resets port 2
RESET_P1
0 W A logic high softly resets port 1
Table 22. Global Pushbuttons
Writing a 1 to CLR_INT (Table 22) clears all the event
registers and the corresponding interrupt bits in register
R00h. Writing a 1 to RESET_P_ turns off power to the cor-
responding port and resets only the status and event
registers of that port. After execution, the bits reset to 0.
Writing a 1 to RESET_IC causes a global software reset,
after which the register map is set back to its reset state.
A reset sets R1Ah = 00h.
Enable SMODE function (Table 24) by setting
EN_WHDOG (R1Fh[7]) to 1. SMODE_ bit goes high when
the watchdog counter reaches zero and the port(s)
switch over to hardware-controlled mode. SMODE_ also
goes high each and every time the software tries to
power-on a port but is denied since the port is in hard-
ware mode. A reset sets R1Ch = 00h.
Set EN_WHDOG (R1Fh[7]) to 1 (Table 25) to enable the
watchdog function. When activated, the watchdog timer
counter, WDTIME[7:0], continuously decrements toward
zero once every 164ms. Once the counter reaches zero
(also called watchdog expiry), the MAX5945 enters hard-
ware-controlled mode and each port shifts to a mode set
by the HWMODE_ bit in register R1Fh (Table 24). Use
software to set WDTIME and continuously set this register
to some non-zero value before the register reaches zero
to prevent a watchdog expiry. In this way, the software
gracefully manages the power to ports upon a system
crash or switchover.
While in hardware-controlled mode, the MAX5945
ignores all requests to turn the power on and the flag
SMODE_ indicates that the hardware took control of the
MAX5945 operation. In addition, the software is not
allowed to change the mode of operation in hardware-
controlled mode. A reset sets R1Eh = 00h.
Setting EN_WHDOG (Table 26) high activates the
watchdog counter. When the counter reaches zero, the
port switches to the hardware-controlled mode deter-
mined by the corresponding HWMODE_ bit. A low in
HWMODE_ switches the port into shutdown by setting
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 31
ADDRESS = 1Bh
SYMBOL
BIT R/W
DESCRIPTION
7R
ID_CODE[4]
6R
ID_CODE[3]
5R
ID_CODE[2]
4R
ID_CODE[1]
ID_CODE
3R
ID_CODE[0]
2R
REV [2]
1R
REV [1]
REV
0R
REV [0]
Table 23. ID Register
ID register keeps track of the device ID number and revision. The MAX5945’s ID_CODE[4:0] = 11000b. Contact the factory for
REV[2:0] value.
ADDRESS = 1Ch
SYMBOL
BIT
CoR DESCRIPTION
Reserved
7 — Reserved
Reserved
6 — Reserved
Reserved
5 — Reserved
Reserved
4 — Reserved
SMODE4
3 CoR Hardware control flag for port 4
SMODE3
2 CoR Hardware control flag for port 3
SMODE2
1 CoR Hardware control flag for port 2
SMODE1
0 CoR Hardware control flag for port 1
Table 24. SMODE Register
MAX5945
the bits in register R12h to 00. A high in HWMODE_
switches the port into auto mode by setting the bits in
register R12h to 11. If WD_INT_EN is set, an interrupt is
sent if any of the SMODE bits are set.
A reset sets R1Fh = 00h.
Use IGATE[2:0] (Table 27) to set the gate pin pullup
current, IPU, according to the following formula:
IPU = 50µA - 6.25 x N
where N is the decimal value of IGATE[2:0].
Use AC_TH[2:0] to program the current threshold of the
AC disconnect comparator according to the following
formula:
IAC_TH = 213.68µA + 28.33µA x N
where N is the decimal value of AC_TH[2:0].
Note: The programmed value has the same percent-
age tolerance as the value specified in the Electrical
Characteristics.
When set low, DET_BYP inhibits port power-on if the
discovery detection was bypassed in AUTO mode.
When set high, it allows the part to turn on power to a
non-IEEE 802.3af load without doing detection. If
OSCF_RS is set high, the OSC_FAIL bit is ignored.
A reset sets R23h = 04h, which sets IPU = 50µA and
IAC_TH = 325µA as shown in the Electrical
Characteristics.
Use R27h (Table 28) to program the current-limit
threshold, VSU_LIM, and the nominal load disconnect
detection time, tDISC nominal.
Use IMAX[3:0] to program the current-limit trip voltage
according to the following formula:
VSU_LIM = 135mV + 19.25mV x N
where N is the decimal value of IMAX[3:0]. The
VFAULT_LIM limit scales proportionally to the VSU_LIM
value (IFAULT = 88% of VSU_LIM).
A reset sets R27h = 47h, which sets VSU_LIM = 212mV
(typical) as shown in the Electrical Characteristics. The
default threshold is set to meet the IEEE 802.3af stan-
dard when using an RSENSE = 0.5Ω±1%, 100ppm.
Quad Network Power Controller
for Power-Over-LAN
32 ______________________________________________________________________________________
ADDRESS = 1Eh
SYMBOL
BIT
R/W DESCRIPTION
7 R/W WDTIME[7]
6 R/W WDTIME[6]
5 R/W WDTIME[5]
4 R/W WDTIME[4]
3 R/W WDTIME[3]
2 R/W WDTIME[2]
1 R/W WDTIME[1]
WDTIME
0 R/W WDTIME[0]
Table 25. Watchdog Timer Register
ADDRESS = 1Fh
SYMBOL
BIT R/W
DESCRIPTION
EN_WHDOG
7
R/W
A logic high enables the watchdog function
WD_INT_EN
6 — Enables interrupt on SMODE_ bits
Reserved 5 —
Reserved 4
R/W
HWMODE4
3
R/W
Port 4 switches to AUTO if logic high and to SHUTDOWN if logic low when watchdog timer expires
HWMODE3
2
R/W
Port 3 switches to AUTO if logic high and to SHUTDOWN if logic low when watchdog timer expires
HWMODE2
1
R/W
Port 2 switches to AUTO if logic high and to SHUTDOWN if logic low when watchdog timer expires
HWMODE1
0
R/W
Port 1 switches to AUTO if logic high and to SHUTDOWN if logic low when watchdog timer expires
Table 26. Switch Mode Register
Use TF_PR[3:0] to set the nominal value for tDISC
according to the following formula:
tDISC nominal = 238ms + 16ms x N
where N is the decimal value of the binary words
TF_PR[3:0].
A reset sets R27h = 47h, which sets tDISC nominal =
350ms as shown in the Electrical Characteristics. Use
R27h in conjunction with the two TDISC[1:0] bits in reg-
ister R16h to program the values of tDISC from 60ms to
almost 340ms with a 16ms resolution.
Example: Set TD_PR[3:0] = 1111b, TDISC[1:0] = 11b
Then:
tDISC = 2 x tDISC nominal
= 2 x (238ms + 16ms x 15)
= 956ms
Note: The programmed value has the same percent-
age tolerance as the value specified in the Electrical
Characteristics.
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 33
ADDRESS = 23h
SYMBOL
BIT
R/W DESCRIPTION
7 R/W IGATE[2]
6 R/W IGATE[1]IGATE
5 R/W IGATE[0]
DET_BYP
4 R/W Detect bypass protection in AUTO mode
OSCF_RS
3 R/W OSC_FAIL Reset Bit
2 R/W AC_TH[2]
1 R/W AC_TH[1]
AC_TH
0 R/W AC_TH[0]
Table 27. Program Register 1
ADDRESS = 27h
SYMBOL
BIT
R/W DESCRIPTION
7 R IMAX[3]. VSU_LIM programming bit 3.
6 R IMAX[2]. VSU_LIM programming bit 2.
5 R IMAX[1]. VSU_LIM programming bit 1.
IMAX
4 R IMAX[0]. VSU_LIM programming bit 0.
3 R TD_PR[3]. tDISC nominal programming bit 3.
2 R TD_PR [2]. tDISC nominal programming bit 2.
1 R TD_PR [1]. tDISC nominal programming bit 1.
TD_PR
0 R TD_PR [0]. tDISC nominal programming bit 0.
Table 28. Program Register 2
MAX5945
Use the program registers (Table 29) to set the nominal
value for tFAULT and tSTART for all ports according to
the following formula:
tFAULT nominal = 40.96ms + 2.72ms x N
tSTART nominal = 40.96ms + 2.72ms x N
where N is the decimal value of TF_PR[3:0] or
TS_PR[3:0], respectively.
A reset sets R28h = 77h, which sets tFAULT = tSTART =
60ms as shown in the Electrical Characteristics. Use
R28h in conjunction with the two TSTART and TFAULT
bits in register R16h to program the values of tFAULT
and tSTART from about 20ms to almost 330ms with a
2.72ms resolution.
Example: Set TF_PR[3:0] = 1111b, TFAULT[1:0] = 11b
Then:
tFAULT = 4 x tFAULT nominal
= 4 x (40.96ms + 2.72ms x 15)
= 327ms
Note: The programmed value has the same percent-
age tolerance as the value specified in the Electrical
Characteristics.
Quad Network Power Controller
for Power-Over-LAN
34 ______________________________________________________________________________________
ADDRESS = 28h
SYMBOL
BIT
R/W DESCRIPTION
7 R TF_PR[3]. tFAULT nominal programming bit 3.
6 R TF_PR[2]. tFAULT nominal programming bit 2.
5 R TF_PR[1]. tFAULT nominal programming bit 1.
TF_PR
4 R TF_PR[0]. tFAULT nominal programming bit 0.
3 R TS_PR[3]. tSTART nominal programming bit 3.
2 R TS_PR[2]. tSTART nominal programming bit 2.
1 R TS_PR[1]. tSTART nominal programming bit 1.
TS_PR
0 R TS_PR[0]. tSTART nominal programming bit 0.
Table 29. Program Register 3
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 35
Table 30. Register Map Summary
ADDR
REGISTER
NAME
R/W PORT
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET
STATE
INTERRUPTS
00h
Interrupt RO G SUP_FLT TSTR_FLT IMAX_FLT CL_END DET_END LD_DISC PG_INT PE_INT
0000,0000
01h
Int Mask
R/W
G MASK7 MASK6
MASK5 MASK4
MASK3
MASK2 MASK1
MASK0
AAA0,0A00
EVENTS
02h
Power Event RO 4321
0000,0000
03h
Power Event
CoR
CoR PG_CHG4 PG_CHG3 PG_CHG2 PG_CHG1
PWEN_
CHG4
PWEN_
CHG3
PWEN_
CHG2
PWEN_
CHG1
04h
Detect Event RO 4321
0000,0000
05h
Detect Event
CoR
CoR CL_END4 CL_END3 CL_END2 CL_END1 DET_END4 DET_END3 DET_END2 DET_END1
06h
Fault Event RO 4321
0000,0000
07h
Fault Event
CoR
CoR LD_DISC4 LD_DISC3 LD_DISC2 LD_DISC1 IMAX_FLT4 IMAX_FLT3 IMAX_FLT2 IMAX_FLT1
08h
Tstart Event RO 4321
0000,0000
09h
Tstart Event
CoR
CoR
IVC4 IVC3 IVC2 IVC1
STRT_FLT4 STRT_FLT3 STRT_FLT2 STRT_FLT1
0Ah
Supply Event RO 4321
0011,0101*
0Bh
Supply Event
CoR
CoR
TSD
VDD_OV VDD_UV VEE UVLO VEE_OV VEE_UV OSC_FAIL VDD_UVLO
STATUS
0Ch
Port 1 Status RO
1
reserved CLASS1[2] CLASS1[1] CLASS1[0] reserved DET_ST1
[2]
DET_ST1
[1]
DET_ST1
[0]
0000,0000
0Dh
Port 2 Status RO
2
reserved CLASS2[2] CLASS2[1] CLASS2[0] reserved DET_ST2
[2]
DET_ST2
[1]
DET_ST2
[0]
0000,0000
0Eh
Port 3 Status RO
3
reserved CLASS3[2] CLASS3[1] CLASS3[0] reserved DET_ST3
[2]
DET_ST3
[1]
DET_ST3
[0]
0000,0000
0Fh
Port 4 Status RO
4
reserved CLASS4[2] CLASS4[1] CLASS4[0] reserved DET_ST4
[2]
DET_ST4
[1]
DET_ST4
[0]
0000,0000
10h
Power Status RO 4321 PGOOD4 PGOOD3 PGOOD2 PGOOD1 PWR_EN4 PWR_EN3 PWR_EN2 PWR_EN1
0000,0000
11h
Pin Status
RO
G
reserved reserved
A3 A2 A1 A0
MIDSPAN
AUTO 00A3A2,
A1A0MA
*UV and UVLO bits of VEE and VDD asserted depend on the order VEE and VDD supplies are brought up.
A = AUTO pin state, A3..0 = ADDRESS pin states, M = MIDSPAN pin state, R = contact factory for current revision code Table 15a.
MAX5945
Quad Network Power Controller
for Power-Over-LAN
36 ______________________________________________________________________________________
Table 30. Register Map Summary (continued)
ADDR
REGISTER
NAME
R/W
PORT
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET
STATE
CONFIGURATION
12h
Operating
Mode
R/W 4321
P4_M1 P4_M0 P3_M1 P3_M0 P2_M1 P2_M0 P1_M1 P1_M0
AAAA,AAAA
13h
Disconnect
Enable
R/W 4321 ACD_EN4 ACD_EN3 ACD_EN2 ACD_EN1 DCD_EN4 DCD_EN3 DCD_EN2 DCD_EN1
0000,AAAA
14h
Det/Class
Enable
R/W 4321 CLASS_EN4
CLASS_EN
3
CLASS_EN
2
CLASS_EN
1
DET_EN4 DET_EN3 DET_EN2 DET_EN1
AAAA,AAAA
15h
Backoff
Enable
R/W 4321 reserved reserved reserved reserved Bckoff4 Bckoff3 Bckoff2 Bckoff1
0000,MMMM
16h
Timing Config R/W G RSTR[1] RSTR[0] TSTART[1] TSTART[0] TFAULT[1] TFAULT[0] TDISC[1] TDISC[0]
0000,0000
17h
Misc Config R/W
G INT_EN
RSTR_EN reserved reserved POFF_CL CL_DISC reserved reserved
1100,0000
PUSHBUTTONS
18h
Reserved
R/W
G
reserved reserved reserved reserved reserved reserved reserved reserved
19h
Power Enable WO 4321 PWR_OFF4 PWR_OFF3 PWR_OFF2 PWR_OFF1 PWR_ON4 PWR_ON3 PWR_ON2 PWR_ON1
0000,0000
1Ah
Global
WO
G
CLR_INT reserved reserved RESET_IC RESET_P4 RESET_P3 RESET_P2 RESET_P1
0000,0000
GENERAL
1Bh
ID RO G ID_CODE[ 4] ID_CODE[ 3] ID_CODE[ 2] ID_CODE[ 1] ID_CODE[ 0] REV [2] REV [1] REV [0]
1100,0RRR
1Ch
SMODE
CoR 4321 reserved reserved reserved reserved SMODE4 SMODE3 SMODE2 SMODE1
00000000
1Dh
Reserved G reserved reserved reserved reserved Reserved reserved reserved reserved
00000000
1EH
Watchdog
R/W
G
WDTIME[7] WDTIME[6] WD TI ME [ 5] WDTIME[4] WDTIME[3] WDTIME[2] WDTIME[1] WDTIME[0]
00000000
1FH
Switch Mode R/W 4321 EN_ WHDOG WD_INT_EN reserved reserved HWMODE4 HWMODE3 HWMODE2 HWMODE1
00000000
MAXIM RESERVED
20H
Reserved G reserved reserved reserved reserved Reserved reserved reserved reserved
00000000
21H
Reserved G
reserved reserved reserved reserved Reserved reserved reserved reserved
00000000
22H
Reserved G reserved reserved reserved reserved Reserved reserved reserved reserved
00000000
23H
Program1
R/W 4321 IGATE[2] IGATE[1] IGATE[0] DET_BYP OSCF_RS AC_TH[0] AC_TH[0] AC_TH[0]
00000100
24h
Reserved G reserved reserved reserved reserved Reserved reserved reserved reserved
00000000
25h
Reserved G
reserved reserved reserved reserved Reserved reserved reserved reserved
00000000
26h
Reserved G
reserved reserved reserved reserved Reserved reserved reserved reserved
00000000
27H
Program2 R/W G IMAX[3] IMAX[2] IMAX[1] IMAX[0] TD[3] TD[2] TD[1] TD[0]
01000111
28H
Program3
R/W
G
TF_PR[3]
TF_PR[2]
TF_PR[1]
TF_PR[0]
TS_PR[3]
TS_PR[2]
TS_PR[1]
TS_PR[0]
01110111
*UV and UVLO bits of VEE and VDD asserted depend on the order VEE and VDD supplies are brought up.
A = AUTO pin state, A3..0 = ADDRESS pin states, M = MIDSPAN pin state, R = contact factory for current revision code Table 15a.
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 37
Figure 14. PoE System Block Diagram
MAX5945
QUAD PoE
CONTROLLER
MAX5020
-48V TO +3.3V
DC-DC
MAX5940B
PD INTERFACE
CONTROLLER
MAX5014
DC-DC
CONVERTER
GND
-48V
PHY
DATA
PHY LOAD
DATA
POWER
3.3V -48V
POWER
MAX5941/MAX5942
PD INTERFACE AND
DC-DC CONVERTER
OR
PSE (SWITCHES/ROUTERS, ETC) PD (IP PHONE, WIRELESS ACCESS POINT, SECURITY CAMERAS, ETC.)
RJ–45RJ–45
POWER AND DATA
OVER TWISTED-PAIR
ETHERNET CABLE
VOUT
Applications Information
MAX5945
Quad Network Power Controller
for Power-Over-LAN
38 ______________________________________________________________________________________
Figure 15. PoE System Diagram of One Complete Port, Endpoint PSE
MAX5945
-48V
GATE_
INTERNAL PULLDOWN
(MANUAL MODE)
1kΩ
-48VRTN
FDT3612
100V, 120mΩ
SOT-223
SENSE_
VEE OUT_
OFF
ON
DET_
SDAIN
SDAOUT
SCL
DGND
VDD
A0 A1 A2 A3
OSC_IN
AUTO
MIDSPAN
AGND
INTERNAL PULLDOWN
(SIGNAL MODE)
0.5Ω
1% 1N4448
1kΩ
1 OF 4 CHANNELS
1.8V TO 5V,
(REF TO DGND)
INT
RESET
3kΩ
3kΩ
180Ω
180Ω
180Ω
OPTIONAL BUFFER
INTERNAL
50kΩ PULLUP 4.7kΩ
1kΩ
VDD
1N4002
HPCL063L
OPTIONAL BUFFER
OPTIONAL BUFFER
HPCL063L
HPCL063L
VCCRTN
VCC (3.3V)
SCL
SDA
SERIAL INTERFACE
3kΩ
3kΩ
ISOLATION
0.47µF
100V
SHD_
SINE WAVE
100Hz ±10%
PEAK AMPLITUDE 2.2V ±0.1V
VALLEY AMPLITUDE 0.2V ±0.1V
SMBJ
58CA 0.1µF 2.2MΩ
-48VOUT
8
7
5
4
6
3
2
1
-48VOUT
0.1µF
0.1µF
0.1µF
0.1µF
75Ω
75Ω75Ω
75Ω
1000pF
250VAC
24
22
21
19
23
20
RX1+
RX1-
TX1+
TX1-
RXT1
TXCT1
RD1+
RD1-
TD1+
TD1-
1
3
4
5
PHY 1/2 OF
H2005A
RJ–45
CONNECTOR
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 39
Figure 16. PoE System Diagram of One Complete Port, Midspan PSE
MAX5945
-48V
GATE_
INTERNAL PULLDOWN
(MANUAL MODE)
1kΩ
-48VRTN
FDT3612
100V, 120mΩ
SOT-223
SENSE_
VEE OUT_
OFF
ON
DET_
SDAIN
SDAOUT
SCL
DGND
VDD
A0 A1 A2 A3
OSC_IN
AUTO
MIDSPAN
AGND
INTERNAL PULLDOWN
(SIGNAL MODE)
0.5Ω
1% 1N4448
1kΩ
1 OF 4 CHANNELS
1.8V TO 5V
(REF TO DGND)
INT
RESET
3kΩ
3kΩ
180Ω
180Ω
180Ω
OPTIONAL BUFFER
INTERNAL
50kΩ PULLUP 4.7kΩ
1kΩ
VDD
1N4002
HPCL063L
OPTIONAL BUFFER
OPTIONAL BUFFER
HPCL063L
HPCL063L
VCCRTN
VCC (3.3V)
SCL
SDA
SERIAL INTERFACE
3kΩ
3kΩ
ISOLATION
0.47µF
100V
SHD_
SINE WAVE
100Hz ±10%
PEAK AMPLITUDE 2.2V ±0.1V
VALLEY AMPLITUDE 0.2V ±0.1V
SMBJ
58CA 0.1µF 2.2MΩ
-48VOUT
8
7
5
4
6
3
2
1
RJ–45
CONNECTOR
-48VOUT
DATA
MAX5945
Quad Network Power Controller
for Power-Over-LAN
40 ______________________________________________________________________________________
Figure 17. -48V to +3.3V (300mA) Boost Converter Solution for VDIG
GND
-48V
-48V
GND
C6
0.47µF
100V
R10
2Ω
R6
1Ω
C3
15nF
Q4
MMBTA56
R5
1kΩ
L1
68µH, DO3308P-683
MAX5020
1
2
3
4
8
7
6
5
V+
VDD
FB
VCC
NDRV
GND
CS
C2
0.022µF
R8
30Ω
C1
0.1µF
C8
2.2µF
R4
1Ω
R9
1Ω
GATE
SOURCE
DRAIN
Q1
Si2328 DS
C9
4.7µH
C7
0.22µF
R7
1.02kΩ
R2
6.81kΩ
R3
2.61kΩ
Q3
MMBTA56
D1
DIODES INC.: B1100
C4
220µF
Sanyo 6SPS220M
R1
2.6kΩ
Q2
MMBTA56
C5
4.7µF
+3.3V
+3.3V
GND
300mA
SS_SHDN
Figure 18. Layout Example for Boost Converter Solution for VDIG
1700 (mils)
965 (mils)
1700 (mils)
965 (mils)
1700 (mils)
965 (mils)
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 41
DESIGNATION
DESCRIPTION
C1 0.1µF, 25V ceramic capacitor
C2 0.022µF, 25V ceramic capacitor
C3 15nF, 25V ceramic capacitor
C4 220µF capacitor
Sanyo 6SVPA220MAA
C5 4.7µF, 16V ceramic capacitor
C6 0.1µF, 100V ceramic capacitor
C7 0.22µF, 16V ceramic capacitor
C8 0.22µF, 16V ceramic capacitor
C9 4.7nF, 16V ceramic capacitor
D1 B1100 100V Schottky diode
L1 68µH inductor
Coilcraft DO3308P-683 or equivalent
Q1 Si2328DS
Vishay n-channel MOSFET, SOT23
Q2 MMBTA56 small-signal PNP
Q3 MMBTA56 small-signal PNP
Q4 MMBTA56 small-signal PNP
R1 2.61kΩ ±1% resistor
R2 6.81kΩ ±1% resistor
R3 2.61kΩ ±1% resistor
R4 1Ω ±1% resistor
R5 1kΩ ±1% resistor
R6 1Ω ±1% resistor
R7 1.02kΩ ±1% resistor
R8 30Ω ±1% resistor
R9 1Ω ±1% resistor
R10 2Ω ±1% resistor
U1 High-voltage PWM IC
MAX5020ESA (8-pin SO)
Component List Chip Information
TRANSISTOR COUNT: 148,768
PROCESS: BiCMOS
MAX5945
Quad Network Power Controller
for Power-Over-LAN
42 ______________________________________________________________________________________
MAX5945
-48V
GATE_
INTERNAL PULLDOWN
(MANUAL MODE)
1kΩ
-48VRTN
FDT3612
100V, 120mΩ
SOT-223
SENSE_
VEE OUT_
OFF
ON
DET_
SDAIN
SDAOUT
SCL
DGND
VDD
A0 A1 A2 A3
OSC_IN
AUTO
MIDSPAN
AGND
INTERNAL PULLDOWN
(SIGNAL MODE)
0.5Ω
1%
-48V
OUTPUT TO
PORT
-48V RTN
OUTPUT TO PORT
NOTE: ALL SIGNAL PINS ARE REFERENCED TO DGND.
DGND RANGE IS BETWEEN VEE AND (AGND + 4V).
1N4448
1 OF 4 CHANNELS
1.8V TO 3.7V,
(REF TO DGND)
INT
RESET
3kΩ
3kΩ
180Ω
180Ω
180Ω
OPTIONAL BUFFER
INTERNAL
50kΩ PULLUP 4.7kΩ
1kΩ
VDD
CAN BE UP TO 100kΩ
HPCL063L
OPTIONAL BUFFER
OPTIONAL BUFFER
HPCL063L
HPCL063L
VCCRTN
VCC (3.3V)
SCL
SDA
SERIAL INTERFACE
3kΩ
3kΩ
ISOLATION
N.C.
SHD_
Typical Operating Circuits
Typical Operating Circuit 1 (without AC Load Removal Detection)
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 43
MAX5945
-48V
GATE_
INTERNAL PULLDOWN
(MANUAL MODE)
1kΩ
-48VRTN
FDT3612
100V, 120mΩ
SOT-223
SENSE_
VEE OUT_
OFF
ON
DET_
SDAIN
SDAOUT
SCL
DGND
VDD
A0 A1 A2 A3
OSC_IN
AUTO
MIDSPAN
AGND
INTERNAL PULLDOWN
(SIGNAL MODE)
0.5Ω
1%
-48V
OUTPUT TO
PORT
-48V RTN
OUTPUT TO PORT
NOTE: ALL SIGNAL PINS ARE REFERENCED TO DGND.
1N4448
1kΩ
1 OF 4 CHANNELS
1.8V TO 3.7V,
(REF TO DGND)
INT
RESET
3kΩ
3kΩ
180Ω
180Ω
180Ω
OPTIONAL BUFFER
INTERNAL
50kΩ PULLUP 4.7kΩ
1kΩ
VDD
1N4002
CAN BE UP TO 100kΩ
HPCL063L
OPTIONAL BUFFER
OPTIONAL BUFFER
HPCL063L
HPCL063L
VCCRTN
VCC (3.3V)
SCL
SDA
SERIAL INTERFACE
3kΩ
3kΩ
ISOLATION
DGND MUST BE CONNECTED DIRECTLY TO AGND
FOR AC DISCONNECT DETECTION CIRCUIT TO OPERATE.
0.47µF
100V
SHD_
SINE WAVE
100Hz ±10%
PEAK AMPLITUDE 2.2V ±0.1V
VALLEY AMPLITUDE 0.2V ±0.1V
Typical Operating Circuits (continued)
Typical Operating Circuit 2 (with AC Load Removal Detection)
MAX5945
Quad Network Power Controller
for Power-Over-LAN
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
44 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
SSOP.EPS
PACKAGE OUTLINE, 36L SSOP, 0.80 MM PITCH
1
1
21-0040 E
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
FRONT VIEW
MAX
0.011
0.104
0.017
0.299
0.013
INCHES
0.291
0.009
E
C
DIM
0.012
0.004
B
A1
MIN
0.096A
0.23
7.40 7.60
0.32
MILLIMETERS
0.10
0.30
2.44
MIN
0.44
0.29
MAX
2.65
0.040
0.020L0.51 1.02
H 0.4140.398 10.11 10.51
e 0.0315 BSC 0.80 BSC
D 0.6120.598 15.20 15.55
HE
A1 A
D
eB0∞-8∞
L
C
TOP VIEW
SIDE VIEW
1
36
